WO2007017371A3 - Verfahren und vorrichtung zur festlegung eines startzustandes bei einem rechnersystem mit wenigstens zwei ausführungseinheiten durch markieren von registern - Google Patents

Verfahren und vorrichtung zur festlegung eines startzustandes bei einem rechnersystem mit wenigstens zwei ausführungseinheiten durch markieren von registern Download PDF

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Publication number
WO2007017371A3
WO2007017371A3 PCT/EP2006/064607 EP2006064607W WO2007017371A3 WO 2007017371 A3 WO2007017371 A3 WO 2007017371A3 EP 2006064607 W EP2006064607 W EP 2006064607W WO 2007017371 A3 WO2007017371 A3 WO 2007017371A3
Authority
WO
WIPO (PCT)
Prior art keywords
start status
determining
computer system
execution units
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2006/064607
Other languages
English (en)
French (fr)
Other versions
WO2007017371A2 (de
Inventor
Reinhard Weiberle
Bernd Mueller
Eberhard Boehl
Yorck Collani
Rainer Gmehlich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE502006003116T priority Critical patent/DE502006003116D1/de
Priority to US11/990,233 priority patent/US20100011183A1/en
Priority to EP06777942A priority patent/EP1915686B1/de
Priority to JP2008525517A priority patent/JP2009505179A/ja
Publication of WO2007017371A2 publication Critical patent/WO2007017371A2/de
Publication of WO2007017371A3 publication Critical patent/WO2007017371A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Verfahren zur Festlegung eines Startzustandes bei einem Rechnersystem mit wenigstens zwei Ausführungseinheiten, wobei zwischen einem Performanzmodus und einem Vergleichsmodus umgeschaltet wird und bei Umschaltung aus dem Performanzmodus in den Vergleichsmodus ein Startzustand für den Vergleichsmodus erzeugt wird, dadurch gekennzeichnet, dass für den Startzustand potentiell anzugleichende Speicher oder Speicherbereiche mit einer Kennung versehen werden, ob die Daten und/oder Befehle in diesen Speichern oder Speicherbereichen für den Startzustand geändert werden müssen oder nicht geändert werden müssen.
PCT/EP2006/064607 2005-08-08 2006-07-25 Verfahren und vorrichtung zur festlegung eines startzustandes bei einem rechnersystem mit wenigstens zwei ausführungseinheiten durch markieren von registern Ceased WO2007017371A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE502006003116T DE502006003116D1 (de) 2005-08-08 2006-07-25 Verfahren und vorrichtung zur festlegung eines startzustandes bei einem rechnersystem mit wenigstens zwei ausführungseinheiten durch markieren von registern
US11/990,233 US20100011183A1 (en) 2005-08-08 2006-07-25 Method and device for establishing an initial state for a computer system having at least two execution units by marking registers
EP06777942A EP1915686B1 (de) 2005-08-08 2006-07-25 Verfahren und vorrichtung zur festlegung eines startzustandes bei einem rechnersystem mit wenigstens zwei ausführungseinheiten durch markieren von registern
JP2008525517A JP2009505179A (ja) 2005-08-08 2006-07-25 少なくとも２つの実行ユニットを有する計算機システムにおいてレジスタのマーキングによってスタート状態を定める方法および装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005037226A DE102005037226A1 (de) 2005-08-08 2005-08-08 Verfahren und Vorrichtung zur Festlegung eines Startzustandes bei einem Rechnersystem mit wenigstens zwei Ausführungseinheiten durch markieren von Registern
DE102005037226.0 2005-08-08

Publications (2)

Publication Number Publication Date
WO2007017371A2 WO2007017371A2 (de) 2007-02-15
WO2007017371A3 true WO2007017371A3 (de) 2007-04-26

Family

ID=37605812

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/064607 Ceased WO2007017371A2 (de) 2005-08-08 2006-07-25 Verfahren und vorrichtung zur festlegung eines startzustandes bei einem rechnersystem mit wenigstens zwei ausführungseinheiten durch markieren von registern

Country Status (8)

Country Link
US (1) US20100011183A1 (de)
EP (1) EP1915686B1 (de)
JP (1) JP2009505179A (de)
CN (1) CN101243405A (de)
AT (1) ATE425493T1 (de)
DE (2) DE102005037226A1 (de)
ES (1) ES2320806T3 (de)
WO (1) WO2007017371A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5507830B2 (ja) * 2008-11-04 2014-05-28 ルネサスエレクトロニクス株式会社 マイクロコントローラ及び自動車制御装置
JP2010198131A (ja) * 2009-02-23 2010-09-09 Renesas Electronics Corp プロセッサシステム、及びプロセッサシステムの動作モード切り替え方法
US9473752B2 (en) 2011-11-30 2016-10-18 Qualcomm Incorporated Activation of parameter sets for multiview video coding (MVC) compatible three-dimensional video coding (3DVC)
CN106502811B (zh) * 2016-10-12 2020-03-24 北京精密机电控制设备研究所 一种1553b总线通信故障处理方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0817053A1 (de) * 1996-07-01 1998-01-07 Sun Microsystems, Inc. Speicherverwaltung in fehlertoleranten Computersystemen
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US20040006722A1 (en) * 2002-07-03 2004-01-08 Safford Kevin David Method and apparatus for recovery from loss of lock step

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000181738A (ja) * 1998-12-18 2000-06-30 Fujitsu Ltd 二重化システム及びメモリ制御方法
US6640313B1 (en) * 1999-12-21 2003-10-28 Intel Corporation Microprocessor with high-reliability operating mode
US6772368B2 (en) * 2000-12-11 2004-08-03 International Business Machines Corporation Multiprocessor with pair-wise high reliability mode, and method therefore
KR20060026884A (ko) * 2003-06-24 2006-03-24 로베르트 보쉬 게엠베하 프로세서 유닛의 적어도 2개의 작동 모드 사이의 전환 방법및 상응하는 프로세서 유닛
DE502005005286D1 (de) * 2004-10-25 2008-10-16 Bosch Gmbh Robert Vorrichtung und verfahren zur modusumschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0817053A1 (de) * 1996-07-01 1998-01-07 Sun Microsystems, Inc. Speicherverwaltung in fehlertoleranten Computersystemen
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US20040006722A1 (en) * 2002-07-03 2004-01-08 Safford Kevin David Method and apparatus for recovery from loss of lock step

Also Published As

Publication number Publication date
JP2009505179A (ja) 2009-02-05
ES2320806T3 (es) 2009-05-28
DE102005037226A1 (de) 2007-02-15
DE502006003116D1 (de) 2009-04-23
US20100011183A1 (en) 2010-01-14
EP1915686A2 (de) 2008-04-30
EP1915686B1 (de) 2009-03-11
WO2007017371A2 (de) 2007-02-15
ATE425493T1 (de) 2009-03-15
CN101243405A (zh) 2008-08-13

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