WO2007030126A3 - Method, system, and apparatus for gating configurations and improved contacts in nanowire-based electronic devices - Google Patents

Method, system, and apparatus for gating configurations and improved contacts in nanowire-based electronic devices Download PDF

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Publication number
WO2007030126A3
WO2007030126A3 PCT/US2005/037237 US2005037237W WO2007030126A3 WO 2007030126 A3 WO2007030126 A3 WO 2007030126A3 US 2005037237 W US2005037237 W US 2005037237W WO 2007030126 A3 WO2007030126 A3 WO 2007030126A3
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WO
WIPO (PCT)
Prior art keywords
snowier
contact
length
gate
electronic devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/037237
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French (fr)
Other versions
WO2007030126A2 (en
WO2007030126A9 (en
Inventor
Shahriar Mostarshed
Jian Chen
Francisco Leon
Yaoling Pan
Linda T Romano
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Nanosys Inc
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Nanosys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanosys Inc filed Critical Nanosys Inc
Priority to JP2007536993A priority Critical patent/JP2008517468A/en
Priority to CN2005800431389A priority patent/CN101401210B/en
Priority to EP05858523A priority patent/EP1810340A2/en
Priority to CA2589432A priority patent/CA2589432C/en
Priority to AU2005336130A priority patent/AU2005336130B2/en
Publication of WO2007030126A2 publication Critical patent/WO2007030126A2/en
Anticipated expiration legal-status Critical
Publication of WO2007030126A9 publication Critical patent/WO2007030126A9/en
Publication of WO2007030126A3 publication Critical patent/WO2007030126A3/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36—Unipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one snowier; a gate contact is positioned along part of the length of the snowier, and a dielectric material layer is between the gate contact and the at least one snowier. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the snowier length. In another aspect, an electronic device includes a snowier having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the snowier along a portion of the length of the snowier. A second gate region is positioned along the length of the snowier between the snowier and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the snowier at respective exposed portions of the semiconductor core.
PCT/US2005/037237 2004-10-15 2005-10-14 Method, system, and apparatus for gating configurations and improved contacts in nanowire-based electronic devices Ceased WO2007030126A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2007536993A JP2008517468A (en) 2004-10-15 2005-10-14 Method, system, and apparatus for gate opening and closing and improved contacts in nanowire based electronic devices
CN2005800431389A CN101401210B (en) 2004-10-15 2005-10-14 Method, system, and apparatus for gating configurations and improved contacts in nanowire-based electronic devices
EP05858523A EP1810340A2 (en) 2004-10-15 2005-10-14 Method, system, and apparatus for gating configurations and improved contacts in nanowire­ based electronic devices
CA2589432A CA2589432C (en) 2004-10-15 2005-10-14 Method, system, and apparatus for gating configurations and improved contacts in nanowire-based electronic devices
AU2005336130A AU2005336130B2 (en) 2004-10-15 2005-10-14 Method, system, and apparatus for gating configurations and improved contacts in nanowire-based electronic devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61876204P 2004-10-15 2004-10-15
US60/618,762 2004-10-15

Publications (3)

Publication Number Publication Date
WO2007030126A2 WO2007030126A2 (en) 2007-03-15
WO2007030126A9 WO2007030126A9 (en) 2007-05-18
WO2007030126A3 true WO2007030126A3 (en) 2009-04-16

Family

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PCT/US2005/037237 Ceased WO2007030126A2 (en) 2004-10-15 2005-10-14 Method, system, and apparatus for gating configurations and improved contacts in nanowire-based electronic devices

Country Status (8)

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US (3) US7473943B2 (en)
EP (1) EP1810340A2 (en)
JP (1) JP2008517468A (en)
KR (1) KR20070063597A (en)
CN (1) CN101401210B (en)
AU (1) AU2005336130B2 (en)
CA (1) CA2589432C (en)
WO (1) WO2007030126A2 (en)

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