WO2007059443A3 - Clock signal generation techniques for memories that do not generate a strobe - Google Patents

Clock signal generation techniques for memories that do not generate a strobe Download PDF

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Publication number
WO2007059443A3
WO2007059443A3 PCT/US2006/060797 US2006060797W WO2007059443A3 WO 2007059443 A3 WO2007059443 A3 WO 2007059443A3 US 2006060797 W US2006060797 W US 2006060797W WO 2007059443 A3 WO2007059443 A3 WO 2007059443A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
generate
memory
strobe
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/060797
Other languages
French (fr)
Other versions
WO2007059443A2 (en
Inventor
Vaishnav Srinivas
Sanat Kapoor
Srinivas Maddali
Vivek Mohan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to KR1020087013924A priority Critical patent/KR101064855B1/en
Priority to AT06839836T priority patent/ATE461487T1/en
Priority to CN2006800507823A priority patent/CN101356514B/en
Priority to JP2008540362A priority patent/JP4891329B2/en
Priority to EP06839836A priority patent/EP1946214B1/en
Priority to DE602006013023T priority patent/DE602006013023D1/en
Publication of WO2007059443A2 publication Critical patent/WO2007059443A2/en
Publication of WO2007059443A3 publication Critical patent/WO2007059443A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.
PCT/US2006/060797 2005-11-10 2006-11-10 Clock signal generation techniques for memories that do not generate a strobe Ceased WO2007059443A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020087013924A KR101064855B1 (en) 2005-11-10 2006-11-10 Clock signal generation technology for memories that do not generate strobes
AT06839836T ATE461487T1 (en) 2005-11-10 2006-11-10 CLOCK SIGNAL GENERATION METHOD FOR MEMORY THAT DOES NOT GENERATE IMPULSES
CN2006800507823A CN101356514B (en) 2005-11-10 2006-11-10 Clock circuit, method for generating clock signal and memory system
JP2008540362A JP4891329B2 (en) 2005-11-10 2006-11-10 A clock signal generation technique for memory that does not generate strobes.
EP06839836A EP1946214B1 (en) 2005-11-10 2006-11-10 Clock signal generation techniques for memories that do not generate a strobe
DE602006013023T DE602006013023D1 (en) 2005-11-10 2006-11-10 CLOCK SIGNAL PROCESSING FOR MEMORIES WHICH DO NOT PRODUCE IMPULSE

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US73542105P 2005-11-10 2005-11-10
US60/735,421 2005-11-10
US11/364,296 US7656743B2 (en) 2005-11-10 2006-02-28 Clock signal generation techniques for memories that do not generate a strobe
US11/364,296 2006-02-28

Publications (2)

Publication Number Publication Date
WO2007059443A2 WO2007059443A2 (en) 2007-05-24
WO2007059443A3 true WO2007059443A3 (en) 2007-07-26

Family

ID=37891473

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/060797 Ceased WO2007059443A2 (en) 2005-11-10 2006-11-10 Clock signal generation techniques for memories that do not generate a strobe

Country Status (8)

Country Link
US (1) US7656743B2 (en)
EP (1) EP1946214B1 (en)
JP (1) JP4891329B2 (en)
KR (1) KR101064855B1 (en)
CN (1) CN101356514B (en)
AT (1) ATE461487T1 (en)
DE (1) DE602006013023D1 (en)
WO (1) WO2007059443A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5092770B2 (en) * 2008-01-29 2012-12-05 富士通セミコンダクター株式会社 Phase lock loop circuit and delay lock loop circuit
US8045356B2 (en) * 2009-02-27 2011-10-25 Micron Technology, Inc. Memory modules having daisy chain wiring configurations and filters
US8045402B2 (en) * 2009-06-29 2011-10-25 Arm Limited Assisting write operations to data storage cells
US9442186B2 (en) * 2013-05-13 2016-09-13 Microsoft Technology Licensing, Llc Interference reduction for TOF systems
US10462452B2 (en) 2016-03-16 2019-10-29 Microsoft Technology Licensing, Llc Synchronizing active illumination cameras

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479647A (en) * 1993-11-12 1995-12-26 Intel Corporation Clock generation and distribution system for a memory controller with a CPU interface for synchronizing the CPU interface with a microprocessor external to the memory controller
EP0525221B1 (en) * 1991-07-20 1995-12-27 International Business Machines Corporation Quasi-synchronous information transfer and phase alignment means for enabling same
US6466491B2 (en) * 2000-05-19 2002-10-15 Fujitsu Limited Memory system and memory controller with reliable data latch operation
US6760261B2 (en) * 2002-09-25 2004-07-06 Infineon Technologies Ag DQS postamble noise suppression by forcing a minimum pulse length

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735277A (en) * 1971-05-27 1973-05-22 North American Rockwell Multiple phase clock generator circuit
US4835403A (en) * 1986-12-30 1989-05-30 Bell & Howell Company Clocked optical sensing apparatus
US4959557A (en) * 1989-05-18 1990-09-25 Compaq Computer Corporation Negative feedback circuit to control the duty cycle of a logic system clock
US6130550A (en) * 1993-01-08 2000-10-10 Dynalogic Scaleable padframe interface circuit for FPGA yielding improved routability and faster chip layout
JPH06314217A (en) * 1993-04-28 1994-11-08 Tokyo Electric Co Ltd Electronic instrument
JPH08221315A (en) * 1995-02-15 1996-08-30 Hitachi Ltd Information processing device
JP3463727B2 (en) * 1997-05-09 2003-11-05 株式会社アドバンテスト Clock pulse transmission circuit
US6127865A (en) * 1997-05-23 2000-10-03 Altera Corporation Programmable logic device with logic signal delay compensated clock network
JP3783845B2 (en) * 2001-05-09 2006-06-07 三菱電機株式会社 In-vehicle electronic control unit
CN1442980A (en) * 2002-03-04 2003-09-17 赵达镐 Network exchange device and its operation method
US6980060B2 (en) * 2003-10-23 2005-12-27 International Business Machines Corporation Adaptive method and apparatus to control loop bandwidth of a phase lock loop
WO2006020627A1 (en) * 2004-08-11 2006-02-23 Aureon Laboratories, Inc. Systems and methods for automated diagnosis and grading of tissue images
US7312646B2 (en) * 2005-05-13 2007-12-25 Packet Digital Method and apparatus for controlling switching transients
US7323946B2 (en) * 2005-10-20 2008-01-29 Honeywell International Inc. Lock detect circuit for a phase locked loop

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0525221B1 (en) * 1991-07-20 1995-12-27 International Business Machines Corporation Quasi-synchronous information transfer and phase alignment means for enabling same
US5479647A (en) * 1993-11-12 1995-12-26 Intel Corporation Clock generation and distribution system for a memory controller with a CPU interface for synchronizing the CPU interface with a microprocessor external to the memory controller
US6466491B2 (en) * 2000-05-19 2002-10-15 Fujitsu Limited Memory system and memory controller with reliable data latch operation
US6760261B2 (en) * 2002-09-25 2004-07-06 Infineon Technologies Ag DQS postamble noise suppression by forcing a minimum pulse length

Also Published As

Publication number Publication date
JP4891329B2 (en) 2012-03-07
EP1946214B1 (en) 2010-03-17
KR20080072908A (en) 2008-08-07
JP2009516270A (en) 2009-04-16
CN101356514A (en) 2009-01-28
DE602006013023D1 (en) 2010-04-29
US20070104015A1 (en) 2007-05-10
CN101356514B (en) 2010-09-15
ATE461487T1 (en) 2010-04-15
EP1946214A2 (en) 2008-07-23
US7656743B2 (en) 2010-02-02
WO2007059443A2 (en) 2007-05-24
KR101064855B1 (en) 2011-09-14

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