WO2007076503A3 - Non-volatile memory operated on. the basis of a two-step bit-line precharge operation and a two-pass sensing operation - Google Patents

Non-volatile memory operated on. the basis of a two-step bit-line precharge operation and a two-pass sensing operation Download PDF

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Publication number
WO2007076503A3
WO2007076503A3 PCT/US2006/062605 US2006062605W WO2007076503A3 WO 2007076503 A3 WO2007076503 A3 WO 2007076503A3 US 2006062605 W US2006062605 W US 2006062605W WO 2007076503 A3 WO2007076503 A3 WO 2007076503A3
Authority
WO
WIPO (PCT)
Prior art keywords
volatile memory
sensing
basis
line precharge
step bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/062605
Other languages
French (fr)
Other versions
WO2007076503A2 (en
Inventor
Shou-Chang Tsao
Yan Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/322,427 external-priority patent/US7447094B2/en
Priority claimed from US11/323,569 external-priority patent/US7733704B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Priority to EP06848784A priority Critical patent/EP1966803A2/en
Publication of WO2007076503A2 publication Critical patent/WO2007076503A2/en
Publication of WO2007076503A3 publication Critical patent/WO2007076503A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Read Only Memory (AREA)

Abstract

Power-saving techniques are employed in sensing a group of non-volatile memory cells in parallel. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will still be able to be detected in a subsequent pass.
PCT/US2006/062605 2005-12-29 2006-12-26 Non-volatile memory operated on. the basis of a two-step bit-line precharge operation and a two-pass sensing operation Ceased WO2007076503A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06848784A EP1966803A2 (en) 2005-12-29 2006-12-26 Non-volatile memory operated on the basis of a two-step bit-line precharge operation and a two-pass sensing operation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/322,427 US7447094B2 (en) 2005-12-29 2005-12-29 Method for power-saving multi-pass sensing in non-volatile memory
US11/323,569 US7733704B2 (en) 2005-12-29 2005-12-29 Non-volatile memory with power-saving multi-pass sensing
US11/322,427 2005-12-29
US11/323,569 2005-12-29

Publications (2)

Publication Number Publication Date
WO2007076503A2 WO2007076503A2 (en) 2007-07-05
WO2007076503A3 true WO2007076503A3 (en) 2007-11-15

Family

ID=38191878

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/062605 Ceased WO2007076503A2 (en) 2005-12-29 2006-12-26 Non-volatile memory operated on. the basis of a two-step bit-line precharge operation and a two-pass sensing operation

Country Status (3)

Country Link
EP (1) EP1966803A2 (en)
TW (1) TWI315878B (en)
WO (1) WO2007076503A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI425516B (en) * 2009-05-08 2014-02-01 Macronix Int Co Ltd Memory device and method of operating same
US8659963B2 (en) 2012-01-05 2014-02-25 International Business Machines Corporation Enhanced power savings for memory arrays

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56143592A (en) * 1980-04-09 1981-11-09 Toshiba Corp Semiconductor memory device
US4852064A (en) * 1987-06-27 1989-07-25 Samsung Electronics Co., Ltd. Precharge circuit for use in a semiconductor memory device
US6144600A (en) * 1998-03-16 2000-11-07 Nec Corporation Semiconductor memory device having first and second pre-charging circuits
WO2004029984A2 (en) * 2002-09-24 2004-04-08 Sandisk Corporation Non-volatile memory and its sensing method
US20050057966A1 (en) * 2003-09-16 2005-03-17 Micron Technology, Inc. Boosted substrate/tub programming for flash memories
US20050078524A1 (en) * 2003-10-09 2005-04-14 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US20050162951A1 (en) * 2004-01-23 2005-07-28 Dudeck Dennis E. Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56143592A (en) * 1980-04-09 1981-11-09 Toshiba Corp Semiconductor memory device
US4852064A (en) * 1987-06-27 1989-07-25 Samsung Electronics Co., Ltd. Precharge circuit for use in a semiconductor memory device
US6144600A (en) * 1998-03-16 2000-11-07 Nec Corporation Semiconductor memory device having first and second pre-charging circuits
WO2004029984A2 (en) * 2002-09-24 2004-04-08 Sandisk Corporation Non-volatile memory and its sensing method
US20050057966A1 (en) * 2003-09-16 2005-03-17 Micron Technology, Inc. Boosted substrate/tub programming for flash memories
US20050078524A1 (en) * 2003-10-09 2005-04-14 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US20050162951A1 (en) * 2004-01-23 2005-07-28 Dudeck Dennis E. Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase

Also Published As

Publication number Publication date
TW200741736A (en) 2007-11-01
TWI315878B (en) 2009-10-11
EP1966803A2 (en) 2008-09-10
WO2007076503A2 (en) 2007-07-05

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