WO2007114705A1 - Phase locked oscillator - Google Patents

Phase locked oscillator Download PDF

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Publication number
WO2007114705A1
WO2007114705A1 PCT/NO2007/000066 NO2007000066W WO2007114705A1 WO 2007114705 A1 WO2007114705 A1 WO 2007114705A1 NO 2007000066 W NO2007000066 W NO 2007000066W WO 2007114705 A1 WO2007114705 A1 WO 2007114705A1
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WIPO (PCT)
Prior art keywords
frequency
oscillator
multiplier
phase detector
signal
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Ceased
Application number
PCT/NO2007/000066
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French (fr)
Inventor
Ben Jarle Imenes
Stig Rooth
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Norspace AS
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Norspace AS
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Publication date
Application filed by Norspace AS filed Critical Norspace AS
Priority to US12/295,021 priority Critical patent/US7876164B2/en
Priority to AT07747553T priority patent/ATE463880T1/en
Priority to DE602007005791T priority patent/DE602007005791D1/en
Priority to EP07747553A priority patent/EP2011229B1/en
Publication of WO2007114705A1 publication Critical patent/WO2007114705A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/20—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path

Definitions

  • the present invention is in general related to oscillator circuits for use as signal sources in communication and radar applications.
  • the present invention is related to a phase locked oscillator intended for, but not restricted to, use in frequency converters devices, such as frequency up- converters or frequency down-converters.
  • Voltage controlled oscillators are phase locked for applications in VHF, UHF and microwave frequency ranges. Typical applications of such phase locked oscillators are abundant in the field of communication systems technology and radar applications as stable, low-phase noise signal sources.
  • Digital phase locking can, for example, be achieved by using a frequency divider to divide a high frequency of a VCO to a lower frequency of a crystal reference. Such a technique is useful at low frequencies down to about IMHz, but can also be used at higher frequencies up to and beyond 3GHz. A limitation of these devices is their phase noise characteristics.
  • An example of a phase locked loop realized in digital form has been described, for example in United States Patent no. 5,061,904 to Mantopoulos et al.
  • Analog phase locking of oscillators can be achieved using a sampling phase detector (SPD), see for example "TJieory and Application of Sampling Phase Detector, Application Note APN5001", from Skyworks Solutions, Inc., dated July 21 , 2005, where it is described how the SPD can be used for phase locking a dielectric resonator Oscillator (DRO).
  • SPD sampling phase detector
  • DRO dielectric resonator Oscillator
  • an analog phase locked oscillator comprising a sampling phase detector, a loop filter, a voltage controlled oscillator, a frequency multiplier, a feedback loop, where the feedback loop connects the output of said oscillator with the input of said phase detector through said frequency multiplier.
  • the sampling phase detector is adapted to perform a discrete phase comparison between a reference frequency and the multiplied feedback signal
  • the voltage controlled oscillator is adapted to give out a constant frequency at a multiply of the reference frequency divided with the multiplication factor of the multiplier.
  • the voltage controlled oscillator comprises an acoustic wave component, for example a surface acoustic wave component.
  • the surface acoustic wave based oscillator is adapted for operation in the frequency range of 100MHz - 2,5GHz.
  • the signal frequency multiplier comprises a non-linear electric circuit module.
  • the signal frequency multiplier device comprises a transistor based multiplier circuit.
  • the signal frequency multiplier device comprises a diode based multiplier circuit.
  • the feedback loop is impedance matched to a generally 50Ohm system at each end.
  • phase locked oscillator based on a sampling phase detector (SPD) according to the invention will now be described in more detail with reference to the two accompanying drawings:
  • Fig. 1 is a schematic diagram illustrating the phase locked oscillator based on a sampling phase detector according to the invention.
  • Fig. 2 is an extended schematic diagram illustrating the phase locked oscillator based on a sampling phase detector with a discrete phase comparison function according to the invention.
  • FIG. 1 there is shown an example embodiment of a phase locked oscillator based on a sampling phase detector according to the invention.
  • a reference frequency signal 1, denoted /R EF is provided at a first input of a type of harmonic mixer known as a sampling phase detector (SPD) 2.
  • SPD sampling phase detector
  • the output of the sampling phase detector 2 is filtered in a low pass loop filter 3 in order to remove high frequency harmonics above a frequency given by the characteristics of the filter 3.
  • VCO voltage controlled oscillator
  • the voltage controlled oscillator 4 is a device with high Q-factor (quality factor) in order to avoid the possibility of locking on several frequencies within the resonance of the VCO 4.
  • an ordinary analogue phase locked oscillator a phase detector continuously compares the phase of the reference signal with the phase of the feedback signal.
  • an ordinary phase detector is replaced with a non-continuously phase detector that samples the phase of the feedback signal from the VCO 4.
  • the period of the sample pulse is the same as the period of the reference signal 1, and the sample pulse is sampling directly on the RF- signal from the VCO 4.
  • the SPD compares the phase of the two signals which are different in frequency.
  • a surface acoustic wave (SAW) device is particularly attractive as the resonating element in the voltage controlled oscillator 4 due to its small size and the high Q-factor.
  • SAW surface acoustic wave
  • other types of voltage controlled oscillators 4 could also be used, for example oscillators based on dielectric resonators. Dielectric ceramic resonators are more attractive at higher frequencies, above the possible operating ranges of SAW-based VCO devices.
  • a first output of the SAW VCO 4 is applied to the multiplier 7 in the feedback loop 9 providing a second input signal to the sampling phase detector (SPD) 2, thereby closing the phase locked loop, while a second output of the SAW VCO 4 is the signal output 8 of the phase locked oscillator according to the invention.
  • SPD sampling phase detector
  • a characteristic feature of the present invention is that a frequency multiplier 7 is inserted in the feedback loop 9 for multiplying the frequency of the signal from the SAW VCO 4 by a factor M.
  • the frequency multiplier 7 can be a frequency doubling device, a tripling device or a higher order multiplication device.
  • a frequency doubler device is described in the publication "Switching Diode Frequency Doublers" by Charles Wenzel, at the web-address http://www.wenzel.com/pdffiles/diodedbl.pdf , printed on March 26, 2006.
  • a person skilled in the art will realize that such a frequency doubler can be realized in a number of similar, but slightly different ways, and still be useful in this invention.
  • the multiplier 7 in the feedback loop 9 makes it possible to lock on to the sub harmonic of the reference frequency 1. With this feature the phase locked oscillator can be locked to a frequency grid where the frequency points have a distance smaller than the reference frequency 1. This enables the SPD based phase locked oscillator to have a wider range of use.
  • the SPLO will not lock to the frequency closest to the free-running frequency of the VCO 4, but rather to a multiple of the free running frequency of the VCO 4, the multiple frequency being defined by the frequency multiplier 7 of the feedback loop 9.
  • the SAW VCO resonator frequency can be selected at the half of this frequency, by setting the multiplier M equal to 2 in the feedback loop 9. It should be noted that the choice of the H 11 ' harmonic is somewhat arbitrary, any available comparing frequency in the SPD 2 could in principle be used. As an example H could be chosen to be 233.
  • the signal frequency at the output 8 of the device, four, is thus given by the following equation:
  • any non-linear circuit device could be used to obtain the signal multiplication effect in the signal multiplications device 7.
  • one preferred device is a transistor based multiplier circuit, otherwise known to a person skilled in the art.
  • a diode based multiplier circuit could also be used.
  • Fig. 2 is an extended schematic illustration of the phase locked oscillator based on a sampling phase detector (SPD) 2.
  • the SPD 2 according to the present invention performs a discrete phase comparison, and this is clarified by introducing the generation of the sample pulse in the illustration of the SPD 2 component in this figure.
  • the selected harmonic of the reference signal 1 generated in the SPD 2 is given by the following equation:
  • the oscillator circuit of the present invention can either be realized as a combined hybrid/discrete circuit, or it can be a fully hybridized circuit.
  • the SPD 2 will be a hybrid device.
  • the VCO 4 could be a hybrid component.
  • the SAW component is normally mounted in a separate hermetic package.
  • the circuit is typically in addition provided with a regulated power supply (not illustrated) for providing power to all the components.
  • a power supply device could also be realized as a hybrid component.
  • the actual circuit is typically a design based on discrete components, however, it can be envisaged that parts of the circuit could be designed as a combined discrete/hybrid circuit or a fully hybridized circuit.
  • the present invention provides an phase locked oscillator device where an input of a relatively low frequency, perhaps at about 1 OMHz, can be used to provide a wider choice of output frequencies 8 at frequencies larger than the input frequency, with a higher resolution than the input reference frequency 1.
  • This wider choice of output frequencies 8 is a result of using a multiplier 7 in the architecture of a phase locked oscillator based on a SPD 2.
  • An input reference of 10MHz is often a readily available clocking signal in many applications, and it will not be required to provide a separate clock, if the 10MHz clock signal can be utilized. In some embodiments a separate clock may be necessary to provide the desired input reference signal frequency I 5 however, an additional clock unit adds to the cost of the circuit.
  • a typical application of the oscillator circuit of the present invention is in frequency up- converter devices and frequency down-converter devices for shifting communication or radar signals from frequency bands that are suitable for electronic processing and for shifting signals to/from frequency bands to be used during transmission between different communication system units.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

There is provided an analog phase locked oscillator comprising a sampling phase detector (2), a loop filter (3), a voltage controlled oscillator (4), a frequency multiplier (7) and a feedback loop (9) where the feedback loop (9) connects the output of said oscillator (4) with the input of said phase detector (2) through said frequency multiplier (7). The sampling phase detector (2) is adapted to perform a discrete phase comparison between a reference frequency (1) and the multiplied feedback signal. The voltage controlled oscillator (4) is adapted to give out a constant frequency at a multiply of the reference frequency (1) divided with the multiplication factor of the multiplier (7).

Description

PHASE LOCKED OSCILLATOR
TECHNICAL FIELD OF THE INVENTION
The present invention is in general related to oscillator circuits for use as signal sources in communication and radar applications.
More particularly, the present invention is related to a phase locked oscillator intended for, but not restricted to, use in frequency converters devices, such as frequency up- converters or frequency down-converters.
BACKGROUND TO THE INVENTION Voltage controlled oscillators (VCOs) are phase locked for applications in VHF, UHF and microwave frequency ranges. Typical applications of such phase locked oscillators are abundant in the field of communication systems technology and radar applications as stable, low-phase noise signal sources.
Both digital and analog phase lock techniques are known. Digital phase locking can, for example, be achieved by using a frequency divider to divide a high frequency of a VCO to a lower frequency of a crystal reference. Such a technique is useful at low frequencies down to about IMHz, but can also be used at higher frequencies up to and beyond 3GHz. A limitation of these devices is their phase noise characteristics. An example of a phase locked loop realized in digital form has been described, for example in United States Patent no. 5,061,904 to Mantopoulos et al.
Analog phase locking of oscillators can be achieved using a sampling phase detector (SPD), see for example "TJieory and Application of Sampling Phase Detector, Application Note APN5001", from Skyworks Solutions, Inc., dated July 21 , 2005, where it is described how the SPD can be used for phase locking a dielectric resonator Oscillator (DRO). United States patent no. US 6,753,704 Bl to Desgrez et al. describes an example of an analog sampling phase detector.
Such techniques are generally attractive because of the low phase noise levels that are achievable in such circuits. A limitation of the SPLO (Sampling Phase Locked Oscillator) solution has been the limitations in frequency selection as only integer times the reference frequency could be generated.
Hence it is an objective of the present invention to provide a phase locked oscillator with a wider choice available in the choice of output frequency than has previously been possible.
SHORT SUMMARY OF THE INVENTION In order to achieve the objectives set forth above there is thus provided an analog phase locked oscillator comprising a sampling phase detector, a loop filter, a voltage controlled oscillator, a frequency multiplier, a feedback loop, where the feedback loop connects the output of said oscillator with the input of said phase detector through said frequency multiplier. The sampling phase detector is adapted to perform a discrete phase comparison between a reference frequency and the multiplied feedback signal, and the voltage controlled oscillator is adapted to give out a constant frequency at a multiply of the reference frequency divided with the multiplication factor of the multiplier.
In a preferred embodiment of the phase locked oscillator according to the invention the voltage controlled oscillator comprises an acoustic wave component, for example a surface acoustic wave component.
In a further preferred embodiment of the phase locked oscillator according to the invention the surface acoustic wave based oscillator is adapted for operation in the frequency range of 100MHz - 2,5GHz.
In a still preferred embodiment of the phase locked oscillator according to the invention the signal frequency multiplier comprises a non-linear electric circuit module. In a yet still preferred embodiment of the phase locked oscillator according to the invention the signal frequency multiplier device comprises a transistor based multiplier circuit.
In a further still preferred embodiment of the phase locked oscillator according to the invention the signal frequency multiplier device comprises a diode based multiplier circuit.
In a yet a preferred embodiment of the phase locked oscillator according to the invention the feedback loop is impedance matched to a generally 50Ohm system at each end.
SHORT DESCRIPTION OF THE DRAWINGS
The phase locked oscillator based on a sampling phase detector (SPD) according to the invention will now be described in more detail with reference to the two accompanying drawings:
Fig. 1 is a schematic diagram illustrating the phase locked oscillator based on a sampling phase detector according to the invention.
Fig. 2 is an extended schematic diagram illustrating the phase locked oscillator based on a sampling phase detector with a discrete phase comparison function according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to Fig. 1 there is shown an example embodiment of a phase locked oscillator based on a sampling phase detector according to the invention. A reference frequency signal 1, denoted /REF, is provided at a first input of a type of harmonic mixer known as a sampling phase detector (SPD) 2. The output of the sampling phase detector 2 is filtered in a low pass loop filter 3 in order to remove high frequency harmonics above a frequency given by the characteristics of the filter 3. After filtering the signal is applied to a voltage controlled oscillator (VCO) 4. Preferably the voltage controlled oscillator 4 is a device with high Q-factor (quality factor) in order to avoid the possibility of locking on several frequencies within the resonance of the VCO 4.
In an ordinary analogue phase locked oscillator a phase detector continuously compares the phase of the reference signal with the phase of the feedback signal. In a SPD based phased locked oscillator according to the present invention, an ordinary phase detector is replaced with a non-continuously phase detector that samples the phase of the feedback signal from the VCO 4. The period of the sample pulse is the same as the period of the reference signal 1, and the sample pulse is sampling directly on the RF- signal from the VCO 4. Thus the SPD compares the phase of the two signals which are different in frequency.
In the frequency range of 100MHz — 2, 5GHz a surface acoustic wave (SAW) device is particularly attractive as the resonating element in the voltage controlled oscillator 4 due to its small size and the high Q-factor. However, other types of voltage controlled oscillators 4 could also be used, for example oscillators based on dielectric resonators. Dielectric ceramic resonators are more attractive at higher frequencies, above the possible operating ranges of SAW-based VCO devices.
A first output of the SAW VCO 4 is applied to the multiplier 7 in the feedback loop 9 providing a second input signal to the sampling phase detector (SPD) 2, thereby closing the phase locked loop, while a second output of the SAW VCO 4 is the signal output 8 of the phase locked oscillator according to the invention. An attractive feature of this circuit is that the excess noise is very low, close to the theoretical minimum of the multiplied reference 1. Thus the phase noise performance is clearly a benefit compared to an ordinary phase locked oscillator.
A characteristic feature of the present invention is that a frequency multiplier 7 is inserted in the feedback loop 9 for multiplying the frequency of the signal from the SAW VCO 4 by a factor M. The frequency multiplier 7 can be a frequency doubling device, a tripling device or a higher order multiplication device. One example of a frequency doubler device is described in the publication "Switching Diode Frequency Doublers" by Charles Wenzel, at the web-address http://www.wenzel.com/pdffiles/diodedbl.pdf , printed on March 26, 2006. A person skilled in the art will realize that such a frequency doubler can be realized in a number of similar, but slightly different ways, and still be useful in this invention. The multiplier 7 in the feedback loop 9 makes it possible to lock on to the sub harmonic of the reference frequency 1. With this feature the phase locked oscillator can be locked to a frequency grid where the frequency points have a distance smaller than the reference frequency 1. This enables the SPD based phase locked oscillator to have a wider range of use.
As opposed to a traditional sampling phase-locked oscillator (SPLO) where the VCO 4 is locked on the harmonic frequency of the reference frequency 1 which is closest to the free-running frequency of the VCO 4, in the circuit according to the present invention the SPLO will not lock to the frequency closest to the free-running frequency of the VCO 4, but rather to a multiple of the free running frequency of the VCO 4, the multiple frequency being defined by the frequency multiplier 7 of the feedback loop 9.
In this way a main limitation of the prior art known to these inventors is overcome in that the introduction of a multiply-by-M in the loop enables a finer resolution of the selected output frequency 8. Multiplication by 2, 3, 4 or higher can be achieved, for example by arranging several frequency doublers or triplers in cascade.
If for example, the H11' harmonic is selected as comparing frequency in the sampling phase detector 2, the SAW VCO resonator frequency can be selected at the half of this frequency, by setting the multiplier M equal to 2 in the feedback loop 9. It should be noted that the choice of the H11' harmonic is somewhat arbitrary, any available comparing frequency in the SPD 2 could in principle be used. As an example H could be chosen to be 233. The signal frequency at the output 8 of the device, four, is thus given by the following equation:
10UT = (H - UF I M) (1) , where H is the order of harmonic of the selected comparing frequency, /REF is the reference frequency 1 and M is the multiplication factor in the feedback multiplier 7.
As a result of this method, a resolution of '/REF/2 can be obtained.
Basically, any non-linear circuit device could be used to obtain the signal multiplication effect in the signal multiplications device 7. However, one preferred device is a transistor based multiplier circuit, otherwise known to a person skilled in the art. As an alternative, a diode based multiplier circuit could also be used.
Fig. 2 is an extended schematic illustration of the phase locked oscillator based on a sampling phase detector (SPD) 2. The SPD 2 according to the present invention performs a discrete phase comparison, and this is clarified by introducing the generation of the sample pulse in the illustration of the SPD 2 component in this figure. The selected harmonic of the reference signal 1 generated in the SPD 2 is given by the following equation:
H = {M - fOUT)lfmF (2)
, where Mis the multiplication factor of the feedback multiplier 7, four is the output frequency 8 andfiusF is the reference frequency 1.
The oscillator circuit of the present invention can either be realized as a combined hybrid/discrete circuit, or it can be a fully hybridized circuit. Typically, at least the SPD 2 will be a hybrid device. Further, the VCO 4 could be a hybrid component. The SAW component is normally mounted in a separate hermetic package. The circuit is typically in addition provided with a regulated power supply (not illustrated) for providing power to all the components. A power supply device could also be realized as a hybrid component. The actual circuit is typically a design based on discrete components, however, it can be envisaged that parts of the circuit could be designed as a combined discrete/hybrid circuit or a fully hybridized circuit.
In conclusion, the present invention provides an phase locked oscillator device where an input of a relatively low frequency, perhaps at about 1 OMHz, can be used to provide a wider choice of output frequencies 8 at frequencies larger than the input frequency, with a higher resolution than the input reference frequency 1. This wider choice of output frequencies 8 is a result of using a multiplier 7 in the architecture of a phase locked oscillator based on a SPD 2. An input reference of 10MHz is often a readily available clocking signal in many applications, and it will not be required to provide a separate clock, if the 10MHz clock signal can be utilized. In some embodiments a separate clock may be necessary to provide the desired input reference signal frequency I5 however, an additional clock unit adds to the cost of the circuit.
A typical application of the oscillator circuit of the present invention is in frequency up- converter devices and frequency down-converter devices for shifting communication or radar signals from frequency bands that are suitable for electronic processing and for shifting signals to/from frequency bands to be used during transmission between different communication system units.

Claims

C l a i m s
1. An analog phase locked oscillator comprising
- a sampling phase detector (2), - a loop filter (3),
- a voltage controlled oscillator (4),
- a frequency multiplier (7),
- a feedback loop (9) wherein the feedback loop (9) connects the output of said oscillator (4) with the input of said phase detector (2) through the frequency multiplier (7), the sampling phase detector (2) is adapted to perform a discrete phase comparison between a reference frequency (1) and the multiplied feedback signal, the voltage controlled oscillator (4) is adapted to give out a constant frequency at a multiply of the reference frequency (1) divided with the multiplication factor of the multiplier (7).
2. Oscillator according to claim 1, wherein the voltage controlled oscillator (4) comprises an acoustic wave component, for example a surface acoustic wave device.
3. Oscillator according to claim 2, wherein the surface acoustic wave based oscillator is adapted for operation in the frequency range of 100MHz - 2, 5GHz.
4. Oscillator according to claim I5 wherein the signal frequency multiplier (7) comprises a non-linear electric circuit module.
5. Oscillator according to claim 4, wherein said signal frequency multiplier (7) comprises a transistor based multiplier circuit.
6. Oscillator according to claim 4, wherein the signal frequency multiplier (7) comprises a diode based multiplier circuit.
7. Oscillator according to claim 1, wherein the feedback loop (9) is impedance matched to a generally 50Ohm system at each end.
PCT/NO2007/000066 2006-03-30 2007-02-21 Phase locked oscillator Ceased WO2007114705A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US12/295,021 US7876164B2 (en) 2006-03-30 2007-02-21 Phase locked oscillator
AT07747553T ATE463880T1 (en) 2006-03-30 2007-02-21 PHASE LOCKED OSCILLATOR
DE602007005791T DE602007005791D1 (en) 2006-03-30 2007-02-21 LAMP-LOCKED OSCILLATOR
EP07747553A EP2011229B1 (en) 2006-03-30 2007-02-21 Phase locked oscillator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NO20061439 2006-03-30
NO20061439A NO324467B1 (en) 2006-03-30 2006-03-30 Phase load oscillator

Publications (1)

Publication Number Publication Date
WO2007114705A1 true WO2007114705A1 (en) 2007-10-11

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US (1) US7876164B2 (en)
EP (1) EP2011229B1 (en)
AT (1) ATE463880T1 (en)
DE (1) DE602007005791D1 (en)
NO (1) NO324467B1 (en)
WO (1) WO2007114705A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101198319B1 (en) 2011-04-21 2012-12-06 (주)젠믹스텍 Phase Locked Dielectric Resonator Oscillator
WO2017209986A1 (en) * 2016-06-01 2017-12-07 Xilinx, Inc. Phase-locked loop having a sampling phase detector
US20220329248A1 (en) * 2022-06-16 2022-10-13 Intel Corporation Apparatus, system, and method of a digitally-controlled frequency multiplier

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0701812D0 (en) * 2007-01-31 2007-03-14 Qinetiq Ltd Antenna system and radar system incorporating the same
US8040190B2 (en) * 2008-05-01 2011-10-18 Csem Centre Suisse D'electronique Et De Microtechnique Sa-Recherche Et Developpement Phase-locked loop
US7940130B2 (en) * 2009-05-22 2011-05-10 Agilent Technologies, Inc. Frequency generator and method of frequency generation with multiple sampling phase detectors
CN102315927A (en) * 2011-06-30 2012-01-11 大唐移动通信设备有限公司 Clock synchronization device and method
CN107925559B (en) 2016-03-11 2020-06-02 华为技术有限公司 Apparatus and method for supporting multi-clock domain clock delivery
KR101959789B1 (en) * 2017-10-20 2019-03-20 국방과학연구소 Frequency synthesizer
FR3086131B1 (en) * 2018-09-14 2021-06-04 Commissariat Energie Atomique LOCKING ADJUSTMENT OF AN INJECTION LOCKING FREQUENCY MULTIPLIER
CN112234986B (en) * 2020-09-04 2021-07-13 上海鸿晔电子科技股份有限公司 Signal source

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4720688A (en) * 1985-05-15 1988-01-19 Matsushita Electric Industrial Co., Ltd. Frequency synthesizer
WO2000077936A1 (en) * 1999-06-11 2000-12-21 Telefonaktiebolaget Lm Ericsson (Publ) An arrangement in an electronics system
US20020145475A1 (en) * 2001-04-10 2002-10-10 Apa Wireless Technologies Dual conversion RF synthesizer utilizing improved push-push VCO design

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2044025B (en) * 1978-11-14 1982-12-22 Rohde & Schwarz Standard frequency generator
US5055800A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Fractional n/m synthesis
US5345193A (en) * 1993-07-28 1994-09-06 Wiltron Company Phase locked loop with loop gain stabilization circuit
US5748144A (en) * 1996-01-26 1998-05-05 Trimble Navigation Limited GPS timing receiver using oversampling
EP0903860A1 (en) * 1997-09-17 1999-03-24 Matsushita Electric Industrial Co., Ltd. PLL frequency synthesizer
US20070104292A1 (en) * 2005-11-04 2007-05-10 Peter Gregorius Timing recovery phase locked loop

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4720688A (en) * 1985-05-15 1988-01-19 Matsushita Electric Industrial Co., Ltd. Frequency synthesizer
WO2000077936A1 (en) * 1999-06-11 2000-12-21 Telefonaktiebolaget Lm Ericsson (Publ) An arrangement in an electronics system
US20020145475A1 (en) * 2001-04-10 2002-10-10 Apa Wireless Technologies Dual conversion RF synthesizer utilizing improved push-push VCO design

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LEFEVRE P ET AL: "A FULL GAAS MMIC PHASE-LOCKED OSCILLATOR USING SAMPLING PHASE DETECTOR AND A SAMPLING FREQUENCY DETECTOR", 2000 EUROPEAN CONFERENCE ON WIRELESS TECHNOLOGY CONFERENCE PROCEEDINGS. ECWT 2000. PARIS, OCT. 5 - 6, 2000, EUROPEAN CONFERENCE ON WIRELESS TECHNOLOGY. ECWT, LONDON : CMP, GB, 5 October 2000 (2000-10-05), pages 17 - 20, XP001060790, ISBN: 0-86213-217-7 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101198319B1 (en) 2011-04-21 2012-12-06 (주)젠믹스텍 Phase Locked Dielectric Resonator Oscillator
WO2017209986A1 (en) * 2016-06-01 2017-12-07 Xilinx, Inc. Phase-locked loop having a sampling phase detector
US20220329248A1 (en) * 2022-06-16 2022-10-13 Intel Corporation Apparatus, system, and method of a digitally-controlled frequency multiplier
US12562745B2 (en) * 2022-06-16 2026-02-24 Intel Corporation Apparatus, system, and method of a digitally-controlled frequency multiplier

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US7876164B2 (en) 2011-01-25
EP2011229A1 (en) 2009-01-07
ATE463880T1 (en) 2010-04-15
US20090115534A1 (en) 2009-05-07
EP2011229B1 (en) 2010-04-07
NO324467B1 (en) 2007-10-22

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