WO2007118401A1 - Method and system of syntonic circuit modulation controlling - Google Patents

Method and system of syntonic circuit modulation controlling Download PDF

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Publication number
WO2007118401A1
WO2007118401A1 PCT/CN2007/000509 CN2007000509W WO2007118401A1 WO 2007118401 A1 WO2007118401 A1 WO 2007118401A1 CN 2007000509 W CN2007000509 W CN 2007000509W WO 2007118401 A1 WO2007118401 A1 WO 2007118401A1
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WO
WIPO (PCT)
Prior art keywords
voltage
modulation control
vloop
pulse width
width modulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2007/000509
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English (en)
French (fr)
Inventor
Chunhui Zhu
Haizhou Zhao
Zhiyu Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vertiv Tech Co Ltd
Vertiv Sweden AB
Vertiv Energy Systems Inc
Original Assignee
Emerson Network Power Co Ltd
Emerson Network Power Energy Systems AB
Emerson Network Power Energy Systems Noth America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Emerson Network Power Co Ltd, Emerson Network Power Energy Systems AB, Emerson Network Power Energy Systems Noth America Inc filed Critical Emerson Network Power Co Ltd
Priority to US12/297,044 priority Critical patent/US8284570B2/en
Priority to EP07710934A priority patent/EP2009758A4/en
Publication of WO2007118401A1 publication Critical patent/WO2007118401A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to electrical communication technologies, and in particular, to a resonant circuit modulation control method and system. Background technique
  • the conventional converter generally uses a frequency modulation control (PFM) to obtain a desired output voltage by adjusting the operating frequency of the switching transistor in the resonant circuit.
  • PFM frequency modulation control
  • the series resonant DC/DC converter adopts a resonant conversion technique. Since the resonant element operates in a sinusoidal resonant state, the voltage on the switching transistor naturally crosses zero, and zero voltage turn-on can be realized, and the output rectifier diode can be eliminated. Reverse recovery, reducing power loss and improving efficiency.
  • This topology usually uses FM control to stabilize the output voltage by changing the operating frequency of the switching transistor.
  • Figure 1 shows the basic form of a full-bridge series resonant DC/DC converter. The relationship between the output voltage gain M and the operating frequency is -
  • Lr is the resonant inductance value
  • f is the operating frequency of the switching transistor
  • Cr is the resonant capacitance value
  • Po is the output power
  • a major difficulty with series resonant converters is that the output voltage is difficult to stabilize under light load and no load conditions.
  • the output voltage of the series resonant topology decreases as the switching frequency increases.
  • the output voltage is stabilized by adjusting the operating frequency.
  • the operating frequency is raised to a certain value, the operating frequency adjusts the output voltage greatly, even Will increase the output voltage.
  • the operating frequency needs to rise very high, but the operating frequency is too high and Too wide adjustment range will increase the difficulty of magnetic component design, and the higher the operating frequency, the greater the circuit loss.
  • some designs use an output with a fixed load. This method stabilizes the output voltage under light load and no-load conditions, but this increases the no-load loss of the power supply and reduces the power supply efficiency.
  • a half-bridge series resonant circuit and a full-bridge series resonant circuit can cause similar problems.
  • the object of the present invention is to provide a low-cost, high-efficiency resonant circuit modulation control method and system, which can solve the problem that the prior art variable frequency control causes the operating frequency to be too high and the adjustment range to be too wide, thereby increasing the difficulty of designing the magnetic component. , and the problem of reducing power efficiency.
  • the resonant circuit modulation control system used in the present invention is characterized in that: the control chip of the resonant circuit is connected to the related control device, and the control device provides voltage matching and resistance control to the control chip, and the control device modulates according to the input voltage.
  • the control chip provides control parameters, and the control chip modulates the resonant circuit accordingly.
  • the control chip is a phase-shifted pulse width modulation control chip, and the PWM generator and the oscillator in the phase-shifted pulse width modulation control chip are respectively connected to a voltage matching module and a resistance control module in the control device, and the voltage is
  • the matching module and the resistance control module provide control parameters to the phase shift pulse width modulation control chip according to the input voltage, and the phase shift pulse width modulation control chip modulates the resonance circuit accordingly.
  • the voltage matching module and the resistance control module both use the loop voltage V op as an input voltage; the voltage matching module uses a phase shift voltage interval corresponding to the loop voltage Vloop and a PWM generator of the phase shift pulse width modulation control chip.
  • the voltage ranges for phase shifting are matched;
  • the resistor control module is connected between the loop voltage Vloop and the oscillator of the phase shift pulse width modulation control chip, so that the external equivalent resistance of the oscillator is adjusted correspondingly with the change of the loop voltage Vloop.
  • the voltage matching module includes an operational amplifier U701, a first voltage dividing submodule, and a current limiting circuit, wherein a resistor R714 is connected between the opposite end of the operational amplifier U701 and the ground, and a resistor R711 is connected to the output end. ;
  • the same end of the operational amplifier U701 is connected to the voltage dividing end of the first voltage dividing submodule; a current limiting circuit is connected between the output end of the operational amplifier U701 and the PWM generator of the phase shifting pulse width modulation control chip.
  • the resistance control module includes a second voltage dividing submodule, and a resistor R703 is connected between the voltage dividing end of the second voltage dividing submodule and the oscillator of the phase shifting pulse width modulation control chip.
  • the control chip is a pulse width modulation control chip, and the COMP end and the RT end of the pulse width modulation control chip are respectively connected to a voltage matching module and a resistance control module in the control device, and the voltage matching module and the resistance control module According to the input voltage, the pulse width modulation control chip is provided with corresponding control parameters, and the pulse width modulation control chip modulates the resonance circuit accordingly.
  • the voltage matching module and the resistance control module both use the loop voltage Vloop as an input voltage; the voltage matching module adjusts the widened voltage interval corresponding to the loop voltage Vloop and the voltage widened by the pulse width modulation control chip COMP end.
  • the range matches;
  • the resistor control module is connected between the loop voltage Vloop and the RT end of the pulse width modulation control chip, so that the external equivalent resistance of the RT terminal is adjusted correspondingly with the change of the loop voltage Vloop.
  • the voltage matching module includes an operational amplifier U701, a first voltage dividing submodule, and a current limiting circuit, wherein a resistor R714 is connected between the opposite end of the operational amplifier U701 and the ground, and a resistor R711 is connected to the output end. ;
  • the same end of the operational amplifier U701 is connected to the voltage dividing end of the first voltage dividing submodule;
  • a current limiting circuit is connected between the output end of the operational amplifier U701 and the COMP end of the pulse width modulation control chip.
  • the resistance control module includes a second voltage dividing submodule, and a resistor R703 is connected between the voltage dividing end of the second voltage dividing submodule and the oscillator of the phase shifting pulse width modulation control chip.
  • the first voltage dividing submodule includes series resistors R712, 713 and is connected between the loop voltage Vloop and ground.
  • the second voltage dividing submodule comprises series resistors R701, R702 and is connected between the loop voltage Vloop and the ground.
  • the resistance control module further includes a comparison voltage sub-module, the comparison voltage sub-module generates a reference level Vref, and the reference level Vref, the loop voltage Vloop and the input end of the second voltage dividing sub-module 31
  • the first diode D702 and the second diode D701 are respectively connected, and the cathodes of the first diode D702 and the second diode D701 are connected to the second voltage dividing submodule.
  • the resonant circuit modulation control method is characterized in that: the phase shift pulse width modulation control chip is used, and the voltage matching module and the resistance control module realize a frequency modulation, a widening and a mixed control mode of the resonance circuit. It takes the following steps:
  • the loop voltage Vloop when the loop voltage Vloop operates in the first interval, the loop voltage Vloop causes the resistance control module to act on the phase shifting pulse width modulation control chip to generate the frequency modulation control; meanwhile, the loop voltage Vloop causes the voltage matching module to act on the phase shifting pulse
  • the wide modulation control chip generates a widening control
  • the loop voltage Vloop when the loop voltage Vloop operates in the second interval, the loop voltage Vloop causes the voltage matching module to act on the phase shift pulse width modulation control chip to generate the maximum duty ratio Dmax, and the loop voltage Vloop causes the resistance control module to act on the phase shift
  • the pulse width modulation control chip generates frequency modulation control. It takes the following steps:
  • the resistance control module When the loop voltage Vloop operates in the first interval, the resistance control module generates a constant equivalent resistance to the phase-shifted pulse width modulation control chip and outputs a pulse frequency maximum value fmax, and the loop voltage Vloop causes the voltage matching module to act on the shift
  • the phase pulse width modulation control chip generates a width adjustment control
  • the loop voltage Vloop when the loop voltage Vloop operates in the second interval, the loop voltage Vloop causes the resistance control module to act on the phase shifting pulse width modulation control chip to generate the frequency modulation control; meanwhile, the loop voltage Vloop causes the voltage matching module to act on the phase shifting pulse
  • the wide modulation control chip generates a widening control
  • the loop voltage Vloop when the loop voltage Vloop operates in the third interval, the loop voltage Vloop causes the voltage matching module to act on the phase shift pulse width modulation control chip to generate the maximum duty ratio Dmax, and the loop voltage Vloop causes the resistance control module to act on the phase shift
  • the pulse width modulation control chip generates frequency modulation control.
  • the maximum duty ratio Dmax is 50%.
  • the first interval is a phase shift voltage interval of the loop voltage Vloop when the resonant circuit is unloaded or lightly loaded.
  • the third interval is a frequency modulation voltage interval of the loop voltage Vloop when the resonant circuit is heavily loaded.
  • the resonant circuit modulation control method is characterized in that: a pulse width modulation control chip is adopted, and a voltage matching module and a resistance control module are used to implement a frequency modulation, a widening, and a mixed control mode of the resonant circuit. It takes the following steps:
  • the loop voltage Vloop when the loop voltage Vloop operates in the first interval, the loop voltage Vloop causes the resistance control module to act on the pulse width modulation control chip to generate the frequency modulation control; meanwhile, the loop voltage Vloop causes the voltage matching module to act on the pulse width modulation control chip Generating a widening control;
  • the loop voltage Vloop when the loop voltage Vloop operates in the second interval, the loop voltage Vloop causes the voltage matching module to act on the pulse width modulation control chip to generate the maximum duty ratio Dmax, and the loop voltage Vloop causes the resistance control module to act on the pulse width modulation control
  • the chip produces FM control. It uses the following steps:
  • the resistance control module when the loop voltage Vloop operates in the first interval, the resistance control module generates a constant equivalent resistance to the pulse width modulation control chip and outputs a pulse frequency maximum value fmax, and the loop voltage Vloop causes the voltage matching module to act on the pulse width
  • the modulation control chip generates a widening control
  • the loop voltage Vloop when the loop voltage Vloop operates in the second interval, the loop voltage Vloop causes the resistance control module to act on the pulse width modulation control chip to generate the frequency modulation control; meanwhile, the loop voltage Vloop causes the voltage matching module to act on the pulse width modulation control chip Generating a widening control;
  • the loop voltage Vloop when the loop voltage Vloop operates in the third interval, the loop voltage Vloop causes the voltage matching module to act on the pulse width modulation control chip to generate the maximum duty ratio Dmax, and the loop voltage Vloop causes the resistance control module to act on the pulse width modulation control
  • the chip produces FM control.
  • the maximum duty ratio Dmax is 50%.
  • the first interval is a widened voltage interval of the loop voltage Vloop when the resonant circuit is unloaded or lightly loaded.
  • the third interval is a frequency modulation voltage interval of the loop voltage Vloop when the resonant circuit is heavily loaded.
  • the loop voltage Vloop is an output voltage of the resonant circuit output voltage Vo after passing through the sampling circuit and the regulator.
  • the control chip of the resonant circuit is connected to the related control device, and the control device provides voltage matching and resistance control to the control chip, and the control device provides control parameters to the modulation control chip according to the input voltage.
  • the control chip modulates the resonant circuit accordingly.
  • the control chip uses a pulse width modulation control chip or a phase shift pulse width modulation control chip, and the PWM generator and the oscillator of the phase shift pulse width modulation control chip are respectively connected with the voltage matching module.
  • the resistance control module, the voltage matching module and the resistance control module provide corresponding control parameters to the phase-shifted pulse width modulation control chip according to the input voltage, thereby implementing corresponding modulation.
  • the voltage matching module and the resistance control module use the loop voltage Vloop as the input voltage.
  • the loop voltage Vloop operates in the first interval, the Vloop of the interval is smaller, and the converter operates at no load or light load, and the loop voltage Vloop causes the resistance control module to act on the phase shift pulse width modulation control chip.
  • FM control at the same time, the loop voltage Vloop makes the voltage
  • the matching module acts on the phase shifting pulse width modulation control chip to generate the widening control.
  • the voltage matching module uses the operational amplifier U701 and the simple discrete component
  • the resistance control module uses the resistor or the resistor combination to connect with the RT terminal.
  • the structure is relatively simple and the cost is low. Compared with the prior art, under the premise of obtaining the same modulation performance, the invention reduces the difficulty of designing the magnetic component and improves the power supply efficiency.
  • FIG. 1 is a schematic diagram of a full bridge series resonant circuit
  • FIG. 2 is a schematic diagram of a control structure of a phase-shifted pulse width modulation control chip according to the present invention
  • FIG. 3 is a schematic diagram of a voltage matching module and a resistance control module of the embodiment 1 using a phase-shifted pulse width modulation control chip
  • Figure 5 is a schematic diagram showing the driving waveforms of four switching tubes in which the full-bridge resonant circuit operates in the frequency-only mode;
  • FIG. 6 is a schematic diagram showing driving waveforms of four switching tubes in which the full-bridge resonant circuit operates in both the frequency modulation and the widening mode or only the widening mode;
  • FIG. 7 is a schematic diagram of a voltage matching module and a resistance control module of Embodiment 2 using a phase shifting pulse width modulation control chip according to the present invention
  • FIG. 9 is a schematic diagram of a half bridge series resonant circuit
  • Figure 10a shows the driving waveforms of two switching tubes in which the half-bridge resonant circuit operates in the frequency-only mode. Intention
  • Figure 10b is a schematic diagram showing driving waveforms of two switching tubes in which the half-bridge resonant circuit operates in both the frequency modulation and the widening mode or only the widening mode;
  • FIG. 11 is a schematic diagram of a control structure of a pulse width modulation control chip according to the present invention.
  • FIG. 12 is a schematic diagram of a voltage matching module and a resistance control module of Embodiment 3 of a pulse width modulation control chip according to the present invention
  • FIG. 14 is a schematic diagram of a voltage matching module and a resistance control module of Embodiment 4 of a pulse width modulation control chip according to the present invention
  • the present invention includes a phase shifting pulse width modulation control chip 1.
  • the EAOUT terminal of the PWM generator and the RT terminal of the oscillator are respectively connected in the phase shifting pulse width modulation control chip 1.
  • the voltage matching module 2 and the resistance control module 3, the voltage matching module 2 and the resistance control module 3 provide corresponding control parameters to the phase-shifted pulse width modulation control chip 1 according to the input voltage (ie, the loop voltage Vloop), phase shift pulse width modulation control.
  • Chip 1 modulates the resonant circuit accordingly, as shown in Figure 1, the full-bridge series resonant circuit, the four output signals of the phase-shifted pulse width modulation control chip 1 PWM1, PWM2, PWM3, PWM4 to the full-bridge series resonant circuit Sl, S2, S4, and S3 are modulated.
  • the voltage matching module 2 and the resistance control module 3 both use the loop voltage Vloop as the input voltage, and the loop voltage Vloop is the resonant circuit output voltage Vo through the sampling circuit and the regulator (such as a PID regulator).
  • the voltage matching module 2 includes an operational amplifier U701 and a first partial voltage sub-module 21, wherein
  • a resistor R714 is connected between the opposite end of the operational amplifier U701 and ground, and a resistor R711 is connected to the output terminal.
  • the same end of the operational amplifier U701 is connected to the voltage dividing end of the first voltage dividing submodule 21, and the first voltage dividing submodule 21 includes series resistors R712 and R713, and is connected to the loop voltage Vloop and Between the ground, the connection point of the resistor R712 and the resistor R713 is directly connected to the same end of the operational amplifier U701.
  • a current limiting circuit 22 is connected between the output end of the operational amplifier U701 and the EAOUT terminal of the PWM generator in the phase shifting pulse width modulation control chip 1.
  • the current limiting circuit 22 includes a series resistor R715, a resistor R716, and The capacitor C1, the resistor R715 and the resistor R716 are connected in series between the output end of the operational amplifier U701 and the EAOUT terminal, and the capacitor C1 is connected between the connection point of the resistor R715 and the resistor R716 and the ground, wherein the capacitor C1 functions as a voltage regulator and a filter.
  • the voltage matching module 2 matches the phase shift voltage interval corresponding to the loop voltage Vloop with the voltage range in which the EAOUT terminal of the phase shift pulse width modulation control chip 1 is phase-shifted, and the specific proportional parameter in the matching can be combined with the phase shift pulse.
  • the resistance control module 3 includes a second voltage dividing submodule 31.
  • the second voltage dividing submodule 31 includes series resistors R701 and R702 and is connected between the loop voltage Vloop and the ground.
  • a resistor R703 is connected between the connection point between R701 and R702 and the RT terminal, and the resistance control module 3 is connected between the loop voltage Vloop and the RT terminal of the phase shift pulse width modulation control chip 1, so that the RT terminal has an external equivalent resistance. Adjust accordingly as the loop voltage Vloop changes.
  • the working process of this embodiment is as follows. - AA1, when the loop voltage Vloop operates in the first interval, as shown in FIG. 4, that is, Vloop is greater than xV and less than yV, the loop voltage Vloop causes the resistance control module 3 to act on the phase shift.
  • the pulse width modulation control chip 1 generates frequency modulation control; meanwhile, the loop voltage Vloop causes the voltage matching module 2 to act on the phase shift pulse width modulation control chip 1 to generate a widening control.
  • Vloop When Vloop is greater than xV and less than yV, then the converter operates in a light load or no load state.
  • the operating voltage range of Vloop is [2, 6]V, and Vloop passes through voltage matching module 2, as shown in Figure 6.
  • PWM Pulse Width Modulation
  • the duty cycle changes from 0% to 50%.
  • the loop voltage When the loop voltage is xV, the corresponding duty ratio is 0%.
  • the resistance control module 3 composed of the resistors R701, R702 and R703 changes the external equivalent resistance of the RT terminal to change the operating frequency, that is, the PFM control can be performed, and the loop voltage Vloop increases from xV to yV, since xV is The minimum output voltage of the control loop, Vloop through the resistors R701, R702 and R703 minimizes the external equivalent resistance of the RT terminal, so the frequency of the output pulse of the phase shift pulse width modulation control chip is the maximum value fmax.
  • Vloop can perform PWM and PFM control simultaneously in the voltage range [x, y], and the resonant circuit operates in both frequency modulation and widening mode.
  • the Vloop passes through the voltage matching module composed of the operational amplifier U701 and its peripheral circuits, so that the equivalent duty ratio of the two switching tubes that are simultaneously turned on is zero.
  • the loop voltage Vloop when the loop voltage Vloop operates in the second interval, as shown in FIG. 4, that is, Vloop is greater than yV and less than zV, the loop voltage Vloop causes the voltage matching module 2 to act on the phase shift pulse width modulation control chip 1 to generate the maximum The space ratio Dmax, the loop voltage Vloop causes the resistance control module 3 to act on the phase shift pulse width modulation control chip 1 to generate frequency modulation control.
  • Vloop When Vloop is greater than yV and less than zV, then the converter operates in a heavy load state. For example, at this time, the operating voltage range of Vloop is [6, 12]V, and Vloop passes through voltage matching module 2, as shown in FIG. The equivalent duty cycle of both switches that are turned on at the same time is 50%.
  • the Vloop changes the operating frequency by changing the external equivalent resistance of the RT terminal through the resistors R701, R702 and R703, which means that the PFM control can be performed, and the operating frequency decreases as the Vloop increases.
  • the value of Vloop is zV
  • Vloop passes the resistors R701, R702 and R703 to maximize the external equivalent resistance of the RT terminal, so the frequency of the output pulse of the phase-shifted pulse width modulation control chip 1 is The minimum value is fmin.
  • Example 2 Example 2:
  • the resistance control module 3 further includes a comparison voltage sub-module 32, which generates a reference level Vref, a reference level.
  • a first diode D702 and a second diode D701 are connected between the Vref, the loop voltage Vloop and the input end of the second voltage dividing submodule 31, and the anodes of the first diode D702 and the second diode D701 are respectively connected It is connected to the second partial pressure sub-module 31.
  • the comparison voltage sub-module 32 provides a reference level Vref with a precision reference component U702, a voltage divider Vc via resistors R704, R705, and R706, and a voltage drop from the resistor R706 to a precision reference component U702.
  • a filter capacitor C2 is connected between the reference level Vref and ground.
  • the resistance control module 3 when the loop voltage Vloop operates in the first interval, as shown in FIG. 8, that is, Vloop is greater than aV and smaller than bV, the resistance control module 3 generates a constant equivalent resistance to the phase-shifted pulse width modulation control chip 1 and outputs it.
  • the pulse frequency maximum value fmax the loop voltage Vloop causes the voltage matching module 2 to act on the phase shift pulse width modulation control chip 1 to generate a widening control.
  • the Vloop is in the voltage range [a, b].
  • the converter operates in a light load or no load state.
  • the operating voltage range of the Vloop is [2, 5] V, due to the reference.
  • the test level Vref is bV (bV is 5V at this time)
  • the second diode D701 is turned off
  • the first diode D702 is turned on
  • the reference voltage Vref (the magnitude of the voltage is bV) remains unchanged
  • RT The external equivalent resistance of the terminal is also kept constant, so the frequency of the output pulse of the phase shift pulse width modulation control chip 1 is kept at the maximum value fmax.
  • the Vloop passes through the voltage matching module composed of U701 and its peripheral circuits, and the equivalent duty ratio of the two switching tubes that are simultaneously turned on is zero.
  • the equivalent duty ratio of the two switching tubes that are simultaneously turned on can be adjusted by phase shifting, that is, PWM control can be performed, and when Vloop is equal to aV, the duty is occupied.
  • the ratio is 0%, increasing from aV to bV with Vloop, and the duty cycle is increased from 0% to Db%.
  • the loop voltage Vloop when the loop voltage Vloop operates in the second interval, as shown in FIG. 8, that is, Vloop is greater than bV and smaller than cV, the loop voltage Vloop causes the resistance control module 3 to act on the phase shift pulse width modulation control chip 1 to generate frequency modulation control. At the same time, the loop voltage Vloop causes the voltage matching module 2 to act on the phase shift pulse width modulation control chip 1 to generate a widening control.
  • Vloop When Vloop is greater than bV and less than cV, then the converter operates between light load and heavy load.
  • the operating voltage range of Vloop is [5, 7]V, and Vloop passes through voltage matching module 2.
  • the phase shift can be used to adjust the equivalent duty ratio of the two switching tubes that are simultaneously turned on, that is, PWM control can be performed.
  • the duty cycle changes from Db% to 50%.
  • the loop voltage is bV
  • the corresponding duty ratio is Db%.
  • the loop voltage is cV
  • the second diode D701 is turned on, and the first diode D702 is turned off, and the loop voltage Vloop is changed by the resistance control module 3 composed of the resistors R701, R702, and R703 to change the RT terminal to the outside.
  • the equivalent resistance changes the operating frequency, that is, the PFM control can be performed.
  • the loop voltage Vloop increases from bV to eV
  • the operating frequency decreases as the Vloop increases
  • the phase-shift pulse width modulation control chip 1 outputs when the Vloop is bV.
  • the frequency of the pulse is the maximum value fmax, and when Vloop is cV, the frequency is reduced to fc.
  • Vloop can perform PWM and PFM control simultaneously in the voltage range [b, c], and the resonant circuit operates in both frequency modulation and widening mode.
  • the loop voltage Vloop when the loop voltage Vloop operates in the third interval, as shown in FIG. 8, that is, Vloop is greater than cV and less than dV, the loop voltage Vloop causes the voltage matching module 2 to act on the phase shifting pulse width modulation control chip 1 to generate the maximum The space ratio Dmax, the loop voltage Vloop causes the resistance control module 3 to act on the phase shift pulse width modulation control chip 1 to generate the frequency modulation control.
  • the third interval is the frequency modulation voltage interval of the loop voltage Vloop when the resonant circuit is heavily loaded.
  • the converter operates in a heavy load state.
  • the operating voltage range of Vloop is [7, 12]V. After Vloop passes through voltage matching module 2, as shown in Figure 8, The equivalent duty cycle of both switches that are turned on is 50%.
  • the second diode D701 is turned on, and the first diode D702 is turned off, and the Vloop changes the operating frequency by changing the external equivalent resistance of the RT terminal through the resistors R701, R702, and R703.
  • PFM control is performed, and as the Vloop increases, the operating frequency decreases.
  • Vloop passes the resistors R701, R702, and R703 to maximize the external equivalent resistance of the RT terminal, so the frequency of the output pulse of the phase-shifted pulse width modulation control chip 1 is The minimum value is fmin.
  • the control of the full-bridge resonant circuit by the phase-shifting pulse width modulation control chip 1 is reflected, and the present invention can also control the half-bridge resonant circuit.
  • the half-bridge series resonant circuit shown in FIG. In practical applications, only the four output signals PWM1, PWM2, PWM3, and PWM4 of the phase-shifted pulse width modulation control chip 1 need to be combined and combined, for example, logically outputting the output signals PWM1 and PWM3, PWM2, and PWM4, respectively.
  • the generated two outputs are respectively modulated by S1 and S2 of the half bridge series resonant circuit in FIG.
  • the present invention includes a pulse width modulation control chip 10.
  • the COMP terminal and the RT terminal of the pulse width modulation control chip 10 are respectively connected to the voltage matching module 2 and the resistance control module 3, and the voltage.
  • the matching module 2 and the resistance control module 3 provide corresponding control parameters to the pulse width modulation control chip 10 according to the input voltage (ie, the loop voltage Vloop), and the pulse width modulation control chip 10 modulates the resonant circuit accordingly, as shown in FIG.
  • the two output signals PWM1 and PWM2 of the pulse width modulation control chip 10 modulate the S1 and S2 of the half bridge series resonant circuit.
  • the voltage matching module 2 and the resistance control module 3 both use the loop voltage Vloop as the input voltage, and the loop voltage Vloop is the resonant circuit output voltage Vo through the sampling circuit and the regulator (such as a PID regulator).
  • the voltage matching module 2 includes an operational amplifier U701 and a first-dividing sub-module 21, wherein
  • a resistor R714 is connected between the opposite end of the operational amplifier U701 and the ground, and a resistor R711 is connected to the output terminal.
  • the forward end of the operational amplifier U701 is connected to the voltage dividing end of the first voltage dividing submodule 21, and the first voltage dividing submodule 21 includes series resistors R712 and R713, and is connected to the loop voltage Vloop and Between the ground, the connection point of the resistor R712 and the resistor R713 is directly connected to the forward end of the operational amplifier U701.
  • a current limiting circuit 22 is connected between the output end of the operational amplifier U701 and the COMP terminal of the pulse width modulation control chip 10.
  • the current limiting circuit 22 includes a series resistor R715, a resistor R716 and a capacitor C1, and a resistor R715 and
  • the resistor R716 is connected in series between the output end of the operational amplifier U701 and the RT terminal, and the capacitor C1 is connected between the connection point of the resistor 715 and the resistor R716 and the ground, wherein the capacitor C1 functions as a voltage regulator and a filter.
  • the voltage matching module 2 matches the widened voltage interval corresponding to the loop voltage Vloop with the voltage range in which the COMP end of the pulse width modulation control chip 10 is widened, and the specific proportional parameter in the matching can be combined with the pulse width modulation control chip.
  • the resistance control module 3 includes a second voltage dividing sub-module 31.
  • the second voltage dividing sub-module 31 includes series resistors R701 and R702 and is connected between the loop voltage Vloop and the ground.
  • a resistor R703 is connected between the connection point between R701 and R702 and the RT terminal, and the resistance control module 3 is connected between the loop voltage Vloop and the RT terminal of the pulse width modulation control chip 10, so that the external equivalent resistance of the RT terminal is connected with the loop. The change of the circuit voltage Vloop is adjusted accordingly.
  • the loop voltage Vloop when the loop voltage Vloop operates in the first interval, as shown in FIG. 13, that is, V op is greater than xV and less than yV, the loop voltage Vloop causes the resistance control module 3 to act on the pulse width modulation control chip 10 to generate frequency modulation control; At the same time, the loop voltage Vloop causes the voltage matching module 2 to act on the pulse width modulation control chip 10 to generate a widening control.
  • Vloop When Vloop is greater than xV and less than yV, then the converter operates in light load or no load state.
  • the operating voltage range of Vloop is [2, 6]V, and Vloop passes through voltage matching module 2, as shown in Figure 10b. It can be adjusted to adjust the duty cycle of the switch by widening, that is, PWM (Pulse Width Modulation) control.
  • the duty cycle changes from 0% to 50%.
  • the loop voltage When the loop voltage is xV, the corresponding duty ratio is 0%.
  • the PFM control can be performed, and the loop voltage Vloop increases from xV to yV, since xV is The minimum output voltage of the control loop, Vloop through the resistors R701, R702 and R703 minimizes the external equivalent resistance of the RT terminal, so the frequency of the output pulse of the pulse width modulation control chip 10 is the maximum value fma X . Therefore, Vloop can perform PWM and PFM control simultaneously in the voltage range [x, y], and the resonant circuit operates in both frequency modulation and widening mode.
  • the Vloop passes through the voltage matching module composed of the operational amplifier U701 and its peripheral circuits, so that the duty cycle of the switching transistor is zero.
  • the loop voltage Vloop when the loop voltage Vloop operates in the second interval, as shown in FIG. 13, that is, Vloop is greater than yV and smaller than zV, the loop voltage Vloop causes the voltage matching module 2 to act on the pulse width modulation control chip 1 to generate the maximum duty ratio. Dmax, the loop voltage Vloop causes the resistance control module 3 to act on the pulse width modulation control chip 10 to generate frequency modulation control.
  • Vloop When Vloop is greater than yV and less than zV, then the converter operates in a heavy load state.
  • the operating voltage range of Vloop is [6, 12]V, and Vloop passes through voltage matching module 2, as shown in Figure 10a.
  • the duty cycle of both switches is 50%.
  • the Vloop changes the operating frequency through the resistors R701, R702 and R703 to change the external equivalent resistance of the RT terminal, that is, the PFM control can be performed, and the operating frequency decreases as the Vloop increases.
  • the value of Vloop is zV
  • Vloop passes the resistors R701, R702, and R703 to maximize the external equivalent resistance of the RT terminal, so the frequency of the output pulse of the pulse width modulation control chip 10 is the minimum value. Fmin.
  • Example 4 Example 4:
  • the resistance control module 3 further includes a comparison voltage sub-module 32, which generates a reference level Vref, a reference level.
  • a first diode D702 and a second diode D701 are connected between the Vref, the loop voltage Vloop and the input end of the second voltage dividing submodule 31, and the anodes of the first diode D702 and the second diode D701 are respectively connected It is connected to the second partial pressure sub-module 31.
  • the comparison voltage sub-module 32 uses the precision reference component U702 to provide a reference level Vref, the voltage Rc is divided by the resistors R704, R705, and R706, and the voltage drop of the resistor R706 supplies the operating voltage to the precision reference component U702.
  • a filter capacitor C2 is also connected between the reference level Vref and ground. '
  • the resistance control module 3 when the loop voltage Vloop operates in the first interval, as shown in FIG. 15, that is, Vloop is greater than aV and smaller than bV, the resistance control module 3 generates a constant equivalent resistance to the pulse width modulation control chip 1 and maximizes its output pulse.
  • the value fmax the loop voltage Vloop causes the voltage matching module 2 to act on the pulse width modulation control chip 10 to generate a widening control.
  • Vloop is in the voltage range [a, b], at which time the converter works Light load or no load state, for example, the operating voltage range of Vloop is [2, 5]V at this time, because the reference level Vre f is bV (when bV is 5V), the second diode D701 is turned off.
  • the first diode D702 is turned on, the reference voltage Vref (the magnitude of the voltage value is bV) remains unchanged, and the external equivalent resistance of the RT terminal is also kept constant, so the frequency of the output pulse of the pulse width modulation control chip 10 is maintained.
  • Maximum value fmax is the reference voltage range [a, b]V at this time, because the reference level Vre f is bV (when bV is 5V), the second diode D701 is turned off.
  • the first diode D702 is turned on, the reference voltage Vref (the magnitude of the voltage value is bV) remains unchanged, and the external equivalent resistance of the RT terminal is also kept
  • Vloop when Vloop is less than aV, Vloop passes through the voltage matching module composed of U701 and its peripheral circuits, and the duty cycle of the switching transistor is zero.
  • the duty cycle of the switching transistor can be adjusted, that is, PWM control can be performed.
  • Vloop is equal to aV
  • the duty ratio is 0%
  • the Vloop is increased by aV.
  • the duty cycle is increased from 0% to Db%.
  • the loop voltage Vloop When the loop voltage Vloop operates in the second interval, as shown in FIG. 15, that is, Vloop is greater than bV and smaller than cV, the loop voltage Vloop causes the resistance control module 3 to act on the pulse width modulation control chip 10 to generate frequency modulation control; The circuit voltage Vloop causes the voltage matching module 2 to act on the pulse width modulation control chip 10 to generate a widening control.
  • Vloop When Vloop is greater than bV and less than cV, then the converter operates between light load and heavy load.
  • the operating voltage range of Vloop is [5, 7]V, and Vloop passes through voltage matching module 2.
  • Vloop passes through voltage matching module 2.
  • the duty ratio changes from Db% to 50%.
  • the loop voltage is bV
  • the corresponding duty ratio is Db%.
  • the loop voltage is cV
  • the second diode D701 is turned on, and the first diode D702 is turned off, and the loop voltage Vloop is changed by the resistance control module 3 composed of the resistors R701, R702, and R703 to change the RT terminal to the outside.
  • the equivalent resistance changes the operating frequency, that is, the PFM control can be performed.
  • the loop voltage Vloop increases from bV to cV
  • the operating frequency decreases as the Vloop increases, and when the Vloop is bV, the pulse width modulation control chip 10 outputs the pulse.
  • the frequency is the maximum value fmax, and when Vloop is cV, the frequency is reduced to fc.
  • Vloop can perform PWM and PFM control simultaneously in the voltage range [b, c], and the resonant circuit operates in both frequency modulation and widening mode.
  • the loop voltage Vloop When the loop voltage Vloop operates in the third interval, as shown in FIG. 15, that is, Vloop is greater than cV and less than dV, the loop voltage Vloop causes the voltage matching module 2 to act on the pulse width modulation control chip 10 to generate the maximum duty ratio Dmax, The loop voltage Vloop causes the resistance control module 3 to act on the pulse width modulation control chip 10 to generate frequency modulation control.
  • Vloop When Vloop is greater than cV and less than dV, then the converter operates in heavy load For example, the operating voltage range of Vloop is [7, 12]V. After Vloop passes through voltage matching module 2, as shown in Figure 15, the duty cycle of the switching transistor is 50%.
  • the Vloop changes the operating frequency by changing the external equivalent resistance of the RT terminal through the resistors R701, R702, and R703.
  • PFM control is performed, and as the Vloop increases, the operating frequency decreases.
  • Vloop passes the resistors R701, R702 and R703 to maximize the external equivalent resistance of the RT terminal, so the frequency of the output pulse of the pulse width modulation control chip 10 is the minimum.
  • fmin the value of Vloop.
  • the control of the half-bridge resonant circuit by the pulse width modulation control chip 10 is reflected, and the present invention can also control the full-bridge resonant circuit.
  • the full-bridge series resonant circuit as shown in FIG.
  • only the two output signals PWM1 and PWM2 of the pulse width modulation control chip 10 need to be group-modulated for the S1, S2, S3, and S4 of the full-bridge series resonant circuit in FIG. 1, for example, pulse width modulation control.
  • the output signal PWM1 of the chip 10 simultaneously controls S1 and S3 of the full-bridge series resonant circuit, and the output signal PWM2 of the pulse width modulation control chip 10 simultaneously controls S2 and S4 of the full-bridge series resonant circuit.
  • the maximum duty ratio of the output pulse of the control chip is described as 50%, the two switching tubes of the same bridge arm are complementarily turned on, and the total duty ratio is 1, and the condition of the description method is that the two paths are not counted.
  • the dead time of the drive pulse In order to make the two switching tubes of the same bridge arm not pass through, a certain dead time should be set between the two driving pulses, so in fact, the maximum duty ratio of the control chip output pulse must be less than 50%, the same bridge arm
  • the upper two switching tubes are complementarily turned on, and the total duty ratio of the two is less than one.
  • the dead time between the two driving pulses can be adjusted by the design of the circuit, and therefore, in front
  • the ideal state is reflected in the description, but has no effect on the circuit design of the present invention.

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Description

一种谐振电路调制控制方法和系统 技术领域
本发明涉及电通信技术， 尤其涉及一种谐振电路调制控制方法和系统。 背景技术
现有的变换器一般釆用调频控制方式 （PFM : Pulse Frequency Modulation)， 通过调节谐振电路中开关管的工作频率来获得所需要的输出电 压。
以串联谐振变换器为例， 串联谐振 DC/DC变换器采用谐振变换技术， 由 于谐振元件工作在正弦谐振状态， 开关管上的电压自然过零， 可以实现零电 压开通， 同时可以消除输出整流二极管的反向恢复， 减小电源损耗， 提高效 率。 这种拓扑通常采用调频控制方式， 通过改变开关管的工作频率来稳定输 出电压。 图 1 为全桥串联谐振 DC/DC变换器的基本形式， 输出电压增益 M 与工作频率的关系为-
0.5
Figure imgf000003_0001
1
/0 =
(b)
Figure imgf000003_0002
在上述 （a) 、 (b) 和 （c) 式中， Lr为谐振电感值， f 为开关管的工作 频率， Cr为谐振电容值， Po为输出功率。
从式 （a) 中可以发现， 当工作频率大于谐振频率， 工作频率越高， 电压 增益 M越低。 同理， 当工作频率小于谐振频率， 工作频率越低， 电压增益 M 越低。
串联谐振变换器一个主要的难点问题在于轻载和空载条件下输出电压难 以稳定。 串联谐振拓扑的输出电压随着开关频率的升高而降低。 当串联谐振 变换器的负载减小至轻载或空载状态时， 通过调节工作频率来稳定输出电压， 当工作频率升高到一定值时， 工作频率对输出电压的调节能力就大大降低， 甚至会使输出电压上升。
这样， 为了稳定输出电压， 工作频率需要升很高， 但是工作频率过高和 调节范围过宽都会增加磁性元件设计的难度， 而且工作频率越高， 电路损耗 也越大。 在电源行业中， 有的设计中采用输出端加上固定的负载， 利用这种 方法在轻载和空载条件下稳定输出电压， 但这样会增加电源的空载损耗， 降 低电源效率。 同样， 半桥串联谐振电路与全桥串联谐振电路会产生类似的问 题。
总之， 单纯的变频控制会导致工作频率过高和调节范围过宽， 增加磁性 元件设计的难度， 以及降低电源效率， 所以， 简单的调频控制无法满足变换 器在轻载和空载时输出电压稳定的要求。 发明内容
本发明的目的在于提供一种成本低， 效率高的谐振电路调制控制方法和 系统， 以解决现有技术中单纯的变频控制会导致工作频率过高和调节范围过 宽， 增加磁性元件设计的难度， 以及降低电源效率的问题。 本发明所采用的谐振电路调制控制系统， 其特征在于： 它采用谐振电路 的控制芯片与有关控制装置连接， 所述控制装置向控制芯片提供电压匹配和 电阻控制， 该控制装置根据输入电压向调制控制芯片提供控制参数， 控制芯 片对谐振电路进行相应调制。 所述控制芯片为移相脉宽调制控制芯片， 所述移相脉宽调制控制芯片中 的 PWM发生器、 振荡器分别连接所述控制装置中的电压匹配模块和电阻控 制模块， 所述的电压匹配模块和电阻控制模块根据输入电压向移相脉宽调制 控制芯片提供控制参数， 移相脉宽调制控制芯片对谐振电路进行相应调制。 所述的电压匹配模块和电阻控制模块均以环路电压 V op为输入电压； 所述的电压匹配模块将环路电压 Vloop对应的移相电压区间与移相脉宽 调制控制芯片的 PWM发生器进行移相的电压范围相匹配；
所述的电阻控制模块连接于环路电压 Vloop与移相脉宽调制控制芯片的 振荡器之间， 使振荡器对外的等效电阻随环路电压 Vloop 的变化进行相应调 整。 所述的电压匹配模块包括运放 U701、第一分压子模块和限流电路，其中， 所述运放 U701 的反向端与地之间连接电阻 R714, 并与输出端之间连接 电阻 R711 ; 所述运放 U701的同向端与第一分压子模块的分压端相连； 所述运放 U701的输出端与移相脉宽调制控制芯片的 PWM发生器之间连 接限流电路。 所述的电阻控制模块包括第二分压子模块， 该第二分压子模块的分压端 与所述移相脉宽调制控制芯片的振荡器之间连接电阻 R703。 所述控制芯片为脉宽调制控制芯片，所述脉宽调制控制芯片的 COMP端、 RT端分别连接所述控制装置中的电压匹配模块和电阻控制模块， 所述的电压 匹配模块和电阻控制模块根据输入电压向脉宽调制控制芯片提供相应的控制 参数， 脉宽调制控制芯片对谐振电路进行相应调制。 所述的电压匹配模块和电阻控制模块均以环路电压 Vloop为输入电压； 所述的电压匹配模块将环路电压 Vloop对应的调宽电压区间与脉宽调制 控制芯片 COMP端进行调宽的电压范围相匹配；
所述的电阻控制模块连接于环路电压 Vloop与脉宽调制控制芯片的 RT端 之间， 使 RT端对外的等效电阻随环路电压 Vloop的变化进行相应调整。 所述的电压匹配模块包括运放 U701、第一分压子模块和限流电路，其中， 所述运放 U701 的反向端与地之间连接电阻 R714， 并与输出端之间连接 电阻 R711 ;
所述运放 U701的同向端与第一分压子模块的分压端相连；
所述运放 U701 的输出端与脉宽调制控制芯片 COMP端之间连接限流电 路。 所述的电阻控制模块包括第二分压子模块， 该第二分压子模块的分压端 与所述移相脉宽调制控制芯片的振荡器之间连接电阻 R703。 所述的第一分压子模块包括串联电阻 R712、 713 , 并连接于环路电压 Vloop与地之间。 所述的第二分压子模块包括串联电阻 R701、 R702, 并连接于环路电压 Vloop与地之间。 所述的电阻控制模块还包括比较电压子模块， 所述比较电压子模块产生 参考电平 Vref， 所述的参考电平 Vref、 环路电压 Vloop与第二分压子模块 31 的输入端之间分别连接第一二极管 D702和第二二极管 D701， 所述的第一二 极管 D702和第二二极管 D701的负极与第二分压子模块相连。 这种谐振电路调制控制方法， 其特征在于： 釆用移相脉宽调制控制芯片， 通过电压匹配模块和电阻控制模块对谐振电路实现调频、 调宽及其混合的控 制模式。 它采用如下步骤：
AA1、 当环路电压 Vloop工作于第一区间时， 环路电压 Vloop使电阻控制模 块作用于移相脉宽调制控制芯片产生调频控制；同时，环路电压 Vloop 使电压匹配模块作用于移相脉宽调制控制芯片产生调宽控制；
AA2、 当环路电压 Vloop工作于第二区间时， 环路电压 Vloop使电压匹配模 块作用于移相脉宽调制控制芯片产生最大占空比 Dmax， 环路电压 Vloop使电阻控制模块作用于移相脉宽调制控制芯片产生调频控制。 它采用如下步骤：
BA 当环路电压 Vloop工作于第一区间时， 电阻控制模块对移相脉宽调制 控制芯片产生恒定等效电阻并使其输出脉冲频率最大值 fmax， 环路电 压 Vloop使电压匹配模块作用于移相脉宽调制控制芯片产生调宽控制；
BA2、 当环路电压 Vloop工作于第二区间时， 环路电压 Vloop使电阻控制模 块作用于移相脉宽调制控制芯片产生调频控制； 同时， 环路电压 Vloop 使电压匹配模块作用于移相脉宽调制控制芯片产生调宽控制；
BA3、 当环路电压 Vloop工作于第三区间时， 环路电压 Vloop使电压匹配模 块作用于移相脉宽调制控制芯片产生最大占空比 Dmax， 环路电压 Vloop使电阻控制模块作用于移相脉宽调制控制芯片产生调频控制。 所述的最大占空比 Dmax为 50%。 所述的第一区间为谐振电路空载或轻载时环路电压 Vloop 的移相电压区 间。 所述的第三区间为谐振电路重载时环路电压 Vloop的调频电压区间。 这种谐振电路调制控制方法， 其特征在于： 采用脉宽调制控制芯片， 通 过电压匹配模块和电阻控制模块对谐振电路实现调频、 调宽及其混合的控制 模式。 它采用如下步骤：
AB1、 当环路电压 Vloop工作于第一区间时， 环路电压 Vloop使电阻控制模 块作用于脉宽调制控制芯片产生调频控制； 同时， 环路电压 Vloop使 电压匹配模块作用于脉宽调制控制芯片产生调宽控制；
AB2、 当环路电压 Vloop工作于第二区间时， 环路电压 Vloop使电压匹配模 块作用于脉宽调制控制芯片产生最大占空比 Dmax， 环路电压 Vloop 使电阻控制模块作用于脉宽调制控制芯片产生调频控制。 它釆用如下步骤：
BB1、 当环路电压 Vloop工作于第一区间时， 电阻控制模块对脉宽调制控制 芯片产生恒定等效电阻并使其输出脉冲频率最大值 fmax， 环路电压 Vloop使电压匹配模块作用于脉宽调制控制芯片产生调宽控制；
BB2、 当环路电压 Vloop工作于第二区间时， 环路电压 Vloop使电阻控制模 块作用于脉宽调制控制芯片产生调频控制； 同时，环路电压 Vloop使电 压匹配模块作用于脉宽调制控制芯片产生调宽控制；
BB3、 当环路电压 Vloop工作于第三区间时， 环路电压 Vloop使电压匹配模 块作用于脉宽调制控制芯片产生最大占空比 Dmax， 环路电压 Vloop使 电阻控制模块作用于脉宽调制控制芯片产生调频控制。 所述的最大占空比 Dmax为 50%。 所述的第一区间为谐振电路空载或轻载时环路电压 Vloop 的调宽电压区 间。 所述的第三区间为谐振电路重载时环路电压 Vloop的调频电压区间。 所述的环路电压 Vloop为谐振电路输出电压 Vo经过采样电路和调节器后 的输出电压。 本发明的有益效果为： 在本发明中，釆用谐振电路的控制芯片与有关控制 装置连接， 通过控制装置向控制芯片提供电压匹配和电阻控制， 控制装置根 据输入电压向调制控制芯片提供控制参数， 控制芯片对谐振电路进行相应调 制， 例如， 控制芯片釆用脉宽调制控制芯片或者移相脉宽调制控制芯片， 在 移相脉宽调制控制芯片的 PWM发生器、 振荡器分别连接电压匹配模块和电 阻控制模块， 电压匹配模块和电阻控制模块根据输入电压向移相脉宽调制控 制芯片提供相应的控制参数， 实现相应调制， 例如， 电压匹配模块和电阻控 制模块以环路电压 Vloop为输入电压， 当环路电压 Vloop工作于第一区间时， 该区间的 Vloop较小， 体现为变换器工作在空载或轻载， 环路电压 Vloop使 电阻控制模块作用于移相脉宽调制控制芯片产生调频控制， 同时， 环路电压 Vloop使电压匹配模块作用于移相脉宽调制控制芯片产生调宽控制，在系统控 制结构中， 电压匹配模块采用运放 U701及简单分立元件， 电阻控制模块釆用 电阻或电阻组合与 RT端之间连接，结构较为简单，成本低，相对于现有技术， 在获得相同调制性能的前提下， 本发明降低了磁性元件设计的难度， 提高了 电源效率。 附图说明
图 1为一种全桥串联谐振电路示意图；
图 2为本发明采用移相脉宽调制控制芯片的控制结构总体示意图； 图 3为本发明采用移相脉宽调制控制芯片实施例 1 电压匹配模块和电阻 控制模块示意图；
图 4为本发明釆用移相脉宽调制控制芯片实施例 1环路电压与工作频率 及占空比的对应关系曲线；
图 5 为全桥谐振电路工作在只调频方式下的四个开关管的驱动波形示意 图；
图 6为全桥谐振电路工作在既调频又调宽方式或只调宽方式下的四个开 关管的驱动波形示意图；
图 7为本发明采用移相脉宽调制控制芯片实施例 2电压匹配模块和电阻 控制模块示意图；
图 8为本发明采用移相脉宽调制控制芯片实施例 2环路电压与工作频率 及占空比的对应关系曲线；
图 9为一种半桥串联谐振电路示意图；
图 10a为半桥谐振电路工作在只调频方式下的两个开关管的驱动波形示 意图；
图 10b为半桥谐振电路工作在既调频又调宽方式或只调宽方式下的两个 开关管的驱动波形示意图；
图 11为本发明采用脉宽调制控制芯片控制结构总体示意图；
图 12为本发明采用脉宽调制控制芯片实施例 3电压匹配模块和电阻控制 模块示意图；
图 13为本发明釆用脉宽调制控制芯片实施例 3环路电压与工作频率及占 空比的对应关系曲线；
图 14为本发明釆用脉宽调制控制芯片实施例 4电压匹配模块和电阻控制 模块示意图；
图 15为本发明采用脉宽调制控制芯片实施例 4环路电压与工作频率及占 空比的对应关系曲线； 具体实施方式
下面根据附图和实施例对本发明作进一步详细说明： 实施例 1 :
如图 2和图 3所示， 本发明包括移相脉宽调制控制芯片 1， 如图 2所示， 移相脉宽调制控制芯片 1中 PWM发生器的 EAOUT端、振荡器的 RT端分别 连接电压匹配模块 2和电阻控制模块 3， 电压匹配模块 2和电阻控制模块 3 根据输入电压（即环路电压 Vloop)向移相脉宽调制控制芯片 1提供相应的控 制参数， 移相脉宽调制控制芯片 1对谐振电路进行相应调制， 如图 1所示的 全桥串联谐振电路，移相脉宽调制控制芯片 1的四个输出信号 PWM1、PWM2、 PWM3、 PWM4对全桥串联谐振电路的 Sl、 S2、 S4、 S3进行调制。
如图 2和图 3所示，电压匹配模块 2和电阻控制模块 3均以环路电压 Vloop 为输入电压，环路电压 Vloop为谐振电路输出电压 Vo经过采样电路和调节器 (如 PID调节器）后的输出电压， 电压匹配模块 2包括运放 U701和第一分压 子模块 21， 其中，
如图 3所示， 运放 U701的反向端与地之间连接电阻 R714, 并与输出端 之间连接电阻 R711。
如图 3所示， 运放 U701的同向端与第一分压子模块 21的分压端相连， 该第一分压子模块 21包括串联电阻 R712、 R713 , 并连接于环路电压 Vloop 与地之间， 电阻 R712和电阻 R713的连接点与运放 U701的同向端直接相连。 如图 3所示，运放 U701的输出端与移相脉宽调制控制芯片 1中 PWM发 生器的 EAOUT端之间连接限流电路 22， 该限流电路 22包括串接电阻 R715、 电阻 R716和电容 Cl， 电阻 R715和电阻 R716串联于运放 U701的输出端与 EAOUT端之间， 电阻 R715和电阻 R716的连接点与地之间连接电容 Cl， 其 中电容 C1起到稳压、 滤波的作用。
电压匹配模块 2将环路电压 Vloop对应的移相电压区间与移相脉宽调制 控制芯片 1 的 EAOUT端进行移相的电压范围相匹配， 至于匹配中的具体比 例参数等， 可结合移相脉宽调制控制芯片 1 的参数， 以及全桥串联谐振电路 的控制参数设置。
如图 2和图 3所示， 该电阻控制模块 3包括第二分压子模块 31， 第二分 压子模块 31包括串联电阻 R701、 R702, 并连接于环路电压 Vloop与地之间， 电阻 R701、 R702之间的连接点与 RT端之间连接电阻 R703, 电阻控制模块 3 连接于环路电压 Vloop与移相脉宽调制控制芯片 1的 RT端之间， 使 RT端对 外的等效电阻随环路电压 Vloop的变化进行相应调整。
本实施例的工作过程如下. - AA1、 当环路电压 Vloop工作于第一区间时， 如图 4所示， 即 Vloop大于 xV 并且小于 yV， 环路电压 Vloop使电阻控制模块 3作用于移相脉宽调制 控制芯片 1产生调频控制； 同时， 环路电压 Vloop使电压匹配模块 2作 用于移相脉宽调制控制芯片 1产生调宽控制。
当 Vloop大于 xV并且小于 yV时， 这时， 变换器工作在轻载或空 载状态， 例如 ， Vloop的工作电压区间为 [2， 6]V， Vloop经过电压 匹配模块 2后，如图 6所示，能通过移相来调节同时开通的（改为"两"） 个开关管的等效占空比， 即能进行脉宽调制 （PWM : Pulse Width Modulation)控制。 占空比从 0%变化到 50%， 当环路电压为 xV时， 所 对应的占空比为 0%， 环路电压为 yV 时， 所对应的占空比为最大值 Dmax=50%。
同时， 经过由电阻 R701、 R702和 R703构成的电阻控制模块 3改 变 RT端对外的等效电阻而改变工作频率， 即能进行 PFM控制， 环路 电压 Vloop从 xV增大至 yV时， 由于 xV为控制环路输出电压最小值， Vloop经过电阻 R701、 R702和 R703使 RT端对外的等效电阻最小， 所 以移相脉宽调制控制芯片输出脉冲的频率是最大值 fmax。
所以 Vloop在电压区间 [x，y]内，能够同时进行 PWM和 PFM控制， 谐振电路工作在既调频又调宽方式。 显然， 当 Vloop小于 xV时， Vloop经过由运放 U701及其外围电 路构成的电压匹配模块后，使得同时开通的两个开关管的等效占空比为 零。
AA2、 当环路电压 Vloop工作于第二区间时， 如图 4所示， 即 Vloop大于 yV 并且小于 zV， 环路电压 Vloop使电压匹配模块 2作用于移相脉宽调制 控制芯片 1产生最大占空比 Dmax， 环路电压 Vloop使电阻控制模块 3 作用于移相脉宽调制控制芯片 1产生调频控制。
当 Vloop大于 yV并且小于 zV时， 这时， 变换器工作在重载状态， 例如 ， 此时 Vloop的工作电压区间为 [6， 12]V， Vloop经过电压匹配 模块 2后，如图 5所示，同时开通的两个开关管的等效占空比均为 50%。
同时， Vloop经过电阻 R701、 R702和 R703改变 RT端对外的等效 电阻而改变工作频率， 即能进行 PFM控制， 随 Vloop的增大， 工作频 率降低。 Vloop的值为 zV时， 因为 zV为控制环路输出电压最大值， Vloop经过电阻 R701、 R702和 R703使 RT端对外的等效电阻最大， 所 以移相脉宽调制控制芯片 1输出脉冲的频率是最小值 fmin。 实施例 2:
本实施例与实施例 1 的区别在于： 在本实施例中， 如图 7所示， 电阻控 制模块 3还包括比较电压子模块 32,该比较电压子模块 32产生参考电平 Vref, 参考电平 Vref、环路电压 Vloop与第二分压子模块 31的输入端之间分别连接 第一二极管 D702和第二二极管 D701， 第一二极管 D702和第二二极管 D701 的负极与第二分压子模块 31相连。
如图 7所示， 比较电压子模块 32釆用精密基准元件 U702提供参考电平 Vref, 通过电阻 R704、 R705、 R706对电源 Vc分压， 由电阻 R706的压降向 精密基准元件 U702提供工作电压， 在参考电平 Vref与地之间还连有滤波电 容 C2。
本实施例的工作过程如下：
BA1、 当环路电压 Vloop工作于第一区间时， 如图 8所示， 即 Vloop大于 aV 并且小于 bV，电阻控制模块 3对移相脉宽调制控制芯片 1产生恒定等 效电阻并使其输出脉冲频率最大值 fmax， 环路电压 Vloop使电压匹配 模块 2作用于移相脉宽调制控制芯片 1产生调宽控制。
如图 8所示， Vloop在电压区间 [a， b]内， 这时， 变换器工作在轻 载或空载状态， 例如， 此时 Vloop的工作电压区间为 [2， 5]V, 由于参 考电平 Vref为 bV (bV此时取值为 5V)， 第二二极管 D701关断， 第 一二极管 D702导通， 基准电压 Vref (电压值的大小为 bV)保持不变， RT端对外的等效电阻也保持恒定不变， 所以移相脉宽调制控制芯片 1 输出脉冲的频率保持最大值 fmax。
显然， 当 Vloop小于 aV时， Vloop经过由 U701及其外围电路构 成的电压匹配模块后， 同时幵通的两个开关管的等效占空比为零。
同时， 如图 8所示， Vloop经过电压匹配模块 2后， 能通过移相 来调节同时开通的两个开关管的等效占空比， 即能进行 PWM控制， 当 Vloop等于 aV时， 占空比为 0%， 随 Vloop由 aV增大至 bV， 占空 比由 0%增至 Db%。
BA2、 当环路电压 Vloop工作于第二区间时， 如图 8所示， 即 Vloop大于 bV 并且小于 cV，环路电压 Vloop使电阻控制模块 3作用于移相脉宽调制 控制芯片 1产生调频控制； 同时， 环路电压 Vloop使电压匹配模块 2 作用于移相脉宽调制控制芯片 1产生调宽控制。
当 Vloop大于 bV并且小于 cV时， 这时， 变换器工作在介于轻载 与重载之间的状态，例如 ， Vloop的工作电压区间为 [5， 7]V ， Vloop 经过电压匹配模块 2后， 能通过移相来调节同时开通的两个开关管的 等效占空比， 即能进行 PWM控制。 占空比从 Db%变化到 50%, 当环 路电压为 bV时， 所对应的占空比为 Db%， 环路电压为 cV时， 所对 应的占空比为最大值 Dmax=50%。
同时， 如图 8所示， 第二二极管 D701导通， 第一二极管 D702关 断， 则环路电压 Vloop经过由电阻 R701、 R702和 R703构成的电阻控 制模块 3改变 RT端对外的等效电阻而改变工作频率， 即能进行 PFM 控制， 环路电压 Vloop从 bV增大至 eV时， 随 Vloop的增大， 工作频 率降低， Vloop为 bV时， 移相脉宽调制控制芯片 1输出脉冲的频率为 最大值 fmax， Vloop为 cV时， 频率降至 fc。
所以 Vloop在电压区间 [b， c]内， 能够同时进行 PWM和 PFM控 制， 谐振电路工作在既调频又调宽方式。
BA3、 当环路电压 Vloop工作于第三区间时， 如图 8所示， 即 Vloop大于 cV 并且小于 dV,环路电压 Vloop使电压匹配模块 2作用于移相脉宽调制 控制芯片 1产生最大占空比 Dmax，环路电压 Vloop使电阻控制模块 3 作用于移相脉宽调制控制芯片 1产生调频控制， 这时， 第三区间为谐 振电路重载时环路电压 Vloop的调频电压区间。 当 Vloop大于 cV并且小于 dV时，这时，变换器工作在重载状态， 例如 ， Vloop的工作电压区间为 [7， 12]V, Vloop经过电压匹配模块 2后， 如图 8所示， 同时开通的两个开关管的等效占空比均为 50%。
同时， 如图 8所示， 第二二极管 D701导通， 第一二极管 D702关 断， 则 Vloop经过电阻 R701、 R702和 R703改变 RT端对外的等效电 阻而改变工作频率， 即能进行 PFM控制， 随 Vloop的增大， 工作频率 降低。 Vloop的值为 dV时，因为 dV为控制环路输出电压最大值， Vloop 经过电阻 R701、 R702和 R703使 RT端对外的等效电阻最大， 所以移 相脉宽调制控制芯片 1输出脉冲的频率是最小值 fmin。 在上述实施例中， 反映了采用移相脉宽调制控制芯片 1 对全桥谐振电路 的控制， 本发明也可以对半桥谐振电路进行控制， 对于如图 9所示的半桥串 联谐振电路示意图， 在实际应用中， 只需要对移相脉宽调制控制芯片 1 的四 个输出信号 PWM1、 PWM2、 PWM3、 PWM4进行分组合并处理， 例如， 对 输出信号 PWM1和 PWM3、 PWM2和 PWM4分别进行逻辑与， 所产生的两 路输出分别对图 9中半桥串联谐振电路的 Sl、 S2进行调制即可。 这样， 通过上述实施例及有关说明详细地阐述了利用移相脉宽调制控制 芯片 1， 通过电压匹配模块 2和电阻控制模块 3对谐振电路实现调频、调宽及 其混合的控制模式。 实施例 3 :
如图 11和图 12所示， 本发明包括脉宽调制控制芯片 10， 如图 11所示， 脉宽调制控制芯片 10的 COMP端、 RT端分别连接电压匹配模块 2和电阻控 制模块 3，电压匹配模块 2和电阻控制模块 3根据输入电压（即环路电压 Vloop) 向脉宽调制控制芯片 10提供相应的控制参数， 脉宽调制控制芯片 10对谐振 电路进行相应调制， 如图 1所示的半桥串联谐振电路， 脉宽调制控制芯片 10 的两个输出信号 PWM1、 PWM2对半桥串联谐振电路的 Sl、 S2进行调制。
如图 11和图 12所示， 电压匹配模块 2和电阻控制模块 3均以环路电压 Vloop为输入电压， 环路电压 Vloop为谐振电路输出电压 Vo经过采样电路和 调节器（如 PID调节器）后的输出电压， 电压匹配模块 2包括运放 U701和第 —分压子模块 21， 其中，
如图 12所示， 运放 U701的反向端与地之间连接电阻 R714, 并与输出端 之间连接电阻 R711。 如图 12所示， 运放 U701的正向端与第一分压子模块 21的分压端相连， 该第一分压子模块 21包括串联电阻 R712、 R713, 并连接于环路电压 Vloop 与地之间， 电阻 R712和电阻 R713的连接点与运放 U701的正向端直接相连。
如图 12所示， 运放 U701的输出端与脉宽调制控制芯片 10中 COMP端 之间连接限流电路 22，该限流电路 22包括串接电阻 R715、电阻 R716和电容 C1 , 电阻 R715和电阻 R716串联于运放 U701的输出端与 RT端之间， 电阻 715和电阻 R716的连接点与地之间连接电容 Cl， 其中电容 C1起到稳压、 滤波的作用。
电压匹配模块 2将环路电压 Vloop对应的调宽电压区间与脉宽调制控制 芯片 10的 COMP端进行调宽的电压范围相匹配，至于匹配中的具体比例参数 等， 可结合脉宽调制控制芯片 10的参数， 以及半桥串联谐振电路的工作参数 设置。
如图 11和图 12所示， 该电阻控制模块 3包括第二分压子模块 31， 第二 分压子模块 31包括串联电阻 R701、 R702, 并连接于环路电压 Vloop与地之 间， 电阻 R701、 R702之间的连接点与 RT端之间连接电阻 R703, 电阻控制 模块 3连接于环路电压 Vloop与脉宽调制控制芯片 10的 RT端之间， 使 RT 端对外的等效电阻随环路电压 Vloop的变化进行相应调整。
本实施例的工作过程如下：
AB1、 当环路电压 Vloop工作于第一区间时， 如图 13所示， 即 V op大于 xV并且小于 yV， 环路电压 Vloop使电阻控制模块 3作用于脉宽调制 控制芯片 10产生调频控制； 同时，环路电压 Vloop使电压匹配模块 2 作用于脉宽调制控制芯片 10产生调宽控制。
当 Vloop大于 xV并且小于 yV时， 这时， 变换器工作在轻载或 空载状态， 例如 ， Vloop的工作电压区间为 [2， 6]V ， Vloop经过电 压匹配模块 2后，如图 10b所示，能通过调宽来调节开关管的占空比， 即能进行脉宽调制 （PWM: Pulse Width Modulation)控制。 占空比从 0%变化到 50%， 当环路电压为 xV时， 所对应的占空比为 0%， 环路 电压为 yV时， 所对应的占空比为最大值 Dmax=50%。
同时， 经过由电阻 R701、 R702和 R703构成的电阻控制模块 3 改变 RT端对外的等效电阻而改变工作频率， 即能进行 PFM控制， 环 路电压 Vloop从 xV增大至 yV时， 由于 xV为控制环路输出电压最小 值， Vloop经过电阻 R701、 R702和 R703使 RT端对外的等效电阻最 小， 所以脉宽调制控制芯片 10输出脉冲的频率是最大值 fmaX。 所以 Vloop在电压区间 [x， y]内， 能够同时进行 PWM和 PFM控 制， 谐振电路工作在既调频又调宽方式。
显然，当 Vloop小于 xV时， Vloop经过由运放 U701及其外围电 路构成的电压匹配模块后， 使得开关管的占空比为零。
AB2、 当环路电压 Vloop工作于第二区间时， 如图 13所示， 即 Vloop大于 yV并且小于 zV， 环路电压 Vloop使电压匹配模块 2作用于脉宽调制 控制芯片 1产生最大占空比 Dmax， 环路电压 Vloop使电阻控制模块 3作用于脉宽调制控制芯片 10产生调频控制。
当 Vloop大于 yV并且小于 zV时， 这时， 变换器工作在重载状 态， 例如 ， 此时 Vloop的工作电压区间为 [6， 12]V, Vloop经过电压 匹配模块 2后， 如图 10a所示， 两个开关管的占空比均为 50%。
同时， Vloop经过电阻 R701、 R702和 R703改变 RT端对外的等 效电阻而改变工作频率， 即能进行 PFM控制， 随 Vloop的增大， 工 作频率降低。 Vloop的值为 zV时， 因为 zV为控制环路输出电压最大 值， Vloop经过电阻 R701、 R702和 R703使 RT端对外的等效电阻最 大， 所以脉宽调制控制芯片 10输出脉冲的频率是最小值 fmin。 实施例 4:
本实施例与实施例 3的区别在于： 在本实施例中， 如图 14所示， 电阻控 制模块 3还包括比较电压子模块 32，该比较电压子模块 32产生参考电平 Vref, 参考电平 Vref、环路电压 Vloop与第二分压子模块 31的输入端之间分别连接 第一二极管 D702和第二二极管 D701， 第一二极管 D702和第二二极管 D701 的负极与第二分压子模块 31相连。
如图 14所示，比较电压子模块 32采用精密基准元件 U702提供参考电平 Vref, 通过电阻 R704、 R705、 R706对电源 Vc分压， 由电阻 R706的压降向 精密基准元件 U702提供工作电压， 在参考电平 Vref 与地之间还连有滤波电 容 C2。 '
本实施例的工作过程如下：
BB1、 当环路电压 Vloop工作于第一区间时， 如图 15所示， 即 Vloop大于 aV并且小于 bV, 电阻控制模块 3对脉宽调制控制芯片 1产生恒定等 效电阻并使其输出脉冲最大值 fmax， 环路电压 Vloop使电压匹配模 块 2作用于脉宽调制控制芯片 10产生调宽控制。
如图 15所示， Vloop在电压区间 [a， b]内， 这时， 变换器工作在 轻载或空载状态， 例如， 此时 Vloop的工作电压区间为 [2， 5]V， 由于 参考电平 Vref为 bV (此时 bV取值为 5V)， 第二二极管 D701关断， 第一二极管 D702导通， 基准电压 Vref (电压值的大小为 bV)保持不 变， RT 端对外的等效电阻也保持恒定不变， 所以脉宽调制控制芯片 10输出脉冲的频率保持最大值 fmax。
显然， 当 Vloop小于 aV时， Vloop经过由 U701及其外围电路构 成的电压匹配模块后， 开关管的占空比为零。
同时， 如图 15所示， Vloop经过电压匹配模块 2后， 能调节开 关管的占空比， 即能进行 PWM控制， 当 Vloop等于 aV时， 占空比 为 0%， 随 Vloop由 aV增大至 bV， 占空比由 0%增至 Db%。
当环路电压 Vloop工作于第二区间时， 如图 15所示， 即 Vloop大于 bV并且小于 cV， 环路电压 Vloop使电阻控制模块 3作用于脉宽调制 控制芯片 10产生调频控制； 同时，环路电压 Vloop使电压匹配模块 2 作用于脉宽调制控制芯片 10产生调宽控制。
当 Vloop大于 bV并且小于 cV时， 这时， 变换器工作在介于轻 载与重载之间的状态， 例如 ， Vloop 的工作电压区间为 [5 , 7]V ， Vloop经过电压匹配模块 2后， 能开关管的占空比， 即能进行 PWM 控制。 占空比从 Db%变化到 50%， 当环路电压为 bV时， 所对应的占 空比为 Db%， 环路电压为 cV 时， 所对应的占空比为最大值 Dmax=50%。
同时， 如图 15所示， 第二二极管 D701导通， 第一二极管 D702 关断， 则环路电压 Vloop经过由电阻 R701、 R702和 R703构成的电 阻控制模块 3改变 RT端对外的等效电阻而改变工作频率， 即能进行 PFM控制， 环路电压 Vloop从 bV增大至 cV时， 随 Vloop的增大， 工作频率降低， Vloop为 bV时， 脉宽调制控制芯片 10输出脉冲的频 率为最大值 fmax， Vloop为 cV时， 频率降至 fc。
所以 Vloop在电压区间 [b， c]内， 能够同时进行 PWM和 PFM控 制， 谐振电路工作在既调频又调宽方式。
当环路电压 Vloop工作于第三区间时， 如图 15所示， 即 Vloop大于 cV并且小于 dV， 环路电压 Vloop使电压匹配模块 2作用于脉宽调制 控制芯片 10产生最大占空比 Dmax,环路电压 Vloop使电阻控制模块 3作用于脉宽调制控制芯片 10产生调频控制。
当 Vloop大于 cV并且小于 dV时， 这时， 变换器工作在重载状 态， 例如 ， Vloop的工作电压区间为 [7， 12]V， Vloop经过电压匹配 模块 2后， 如图 15所示， 开关管的占空比为 50%。
同时， 如图 15所示， 第二二极管 D701导通， 第一二极管 D702 关断， 则 Vloop经过电阻 R701、 R702和 R703改变 RT端对外的等效 电阻而改变工作频率， 即能进行 PFM控制， 随 Vloop的增大， 工作 频率降低。' Vloop的值为 dV时，因为 dV为控制环路输出电压最大值， Vloop经过电阻 R701、 R702和 R703使 RT端对外的等效电阻最大， 所以脉宽调制控制芯片 10输出脉冲的频率是最小值 fmin。 在上述实施例中， 反映了采用脉宽调制控制芯片 10对半桥谐振电路的控 制， 本发明也可以对全桥谐振电路进行控制， 对于如图 1 所示的全桥串联谐 振电路示意图， 在实际应用中， 只需要使脉宽调制控制芯片 10的两个输出信 号 PWM1、 PWM2对图 1中全桥串联谐振电路的 Sl、 S2、 S3、 S4进行分组 调制即可， 例如， 脉宽调制控制芯片 10的输出信号 PWM1 同时控制全桥串 联谐振电路的 S1和 S3，脉宽调制控制芯片 10的输出信号 PWM2同时控制全 桥串联谐振电路的 S2和 S4即可。
在本发明中， 将控制芯片输出脉冲的最大占空比描述为 50%， 同一桥臂 的两开关管互补导通，且总的占空比为 1， 这种描述方法的条件是不计两路驱 动脉冲的死区时间。 为了使同一桥臂的两开关管不直通， 要在两路驱动脉冲 之间设定有一定的死区时间， 所以实际上控制芯片输出脉冲的最大占空比一 定会小于 50%， 同一桥臂上的两个开关管互补导通， 两者总的占空比小于 1 , 同时为了提高谐振电路的工作特性， 可以通过电路的设计调整两路驱动脉冲 之间的死区时间， 因此， 在前面的描述中反映了理想状态， 但对本发明的电 路设计没有影响。
这样， 通过上述实施例及有关说明详细地阐述了利用脉宽调制控制芯片 10， 通过电压匹配模块 2和电阻控制模块 3对谐振电路实现调频、 调宽及其 混合的控制模式。

Claims

权利要求书
1. 一种谐振电路调制控制系统， 其特征在于： 它采用谐振电路的控制芯片 与有关控制装置连接， 所述控制装置向控制芯片提供电压匹配和电阻控制， 该控制装置根据输入电压向调制控制芯片提供控制参数， 控制芯片对谐振电 路进行相应调制。
2. 根据权利要求 1所述的谐振电路调制控制系统， 其特征在于： 所述控制 芯片为移相脉宽调制控制芯片， 所述移相脉宽调制控制芯片中的 PWM发生 器、 振荡器分别连接所述控制装置中的电压匹配模块和电阻控制模块， 所述 的电压匹配模块和电阻控制模块根据输入电压向移相脉宽调制控制芯片提供 控制参数， 移相脉宽调制控制芯片对谐振电路进行相应调制。
3. 根据权利要求 2所述的谐振电路调制控制系统， 其特征在于：
所述的电压匹配模块和电阻控制模块均以环路电压 Vloop为输入电压； 所述的电压匹配模块将环路电压 Vloop对应的移相电压区间与移相脉宽 调制控制芯片的 PWM发生器进行移相的电压范围相匹配；
所述的电阻控制模块连接于环路电压 Vloop与移相脉宽调制控制芯片的 振荡器之间， 使振荡器对外的等效电阻随环路电压 Vloop 的变化进行相应调 整。
4. 根据权利要求 3所述的谐振电路调制控制系统， 其特征在于： 所述的电 压匹配模块包括运放 （U701 )、 第一分压子模块 （21 ) 和限流电路 （22)， 其 中，
所述运放 （U701 ) 的反向端与地之间连接电阻 （R714) , 并与输出端之 间连接电阻 （R711 );
所述运放 （U701 ) 的同向端与第一分压子模块 （21 ) 的分压端相连； 所述运放 （U701 ) 的输出端与移相脉宽调制控制芯片的 PWM发生器之 间连接限流电路 （22)。
5. 根据权利要求 4所述的谐振电路调制控制系统， 其特征在于： 所述的电 阻控制模块包括第二分压子模块 （31 )， 该第二分压子模块 （31 ) 的分压端与 所述移相脉宽调制控制芯片的振荡器之间连接电阻 （R703 )。
6. 根据权利要求 1所述的谐振电路调制控制系统， 其特征在于： 所述控制 芯片为脉宽调制控制芯片，所述脉宽调制控制芯片的 COMP端、 RT端分别连 接所述控制装置中的电压匹配模块和电阻控制模块， 所述的电压匹配模块和 电阻控制模块根据输入电压向脉宽调制控制芯片提供相应的工作数据， 脉宽 调制控制芯片对谐振电路进行相应调制。
7. 根据权利要求 6所述的谐振电路调制控制系统， 其特征在于- 所述的电压匹配模块和电阻控制模块均以环路电压 Vloop为输入电压； 所述的电压匹配模块将环路电压 Vloop对应的调宽电压区间与脉宽调制 控制芯片 COMP端进行调宽的电压范围相匹配；
所述的电阻控制模块连接于环路电压 Vloop与脉宽调制控制芯片的 RT端 之间， 使 RT端对外的等效电阻随环路电压 Vloop的变化进行相应调整。
8. 根据权利要求 7所述的谐振电路调制控制系统， 其特征在于： 所述的电 压匹配模块包括运放 （U701 )、 第一分压子模块 （21 ) 和限流电路 （22)， 其 中，
所述运放 （U701 ) 的反向端与地之间连接电阻 （R714), 并与输出端之 间连接电阻 （R711 );
所述运放 （U701 ) 的同向端与第一分压子模块的分压端相连；
所述运放（U701 ) 的输出端与脉宽调制控制芯片 COMP端之间连接限流 电路 (22)。
9. 根据权利要求 8所述的谐振电路调制控制系统， 其特征在于： 所述的电 阻控制模块包括第二分压子模块 （31 )， 该第二分压子模块 （31 ) 的分压端与 所述移相脉宽调制控制芯片的振荡器之间连接电阻 （R703 )。
10. 根据权利要求 4或 8所述的谐振电路调制控制系统， 其特征在于： 所述 的第一分压子模块包括串联电阻（R712)、 (R713 ), 并连接于环路电压 Vloop 与地之间。
1 1. 根据权利要求 5或 9所述的谐振电路调制控制系统， 其特征在于： 所述 的第二分压子模块包括串联电阻（R701 )、 (R702) , 并连接于环路电压 Vloop 与地之间。
12. 根据权利要求 5或 9所述的谐振电路调制控制系统， 其特征在于： 所述 的电阻控制模块还包括比较电压子模块 （32), 所述比较电压子模块 （32) 产 生参考电平 Vref， 所述的参考电平 Vref、 环路电压 Vloop与第二分压子模块
( 31 ) 的输入端之间分别连接第一二极管 （D702) 和第二二极管 （D701 ), 所述的第一二极管 （D702) 和第二二极管 （D701 ) 的负极与第二分压子模块 (31 ) 相连。
13. 一种谐振电路调制控制方法，其特征在于： 采用移相脉宽调制控制芯片， 通过电压匹配模块和电阻控制模块对谐振电路实现调频、 调宽及其混合的控 制模式。
14. 根据权利要求 13所述的谐振电路调制控制方法， 其特征在于： 它采用如 下步骤：
AA1、 当环路电压 Vloop工作于第一区间时， 环路电压 Vloop使电阻控制模 块作用于移相脉宽调制控制芯片产生调频控制； 同时，环路电压 Vloop 使电压匹配模块作用于移相脉宽调制控制芯片产生调宽控制；
AA2、 当环路电压 Vloop工作于第二区间时， 环路电压 Vloop使电压匹配模 块作用于移相脉宽调制控制芯片产生最大占空比 Dmax， 环路电压 Vloop使电阻控制模块作用于移相脉宽调制控制芯片产生调频控制。
15. 根据权利要求 13所述的谐振电路调制控制方法，其特征在于： 它采用如 下步骤：
BA1、 当环路电压 Vloop工作于第一区间时， 电阻控制模块对移相脉宽调制 控制芯片产生恒定等效电阻并使其输出脉冲频率最大值 fmax， 环路电 压 Vloop使电压匹配模块作用于移相脉宽调制控制芯片产生调宽控制;
BA2、 当环路电压 Vloop工作于第二区间时， 环路电压 Vloop使电阻控制模 块作用于移相脉宽调制控制芯片产生调频控制； 同时，环路电压 Vloop 使电压匹配模块作用于移相脉宽调制控制芯片产生调宽控制；
BA3、 当环路电压 Vloop工作于第三区间时， 环路电压 Vloop使电压匹配模 块作用于移相脉宽调制控制芯片产生最大占空比 Dmax， 环路电压 Vloop使电阻控制模块作用于移相脉宽调制控制芯片产生调频控制。
16. 根据权利要求 14或 15所述的谐振电路调制控制方法， 其特征在于： 所 述的最大占空比 Dmax为 50%。
17. 根据权利要求 14或 15所述的谐振电路调制控制方法， 其特征在于： 所 述的第一区间为谐振电路空载或轻载时环路电压 Vloop的移相电压区间。
18. 根据权利要求 15所述的谐振电路调制控制方法， 其特征在于： 所述的第 三区间为谐振电路重载时环路电压 Vloop的调频电压区间。
19. 一种谐振电路调制控制方法， 其特征在于： 采用脉宽调制控制芯片， 通 过电压匹配模块和电阻控制模块对谐振电路实现调频、 调宽及其混合的控制 模式。
20. 根据权利要求 19所述的谐振电路调制控制方法， 其特征在于： 它采用如 下步骤：
AB1、 当环路电压 Vloop工作于第一区间时， 环路电压 Vloop使电阻控制模 块作用于脉宽调制控制芯片产生调频控制； 同时， 环路电压 Vloop使 电压匹配模块作用于脉宽调制控制芯片产生调宽控制； AB2、 当环路电压 Vloop工作于第二区间时， 环路电压 Vloop使电压匹配模 块作用于脉宽调制控制芯片产生最大占空比 Dmax， 环路电压 Vloop 使电阻控制模块作用于脉宽调制控制芯片产生调频控制。
21. 根据权利要求 19所述的谐振电路调制控制方法，其特征在于：它采用如 下步骤：
当环路电压 Vloop工作于第一区间时， 电阻控制模块对脉宽调制控制 芯片产生恒定等效电阻并使其输出脉冲频率最大值 fmax， 环路电压 Vloop使电压匹配模块作用于脉宽调制控制芯片产生调宽控制；
BB2、 当环路电压 Vloop工作于第二区间时， 环路电压 Vloop使电阻控制模 块作用于脉宽调制控制芯片产生调频控制； 同时， 环路电压 Vloop使 电压匹配模块作用于脉宽调制控制芯片产生调宽控制；
BB3、 当环路电压 Vloop工作于第三区间时， 环路电压 Vloop使电压匹配模 块作用于脉宽调制控制芯片产生最大占空比 Dmax， 环路电压 Vloop 使电阻控制模块作用于脉宽调制控制芯片产生调频控制。
22. 根据权利要求 20或 21所述的谐振电路调制控制方法， 其特征在于： 所 述的最大占空比 Dmax为 50%。
23. 根据权利要求 20或 21所述的谐振电路调制控制方法， 其特征在于： 所 述的第一区间为谐振电路空载或轻载时环路电压 Vloop的调宽电压区间。
24. 根据权利要求 21所述的谐振电路调制控制方法，其特征在于：所述的第 三区间为谐振电路重载时环路电压 Vloop的调频电压区间。
25. 根据权利要求 20或 21所述的谐振电路调制控制方法， 其特征在于： 所 述的环路电压 Vloop为谐振电路输出电压 Vo经过采样电路和调节器后的输出 电压。
PCT/CN2007/000509 2006-04-14 2007-02-13 Method and system of syntonic circuit modulation controlling Ceased WO2007118401A1 (en)

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