WO2007131256A3 - Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil - Google Patents

Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil Download PDF

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Publication number
WO2007131256A3
WO2007131256A3 PCT/AT2007/000234 AT2007000234W WO2007131256A3 WO 2007131256 A3 WO2007131256 A3 WO 2007131256A3 AT 2007000234 W AT2007000234 W AT 2007000234W WO 2007131256 A3 WO2007131256 A3 WO 2007131256A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
printed circuit
electronic component
contact
fixing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/AT2007/000234
Other languages
English (en)
French (fr)
Other versions
WO2007131256A2 (de
Inventor
Hannes Voraberger
Gerhard Schmid
Markus Riester
Johannes Stahr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&S Austria Technologie und Systemtechnik AG
Original Assignee
AT&S Austria Technologie und Systemtechnik AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&S Austria Technologie und Systemtechnik AG filed Critical AT&S Austria Technologie und Systemtechnik AG
Priority to JP2009510227A priority Critical patent/JP2009537968A/ja
Priority to US12/227,364 priority patent/US8541690B2/en
Priority to CA002651649A priority patent/CA2651649A1/en
Priority to CN200790000005.8U priority patent/CN201238050Y/zh
Priority to AT07718446T priority patent/ATE504943T1/de
Priority to DE502007006885T priority patent/DE502007006885D1/de
Priority to EP07718446A priority patent/EP2018666B1/de
Publication of WO2007131256A2 publication Critical patent/WO2007131256A2/de
Publication of WO2007131256A3 publication Critical patent/WO2007131256A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H05K1/186—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/005—Punching of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Bei einem Verfahren zum Festlegen eines elektronischen Bauteils (3) auf einer Leiterplatte (2) bzw. Kontaktieren des elektronischen Bauteils (3) mit der Leiterplatte (2) sind folgende Schritte vorgesehen: - Bereitstellen der Leiterplatte (2) mit einer Mehrzahl von Kontakt- bzw. Anschlußflächen (8), - Bereitstellen des elektronischen Bauteils (3) mit einer der Mehrzahl von Kontakt- bzw. Anschlußflächen (8) der Leiterplatte (2) entsprechenden Anzahl von Kontakt- bzw. Anschlußstellen (5) mit einem gegenüber dem Abstand der Kontakt-bzw. Anschlußflächen (8) der Leiterplatte (2) verringerten gegenseitigen Abstand, und - Anordnen bzw. Ausbilden wenigstens einer Zwischenlage (4) zum Entflechten der Kontakt- bzw. Anschlußstellen (5) des elektronischen Bauteils (3) zwischen den Kontakt- bzw. Anschlußflächen (8) der Leiterplatte (2) und den Kontakt-bzw. Anschlußstellen (5) des elektronischen Bauteils (3). Weiters werden ein Verfahren zur Herstellung einer Zwischenlage (4) zum Entflechten als auch ein eine Leiterplatte (2) und einen elektronischen Bauteil (3) unter Verwendung der Zwischenlage (4) zum Entflechten aufweisendes System zur Verfügung gestellt.
PCT/AT2007/000234 2006-05-16 2007-05-15 Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil Ceased WO2007131256A2 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2009510227A JP2009537968A (ja) 2006-05-16 2007-05-15 プリント回路基板上に電子部品を固定する方法ならびにプリント回路基板および少なくとも１つの電子部品を有するシステム
US12/227,364 US8541690B2 (en) 2006-05-16 2007-05-15 Method for fixing an electronic component on a printed circuit board and system comprising a printed circuit board and at least one electronic component
CA002651649A CA2651649A1 (en) 2006-05-16 2007-05-15 Method for fixing an electronic component on a printed circuit board and system comprising a printed circuit board and at least one electronic component
CN200790000005.8U CN201238050Y (zh) 2006-05-16 2007-05-15 包含印制电路板和至少一个电子构件的系统
AT07718446T ATE504943T1 (de) 2006-05-16 2007-05-15 Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte, herstellungverfahren einer trägerlage und einer zwischenlage, sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil
DE502007006885T DE502007006885D1 (de) 2006-05-16 2007-05-15 Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte, herstellungverfahren einer trägerlage und einer zwischenlage, sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil
EP07718446A EP2018666B1 (de) 2006-05-16 2007-05-15 Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte, herstellungverfahren einer trägerlage und einer zwischenlage, sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ATGM393/2006 2006-05-16
AT0039306U AT9551U1 (de) 2006-05-16 2006-05-16 Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil

Publications (2)

Publication Number Publication Date
WO2007131256A2 WO2007131256A2 (de) 2007-11-22
WO2007131256A3 true WO2007131256A3 (de) 2008-04-17

Family

ID=38456750

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AT2007/000234 Ceased WO2007131256A2 (de) 2006-05-16 2007-05-15 Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil

Country Status (10)

Country Link
US (1) US8541690B2 (de)
EP (1) EP2018666B1 (de)
JP (1) JP2009537968A (de)
KR (1) KR20090007410A (de)
CN (1) CN201238050Y (de)
AT (2) AT9551U1 (de)
CA (1) CA2651649A1 (de)
DE (1) DE502007006885D1 (de)
TW (1) TW200814884A (de)
WO (1) WO2007131256A2 (de)

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US9912448B2 (en) * 2012-02-13 2018-03-06 Sentinel Connector Systems, Inc. Testing apparatus for a high speed communications jack and methods of operating the same
DE102015226135A1 (de) * 2015-12-21 2017-06-22 Robert Bosch Gmbh Verfahren zum Herstellen eines elektrischen Schaltungsmoduls und elektrisches Schaltungsmodul
EP3358359B1 (de) * 2017-02-01 2019-08-28 Siemens Aktiengesellschaft Leiterplatte mit implantiertem optischen stromsensor
CN207369413U (zh) * 2017-09-27 2018-05-15 京东方科技集团股份有限公司 一种线路板、显示驱动装置及显示装置
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JP2009537968A (ja) 2009-10-29
DE502007006885D1 (de) 2011-05-19
AT9551U1 (de) 2007-11-15
US8541690B2 (en) 2013-09-24
WO2007131256A2 (de) 2007-11-22
EP2018666B1 (de) 2011-04-06
EP2018666A2 (de) 2009-01-28
KR20090007410A (ko) 2009-01-16
TW200814884A (en) 2008-03-16
ATE504943T1 (de) 2011-04-15
CA2651649A1 (en) 2007-11-22
US20090101398A1 (en) 2009-04-23

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