WO2007134510A1 - A single-desk power supply and a method for providing a power supply - Google Patents

A single-desk power supply and a method for providing a power supply Download PDF

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Publication number
WO2007134510A1
WO2007134510A1 PCT/CN2007/000789 CN2007000789W WO2007134510A1 WO 2007134510 A1 WO2007134510 A1 WO 2007134510A1 CN 2007000789 W CN2007000789 W CN 2007000789W WO 2007134510 A1 WO2007134510 A1 WO 2007134510A1
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Prior art keywords
converter
power supply
isolated
board
control signal
Prior art date
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PCT/CN2007/000789
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English (en)
French (fr)
Inventor
Chengyong Li
Liyuan Zhang
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP18170972.6A priority Critical patent/EP3487054A1/en
Priority to ES07711077.3T priority patent/ES2687248T3/es
Priority to EP07711077.3A priority patent/EP2019479B1/en
Publication of WO2007134510A1 publication Critical patent/WO2007134510A1/zh
Priority to US12/246,867 priority patent/US7847528B2/en
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for DC mains or DC distribution networks
    • H02J1/08—Three-wire DC power distribution systems; Systems having more than three wires
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for DC mains or DC distribution networks
    • H02J1/08—Three-wire DC power distribution systems; Systems having more than three wires
    • H02J1/082—DC supplies with two or more different DC voltage levels

Definitions

  • the present invention relates to power supply technologies, and in particular, to a single board power supply architecture and a power supply method. Background of the invention
  • FIG. 1 is a power supply architecture diagram of a prior art 1.
  • the single board power supply architecture in Figure 1 includes analog non-isolated DC/DC converters 11, 12, 13 and single board chips 14.
  • the analog non-isolated DC/DC converters 11, 12, 13 are analog non-isolated DC/DC converters or analog non-isolated linear DC/DC converters.
  • the single-chip chip 14 has a low-voltage bus voltage such as 12V, 5V or 3.3V
  • the low-voltage bus voltage of 12V, 5V or 3.3V converted by the pre-stage power converter can be directly used; when there are other voltage requirements, Then, the analog non-isolated DC/DC converter needs to convert the low-voltage bus voltage of 12V, 5V or 3.3V into the voltage required by the single-board chip 14.
  • FIG. 2 is a power supply architecture diagram of the prior art 2.
  • the single board power supply frame in Figure 2 The structure includes analog non-isolated DC/DC converters 21, 22, 23 and a single board chip 24, an analog isolated DC/DC converter 25.
  • the analog non-isolated DC/DC converters 21, 22, 23 are analog non-isolated DC/DC converters or analog non-isolated linear DC/DC converters.
  • the 48V bus voltage is converted into 12V, 5V or 3.3V low voltage bus power through the analog isolated DC/DC converter 25.
  • the single chip 24 When the single chip 24 has a low voltage bus voltage such as 12V, 5V or 3.3V, the single The chip chip 24 directly uses a low voltage bus voltage such as 12V, 5V or 3.3V; when there are other voltage requirements, it needs to be 12V, 5V or 3.3 by analog non-isolated DC/DC converter or analog non-isolated linear DC/DC converter. The voltage of the low voltage bus such as V is converted to the voltage required by the single chip.
  • each timing control driving signal is usually generated by a currently dedicated timing control chip, and each timing control driving signal can respectively control the MOS tube power driving amplifiers 305, 306, 307, 308 are in an on or off state to achieve timing control of the current input to the single chip 313.
  • the object of the present invention is to provide a single-board power supply architecture and a power supply method for uniformly, timely, and effectively monitoring the power output of a single board.
  • a single-board power supply architecture includes a connected operational processor and a DC/DC converter (C);
  • the arithmetic processor is configured to send a control signal for controlling a power output to the DC/DC converter (C);
  • the DC/DC converter (C) is configured to convert the received bus voltage to a desired supply voltage output according to the received control signal.
  • a method for providing a single board power supply is:
  • the arithmetic processor sends a control signal for controlling the power output to the DC/DC converter (C), and the DC/DC converter (C) converts the received bus voltage to the required power voltage output according to the received control signal.
  • the single-board power supply architecture and the power supply method provided by the present invention can be sent by the arithmetic processor to the DC/DC converter to control the output of the control power supply, and then received by the DC/DC converter.
  • the control signal converts the received bus voltage to the required supply voltage output. It can be seen that the architecture and method of the present invention can monitor the power output of the single board in a unified, timely, and effective manner.
  • FIG. 3 is a schematic diagram of timing control of the prior art
  • FIG. 4 is a schematic diagram of the power supply architecture of the present invention.
  • Figure 5 is a diagram showing a power supply architecture of Embodiment 1 of the present invention.
  • Embodiment 6 is a power supply architecture diagram of Embodiment 2 of the present invention.
  • Embodiment 7 is a power supply architecture diagram of Embodiment 3 of the present invention.
  • Embodiment 8 is a power supply architecture diagram of Embodiment 4 of the present invention.
  • Embodiment 9 is a power supply architecture diagram of Embodiment 5 of the present invention.
  • Figure 10 is a diagram showing the power supply architecture of Embodiment 6 of the present invention.
  • Embodiment 7 is a power supply architecture diagram of Embodiment 7 of the present invention.
  • Figure 12 is a diagram showing the power supply architecture of Embodiment 8 of the present invention.
  • FIG. 13 is a diagram showing the power supply architecture of Embodiment 9 of the present invention. Mode for carrying out the invention
  • the single-board power supply architecture and the power supply method provided by the present invention can be sent by the arithmetic processor to the DC/DC converter to control the output of the control power supply, and then received by the DC/DC converter according to the received control signal.
  • the bus voltage is converted to the required supply voltage output.
  • the operation processor may further monitor the power output and report the monitoring result to the connected upper computer; and control the timing of the plurality of power output converted by the DC/DC converter by controlling the time when the control signal is sent. .
  • FIG. 4 the core idea of the present invention can be embodied by FIG.
  • the microprocessor (A), the MOS transistor power driver amplifier (B), the DC/DC converter (C), and the single-chip chip (D) are sequentially connected, and the microprocessor (A) is also connected to the upper computer (E).
  • the microprocessor (A) generates a PWM pulse with adjustable duty cycle, and the PWM pulse is amplified by the MOS tube power drive amplifier (B) to drive the DC/DC converter (C) to convert the received bus voltage.
  • the method of driving the DC/DC converter (C) to realize voltage and current conversion is generally as follows: MOS tube power drive amplifier (B) sends a GATE signal formed by amplifying the PWM pulse to a DC/DC converter (C), the GATE signal triggers the DC/DC converter (C) for voltage and current conversion.
  • the microprocessor (A) can monitor the voltage and current output to the single chip (D), and report the monitoring result to the host computer (E) through the communication interface.
  • the microprocessor (A) can adjust the voltage and current output from the DC/DC converter (C) by sending a PWM pulse to the MOS tube power drive amplifier (B).
  • the number of non-isolated DC/DC converters and MOS tube power drive amplifiers in the drawings corresponding to the embodiments of the present invention are generally three;
  • the number of the non-isolated DC/DC converter and the MOS tube power drive amplifier does not have to be three, and may be one or more.
  • FIG. 5 is a diagram showing a power supply architecture of Embodiment 1 of the present invention.
  • a plurality of MOS tube power drive amplifiers and non-isolated DC/DC converters are sequentially connected between the microprocessor A51 and the single chip; between each MOS tube power drive amplifier and the non-isolated DC/DC converter Then it is a series relationship.
  • the microprocessor A51 can be further connected to the host computer E51.
  • the digital processor A51 generates a PWM pulse with adjustable duty ratio, and the FWM pulse is amplified by three MOS tube power drive amplifiers B51 ⁇ B53 respectively, and then drives the non-isolated DC/DC converters C51 ⁇ C53 respectively.
  • the received low voltage bus voltage of 12V, 5V or 3.3V is converted into the chip voltage required for the single chip D51.
  • the low voltage bus voltage can be directly input to the single chip D51.
  • the manner of driving the non-isolated DC/DC converter to implement voltage and current conversion is generally: the MOS tube power drive amplifier sends the GATE signal formed after the PWM pulse is amplified to the non-isolated DC/DC conversion.
  • the GATE signal triggers a non-isolated DC/DC converter to perform voltage and current conversion.
  • the microprocessor A51 can monitor the voltage and current outputted to the single chip D51 by sampling, etc., and report the monitoring result such as the sampling result to the host computer E51 periodically or in real time through the communication interface.
  • the microprocessor A51 can adjust the voltage and current output by the non-isolated DC/DC converter by transmitting a PWM pulse to the MOS tube power drive amplifier.
  • the microprocessor A51 knows that the voltage outputted by the non-isolated DC/DC converter C51 is too large, and the microprocessor A51 sends a PWM pulse for reducing the voltage to the MOS tube power drive amplifier B51; the PWM pulse passes through the MOS After the tube power drives the amplifier B51, the non-isolated DC/DC converter C51 is driven to convert a voltage that is relatively lower than the previous output voltage.
  • the microprocessor A51 can precisely control the time during which each MOS transistor power driving amplifier is turned on or off by controlling the PWM pulse output time. This achieves precise timing control of the current input to the single chip 313, namely: accurate timing control of the single board power supply.
  • Example 2
  • FIG. 6 is a schematic diagram of a power supply architecture according to Embodiment 2 of the present invention. It can be obtained by the transformation based on the first embodiment.
  • the difference between FIG. 6 and FIG. 5 is that an analog non-isolated linear DC/DC converter F61 is further connected in series between the non-isolated DC/DC converter C63 and the single-board chip D61.
  • the analog non-isolated linear DC/DC converter F61 can linearly convert the voltage from the non-isolated DC/DC converter C63, and finally obtain the voltage required by the single-board chip D61 and output it to the single-board chip D61.
  • the analog non-isolated linear DC/DC converter F61 can be connected in series between any non-isolated DC/DC converter and the single-board chip D61.
  • the non-isolated DC/DC converter can be a conventional analog non-isolated DC/DC converter or an analog non-isolated linear DC/DC converter.
  • FIG. 7 is a diagram showing a power supply architecture of Embodiment 3 of the present invention.
  • the power supply architecture can be transformed based on Embodiment 1.
  • the difference between Figure 7 and Figure 5 is:
  • the single-board chip D71 is further connected to the analog non-isolated linear DC/DC converter F71; the analog non-isolated linear DC/DC converter F71 can receive low-voltage bus voltages such as 12V, 5V or 3.3V.
  • the received bus voltage is directly converted into the voltage required by the single chip D71 and output to the single chip D71.
  • Example 4 Example 4:
  • FIG. 8 is a schematic diagram of a power supply architecture according to Embodiment 4 of the present invention.
  • the power supply architecture can be transformed based on Embodiment 3. 8 is different from FIG. 7 in that an analog non-isolated linear DC/DC converter F81 is further connected in series between the non-isolated DC/DC converter C83 and the single-board chip D81.
  • the analog non-isolated linear DC/DC converter F81 can linearly convert the voltage from the non-isolated DC/DC converter C83, and finally obtain the voltage required by the single-board chip D81 and output it to the single-board chip D81.
  • the analog non-isolated linear DC/DC converter F81 can be connected in series between any non-isolated DC/DC converter and the single-board chip D81.
  • the non-isolated DC/DC converter can be a conventional analog non-isolated DC/DC converter or an analog non-isolated linear DC/DC converter.
  • FIG. 9 is a diagram showing a power supply architecture of Embodiment 5 of the present invention.
  • the power supply architecture can be obtained based on Embodiment 1.
  • the difference between FIG. 9 and FIG. 5 is as follows: MOS tube power drive amplifier C104 and isolated DC/DC converter F91 are further connected in series between the microprocessor A91 and the single board chip D91, and the low voltage bus voltages such as 12V, 5V or 3.3V are The isolated DC/DC converter F91 is transformed.
  • the conversion method is as follows: The microprocessor A91 generates a PWM pulse with adjustable duty ratio, and the PWM pulse is amplified by the MOS tube power drive amplifier C104 to drive the isolated DC/DC converter. F91 will convert the currently used 48V bus voltage into a low voltage bus voltage such as 12V, 5V or 3.3V.
  • Example 6 Example 6:
  • FIG. 10 is a diagram showing a power supply architecture of Embodiment 6 of the present invention.
  • the power supply architecture can be transformed based on Embodiment 5.
  • 10 is different from FIG. 9 in that: instead of the MOS transistor power drive amplifier B104, the microprocessor A101 is not the microprocessor A101, so that the microprocessor A102 can relatively independently control the isolated DC/DC converter F101 for voltage, Current conversion.
  • Example 7
  • FIG. 11 is a schematic diagram of a power supply architecture according to Embodiment 7 of the present invention.
  • the power supply architecture can be transformed based on Embodiment 1.
  • Figure 11 differs from Figure 5 in that: single core
  • the chip Dil is further connected to the analog isolated DC/DC converter Gil l, and the low voltage bus voltage such as 12V, 5V or 3.3V is transformed by the analog isolated DC/DC converter G111.
  • the conversion method is: analog isolated DC/DC
  • the converter G111 converts the currently received 48V bus voltage into a low voltage bus voltage such as 12V, 5V or 3.3V.
  • Example 8
  • FIG. 12 is a diagram showing a power supply architecture of Embodiment 8 of the present invention.
  • the power supply architecture can be converted based on Embodiment 7.
  • the difference between Fig. 12 and Fig. 11 is that an analog non-isolated linear DC/DC converter F121 is further connected in series between the non-isolated DC/DC converter C123 and the single chip D121.
  • the analog non-isolated linear DC/DC converter F121 can linearly convert the voltage from the non-isolated DC/DC converter C123, and finally obtain the voltage required by the single-chip chip D121 and output it to the single-board chip D121.
  • the analog non-isolated linear DC/DC converter F121 can be connected in series between any non-isolated DC/DC converter and the single-board chip D121.
  • the non-isolated DC/DC converter can be a conventional analog non-isolated DC/DC converter or an analog non-isolated linear DC/DC converter.
  • FIG. 13 is a diagram showing a power supply architecture of Embodiment 9 of the present invention.
  • the power supply architecture can be converted based on Embodiment 7.
  • the difference between FIG. 13 and FIG. 11 is that: the single-board chip D131 is further connected to the analog non-isolated linear DC/DC converter F131; the analog non-isolated linear DC/DC converter F131 can receive a low-voltage bus voltage such as 12V, 5V or 3.3V.
  • the received bus voltage is directly converted into the voltage required by the single chip D131 and output to the single chip D131.
  • the non-isolated DC/DC converter may include analog non-isolated A DC/DC converter or a digital non-isolated DC/DC converter; the MOS tube power drive amplifier may include a push-pull power drive amplification method or an integrated power drive amplification method.
  • the non-isolated DC/DC converter may include a step-up DC/DC converter capable of implementing boosting, and may also include a non-isolated step-down DC/DC converter capable of implementing step-down;
  • the isolated DC/DC converter can include an isolated step-up DC/DC converter capable of boosting, or an isolated step-down DC/DC converter capable of step-down.
  • the microprocessor may be an arithmetic processor such as a single chip microcomputer, a digital signal processor (DSP), a complex programmable logic device (CPLD), or a field programmable logic gate array (FPGA).
  • DSP digital signal processor
  • CPLD complex programmable logic device
  • FPGA field programmable logic gate array
  • the single-board power supply architecture and the power supply providing method provided by the present invention can perform complicated timing control in the absence of multiple types of analog converters that cannot be uniformly managed, and the application of a professional timing control chip.
  • the unified, timely and effective single board power supply monitoring can be realized by the microprocessor, and the microprocessor can realize the clear timing control of the single board power supply.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc-Dc Converters (AREA)
  • Direct Current Feeding And Distribution (AREA)
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Description

一种单板电源架构及电源提供方法
技术领域 本发明涉及电源技术，尤其涉及一种单板电源架构及电源提供方法。 发明背景
近年来， 随着通信产品单板设计复杂程度的提高， 为单板上的单板 芯片供电的路数越来越多， 导致单板电源的设计越来越复杂。 目前的通 信产品单板电源均釆用模拟电源技术， 所以需要很多种类型的单板模拟 变换器执行用于支持单板电源供电的电压、 电流变换操作。 目前的通信 产品单板电源输入主要有两种方式： 一种是经过前级电源变换器变换出 如 12V、 5V或 3.3V等低压总线电压后再输入单板； 另一种则基于目前 比较常用的 48V系统， 即： 将 48V总线电压直接输入单板。
下面， 基于上述两种电源输入方式筒单介绍现有技术的电源架构。 现有技术一：
参见图 1 , 图 1是现有技术一的电源架构图。 图 1 中的单板电源架 构包括模拟非隔离直流 DC/DC变换器 11、 12、 13和单板芯片 14。其中， 模拟非隔离 DC/DC变换器 11、 12、 13是模拟非隔离 DC/DC变换器或 模拟非隔离线性 DC/DC变换器。 当单板芯片 14对 12V、 5V或 3.3V等 低压总线电压有需求时，可以直接采用经过前级电源变换器变换出的 12V、 5V或 3.3V等低压总线电压； 当有其它电压需求时， 则需要经过 所述模拟非隔离 DC/DC变换器将 12V、 5V或 3.3V等低压总线电压变 换为单板芯片 14所需电压。
现有技术二：
参见图 2, 图 2是现有技术二的电源架构图。 图 2中的单板电源架 构包括模拟非隔离 DC/DC变换器 21、 22、 23和单板芯片 24、 模拟隔离 DC/DC变换器 25。 其中， 模拟非隔离 DC/DC变换器 21、 22、 23是模 拟非隔离 DC/DC变换器或模拟非隔离线性 DC/DC变换器。实际应用时， 48V总线电压经过模拟隔离 DC/DC变换器 25变换为 12V、 5V或 3.3V 等低压总线电， 当单板芯片 24对 12V、 5V或 3.3V等低压总线电压有需 求时,单板芯片 24直接采用 12V、 5V或 3.3V等低压总线电压； 当有其 它电压需求时， 则需要由模拟非隔离 DC/DC 变换器或模拟非隔离线性 DC/DC变换器将 12V、 5V或 3.3V等低压总线电压变换为单板芯片所需 电压。
当单板对输入的电流有时序要求时， 一般需要额外进行复杂的时序 控制。 总体的时序控制原理如图 3所示， 图 3中， 各个时序控制驱动信 号通常是由目前专用的时序控制芯片生成的， 并且各个时序控制驱动信 号可以分别控制 MOS管功率驱动放大器 305、 306、 307、 308处于导通 或截止状态 , 以实现对输入单板芯片 313的电流的时序控制。
为了避免器件因过压等问题而受损， 通常需要对完成转换并输入单 板芯片 313的电压、 电流进行有效监控， 以在监控的基础上进行调整。 由于模拟非隔离 DC/DC 变换器通常只能进行电压、 电流变换， 而无法 对电压、 电流等信号进行有效监控； 所以所述监控通常是由具有电压、 电流监控能力的上位机单独完成的。但是， 上位机的监控能力有限， 如： 当电压出现过压现象时， 上位机对该现象的响应不够及时， 因此无法及 时、 有效地控制 DC/DC变换器降压， 以致于单板芯片 313常常因过压 而烧毁。
显然， 目前的通信系统单板电源架构存在如下问题：
1、 随着单板复杂程度的提高， 单板所需电压越来越复杂， 造成一个 单板需要很多种类型、 并且无法统一管理的模拟变换器； 2、 上位机对电压、 电流的监控能力有限， 使得单板芯片无法得到及 时、 有效的保护；
3、 当单板电压有复杂的时序要求时， 需要应用专业的时序控制芯片 额外进行复杂的时序控制。 发明内容
有鉴于此， 本发明的目的在于提供一种单板电源架构及电源提供方 法， 以统一、 及时、 有效地监控单板电源输出。
为达到上述目的， 本发明的技术方案是这样实现的：
一种单板电源架构， 该单板电源架构包括相连的运算处理器和 DC/DC变换器 （ C );
其中， 所述运算处理器， 用于向 DC/DC变换器（C )发送控制电源 输出的控制信号；
所述 DC/DC变换器（C ), 用于才艮据收到的控制信号将收到的总线 电压变换为所需要的电源电压输出。
一种单板电源提供方法， 该方法为：
运算处理器向 DC/DC变换器 （C )发送控制电源输出的控制信号， DC/DC变换器（C )才艮据收到的控制信号将收到的总线电压变换为所需 要的电源电压输出。
与现有技术相比， 本发明所提供的单板电源架构及电源提供方法， 均可由运算处理器向 DC/DC变换器发送控制电源输出的控制信号， 再 由 DC/DC 变换器根据收到的控制信号将收到的总线电压变换为所需要 的电源电压输出。 可见， 本发明架构和方法均可统一、 及时、 有效地监 控单板电源输出。 附图简要说明
图 1是现有技术一的电源架构图；
图 2是现有技术二的电源架构图；
图 3是现有技术的时序控制示意图；
图 4是本发明电源架构原理简图；
图 5是本发明实施例 1的电源架构图；
图 6是本发明实施例 2的电源架构图；
图 7是本发明实施例 3的电源架构图；
图 8是本发明实施例 4的电源架构图；
图 9是本发明实施例 5的电源架构图；
图 10是本发明实施例 6的电源架构图；
图 11是本发明实施例 7的电源架构图；
图 12是本发明实施例 8的电源架构图；
图 13是本发明实施例 9的电源架构图。 实施本发明的方式
下面结合附图及具体实施例对本发明详细说明。
本发明所提供的单板电源架构及电源提供方法， 均可由运算处理器 向 DC/DC变换器发送控制电源输出的控制信号， 再由 DC/DC变换器根 据收到的控制信号将收到的总线电压变换为所需要的电源电压输出。 并 且， 运算处理器可以进一步监控所述电源输出并将监控结果上报给相连 的上位机； 还可以通过控制发送所述控制信号的时间， 控制 DC/DC 变 换器变换出的多个电源输出的时序。
总体来讲， 本发明的核心思想可以由图 4体现。 图 4中， 微处理器 ( A )、 MOS管功率驱动放大器（B )、 DC/DC变换器（C )和单板芯片 ( D )依次相连， 微处理器 （A )还与上位机（E )相连。
实际应用时，微处理器（A )产生占空比可调的 PWM脉冲，该 PWM 脉沖经过 MOS管功率驱动放大器（ B )放大后驱动 DC/DC变换器（ C ) 将收到的总线电压变换成单板芯片 （D )所需要的芯片电压。 具体而言， 驱动 DC/DC 变换器（C ) 以实现电压、 电流变换的方式通常为： MOS 管功率驱动放大器（B )将放大所述 PWM脉冲后所形成的 GATE信号 发送给 DC/DC变换器（ C ), 由该 GATE信号触发 DC/DC变换器 （ C ) 进行电压、 电流变换。
再有， 微处理器（A )可以监控输出给单板芯片 （D )的电压、 电流， 并将监控结果通过通信接口上报给上位机（E )。 当然， 微处理器 （A ) 可以通过向 MOS管功率驱动放大器（ B )发送 PWM脉冲，来调整 DC/DC 变换器（C )所输出的电压、 电流。
下面参照附图详细说明本发明的实施例。 '
为使实施方式能够清楚明白地体现本发明技术特征， 本发明所列举 的各实施例所对应的附图中的非隔离 DC/DC变换器和 MOS管功率驱动 放大器的数量一般都是 3个； 当然， 在实际应用中， 所述非隔离 DC/DC 变换器和 MOS管功率驱动放大器的数量则不一定必须是三个， 也可以 是一个或多个。 实施例 1 :
参见图 5, 图 5所示为本发明实施例 1的电源架构图。 图 5中， 微 处理器 A51与单板芯片之间依次连接有多路 MOS管功率驱动放大器、 非隔离 DC/DC变换器；每一路 MOS管功率驱动放大器和非隔离 DC/DC 变换器之间则为串联关系。 并且， 微处理器 A51还可以进一步与上位机 E51相连。 实际应用时， 数处理器 A51产生占空比可调的 PWM脉冲，该 FWM 脉冲分三路分别经过 MOS管功率驱动放大器 B51 ~ B53放大后， 分别 驱动非隔离 DC/DC变换器 C51 ~ C53将收到的 12V、 5V或 3.3V等低压 总线电压变换成单板芯片 D51 所需要的芯片电压。 并且， 当单板芯片 D51 对低压总线电压有需求时， 可直接将低压总线电压输入单板芯片 D51。 具体而言， 驱动所述非隔离 DC/DC变换器以实现电压、 电流变换 的方式通常为： MOS管功率驱动放大器将放大所述 PWM脉冲后所形成 的 GATE信号发送给非隔离 DC/DC变换器， 由该 GATE信号触发非隔 离 DC/DC变换器进行电压、 电流变换。
再有，微处理器 A51可以以采样等方式监控输出给单板芯片 D51的 电压、 电流， 并将采样结果等监控结果通过通信接口周期性或实时性地 上报给上位机 E51。 当然， 微处理器 A51可以通过向所述 MOS管功率 驱动放大器发送 PWM脉冲，来调整所述非隔离 DC/DC变换器所输出的 电压、 电流。 比如： 微处理器 A51通过监控获知非隔离 DC/DC变换器 C51所输出的电压偏大，微处理器 A51则向 MOS管功率驱动放大器 B51 发送用于降低电压的 PWM脉沖；该 PWM脉沖经过 MOS管功率驱动放 大器 B51后， 驱动非隔离 DC/DC变换器 C51变换出比之前输出电压相 对低的电压。
另外， 当输出给单板芯片 D51的各电压之间有时序要求时， 微处理 器 A51可通过控制各 PWM脉沖输出时间以精确控制各 MOS管功率驱 动放大器处于导通或截止状态的时间， 以此实现对输入单板芯片 313的 电流的精确时序控制， 即： 实现单板电源的精确时序控制。 实施例 2:
参见图 6, 图 6所示为本发明实施例 2的电源架构图， 该电源架构 可以以实施例 1 为基础变换得到。 图 6与图 5 的区别在于： 在非隔离 DC/DC变换器 C63与单板芯片 D61之间进一步串连有模拟非隔离线性 DC/DC变换器 F61。 模拟非隔离线性 DC/DC变换器 F61可以对来自非 隔离 DC/DC变换器 C63的电压进行线性变换， 最终得到单板芯片 D61 所需要的电压并输出给单板芯片 D61。
在实际应用中， 模拟非隔离线性 DC/DC变换器 F61可以串连于任 意非隔离 DC/DC变换器与单板芯片 D61之间。所述非隔离 DC/DC变换 器可以是普通的模拟非隔离 DC/DC变换器或模拟非隔离线性 DC/DC变 换器。 实施例 3:
参见图 7, 图 7所示为本发明实施例 3的电源架构图， 该电源架构 可以以实施例 1 为基础变换得到。 图 7与图 5 的区别在于： 单板芯片 D71进一步与模拟非隔离线性 DC/DC变换器 F71相连； 模拟非隔离线 性 DC/DC变换器 F71可以接收 12V、 5V或 3.3V等低压总线电压， 并 将收到的总线电压直接变换为单板芯片 D71 所需要的电压再输出给单 板芯片 D71。 实施例 4:
参见图 8, 图 8所示为本发明实施例 4的电源架构图， 该电源架构 可以以实施例 3为基础变换得到。 图 8与图 7的区别在于： 在非隔离 DC/DC变换器 C83与单板芯片 D81之间进一步串连有模拟非隔离线性 DC/DC变换器 F81。 模拟非隔离线性 DC/DC变换器 F81可以对来自非 隔离 DC/DC变换器 C83的电压进行线性变换， 最终得到单板芯片 D81 所需要的电压并输出给单板芯片 D81。 在实际应用中， 模拟非隔离线性 DC/DC变换器 F81可以串连于任 意非隔离 DC/DC变换器与单板芯片 D81之间。所述非隔离 DC/DC变换 器可以是普通的模拟非隔离 DC/DC变换器或模拟非隔离线性 DC/DC变 换器。 实施例 5:
参见图 9, 图 9所示为本发明实施例 5的电源架构图， 该电源架构 可以以实施例 1 为基 变换得到。 图 9与图 5的区别在于： 微处理器 A91与单板芯片 D91之间进一步串联有 MOS管功率驱动放大器 C104 和隔离 DC/DC变换器 F91 , 12V、 5V或 3.3V等低压总线电压是由隔离 DC/DC变换器 F91变换得到的， 该变换方法为： 微处理器 A91产生占 空比可调的 PWM脉冲，该 PWM脉冲经过 MOS管功率驱动放大器 C104 放大后， 驱动隔离 DC/DC变换器 F91将收到的目前较常用的 48V总线 电压变换成 12V、 5V或 3.3V等低压总线电压。 实施例 6:
参见图 10, 图 10所示为本发明实施例 6的电源架构图， 该电源架 构可以以实施例 5为基础变换得到。 图 10与图 9的区别在于： 与 MOS 管功率驱动放大器 B104串联的不是微处理器 A101而是微处理器 A102, 以便微处理器 A102能相对独立地控制隔离 DC/DC变换器 F101进行电 压、 电流变换。 实施例 7:
参见图 11 , 图 11所示为本发明实施例 7的电源架构图， 该电源架 构可以以实施例 1为基础变换得到。 图 11与图 5的区别在于： 单板芯 片 Dil l进一步与模拟隔离 DC/DC变换器 Gil l相连， 12V、 5V或 3.3V 等低压总线电压是由模拟隔离 DC/DC变换器 G111变换得到的，该变换 方法为：模拟隔离 DC/DC变换器 G111将收到的目前较常用的 48V总线 电压变换成 12V、 5V或 3.3V等低压总线电压。 实施例 8:
参见图 12, 图 12所示为本发明实施例 8的电源架构图， 该电源架 构可以以实施例 7为基础变换得到。 图 12与图 11的区别在于： 在非隔 离 DC/DC变换器 C123与单板芯片 D121之间进一步串连有模拟非隔离 线性 DC/DC变换器 F121。 模拟非隔离线性 DC/DC变换器 F121可以对 来自非隔离 DC/DC变换器 C123的电压进行线性变换，最终得到单板芯 片 D121所需要的电压并输出给单板芯片 D121。
在实际应用中， 模拟非隔离线性 DC/DC变换器 F121可以串连于任 意非隔离 DC/DC变换器与单板芯片 D121之间。 所述非隔离 DC/DC变 换器可以是普通的模拟非隔离 DC/DC变换器或模拟非隔离线性 DC/DC 变换器。 实施例 9:
参见图 13, 图 13所示为本发明实施例 9的电源架构图， 该电源架 构可以以实施例 7为基础变换得到。 图 13与图 11的区别在于： 单板芯 片 D131进一步与模拟非隔离线性 DC/DC变换器 F131相连； 模拟非隔 离线性 DC/DC变换器 F131可以接收 12V、5V或 3.3V等低压总线电压， 并将收到的总线电压直接变换为单板芯片 D131所需要的电压再输出给 单板芯片 D131。
在实际应用中， 所述非隔离 DC/DC 变换器可以包含模拟非隔离 DC/DC变换器或者数字非隔离 DC/DC变换器； 所述 MOS管功率驱动 放大器则可以包含推挽功率驱动放大方式或集成功率驱动放大方式。 再 有， 所述非隔离 DC/DC变换器可以包含能够实现升压的升压 DC/DC变 换器， 也可以包含能够实现降压的非隔离降压 DC/DC 变换器； 同理， 所述隔离 DC/DC变换器可以包含能够实现升压的隔离升压 DC/DC变换 器， 也可以包含能够实现降压的隔离降压 DC/DC变换器。
还有， 在实际应用时， 也可以应用其它的功率驱动放大器， 而不应 用 MOS管功率驱动放大器； 并且， 如果微处理器输出的 PWM脉冲所 具有的功率足够大， 以至于可以正常触发非隔离 DC/DC 变换器等 DC/DC变换器进行电压、 电流变换， 那么也可以去掉所述 MOS管功率 驱动放大器， 而使微处理器与 DC/DC 变换器直接相连， 由微处理器所 输出的 PWM脉沖直接控制 DC/DC变换器进行电压、 电流变换。 再有， 所述的微处理器可以是单片机、 数字信号处理器（DSP )、 复杂可编程逻 辑器件 （CPLD )、 现场可编程逻辑门阵列 （FPGA )等运算处理器。 领域以外的其它技术领域， 只要本发明单板电源架构及电源提供方法能 统一、 及时、 有效地监控作为单板电源输出的电压、 电流即可。
由以上所述可见， 本发明提供的单板电源架构及电源提供方法， 在 不出现多种类型并且无法统一管理的模拟变换器、 以及不需要应用专业 的时序控制芯片额外进行复杂时序控制的情况下， 可由微处理器实现统 一、 及时、 有效地单板电源监控， 并可进一步由微处理器实现单板电源 的青确时序控制。

Claims

权利要求书
1、 一种单板电源架构， 其特征在于， 该单板电源架构包括相连的运 算处理器和 DC/DC变换器（ C );
其中， 所述运算处理器， 用于向 DC/DC变换器（C )发送控制电源 输出的控制信号；
所述 DC/DC变换器 （C ), 用于根据收到的控制信号将收到的总线 电压变换为所需要的电源电压输出。
2、 如权利要求 1所述的单板电源架构， 其特征在于， 所述运算处理 器和 DC/DC变换器（ C )之间进一步连接有功率放大器； 该功率放大器 用于放大来自运算处理器的控制信号， 并将放大后的控制信号发送给 DC/DC变换器 （C )。
3、如权利要求 2所述的单板电源架构， 其特征在于， 所述的运算处 理器、 功率放大器、 DC/DC变换器（C ) 的数量分別为一个或多个。
4、如权利要求 1至 3任一项所述的单板电源架构， 其特征在于， 所 述运算处理器是属于微处理器（A ) 的单片机、 数字信号处理器 DSP、 复杂可编程逻辑器件 CPLD或现场可编程逻辑门阵列 FPGA。
5、如权利要求 1至 3任一项所述的单板电源架构， 其特征在于， 所 述 DC/DC变换器（C ) 包含非隔离 DC/DC变换器和 /或隔离 DC/DC变 换器。
6、 如权利要求 5所述的单板电源架构， 其特征在于：
所述非隔离 DC/DC变换器包含非隔离降压 DC/DC变换器和 /或非隔 离升压 DC/DC变换器。
7、 如权利要求 5所述的单板电源架构， 其特征在于：
所述隔离 OC/DC变换器包含隔离降压 DC/DC变换器和 /或隔离升压 DC/DC变换器。
8、如权利要求 1至 3任一项所述的单板电源架构， 其特征在于： 所 述 DC/DC变换器 （C )进一步与接收电源输出的单板芯片 （D )相连。
9、 如权利要求 8所述的单板电源架构， 其特征在于： 所述单板芯片 ( D )单独和 /或与 DC/DC变换器（C )之间进一步连接有模拟非隔离线 性 DC/DC变换器。
10、 如权利要求 1至 3任一项所述的单板电源架构， 其特征在于： 所述运算处理器进一步用于监控所述电源输出并将监控结果上艮给 相连的上位机。
11、 如权利要求 1至 3任一项所述的单板电源架构， 其特征在于， 所述控制信号包含多个控制信号，分別用于控制所述 DC/DC变换器（C ) 变换出多个电源输出； 则所述运算处理器进一步用于：
通过控制发送所述控制信号的时间， 控制 DC/DC变换器（C )变换 出的多个电源输出的时序。
12、 一种单板电源提供方法， 其特征在于， 该方法为：
运算处理器向 DC/DC变换器（C )发送控制电源输出的控制信号， DC/DC变换器（C )才艮据收到的控制信号将收到的总线电压变换为所需 要的电源电压输出。
13、 如权利要求 12所述的方法， 其特征在于， DC/DC变换器 （C ) 收到所述控制信号之前， 进一步将该控制信号发送给功率放大器放大后 再发送给所述 DC/DC变换器（ C )。
14、 如权利要求 12或 13所述的方法， 其特征在于， 所述总线电压 的变换操作包含总线电压升压操作和 /或总线电压降压操作。
15、 如权利要求 12或 13所述的方法， 其特征在于， 进一步对所述 DC/DC变换器 （C ) 的电源输出进行模拟非隔离线性 DC/DC变换。
16、 如权利要求 12或 13所述的方法， 其特征在于： 进一步监控所述电源输出并将监控结果上报给上位机。
17、 如权利要求 12或 13所述的方法， 其特征在于， 所述控制信号 包含多个控制信号， 分别用于控制所述 DC/DC变换器（C )变换出多个 电源输出； 则该方法进一步包括：
通过控制发送所述控制信号的时间， 控制 DC/DC变换器（C )变换 出的多个电源输出的时序。
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ES2687248T3 (es) 2018-10-24
CN100426193C (zh) 2008-10-15
EP3487054A1 (en) 2019-05-22
US7847528B2 (en) 2010-12-07
EP2019479A1 (en) 2009-01-28
EP2019479A4 (en) 2011-07-06

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