WO2007138922A1 - 電子部品、半導体パッケージ及び電子機器 - Google Patents
電子部品、半導体パッケージ及び電子機器 Download PDFInfo
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- WO2007138922A1 WO2007138922A1 PCT/JP2007/060423 JP2007060423W WO2007138922A1 WO 2007138922 A1 WO2007138922 A1 WO 2007138922A1 JP 2007060423 W JP2007060423 W JP 2007060423W WO 2007138922 A1 WO2007138922 A1 WO 2007138922A1
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- Prior art keywords
- layer
- ubm
- electrode pad
- metal layer
- alloy
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/66—Conductive materials thereof
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing of the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
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- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/346—Solder materials or compositions specially adapted therefor
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- H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
- H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
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- H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
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- H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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- H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
- H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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- H10W72/072—Connecting or disconnecting of bump connectors
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- H10W72/241—Dispositions, e.g. layouts
- H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
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- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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Definitions
- the present invention relates to an electronic component, a semiconductor package and an electronic device having a barrier metal layer on an electrode pad.
- solder bumps are formed on the electrode pads on the surface of the LSI chip, and an interposer substrate such as a buildup substrate or a flexible substrate or a mother board is used.
- an interposer substrate such as a buildup substrate or a flexible substrate or a mother board is used.
- solder bumps such as SnPb, SnAg, SnCu, SnAgCu, SnZn, SnZnBi, Snln, etc.
- solder bumps are mainly used during bonding by reflow, repair process, high temperature use of products, etc. It may diffuse to the electrode pads and wiring of A1 and Cu of the component Sn power chip and electrical failure may occur.
- a UBM Under Bump Metal
- carrier metal layer carrier metal layer
- Ni formed by electrolytic plating or NiP formed by electroless plating is often used as a UBM having a nolia function. The reason for this is that Ni can maintain its barrier property even after storage at high temperature which makes it difficult for it to diffuse to Sn.
- Ni has a good solder wettability (adhesion)! /
- the surface of these Ni and NiP is usually electroplated to ensure the solder wettability.
- the wettability to the solder is good due to the substitution process and Au is formed.
- connection structure of the prior art when copper having a thickness of about 1 m is used as an intermediate metal layer between the electrode pad and the solder bump, most of the copper is diffused into the solder bump during reflow, etc. There is a problem that the adhesion between the solder and the solder bumps is reduced, resulting in the loss of reliability. Further, in the case of forming nickel as a magnetic material on the intermediate metal layer by sputtering or the like, there has been a problem that the working efficiency is lowered. Therefore, attempts have been made to solve these problems by using special alloys for UBM.
- FIG. 14 shows a cross-sectional view of a structure in which a Cu Ni-based alloy is used as a barrier metal layer (UBM), and the electrode pad and the solder bump are connected by this barrier metal layer.
- UBM barrier metal layer
- a CuNi-based alloy is used as the North American layer (UBM) 105.
- the uniformity of the film, the film strength, and the film forming efficiency are higher than the conventional vacuum evaporation film forming method which can only prevent the decrease in the adhesion between the intermediate metal layer 104 and the solder bump 106. It is possible to realize low cost.
- Japanese Patent Application Laid-Open No. 2002-203925 proposes a connection structure in which an Au film is provided on a NiP film as a UBM, or a connection structure in which an Au film is provided on a NiCuP film.
- Fig. 15 shows a cross-sectional view of a structure in which an electrode pad and a solder bump are connected using NiP or a NiCuP alloy as UBM.
- a NiP layer (or NiCuP layer) 109 is formed on the metal wiring 108, and further, a high P-Ni layer (or NiCu layer) 110 and a NiSn alloy layer (or NiCuSn alloy layer) 111 are formed. It is formed and connected to the solder bump 112.
- the adhesion strength can be enhanced by adopting a structure in which the occurrence of such a force-Kendall void is suppressed. Disclosure of the invention
- a Ni-rich alloy such as Sn was easily formed. Such a Ni-rich alloy
- connection structure in which a stress or an impact is applied to the bonding interface in the formed connection structure, a phenomenon often occurs in which the bonding strength is reduced due to breakage in the thin alloy layer.
- the alloy layer tends to be broken to lower the bonding strength.
- the content of Cu in the solder is relatively high (about 0.5 to 1%), and Cu Sn, (Cu, Ni) Sn, in the alloy layer at the interface between the UBM and the solder Cu Sn, (Cu, Ni) Sn is relatively high (about 0.5 to 1%), and Cu Sn, (Cu, Ni) Sn, in the alloy layer at the interface between the UBM and the solder Cu Sn, (Cu, Ni) Sn is relatively high (about 0.5 to 1%), and Cu Sn, (Cu, Ni) Sn, in the alloy layer at the interface between the UBM and the solder Cu Sn, (Cu, Ni) Sn is
- Ni-rich alloy refers to a state in which the content of Ni is larger than the content of Cu in an alloy containing Cu, Ni formed at the interface between UBM and solder, ie, Ni / Cu > 1 (meaning the number of atoms) means Conversely, an alloy of NiZCu ⁇ 1 (atomic number basis) is defined as a Cu-rich alloy.
- UBM materials can be used at low cost without using electrically plated lead wires or seed layers.
- An electroless NiP film provided with an Au film that can be formed is often used.
- Ni in the UBM diffuses into the nodna bump, so that a P-rich layer such as a P-rich CuNiP layer or a P-rich NiP layer (a layer mainly composed of NiP) is formed at the interface between the solder bump and the UBM.
- the solder bump may be connected directly to the Cu electrode without using a UBM.
- Cu has the property of being very easy to diffuse to Sn. For this reason, Cu in the electrode diffuses to the solder bump side due to double-sided mounting, use in a high temperature environment for a long time, a repair process, etc., and a break occurs in the Sn alloy part which penetrates into the Cu wiring. There was a thing. Therefore, in order to prevent this in advance and to obtain excellent long-term bonding reliability, it is also necessary to use a UBM having excellent bonding strength and variability between the Cu electrode and the solder bump.
- a conventional Au film-provided Ni film or a UB made of a NiP-based alloy provided with an Au film is used.
- a brittle SnAu alloy may be present at the interface connected to the Au force solder bump used to improve the solder wettability of UBM. The reason is that the formation of a weak intermetallic compound with the Au force ⁇ ⁇ causes a fracture starting from the Au-Sn alloy when stress or impact is applied.
- the present inventor has found an optimum UBM composition that does not decrease bonding strength even after multiple reflow steps and long-term use in a high temperature environment. That is, in order to solve the above problems, the present invention has the following configuration.
- An electrode pad provided on a substrate or a semiconductor element, and a barrier metal layer provided so as to cover the electrode pad, and the noria metal layer is provided on the side opposite to the electrode pad side.
- Electronic component characterized by having a CuNi type alloy layer containing 60 at% Cu and 40 to 85 at% Ni.
- An electrode pad provided on a substrate or a semiconductor element, and a barrier metal layer provided so as to cover the electrode pad, and the noria metal layer is provided on the opposite side to the electrode pad side by 15 at.
- An electronic component comprising a CuNiP-based alloy layer containing at least% of Cu, at least 40 at% of Ni, and at least O at%, and at most 25 at% of P.
- Electronic component characterized by having a CuNiP-based alloy layer containing 60 to 60 at% Cu, 29 to 40 at% Ni and 8 to 16 at% P, and having a Ni content of at least 2.5 times the force content
- a plurality of electronic members consisting of at least one of a substrate and a semiconductor element
- Electrode pads provided on each electronic member,
- a barrier metal layer provided to cover the electrode pad
- a CuNiSn-based alloy layer provided so as to cover the nolia metal layer, and having an average NiZCu ratio of 2.3 or less;
- the barrier metal layer includes a bump and a bump provided to electrically connect electrode pads provided on different electronic members via the barrier metal layer and the CuNiSn alloy layer.
- a semiconductor package characterized by having a CuNi-based alloy layer containing 15 to 60 at% of Cu and 40 to 85 at% of Ni in contact with the CuNiSn-based alloy layer. Page.
- a plurality of electronic members serving as a force of at least one of a substrate and a semiconductor element
- Electrode pads provided on each electronic member,
- a barrier metal layer provided to cover the electrode pad
- a CuNiSn-based alloy layer provided so as to cover the nolia metal layer, and having an average NiZCu ratio of 2.3 or less;
- a P-rich layer containing P provided between the barrier metal layer and the CuNiSn alloy layer, an electrode pad provided on an electronic member different from each other via the nolia metal layer, the CuNiSn alloy layer, and the P-rich layer And a solder bump provided to make electrical connection,
- the semiconductor is characterized in that the noria metal layer has a CuNiP-based alloy layer containing 15 at% or more of Cu, 40 at% or more of Ni, and O at% to 25 at% or less so as to be in contact with the P-rich layer. package.
- a plurality of electronic members comprising at least one of a substrate and a semiconductor element
- Electrode pads provided on each electronic member,
- a barrier metal layer provided to cover the electrode pad
- a CuNiSn-based alloy layer provided so as to cover the nolia metal layer, and having an average NiZCu ratio of 2.3 or less;
- a P-rich layer containing P provided between the barrier metal layer and the CuNiSn alloy layer, an electrode pad provided on an electronic member different from each other via the nolia metal layer, the CuNiSn alloy layer, and the P-rich layer And a solder bump provided to make electrical connection,
- the barrier metal layer said to be in contact with the P-rich layer, 44 ⁇ 60At% of Cu, comprises 29-40 at% Ni and 8 to 16 &% of 1 3, and 2 of Ni content force content 5 What is claimed is: 1.
- a semiconductor package comprising a CuNiP alloy layer that is more than doubled.
- At% represents the proportion of the number of atoms, and may be described as “atomic%”.
- the “P-rich layer containing P” described in the above “5” and “6” includes the first P-rich layer and the second P-rich layer. Rich layer is included.
- a UBM (l) Cu at 15 to 60 at%, Ni at 40 to 85 at%, CuNi based alloy layer, (2) Cu at 15 at% Above, a CuNiP alloy layer containing Ni at 40 at least, P at 0 &% to 25 at%, or (3) 44 to 60 at% Cu, 29 to 40 at% Ni and 8 to 16 at% P
- the electrode pad and solder bump are connected using a CuNiP alloy layer that contains a strong Ni content of at least 2.5 times the P content.
- the “CuNiSn alloy layer” is a layer that is automatically formed between the UBM and the solder bumps by heat treatment after depositing the solder bump material on the UBM.
- the UBM, CuNiSn alloy layer, P-rich layer, and solder bump of the present invention can be clearly determined by using SEM (scanning electron microscope) or using SEM and EDX (energy dispersive X-ray analysis) in combination. It can be determined.
- a long-term bonding reliability that solves the following four problems has conventionally been a problem with UBMs containing Ni, NiP, and Cu by using UBM compositions as described in (1) to (3) above. It is possible to provide a junction with excellent quality.
- UBM of CuNiP-based alloy has a Cu content of at least 15 tat%
- UBM of CuNiP-based alloy, Cu content strength of 4 to 60 at%, Cu content is high, level and It becomes. For this reason, even in these UBMs, Cu in the UBM preferentially diffuses into the solder bumps as well, thereby suppressing the growth of (a) needle-like Ni-rich intermetallic compounds that cause a decrease in bonding strength. .
- solder wettability was not good unless Au plating was applied to the surface.
- (1) CuNi-based alloy layer, or (2), (3) CuNi P-based alloy layer contains Cu excellent in solder wettability, so that solder wettability is Ni or NiP-based. It is superior to alloys. Therefore, the solder bump and the electrode pad can be easily joined without performing the Au plating process.
- This solder wettability improvement effect by Cu is well maintained up to 60 at% of Cu.
- no fragile AuSn layer is formed when bonded to the solder bump. Therefore, (d) the risk of the occurrence of junction failure originating from the AuSn layer is completely eliminated, and good junction reliability can be obtained.
- UBM of CuNi-based alloy containing (1) Cul 5 to 60 at%, Ni 40 to 85 at%, (2) Cu at 15 at% or more, Ni at 40 at least, P at 0 &% on the electrode pad beyond, UBM of CuNiP alloys containing a range of less than 25 at%, or (3) 44 ⁇ 60At% of Cu, wherein Ni and 8 to 16 &% 1 3 29 ⁇ 40At%, and Ni content (atomic
- the UBM of CuNiP alloy is formed which is 2.5 times or more the P content (atomic number basis).
- electrode pads are electrically connected on one or more substrates or semiconductor elements (on electronic members).
- the UBM of the CuNiP-based alloy layer which is
- the average ratio of NiZCu between the UBMs and the solder bumps is 1.2.
- a CuNiSn alloy layer of 3 or less is formed.
- FIG. 1 is a cross-sectional view of an example of the electronic component of the present invention.
- FIG. 2 is a cross-sectional view of an example of the electronic component of the present invention in which solder bumps are formed on UBM.
- FIG. 3 is an enlarged cross-sectional view of an example of the electronic component of the present invention in which a solder bump is formed on a UBM of a CuNi-based alloy.
- FIG. 4 is an enlarged cross-sectional view of an example of the electronic component of the present invention in which a solder bump is formed on a UBM of a CuNiP-based alloy.
- FIG. 5 is a view showing the relationship between the Cu content in UBM and the average NiZCu ratio in the CuNiSn alloy layer.
- Fig. 6 is a cross-sectional view of a connection part where a conventional NiP-based alloy UBM and a SnAgCu solder bump are joined.
- FIG. 7 is a cross-sectional view of an example of a connection portion obtained by joining a CuNiP alloy UBM of the present invention and a SnAgCu solder bump.
- FIG. 8 is a view showing the relationship between the Ni content in UBM and the UBM solution film thickness.
- FIG. 9 is a phase diagram showing the optimum composition range of the UBM of the present invention.
- FIG. 10 is a cross-sectional view of an example of the electronic component of the present invention in which an intermediate layer is provided between UBM and an electrode pad.
- FIG. 1 l is a cross-sectional view of an example of the electronic component of the present invention in which an intermediate layer is provided between a UBM of a CuNi-based alloy and an electrode pad.
- FIG. 12 is a cross-sectional view of an example of the electronic component of the present invention in which an intermediate layer is provided between the UBM of the CuNiP alloy and the electrode pad.
- FIG. 13 is a view showing an example of the semiconductor package of the present invention.
- FIG. 14 is a view showing a cross section of a connection portion in which a conventional CuM alloy UBM is connected to a solder bump.
- FIG. 15 is a view showing a cross section of a connection portion in which a UBM of a conventional NiP alloy or CuNiP alloy is connected to a solder bump.
- FIG. 16 is a phase diagram showing the optimum composition range of the UBM of the present invention.
- Titanium film (one layer in the intermediate metal layer)
- a UBM (barrier metal layer) 3 is formed on an electrode pad 2 of Al, Cu, Ag or the like provided on a substrate or a semiconductor element.
- the electrode pad is electrically connected to the wiring of the substrate or the semiconductor element.
- the UBM 3 is a CuNi-based alloy layer containing (l) Cul 5 to 60 at%, Ni 40 to 85 at% at least on the side opposite to the side in contact with the electrode pad, (2) Cul 5 at% or more, Ni 40 at% or more, P exceed the force S0at%, including CuNiP alloy layer containing in the range of less 25 at%, or (3) 44 ⁇ 60at% of Cu, Ni and 8-16 &% 1 3 29 ⁇ 40At%, and Ni content
- the formation of a CuNiP alloy layer whose amount (based on the number of atoms) is at least 2.5 times the P content (based on the number of atoms)!
- the CuNiP-based alloy layer of (2) it is necessary to contain 15 at% or more of Cu and 40 &% or more of Ni, for example, when P is contained in x (at%),
- the CuNiP alloy layer (3) Te is, 44 ⁇ 60At% of Cu, wherein Ni and 8 to 16 &% 1 3 29 ⁇ 40At%, and Ni content It is an area of 2.5 times or more of P content.
- the UBM that satisfies these conditions is as shown in Figure 16: Cu44—Ni40—P16, Cu60— It is a composition area surrounded by a square of Ni29-Pl l, Cu60-Ni32-P8, Cu52-Ni40-P8.
- the content of P is about 40% of the Ni content, so the Ni content is P It is about 2.5 times more than the content.
- the entire force may be constituted of a CuNi-based alloy layer or a CuNiP-based alloy layer, It is necessary to have a CuM alloy layer or a CuNiP alloy layer on the side opposite to the side in contact with the electrode pad.
- the average NiZCu ratio in the (l) CuNi alloy layer is preferably 0.67-5. 7 and the average NiZCu ratio in the (2) CuNiP alloy layer is 0.60-5.5.
- the average NiZCu ratio in the above (3) CuNiP-based alloy layer is preferably 0.48-0.91. This (1) CuNi alloy layer or (2), the same! ! ? ⁇ ? Average in alloy layer? The ratio of ⁇ ⁇ ! Hardly changes even when heat treatment such as a reflow process is performed, and this ratio can be measured by the same method as the measurement method of FIG. 5 described later.
- the CuNi-based alloy and the CuNiP-based alloy used for UBM 3 are not limited to binary or ternary alloys, respectively.
- a small amount of Ag, Pd, Sn, Pb, etc. is added to improve solder wettability, or Co, Fe, Pd, Pt, W, Ti to improve barrier property. It is also possible to use ternary, quaternary or higher materials to which a small amount of Cr is added.
- the UBM3 of the present invention has a composition C) 5 to 60 at%, C40 5 to 85 at%, (2) Cul 5 at% or more, Ni 40 at% or more, P power 0 at% or more, 25 at% or less, or (3) 44 60 at% of Cu, wherein Ni and 8 to 16 &% 1 3 29 ⁇ 40At%, and 2. Ni content of P content 5 times or more, it is necessary that in any one of the ranges .
- Sn-based solder such as SnPb, SnAg, SnCu, SnAgCu, Snln, SnZn, SnZnBi, etc.
- the average NiZCu ratio in the CuNiSn alloy layer 6 present at this bonding interface is less than 2.3.
- the CuNiSn alloy layer is formed between the UBM and the solder bump when forming the solder bump after laminating the solder bump material on the UBM. Therefore, this average NiZCu ratio means the average NiZ in the CuNiSn alloy layer after forming a solder bump on the UBM and forming the CuNiSn alloy layer. It represents the Cu ratio.
- This CuNiSn-based alloy layer contains Cu-rich (Cu, Ni) Sn or Cu-rich (Cu, Ni) Sn.
- This layer is composed of an alloy containing 6 5 3. This layer is partially Ni-rich (Ni, Cu) Sn or Ni
- the average NiZCu ratio in the uNiSn alloy layer 6 is a composition of 2.3 or less.
- Ni rich (Ni, Cu) Sn 20 to 45 at% Ni, 0 to 20 at% Cu, 55 to 65 at% S
- Fig. 3 shows the UBM3 force (l) for the CuNi-based alloy layer
- Fig. 4 shows the UBM 3 for the (2) or (3) CuNi P-based alloy layer. An enlarged cross-sectional view of the vicinity of the bonding interface is shown.
- a first P rich layer 7 is also formed, which is also composed of a NiCuSnP alloy.
- the first P-rich layer 7 is a layer in which the P content formed by the mutual diffusion of Cu and Sn is slightly higher than that in the periphery. Yarn formation of this first P rich layer 7 is fluid force Typically, it has a composition of about 30 to 50 at% Ni, 20 to 40 at% Sn, 10 to 30 at% P, and 5 to 5 at% Cu. doing.
- a P rich NiP-based alloy (a main component of Ni P is
- the CuNiP-based alloy in the second P-rich layer is a CuNiP alloy containing 45 to 80 at% of Ni, 0 to 30 at% of Cu, and 15 to 30 at% of P.
- the present invention is characterized in that the second P rich layer 8 is extremely thin as compared with the case where the conventional NiP UBM is used.
- the P-rich layer formed when the (2) or (3) CuNiP-based alloy of the present invention is used includes the first P-rich layer 7 and the second P-rich layer 8, and these P-rich layers The concentration of P is slightly higher than UBM's bump!
- the operation and effect of the present invention will be described.
- the generation of the alloy layer of Ni rich (Ni, Cu) Sn or Ni Sn can be significantly suppressed even after use in a high temperature environment.
- Ni-rich CuNiSn alloy means that the NiZCu ratio in the CuNiSn alloy exceeds 1.0
- Cu-rich CuNiSn alloy means NiZCu in the CuNiSn alloy. It means that the ratio is less than 1.0.
- the reason why the decrease in bonding strength due to the heat history becomes remarkable is that CuNiS formed at the interface In this case, almost all of the n-based alloy layer is composed of a Ni-rich CuNiSn-based alloy. Specifically, this is the case where the average NiZCu ratio in the CuNiSn alloy layer exceeds approximately 2.3. Therefore, the average NiZCu ratio in the CuNiSn alloy layer needs to be 2.3 or less. On the other hand, when the Ni-rich CuNiSn alloy and the Cu-rich CuNiSn alloy coexist (when the average NiZCu ratio is approximately in the range of 0.7 ⁇ Ni / Cu ⁇ 2.3), the Ni-rich CuNiSn alloy layer is broken.
- FIG. 5 shows the relationship of the average NiZ Cu ratio in the CuNiSn alloy layer to the Cu content in the UBM when a CuNiP alloy is used for the UBM and SnAg Cu is used as the solder bump as an example.
- Electroless plating is performed using a plating solution containing Ni ions, Cu ions, and sodium hypophosphite. At this time, the concentrations of Ni ions, Cu ions, and sodium hypophosphite in the plating solution are changed.
- the UBM made of CuNiP alloy having different Cu content was formed.
- the interface between the solder bump and the UBM was exposed by cross-sectional processing, and the UBM was compositionally analyzed by SEM-EDS to measure the Cu content.
- CuNiSn alloy is exposed by exposing the interface where solder bump and UBM are joined
- the part corresponding to the layer was compositionally analyzed by SEM-EDS to determine the average NiZCu ratio.
- the area composition analysis was performed by SEM-EDX in a region of 2 m in thickness and 50 m in width.
- the average NiZCu value was determined by measuring the average value of ten CuNiSn alloy layers by point analysis.
- the average NiZCu ratio in the CuNiSn alloy layer is small even under extremely severe temperature conditions of 8 reflows of MAX 300 ° C., and the CuNiSn system with the change in the Cu content in the UBM
- the rate of change of the average NiZCu ratio in the alloy layer is decreasing.
- the Ni-rich alloy layer which is one of the causes of low bonding strength, is not generated at the bonding interface with the solder bumps, and a Cu-rich CuNiSn alloy is It can be seen that the containing alloy layer is formed. That is, it is understood that in the region of Cu content force Sl 5 at% or more in the UBM, the average NiZCu ratio in the CuNiSn alloy layer after reflowing for 1 and 8 times is both 2.3 or less.
- the Cu-rich CuNiSn alloy coexists with a Ni-rich CuNiSn alloy, and it is composed of a Ni-rich CuNiSn alloy in the case of more than 23.
- Tables 1 and 2 show the relationship between the average NiZCu ratio in the CuNiSn-based alloy layer after one and eight reflows, and the bump pull strength, respectively.
- the bump pull strength was measured as follows.
- the bump pull strength is higher than l lOg for all UBM compositions.
- the conditions for forming a normal joint correspond to the conditions shown in Table 2 after eight times of reflowing under mild conditions as shown in Table 1. Therefore, looking at the results in Table 2, when the average NiZCu ratio in the CuNiSn alloy layer is 2.3 or less, the bump pull strength shows a high value of 110 g or more, while the average NiZCu ratio is 2. In the case of values exceeding 3 (3.4, 4. 39), it can be seen that the Ni-rich CuNiSn-based alloy begins to dominate the interface between the UBM and the solder bump, and the bump pull strength is greatly reduced.
- the bump pull strength tends to decrease as the average NiZCu ratio in the CuNiSn alloy increases as the number of reflows increases.
- the average NiZCu ratio becomes smaller as the reflow frequency increases, so the average NiZCu ratio in the CuNiSn alloy layer is suppressed to a low level, and a long time under high temperature environment Even when exposed, the amount of reduction in bump pull strength can be kept small.
- the average NiZCu ratio of the CuNiSn alloy layer is 2.3 or less, a Cu-rich CuNiSn alloy can be contained, and the porosity is not destroyed, as long as UBM and The bonding strength with the solder bumps can maintain a high value. Therefore, the optimum composition of the CuNi-based alloy layer as the UBM can maintain the average NiZCu ratio in the CuNiSn-based alloy layer at 2.3 or less even when the product is used in a long-term high temperature environment, and the solder joint strength does not decrease. Cul 5 to 60 at%, Ni 40 to 85 at%.
- the optimum composition of the CuNiP alloy as UBM is (2) Cul 5 at% or more, Ni 40 at or more, P is more than 0 &%, 25 at% or less, or (3) 44 to 60 at% Cu, wherein Ni and 8 to 16 &% 1 3 29 ⁇ 40At%, and Ni containing chromatic amount is 2. range of more than 5 times the P content.
- P-rich NiP layer (layer mainly composed of NiP) etc. is formed by diffusion of Ni in UBM to solder bumps during solder bump bonding.
- the UBM contains a high content of Cu, which has a high diffusion rate with respect to the solder, the Sn contained in the solder bumps is also easily diffused to the UBM to some extent. For this reason, the occurrence of P-rich NiP layers etc. not containing Sn The width can be suppressed, and a decrease in bonding strength can be prevented.
- FIG. 6 shows a cross-sectional SEM image of the interface when bonded to a SnAgCu solder bump via a CuNiSn alloy layer using a conventional NiP alloy UBM.
- FIG. 7 shows that the CuNiP alloy alloy UBM of the present invention containing Cu at 15 at% or higher, at least 40 at% or higher, P at 0 &% and 25 at% or lower, using SnAgCu solder bump via CuNiSn based alloy layer.
- a P-rich NiP layer (second P-rich layer) is formed at the interface between the UBM and the solder bump.
- P-rich NiP layer layer mainly composed of Ni P: second P-rich layer
- the thickness of the P-rich NiP layer (layer mainly composed of Ni P) is thin instead of P.
- Rich NiSnP layer (a layer having a composition of NiCuSnP, that is, typically, about 30 to 50 at% Ni, 20 to 4 Oat% Sn force, 10 to 30 at% P, and 5 to 5 At% Cu P: IP rich layer ) Is formed thick.
- NiCuSnP that is, typically, about 30 to 50 at% Ni, 20 to 4 Oat% Sn force, 10 to 30 at% P, and 5 to 5 At% Cu P: IP rich layer
- the concentration of P in the UBM by increasing the concentration of P in the UBM, it is possible to improve the variability after reflow a number of times. Therefore, it is desirable to adjust the P content in the UBM appropriately depending on the application. Also, for example, even when P is as much as 25 at%, occurrence of Cu at 15 at% or more, Ni force Oat% or more in the UBM, and P-rich NiP layer if contained, and destruction there was significantly suppressed, and there were no particular problems.
- the UBM has a barrier property higher than that of Cu, a CuNi alloy layer containing (l) Ni at 40 to 85 at%, or (2) a CuNiP alloy containing at least 40 at% of Ni.
- the layer it is possible to secure the solderability and to prevent the decrease of the bonding strength after the high temperature holding.
- FIG. 8 shows barrier properties against SnAgCu solder bumps by the UBM of the CuNiP-based alloy formed in the present invention.
- Figure 8 shows the relationship between the Ni content in UBM and the UBM film thickness after reflow.
- the dissolved film thickness means the reduced film thickness of UBM before and after forming the solder bump.
- the measurement of each characteristic value was performed as follows.
- solder bumps fixed by flux on the UBM were melted and joined using a reflow furnace under a max. 300 ° C. nitrogen atmosphere. This reflow operation was repeated eight times when preparing a sample after eight times of reflow.
- the interface between the solder bump and the UBM was exposed by cross-sectional processing, the composition of the UBM was analyzed by SEM-EDS, and the Ni content was measured.
- the UBM dissolved film thickness decreases remarkably with the increase of the Ni content excellent in the barrier property in the UBM. And in areas where the Ni content is 40 at% or more, the solution film thickness is 5 m or less, and even if the actual film thickness is 5 m after 8 times of reflow, U BM is not dissolved, and ordinary electronic devices It has been found that sufficient noriability can be maintained in the range of use of
- Table 3 shows the bonding strength after eight reflows when various CuNiP-based alloys are used as the UBM.
- the bump pull strength was measured under the same conditions as in Tables 1 and 2. According to the results in Table 3, the Ni content is less than 40 at%! /, And in UBM, the bump pull strength is as low as 92 g or less! I understand that And, when the film thickness is about 5 m, it can be seen that the barrier layer is broken and the bonding strength is sharply reduced due to the peeling of the A1Z solder bump interface.
- the bump pull strength of the CuNiP alloy UBM which has a Ni content force of more than 0 at%, is as high as 120 g or more, and the barrier property is maintained, and such rapid bonding occurs even after storage in a high temperature environment. It can be seen that a reduction in strength does not occur. Therefore, in UBM using CuNi alloy and CuNiP alloy, it is necessary to set the Ni content to 40 at% or more (Cu content is 60 at% or less).
- the noria property of the CuNiP alloy layer is affected not only by the Ni content but also by the P content, and the barrier property is higher as the P content in the UBM is higher.
- the P content is 8 at% or more
- the Cu content is somewhat high, and even if the Ni content is slightly or low, the barrier property can be maintained, so P needs to be 8 at% or more.
- Table 4 shows the UBM film thickness, average NiZCu ratio, and bonding strength after reflow 8 times of CuNiP alloy with P content of 8 at% or more and Ni content of 40 at% or less. The bump pull strength was measured under the same conditions as in Tables 1 and 2.
- the P content shown in Table 3 is 8 at For samples less than 10%, depending on the composition, bonding strength after eight reflows can not be ensured, but as shown in Table 4, UBM with a P content of 8at% or more and a Cu content of 60at% or less is used. For example, it can be seen that the barrier properties can be maintained even if the Ni content force Oat% or less, and the high bonding strength of 120 g or more can be maintained.
- the Ni content in Table 4 is at least 2.5 times the P content.
- the UBM using (1) CuNi alloy or (2), (3) CuNiP alloy according to the present invention unlike the conventional UBM such as Ni NiP alloy, has 15 at% or more of Cu having good wettability. include. For this reason, when solder bumps are formed on these UBMs via the CuNiSn alloy layer, conventional Au-plated CuNi films or Au-plated NiP films are formed. In the vicinity of UBM, non-wettability is obtained. This solder wettability improvement effect by Cu can be obtained without increasing Cu to 60 at% or more.
- the present invention formation of the Ni-rich CuNiSn alloy, formation of the P-rich NiP layer and formation of the CuNiP layer are suppressed even after use in a high temperature environment, and the barrier property is realized. High bonding strength can be maintained.
- the preferred (2) and (3) CuNiP compositions for this are as shown in FIG. 9 in the range of 15 at.% Cu and 60 at.%, 40 at.% ⁇ Ni ⁇ 85 at.%, Oat% ⁇ P ⁇ 25 at. As shown in 16, it is represented by a range of 44 at% ⁇ Cu ⁇ 60 at%, 29 at% ⁇ Ni ⁇ 40 at%, 8 at% ⁇ P ⁇ 16 at%.
- the CuNiP alloy layer 3 may be arranged in two or more layers. However, it is necessary that the composition of the noria metal layer on the outermost surface connected to the CuNiSn alloy layer be a CuNi alloy or a CuNiP alloy.
- middle layer has the following compositions.
- NiP alloy NiP alloy containing 2 to 25 at% of P
- NiB-based alloy NiB-based alloy containing B 1 to 1: L 0 at%
- CoP alloy CoP alloy containing 2 to 25 at% of P.
- the Noria layer of the CuM alloy or the CuNiP alloy may be locally destroyed under extreme use conditions.
- the electrode pads such as A1 and the solder bumps are in direct contact with each other, and the strength of the direct contact portions is almost zero.
- the intermediate layer 9 such as Ni, NiB alloy, NiP alloy, etc., it acts as a very strong Noria layer, and such an extreme decrease in bonding strength can be reduced loosely or in strength. It will be possible to hold back.
- FIG. 11 and 12 show cross-sectional structures when the electronic component having this intermediate layer is connected to the solder bumps.
- Fig. 11 shows the case where UBM of CuNi alloy is used
- Fig. 12 shows the case where UBM of CuNiP alloy is used.
- the electronic components described so far in the present invention include electric circuits such as those provided on a printed circuit board, a flexible substrate, a ceramic substrate, a glass ceramic substrate, a semiconductor substrate, a chip capacitor, a chip resistor, etc. It refers to the general parts to be configured.
- electronic members are electrically connected via a UBM, a solder bump, and the like.
- the electronic member include a substrate (a mother board, an interposer substrate, a semiconductor package, a printed substrate, a flexible substrate, a ceramic substrate, a glass ceramic substrate, a semiconductor substrate, etc.) and a semiconductor chip (semiconductor element).
- a connection form between the electronic members connection between a substrate and a substrate, a semiconductor element and a semiconductor element, and a connection between a substrate and a semiconductor element can be mentioned.
- FIG. 13 shows that the UBM of the present invention is formed on the surface of an electrode pad electrically connected to a semiconductor element, and a solder bump is formed between the electrode pads of these two or more semiconductor elements via a CuNiSn alloy layer. It shows a cross-sectional view of a semiconductor package in which the connected package is mounted on a printed circuit board.
- solder bumps 24 for the primary connection and the respective electrode pads 26, 27, 28, 29 of the mother board substrate 21, the interposer substrate 22 and the semiconductor chip 23 A package structure using UBMs 30, 31, 32, 33 of CuNi-based alloy or CuNiP-based alloy with the solder bumps 25 for next connection can be considered.
- the semiconductor package shown in FIG. 13 is an example, and in the semiconductor package of the present invention, a chip (semiconductor element) and a chip-on-chip in which the electrodes of the chip are connected by solder bumps. Includes package stacks with solder bumps connecting package and package electrodes.
- the chip-on-board in which a chip is connected to a mother board includes one to which the UBM-solder bump connection structure of the present invention is applied.
- the UBM contact bump connection structure of the present invention can be applied to all electronic devices such as mobile phones, computers, digital cameras, memory modules, PDAs and the like.
- a semiconductor wafer having an A1 electrode pad on its surface is subjected to Pd activation or zincate treatment, and then immersed in an electroless CuNiP plating solution maintained at 80 ° C. for about 20 minutes.
- an electroless CuNiP plating solution maintained at 80 ° C. for about 20 minutes.
- the electrode pad material is Cu
- a Pd catalyst can be used to activate the electrode pad, and an electroless CuNiP based alloy layer can be selectively formed on the electrode pad.
- the electroless CuNiP plating solution contains an appropriate amount of Cu ions, Ni ions, sodium hypophosphite, a complexing agent, a pH buffer, a stabilizer and the like.
- the CuNiP alloy UBM containing 5 atm or more of Cu, 40 at% or more of Ni, 25 at% or less of P, and 5 ⁇ m It can be formed.
- a solder bump of SnAgCu is mounted by a ball transfer method, and reflow is performed to bond the UBM and the solder bump.
- a Cu-Ni-Sn alloy layer having an average Ni-Z-Cu ratio of about 0.7 and a P-rich layer between the solder bumps and the UBM is formed.
- the semiconductor wafer is diced into chips, and the build-up substrate on which a CuNiP-based alloy UBM having the same composition is formed is aligned using a mounter, and then placed in a reflow furnace. Build up semiconductor wafer Connect to the board.
- Underfill resin is injected into the flip connection portion produced in this manner to produce CSP or BGA.
- solder ball transfer method other methods such as solder paste printing, the super solder method, the super method, the electrolytic method, the sputtering, and the vapor deposition can be applied as the method for forming the solder bumps. .
- the electrode pad portion was opened by photolithography. Next, it is immersed in an electrolytic CuNi plating solution containing Cu ions and Ni ions, and a current is applied to precipitate a CuNi-based alloy layer on the semiconductor wafer by 5 / ⁇ .
- the contents of Cu and Ni in the plating solution are adjusted, and the desired film composition (Cu: 15 to 60 at%, Ni: 40 to 85 at. %) To be obtained.
- a P source such as sodium hypophosphite may be added to the plating solution.
- a semiconductor wafer is further immersed in a solder plating solution and current is supplied to form a solder bump with a thickness of about 100 m.
- a reflow furnace is used to form a device with a bonding structure that has a CuNiSn alloy layer with an average NiZCu ratio of 2.3 or less at the interface between the Nondap bump and the UBM.
- a buildup substrate having a Cu electrode pad on the surface is treated with Pd catalyst to activate the electrode node surface, and then immersed in the electroless CuNiP plating solution described in the first embodiment to obtain CuNiP. Deposit about 5 / z m of the alloy film. Thereafter, a solder paste is printed on the electrode portion and reflow is performed to form a SnAg solder precoat on the CuNiP alloy layer. After this, by mounting the CSP on which the SnAg solder bump is formed on this printed board, a device having a CuNiSn alloy layer and a P-rich layer with an average NiZCu ratio of 2.3 or less at the interface between the solder bump and the UBM is manufactured. .
- Example 4 Immerse the printed circuit board provided with the Cu electrode pad connected to the plating lead wire on the surface in the electrolytic CuNi plating solution, and connect it to the cathode side to flow the current, so only CuNi on the electrode pad of Cu Based alloy film layer composition (film composition: Cu: 15 to 60 at%, Ni: 40 to 85 at%) is formed 3 / z m.
- SnAgCu paste is printed on the UBM-formed electrode pad and reflow is performed to form solder bumps on the UBM, and a CuNiSn alloy layer with an average NiZCu ratio of 2.3 or less at the interface between the solder bumps and the UBM.
- the surface of the electrode pad is activated by applying a Pd catalyst treatment to a galacera substrate having an Ag electrode pad formed on the surface, and first immersed in an electroless NiP plating solution in order to enhance the adhesion, 1 ⁇ m of NiP alloy Form about m. Thereafter, the NiP plating film is further activated with a Pd catalyst, and then dipped in an electroless CuNiP plating solution to form a CuNiP alloy layer of 20 at% Cu, 6% at Ni, and 20 at% P at about 3 ⁇ m. ,Form. After this, this substrate is immersed in a Sn AgCu melter to form solder bumps on the CuNiP surface.
- a device having a bonding structure having a CuNiSn alloy layer having a mean NiZCu ratio of 2.3 or less and a P-rich layer is formed at the interface between the solder bump and the UBM.
- a semiconductor wafer having A1 electrode pads on the surface is activated by zincate treatment, and then immersed in an electroless CuNiP plating solution maintained at 80 ° C. for about 20 minutes to form a CuNiP alloy on the semiconductor wafer surface. Deposit layer about 5 m.
- an electroless CuNiP plating solution maintained at 80 ° C. for about 20 minutes to form a CuNiP alloy on the semiconductor wafer surface.
- Deposit layer about 5 m.
- the sodium hypophosphite concentration in the electroless CuNiP plating solution about 0.1 to 1. Omol / L
- 44 to 60 at% Cu, 29 to 40 at% Ni and 8 to 16 at% can be formed.
- P has a property of co-depositing with Ni, so P can precipitate only about 40% or less of the Ni content. .
- the Ni content in the CuNiP-based alloy is about 2.5 times or more the P content.
- solder bump of SnAgCu is mounted by a ball transfer method, and the UBM is reflowed. And solder bumps.
- This treatment makes it possible to form a Cu-Ni-Sn alloy layer having an average Ni--Z--Cu ratio of about 0.4 between the solder bumps and the UBM, and a P-rich layer.
- the semiconductor wafer is diced into chips, and aligned with a printed wiring board on which a UNi of a CuNi P-based alloy having the same composition is formed, using a mounter. Thereafter, the device is put into a reflow furnace to form a device having a bonding structure of a Cu-rich CuNiSn alloy layer at the interface between the solder bump and the UBM.
- the UBM formed according to the above Examples 1 to 6 the composition of the solder bump, the average NiZCu ratio in the CuNiSn alloy layer, and the bump pull strength were measured. These characteristic values were measured by the same method as in FIGS. 5 and 8.
- the composition of the solder bump was also measured by the same method as the composition of the UBM. The results are shown in Tables 5 and 6.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/298,285 US20090174052A1 (en) | 2006-05-29 | 2007-05-22 | Electronic component, semiconductor package, and electronic device |
| EP07743857A EP2023384A4 (en) | 2006-05-29 | 2007-05-22 | ELECTRONIC COMPONENT, SEMICONDUCTOR SEALING AND ELECTRONIC ARRANGEMENT |
| JP2008517858A JP5099644B2 (ja) | 2006-05-29 | 2007-05-22 | 電子部品、半導体パッケージ及び電子機器 |
| CN200780019384XA CN101454887B (zh) | 2006-05-29 | 2007-05-22 | 电子部件、半导体封装件和电子器件 |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006-148207 | 2006-05-29 | ||
| JP2006148207 | 2006-05-29 | ||
| JP2007010094 | 2007-01-19 | ||
| JP2007-010094 | 2007-01-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2007138922A1 true WO2007138922A1 (ja) | 2007-12-06 |
Family
ID=38778441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2007/060423 Ceased WO2007138922A1 (ja) | 2006-05-29 | 2007-05-22 | 電子部品、半導体パッケージ及び電子機器 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20090174052A1 (ja) |
| EP (1) | EP2023384A4 (ja) |
| JP (1) | JP5099644B2 (ja) |
| CN (4) | CN102157458B (ja) |
| WO (1) | WO2007138922A1 (ja) |
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| JP2009238905A (ja) * | 2008-03-26 | 2009-10-15 | Nippon Telegr & Teleph Corp <Ntt> | 半導体素子の実装構造および半導体素子の実装方法 |
| WO2009140238A3 (en) * | 2008-05-12 | 2010-02-25 | Texas Instruments Incorporated | Structure and method for reliable solder joints |
| JP2014192383A (ja) * | 2013-03-27 | 2014-10-06 | Fujitsu Ltd | 電子部品及び電子装置の製造方法 |
| JP2015115363A (ja) * | 2013-12-09 | 2015-06-22 | 富士通株式会社 | 電子装置及び電子装置の製造方法 |
| JP2017073497A (ja) * | 2015-10-08 | 2017-04-13 | イビデン株式会社 | プリント配線板およびその製造方法 |
| JP2019085631A (ja) * | 2017-11-09 | 2019-06-06 | 株式会社クオルテック | 電子部品の製造方法、及び電子部品 |
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- 2007-05-22 JP JP2008517858A patent/JP5099644B2/ja not_active Expired - Fee Related
- 2007-05-22 WO PCT/JP2007/060423 patent/WO2007138922A1/ja not_active Ceased
- 2007-05-22 CN CN2011100421454A patent/CN102157458B/zh not_active Expired - Fee Related
- 2007-05-22 US US12/298,285 patent/US20090174052A1/en not_active Abandoned
- 2007-05-22 CN CN200780019384XA patent/CN101454887B/zh not_active Expired - Fee Related
- 2007-05-22 CN CN201210183161.XA patent/CN102738107B/zh not_active Expired - Fee Related
- 2007-05-22 CN CN2012101828814A patent/CN102738106A/zh active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009238905A (ja) * | 2008-03-26 | 2009-10-15 | Nippon Telegr & Teleph Corp <Ntt> | 半導体素子の実装構造および半導体素子の実装方法 |
| WO2009140238A3 (en) * | 2008-05-12 | 2010-02-25 | Texas Instruments Incorporated | Structure and method for reliable solder joints |
| JP2014192383A (ja) * | 2013-03-27 | 2014-10-06 | Fujitsu Ltd | 電子部品及び電子装置の製造方法 |
| JP2015115363A (ja) * | 2013-12-09 | 2015-06-22 | 富士通株式会社 | 電子装置及び電子装置の製造方法 |
| JP2017073497A (ja) * | 2015-10-08 | 2017-04-13 | イビデン株式会社 | プリント配線板およびその製造方法 |
| JP2019085631A (ja) * | 2017-11-09 | 2019-06-06 | 株式会社クオルテック | 電子部品の製造方法、及び電子部品 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102738107B (zh) | 2014-08-27 |
| EP2023384A4 (en) | 2013-01-02 |
| US20090174052A1 (en) | 2009-07-09 |
| CN102157458A (zh) | 2011-08-17 |
| EP2023384A1 (en) | 2009-02-11 |
| CN102738106A (zh) | 2012-10-17 |
| CN101454887B (zh) | 2011-03-23 |
| CN102157458B (zh) | 2012-10-17 |
| CN101454887A (zh) | 2009-06-10 |
| JPWO2007138922A1 (ja) | 2009-10-01 |
| CN102738107A (zh) | 2012-10-17 |
| JP5099644B2 (ja) | 2012-12-19 |
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