WO2008084681A1 - メモリ制御装置、メモリ装置およびメモリ制御方法 - Google Patents

メモリ制御装置、メモリ装置およびメモリ制御方法 Download PDF

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Publication number
WO2008084681A1
WO2008084681A1 PCT/JP2007/074878 JP2007074878W WO2008084681A1 WO 2008084681 A1 WO2008084681 A1 WO 2008084681A1 JP 2007074878 W JP2007074878 W JP 2007074878W WO 2008084681 A1 WO2008084681 A1 WO 2008084681A1
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WO
WIPO (PCT)
Prior art keywords
memory
memory devices
memory control
physical addresses
access commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/074878
Other languages
English (en)
French (fr)
Inventor
Takashi Yamada
Daisuke Imoto
Koji Asai
Nobuyuki Ichiguchi
Tetsuji Mochida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to CN2007800283117A priority Critical patent/CN101495975B/zh
Priority to JP2008553058A priority patent/JP4996626B2/ja
Priority to EP07860107A priority patent/EP2071468A4/en
Priority to US12/443,598 priority patent/US8307190B2/en
Publication of WO2008084681A1 publication Critical patent/WO2008084681A1/ja
Anticipated expiration legal-status Critical
Priority to US13/615,983 priority patent/US8738888B2/en
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Memory System (AREA)

Abstract

　本発明のメモリ制御装置は、マスタから発行された前記メモリアクセス要求を、メモリデバイス毎のアクセスコマンドに分割するコマンド生成部（１０２）と、前記複数のメモリデバイスにアクセスコマンドを発行するコマンド発行部（１０４）、（１０５）と、マスタ（２００）とメモリ（０）、（１）間でデータを必要に応じて入れ換えるデータ制御部（１０６）とを備え、コマンド生成部（１０２）は、分割した複数のアクセスコマンドに対応する前記複数のメモリデバイスの物理アドレスが同じ場合と異なる場合とで、複数のメモリデバイスへ同じ物理アドレスを出力する制御と、異なる物理アドレスを出力する制御とを切り替える。
PCT/JP2007/074878 2006-12-25 2007-12-25 メモリ制御装置、メモリ装置およびメモリ制御方法 Ceased WO2008084681A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN2007800283117A CN101495975B (zh) 2006-12-25 2007-12-25 存储控制装置、存储装置及存储控制方法
JP2008553058A JP4996626B2 (ja) 2006-12-25 2007-12-25 メモリ制御装置、およびメモリ制御方法
EP07860107A EP2071468A4 (en) 2006-12-25 2007-12-25 MEMORY CONTROL DEVICE, MEMORY DEVICE AND MEMORY CONTROL METHOD
US12/443,598 US8307190B2 (en) 2006-12-25 2007-12-25 Memory control device, memory device, and memory control method
US13/615,983 US8738888B2 (en) 2006-12-25 2012-09-14 Memory control device, memory device, and memory control method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2006-347132 2006-12-25
JP2006347132 2006-12-25
JP2007-123987 2007-05-08
JP2007123987 2007-05-08

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/443,598 A-371-Of-International US8307190B2 (en) 2006-12-25 2007-12-25 Memory control device, memory device, and memory control method
US13/615,983 Division US8738888B2 (en) 2006-12-25 2012-09-14 Memory control device, memory device, and memory control method

Publications (1)

Publication Number Publication Date
WO2008084681A1 true WO2008084681A1 (ja) 2008-07-17

Family

ID=39608577

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/074878 Ceased WO2008084681A1 (ja) 2006-12-25 2007-12-25 メモリ制御装置、メモリ装置およびメモリ制御方法

Country Status (6)

Country Link
US (2) US8307190B2 (ja)
EP (1) EP2071468A4 (ja)
JP (1) JP4996626B2 (ja)
KR (1) KR20090065504A (ja)
CN (1) CN101495975B (ja)
WO (1) WO2008084681A1 (ja)

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CN101930414A (zh) * 2009-06-22 2010-12-29 奥林巴斯映像株式会社 数据存取控制装置及数据存取控制方法
CN101930413A (zh) * 2009-06-22 2010-12-29 奥林巴斯映像株式会社 数据传输控制装置和数据传输控制方法
JP2011013909A (ja) * 2009-07-01 2011-01-20 Canon Inc メモリ制御回路
WO2012070247A1 (ja) * 2010-11-26 2012-05-31 パナソニック株式会社 メモリ装置、メモリ制御回路およびメモリ制御システム
JP2013503397A (ja) * 2009-08-26 2013-01-31 クアルコム，インコーポレイテッド デュアルチャネル動作中にアドレス／コントロール信号をインターリーブすることによるシングルチャネルとデュアルチャネルのハイブリッドｄｄｒインターフェース方式
JP2013505616A (ja) * 2009-09-17 2013-02-14 インターナショナル・ビジネス・マシーンズ・コーポレーション エラー検出に応答するためのシステム及び方法
JP2014160538A (ja) * 2004-11-29 2014-09-04 Rambus Inc マイクロスレッドメモリ
JP2018517205A (ja) * 2015-04-23 2018-06-28 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． 拡張メモリにアクセスするための方法、デバイス及びシステム
JP2020042558A (ja) * 2018-09-11 2020-03-19 株式会社東芝 画像描画装置
WO2020223849A1 (en) * 2019-05-05 2020-11-12 Yangtze Memory Technologies Co., Ltd. Memory control system with a sequence processing unit
JP2023168234A (ja) * 2022-05-11 2023-11-24 地平▲線▼（上海）人工智能技▲術▼有限公司 記憶装置、方法、電子機器及び記憶媒体

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CN113704143B (zh) * 2021-08-27 2025-03-18 湖南国科微电子股份有限公司 数据读取方法、装置及计算机设备
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JP2014160538A (ja) * 2004-11-29 2014-09-04 Rambus Inc マイクロスレッドメモリ
CN101930413A (zh) * 2009-06-22 2010-12-29 奥林巴斯映像株式会社 数据传输控制装置和数据传输控制方法
CN101930414A (zh) * 2009-06-22 2010-12-29 奥林巴斯映像株式会社 数据存取控制装置及数据存取控制方法
JP2011013909A (ja) * 2009-07-01 2011-01-20 Canon Inc メモリ制御回路
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Publication number Publication date
US8307190B2 (en) 2012-11-06
US20100030980A1 (en) 2010-02-04
US20130013879A1 (en) 2013-01-10
EP2071468A1 (en) 2009-06-17
EP2071468A4 (en) 2010-11-03
CN101495975A (zh) 2009-07-29
CN101495975B (zh) 2011-10-05
US8738888B2 (en) 2014-05-27
KR20090065504A (ko) 2009-06-22
JPWO2008084681A1 (ja) 2010-04-30
JP4996626B2 (ja) 2012-08-08

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