WO2008091221A2

WO2008091221A2 - Micropackaging method and devices

Info

Publication number: WO2008091221A2
Application number: PCT/SE2008/050093
Authority: WO
Inventors: Thorbjörn EBEFORS; Edvard KÄLVESTEN; Tomas Bauer
Original assignee: Silex Microsystems AB
Current assignee: Silex Microsystems AB
Priority date: 2007-01-25
Filing date: 2008-01-25
Publication date: 2008-07-31
Anticipated expiration: 2009-07-25
Also published as: WO2008091220A1; EP2106617A1; TW200848359A; SE533579C2; EP2106617B1; US8598676B2; EP2121511A4; US20120292736A1; EP2106617A4; US20100053922A1; WO2008091221A3; TWI461348B; SE0700172L; EP2121511A2; EP2121511B1; US20090302414A1

Abstract

The invention relates in one aspect to a method of micro-packaging a component. At least a first and a second semi-conductor substrate are provided, one of which has electrical through connections (vias). A depression in either one of said substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. The invention also relates to a micro-packaged electronic or micromechanic device, comprising a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing. An electronic or micromechanic component is attached to said electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box.

Description

MICROPACKAGING METHOD AND DEVICES

Technical Field The present invention relates to packaging of components for electronic devices, in particular devices requiring small components, such as but not limited to electrical and micromechanical surface micromachined oscillators for computers, mobile phones and the like.

Background of the Invention

Certain components for surface mounting on circuit boards must be packaged in protective casings, quite often in vacuum or other controlled atmosphere/ ambient and also need to be provided with connector legs for mounting or solder bumps for surface mounting. Today most encapsulating casings are made of polymers or ceramic materials. The latter is commonly used for packaged components that are hermetically sealed.

The inner compartment of such ceramic casings is made by milling processes. These processes have inherent drawbacks.

One thing is that the thickness of the package has an inherent lower limit. For e.g. mobile phone applications thickness is a vital parameter, and thus it would be desirable to further reduce the component thicknesses.

Sealing of individual packages is required, i.e. each individual item has to be handled separately for attaching a lid under vacuum, which requires elaborate equipment.

Also, there will always be rounded corners in the interior compartment because of the nature of the milling tools. Also, it is difficult to make very thin walls in such ceramic materials. This puts a lower limit of the size of such casings.

The smallest dimensions are dependent on the dimensions and the pitch between the interconnecting vias to the outside of the package. Package-through vias with small dimensions and small separation/ pitch is desired to further reduce the package size.

Furthermore, there will be material incompatibility between the ceramic in the casing of the package and the components inside, which often are silicon based, as for example MEMS (Microelectromechanical Systems) devices. Differences in e.g. thermal expansion coefficients can cause artefacts.

Summary of the Invention

The object of the invention is to enable further miniaturization of such packaged components.

This object is achieved by the method and the device as defined in the independent claims.

The present invention provides a method of micro-packaging a component. At least a first and second substrate is provided of which the first substrate is a semiconductor substrate being provided with at least one electrical through connection. A compartment is formed in either one or a plurality of the substrates by etching. A component is provided above the first semiconductor substrate so that it covers the at least one through wafer connections and will be located within the compartment. The component is connected to at least one through wafer connection and the substrates are joined to form a sealed micro-packaged device. P There may also be provided a plurality of through wafer connections. Preferably the substrates are semiconductor substrates. Preferably the substrates comprising through wafer connections are thick enough to easily be handled during the manufacturing.

A device according to present invention is a micro-packaged electronic or micromechanic device that comprises a thin walled casing which encloses a compartment. Electrical through connections through the bottom of the casing are connected to an electronic or micromechanic component and the micro-packaged device is hermetically sealed for maintaining a desired atmosphere, suitable vacuum inside. The casing is made of a semiconducting material and the component is located immediately above the through connections.

By the method according to the invention the thickness of packaged components can be reduced at least by 50%.

Hermetic sealing can be made at wafer-level using wafer bonding which significantly simplifies the manufacturing process thereby reducing costs. Furthermore, a higher density of vias is possible in silicon based packages by using photolithography and etching processes than possible by using mechanical machining processes.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus not to be considered limiting on the present invention.

Brief Description of the Drawings

Preferred embodiments of the invention will now be described with reference to the accompanying drawings, wherein

Fig. 1 shows in cross-section an embodiment of a device according to the invention; Fig. 2 shows another embodiment of a device according to the invention;

Fig. 3 is a perspective view of a micro-packaged device seen from the bottom side;

Fig. 4 is perspective view of a micro-packaged device from above with the lid taken off;

Fig. 5a is a perspective view similar to Fig. 3 but with a component to be mounted inside shown in shadow lines;

Fig 5b illustrates a similar device as in Fig 8 (a) but having an insulating trench between the vias;

Fig. 6 illustrates packaging of monolithically integrated components with high density via structures; Fig. 7 shows an array of contiguous vias;

Fig. 8 illustrates the geometry for corner etching of insulating trenches;

Fig. 9 shows a via with trench redundancy;

Fig. 10a illustrates (not to scale) an embodiment wherein the micro-packaged device is made by forming the vias on a flat wafer and making a depression in the "lid wafer" to form a compartment for the component;

Fig. 10b illustrates an embodiment wherein the micro-packaged device is made by forming a compartment by making a depression in both the via wafer and in the "lid wafer";

Fig. 10c illustrates an embodiment wherein the compartment of the micro-packaged device is made by etching a hole in an intermediate substrate;

Fig. 1 1 illustrates an embodiment wherein a discrete component is surface mounted on the via wafer;

Fig. 12a illustrates an embodiment wherein the component is provided using surface micromachining; Fig. 12b illustrates an embodiment wherein the component is connected to one through wafer connection and in addition directly to the via wafer;

Fig. 13 illustrates a micro-packaged component manufactured using a SOI wafer and having an insulating trench separating through wafer connections; and

Fig. 14 illustrates a micro-packaged device according to the invention wherein the component is mounted on the "lid wafer"; and Fig.15 illustrates a bulk micromachined component integrated with an intermediate substrate.

Detailed Description of Preferred Embodiments The invention is based on the use of electrical through connections (or "vias"), which enables connection of packaged micro-components to circuit boards or to other components with the provision of bulky connector legs or pins, and wafer- level hermetic encapsulation. The terms electrical through connection and via are interchangeably used in this application.

Preferably the starting wafers having said vias are semiconductor wafers, more preferably single crystalline silicon wafers, however not limited to this. The term "semiconductor wafer" also comprises other wafer materials typically used in the field, such as glass wafers and ceramic wafers. The terms wafer and substrate are interchangeably used throughout this application since processing preferably is made on wafer level, i.e. many devices are manufactured in parallel.

Preferably, the packaged component is made by using a wafer having been provided with vias in accordance with the teachings of the International Patent Publication WO 2004/084300 Al (Silex Microsystems), the content of which is incorporated herein in its entirety. In particular the invention of WO2004/084300 relates to a method of making an electrical through connection between a first (top) and a second (bottom) surface of a semiconductor substrate. The method comprises creating a trench in the first surface and establishing an insulating enclosure entirely separating a portion of said substrate, defined by said trench, i.e. an insulated through connection. One product manufactured according the method is usable as a starting substrate, a so called interposer, for further manufacturing of micro-electronic and/or micro-mechanic devices. One advantage of this kind of product (interposer) is that the through connections are made of the wafer material and therefore are suitable for the processing usually applied to such wafers, i.e. the wafers can withstand temperatures, chemicals that commonly are used in conventional processing of semiconductor wafers. Another advantage of a wafer having these vias is that the wafer may have a thickness of 300-700μm, which makes it possible to handle the wafers during the further processing. For different applications, such as RF (radio frequency) applications comprising e.g. switches or resonators, there is a need for low resistivity through wafer connections. For such applications other via technologies than the one explained above using the wafer material or e.g. polysilicon as a conductor may have to be used. The international patent application WO 2007/089206 teaches a method to provide a wafer with closely spaced metallic through wafer connections. This wafer is also suitable as a starting substrate for further manufacturing of electronic and or micro-mechanic devices.

Another kind of starting substrates with pre-made vias is a so called SOI (silicon on insulator) wafer, wherein the pre-made vias are made in the device layer of the wafer, i.e. not extending entirely through the whole wafer. The through connections are instead exposed in subsequent process steps.

Thus, the starting substrate for the process according to the invention is a wafer 1 having pre-made vias 2, as can be seen in Figs. 1 and 2. These figures and the following figures are not drawn to scale and serve to illustrate the invention.

The starting wafer should be thicker than about 300μm in order to provide enough rigidity to enable handling of the wafer during processing without risk of breaking it. Preferably the starting wafer comprising the through wafer connections has a thickness of > 100μm, preferably >200μm, more preferably >300μm, still more preferred >400μm, and most preferred >500μm.

Referring to Fig. 1 , in one embodiment, the wafer is first subjected to a patterning to define the compartments 3 in which the components 4 are to be mounted. Example of components are e.g. all kinds of MEMS devices (sensors and actuators), either in discrete form or monolithically integrated on silicon; capacitors and/ or resistors of various materials; EMC Components such as EMI Filters, Transient Voltage Suppressors; Timing Devices such as Crystal Units, Clock Oscillators, TCXO,

VCXO, High Precision Oscillators for Industrial Applications, Ceramic Resonators, SAW Resonators; Crystal Products of various kinds; Filters such as SAW Filters, Monolithic Crystal Filters; RF Modules such as Antenna Switch Module; Piezo Products such as Shock Sensors, Piezoelectric Acoustic Generator Elements, Piezo Buzzers. For the purpose of this application the term "compartment" 3 refers to a volume that has been formed in one or a plurality of substrates in order to receive a component, which subsequently is encapsulated therein. The compartment 3 may, before the encapsulation, be a depression 3a or a hole 3b in one or in a plurality of the substrates ( 1 , 10, 1 1).

A suitable etch is applied to the patterned wafer, and a suitably shaped depression, typically rectangular but not limited to this, is thus formed in any of the via wafer or the lid wafer or in both. An advantage with an etching process as compared to the prior art milling, is that it is possible to make very sharp corners in the "box"- like depression, and furthermore silicon processing using lithography and etching enables making very small "boxes" with accurate dimensions. Then, a second pattern is applied to define mounting members corresponding to the vias 2, i.e. the surface of the vias 2 are covered with etch resistant material. A second etch is applied to etch a deeper depression, whereby protruding members 2 are formed. The depression is suitably 150μm deep, and the height of the protruding members is suitably of the order 20μm, but these measures can of course vary depending on the application in question.

On top of these protruding members 2 pads 5 or bumps of gold (Au), solder, AuSn., PbSn, etc. are formed by any suitable method such as plating, sputtering etc. If the box is made in the lid wafer 10 these bumps 5 are preferably made on the flat via wafer 1 which simplifies the manufacturing.

The component 4 to be mounted in the protective casing can be attached directly to the through wafer connections 2 e.g. by soldering, ultrasonic welding, gluing and wire bonding, in an automated processing using standard surface mounting machines. "Directly" is for the purpose of this application interpreted to mean that there is no additional routing needed to form a contact pad, but as illustrated in Fig. 1 there may be e.g. pads 5 or bumps in-between the component 4 and the through wafer connection 2. By attaching the component 4 directly to the vias the component 4 can be place immediately above the through connections 2. When the component 4 is in place, the entire wafer 1 is put in a vacuum and a lid 10 is applied to cover the entire wafer 1. For bonding the lid 10 to the component wafer 1 , there are several options available.

Fig. 3 illustrates a micro-packaged device having large contact areas 8 on the bottom side of the device. The routing 7 connects the large contact areas 8 with the through connections 2 which extends into the sealed package.

Referring to Fig. 4, one can apply a "frame" 9 of gold on the lid wafer corresponding to the size of the package, i.e. a strip of gold having the same dimensions as the package, such that when the lid wafer is aligned to the component wafer, pressure and heat is applied, there will be a eutectic bonding between the lid 10 and the silicon in the wafer 1. In this case the insulating layer 6-T is not applied.

On the other hand the gold can be applied to the layer 6-T and instead having the lid "silicon clean", i.e. letting the silicon in the lid 10 bond to the gold on the component wafer 1.

A second method is to apply a gold layer on both the lid wafer 10 and the component wafer 1 and apply what is referred to as a thermocompression bonding process.

Thirdly, a solder (e.g. PbSn or AuSn) can be applied on one of the wafers ( 1 , 10, 1 1) and gold on the other and a soldering process is made.

Optionally the bonded wafers can be grinded or polished to reduce the total thickness to a desired thickness suitable for the application in question. E.g. for mobile phones thin packages are essential.

On the back side of the wafer 1 an insulating layer 6-B of e.g. oxide, or any other suitable material is applied. This layer could have been applied before any other processing is done, as could the insulting layer 6-T on the top side of the wafer. In this layer 5 openings are made by patterning/ etching to expose the via to enable contacting to other components or to a circuit board. Suitably there is provided a metallization 7 of e.g. Al that contacts the via material and can be provided as narrow contact strips from the via to the edges of the entire packaged structure. This can be seen in the bottom view in Fig. 3, wherein the Al-strips 7 are shown. At the edges there can be provided larger contact areas 8 for further bonding, commonly referred to as bumps. The skilled man will find possible means for this without inventive work, but as an example can be mentioned various kinds of solder (Pb/Sn, Au/Sn, etc.) for soldering or "flip-chip" mounting. The package can be provided with so called Under Bump Metallization (UBM) and the solder provided on the circuit board, but the solder can also be provided on the package.

Although the figures show only one micro-packaged device, it is to be understood that there can be made several thousand items on one wafer in one batch. With this wafer-level packaging approach according to the invention it is possible on a wafer level to provide several thousands of micro-packaged components wherein the exterior dimensions can be made substantially smaller than with presently used technology.

In a final step in a manufacturing process the wafers are cut up in individual micro- packaged components by e.g. sawing.

Referring to Fig. 2, in one embodiment the bump structures are not made from the vias 2. Instead the depression 3 is made in one etching step, either on the via wafer or the lid wafer or both (the two latter embodiments are schematically illustrated in Fig. 10). Thereafter gold bumps 5' are provided such that they exhibit the same height as the protruding members 2 in Fig. 1. These gold bumps 5' can then be used for attaching a component 4 in a similar fashion as described in connection with Fig. 1.

Fig. 5a illustrates a component 4 which is provided immediately above a depression 3a forming a compartment 3 in a a first semiconductor substrate 1 comprising two through connections extending entirely through the first substrate 1 to the bottom side thereof. The through connections are protruding into the depression. A second substrate 10 is arranged above the component 4. After surface mounting of the component directly to the through wafer connections the compartment is sealed by joining the substrates together to form a sealed micro-packaged device. Fig. 5b illustrates a similar arrangement as shown in Fig.5a but the first substrate having the through connections 2 is a SOI substrate. In addition the first substrate 1 comprises an insulated trench 14 extending entirely through the first substrate 1. The insulating trench 14 is electrically insulating one portion of the first substrate from another, each portion comprising one of the two through wafer connections 2. Thereby the capacitive coupling between the through connections 2 is reduced and in addition, due to the insulating layer between the bulk Si layer and the device layer of the SOI substrate there is a vertical electrical insulation in the device.

Referring to Fig. 6, in one embodiment the reference numerals are used as follows: 100 is a "lid wafer" on which a movable switch 102 is provided, comprising a flexible membrane (the flexing during actuation is shown with a broken line). 101 is a wafer comprising an array of high-density vias 103a-e. 103a is a "dummy" via used for etch load compensation, 103b is used for actuation purposes, 103c is a signal via, 103d is coupled to ground, 103e is another actuation via, 104a and 104b are electrostatic actuation pads, 105 designates Au pads for thermo compression bonding. 106 is a UBM and 107 is a solder bump. 108 are sawing traces.

Fig. 6 illustrates the wafer level packaging according to the invention which enables a considerable decrease in the pitch distance between two neighbouring vias. This is a great advantage that can be obtained when silicon is used for fabricating the hermetic sealed wafer through -connections. On the lid wafer, that preferably is a silicon wafer or a transparent glass wafer, micro structures (e.g. switches or micro mirrors) are integrated in large array configurations using surface micromachining technologies well known to the man skilled in art.

Using the silicon via technology, disclosed in Swedish patent No. SE-526 366 (Silex) a great advantage can be obtained. Namely, the device can be substantially simplified since all lateral metal routing could be avoided because of the vias located immediately below each component. However, routing on both wafers (i.e. component and lid wafer, respectively) and both the front side and back side of the via wafer is still possible to do like in prior art techniques (compare Fig. 3 and Fig. 6) . Especially for switch applications for RF signals the possibility to make micro strip line layouts is a great advantage. Fig. 6 illustrates an example of a device having a large array of identical sub components (=double suspended membrane switch structures ( 102)). The signal contacts ( 104b) on the membrane are individually switched by electrostatic actuation pads ( 104a). In order to make the array of switches as small as possible high density arrays of vias (103b-e) are needed.

Wafer level encapsulation of these microstructures under vacuum (or other controlled ambient) is obtained by bonding the LID wafer and via wafer together. Among the different wafer level bonding alternatives are:

- Au-Au for thermo compression bonding - AuSn, PbSn etc against Au etc for solder bonding

- Au-Si for eutectic bonding

- Si-Si, SiO-Si or SiO-SiO (or other alternative isolating materials such as SiN) for fusion bonding (optional plasma enhanced low temp bonding)

- Si-glass for anodic bonding (optional Al on Si for Al/ glass anodic bonding)

Among the many available ways of adding these bonding materials on the wafer are (but not limited to) : conventional sputter/ evaporation metallization followed by photolithography and etching, lift-off, shadow evaporation/ sputtering, screen printing, preform.

Bonding alternatives as well as methods for applying the materials are well known for the skill man in art.

After the two wafers are bonded together processing as described in Fig 3 is made. There exist several different methods for under bump metallization-UBM (maybe with routing-7), with the option of adding solder bumps-8 for flip-chip surface mounting. An overview of these different technologies are found in for example article "The Use of Solder as an Area-Array Package Interconnect" by Dr. Ning- Cheng Lee in Sept-Oct-99 number of Chip Scale Review (available at http:/ /www.chipscalereview.com/issues/ 1099/ featured 1.htm). For tight via pitch applications (i.e. via pitches less than 150 μm) the solder bumping is preferably made by the photo lithography and electroplating process.

For certain applications it may be necessary to provide wafer through connections by "vias" that are so closely spaced that it will be impossible to make separate vias having the necessary close pitch. A typical centre-to-centre distance for circular vias is about 250μm, if trenches are 10-30μm wide and the diameter of vias is lOOμm. The starting wafer is typically 300-450μm in order to be processed without a handling wafer attached thereto. For such thickness of the wafer the typical trench width is 15-20μm and the via diameter is about 50- 100μm.

Closely spaced through wafer connections can also be accomplished if using a SOI-substrate having a device layer thickness of about 50-200μm, as illustrated in Fig. 5b. For a device layer thickness of lOOμm a typical trench width is about 5μm and the via diameter is about 20 μm.

However, referring to Fig. 7, the inventors have devised a method of making very closely spaced vias, and an example of such vias 2 is schematically shown in Fig. 5 as a top view of a portion of a wafer or substrate 1 having the novel vias provide therein (see also Fig. 6). The filled trenches are designated 54. The idea is to let neighbouring vias share a common insulated trench as at 56 in Fig. 7. A typical centre-to-centre distance for these vias is about 50μm, if trenches are 5- 10μm wide and the side dimension of vias is, typically 35μm.

However, in the process of making arrays of contiguous vias of this type, the problem of varying etch performance over the surface of a wafer is noticeable and will have an influence on the result. In order to make what is referred to as an "etch load compensation", in accordance with an aspect of the invention there will always be made a redundant via at each end of the array. These outermost vias in the array will not be used in operation of the array, but are only present for the above mentioned reason. See Fig. 6, item 103a.

However, there is a further problem associated with the manufacture of this kind of via arrays. This problem occurs in the corners where trenches meet, i.e. at 58 in Fig. 7. What happens is that the applied etch will act on the wafer material from two or more directions (depending on the number of trenches that meet), and the result is that the depth to which the etch will reach will vary and become deeper at the corners. The etch will therefore penetrate through the wafer or reach a stop layer at different times in different locations, which could be detrimental to the result. Referring to Fig. 8, in order to eliminate or at least reduce this problem to be insignificant, the corners are given a special geometry, which corresponds to the encircled part shown at 58 in Fig. 7. The optimal shape can be determined based on etching parameters used for each specific case. Shaping the trenches like this will ideally result in trenches having essentially the same depth, or at least will the etch not be too deep in the corners of the trench structure.

A still further problem can occur with very long trenches, i.e. where the "via" itself occupies a large surface area on the wafer. Namely, in view of the trenches in a standard situation are about 8μm wide, it will suffice if one single particle with conductive properties gets "caught" in the trench and forms a bridge between the via and the surrounding wafer material in order that the via will be short- circuited. The probability of this happening becomes increasingly larger as the length of the trench increases, and will inevitably cause high rejection rates and thus low manufacturing yields.

By making a trench structure introducing a redundancy, this problem can be ameliorated.

The way this is solved by the invention is as follows.

Referring to Fig. 9, two or more trenches are made as concentric circles or squares or rectangles or any other geometric shape on a wafer or substrate 1 , enclosing a via 2, and each circle is connected to the next by radially extending trenches, as shown in Fig. 9, wherein three concentric trenches are connected by the radial trenches.

Fig. 1 Oa-c illustrates different ways to accomplish a compartment 3 for a component 4 to be hermetically sealed. A first substrate 1 having at least one through connection 2 extending entirely through the substrate 1 is provided. The component 4 is directly attached and connected to the through connection 2. Thereby the through connection is covered by the component 4. As illustrated in Fig. 10a, in one embodiment of the method a depression 3a is etched in a second substrate 10. The depression defines the compartment 3 and by joining the substrates 1 , 10 the compartment 3 is sealed.

As illustrated in Fig. 10b depressions 3a are etched in each of the first substrate and the second substrate 1 , 10, whereby the depressions 3a define the compartment 4. The substrates 1 , 10 are joined together and the compartment 3 containing the component 4 is sealed.

As illustrated in Fig. 10c a intermediate substrate 1 1 is provided in addition to the first and second substrates 1 , 10. A hole 3b defining the compartment 3 is etched in the intermediate substrate 1 1 and the three substrates 1 , 10, 1 1 are joined whereby the compartment 3 containing the component 4 is sealed. In another embodiment a depression 3a may be etched in either one or both of the first and second substrates 1 , 10 in addition to the hole 3b etched in the intermediate substrate. Thereby the depression/ depressions and the hole 3b together define the compartment 4.

Referring to Fig. 1 1 , in one embodiment of the present invention the micro- packaged device 15 comprises a first and second semiconductor substrate 1 , 10, which are joined together. The first semiconductor substrate 1 comprises a depression 3a, whereby the first and the second semiconductor substrates 1 , 10 form a sealed compartment 3 in-between. Trough connections 2 are extending entirely through the first substrate 1 from the bottom of the compartment 3 to the other side of the first substrate 1. A micro-electronic or a micro-mechanic component 4, such as e.g. an ASIC or a resonator crystal, is attached directly to the through connections 2 within the sealed compartment 4. A micro-component 4 is attached directly on pads located on two through connections 2, which are extending entirely through a first semiconductor substrate. A getter plate 12 is deposited on the first substrate 1 within the compartment 3. The through connections 2 are by way of example made in the same material as the first substrate and are electrically insulated by a trench enclosing each via connection. The first and the second substrates are by way of example joined by an Au-Si eutectic joint. In the first step of the manufacturing of the micro-packaged component in Fig. 1 1 a first substrate 1 and a second substrate 10 are provided. The first substrate is at least 300 μm, preferably at least 500 μm thick, and comprises the electrical through connections 2, which are extending entirely though the first substrate 1. The second substrate 10 may in this embodiment be thinner than the first substrate 1 since it is not processed to such a large extent that the handling becomes a problem, preferably the thickness is however at least 300 μm. Although Fig. 1 1 shows only one micro-packaged device 15, it is to be understood that there preferably is made a large number of micro-packaged devices in parallel in one batch, i.e. the first and second substrates 1 , 10 are wafers being large enough for making the large number of micro-packaged devices. As mentioned above the wafers should have a sufficient thickness and the through connections 2 are made of the wafer material, in order to be compatible with conventional processing steps used in the field. A depression 3a is formed in the first substrate 1 using photolithography and etching, such as wet etching or dry etching, in such way that the through connections 2 are exposed in the bottom of the depression 3a. The depth of the depression 3a is dependent on the thickness of the component to be packaged, but typically the thickness is about 150 μm. The through connections 2 at the bottom of the depression 3a of the first substrate 1 are bumped and the component 4 is attached to the bumps. Different methods, such as wafer level flip- chip mounting, thermo compression bonding, gluing, wire bonding etc., can be used to attach the component 4. By way of example a gold layer is applied on the second wafer, at least in an area intended to be brought in contact with the first substrate to form the joint. The second substrate 10 or the lid is aligned to the first substrate 1 and pressure and heat is applied, which gives a eutectic bonding between the first and second substrates 1 , 10 and a sealed compartment 3 containing the component 4 is formed. The eutectic bonding is performed at relatively low temperatures (about 360⁰C), which makes it a suitable bonding method when the attachment of the component 4 have yielded a temperature sensitive joint between the component and the through wafer connection. So far all processing is preferably made on wafer- level in one batch. Individual micro-packaged components are typically formed using dicing. In this description of the manufacturing many of the steps or details thereof are on purpose not disclosed since these steps are well known by a person skilled in the art. In a micro-packaged device according to the present invention it is possible to obtain a controlled atmosphere, i.e. vacuum, protective gas, etc., in the sealed compartment. The long term stability of this controlled atmosphere is dependent on the gas permeability of the joint between the wafers of the package, the gas permeability of the wafers and release of gases from components or other structures enclosed within the compartment. Preferably a getter means 17 in the form of e.g. a plate, a thin film, a bump, etc. is enclosed within the compartment to remove gas molecules that find its way into the compartment. A person skilled in the art is familiar with the different getter materials used, since such is commonly used in other hermetically sealed devices.

There are several alternatives to the eutectic bonding that provide bonding at low temperatures, such as thermocompression bonding or solder bonding. AuSn to Au bonding is for example performed above 280⁰C but there is other solders having lower melting temperature. Another alternative is plasma enhanced bonding, whereby the micro-packaged component has to withstand at least 400⁰C. Ther are also polymer bonding methods which can be used to join the substrates of the micro-packaged component.

Fig. 12 illustrates one embodiment of a micro-packaged device according to the invention similar to the micro-packaged device illustrated in Fig. A, although with a different kind of component 4. The component 4 is a monolithically integrated component, by way of example a polysilicon structure, intended to be used e.g. as a resonator structure or accelerometer structure. The polysilicon structure attached to the through wafer connections of the first substrate 1 but is in between these attachment points free-hanging. The polysilicon structure is fabricated on the first substrate after etching the depression 3a using surface micromachining, which may comprise e.g. sacrificial oxide etching to form a gap between the polysilicon structure and the bottom of the depression 3 a. Such a polysilicon structure can in contrast to e.g. an assembled ASIC withstand high temperatures and since neither the first substrate 1 or the second substrate 10 comprise any other temperature sensible parts, high temperature joining processes such as fusion bonding can be used. By way of example the first and the second substrate 1 , 10 of the micro- packaged device in Fig. 12 are activated in the processing step that removes the sacrificial oxide to and thereafter immediately aligned and fusion bonded, preferably at a temperature of about 900- 1000⁰C to form a sealed package.

One advantage with fusion bonded micro-packaged devices is that the package can be made even smaller. The fusion bonding provides a good sealing and the sealing area can be made smaller than for e.g. thermocompression bonding. Furthermore the bond strength may be so high that a possible breakage of the package will likely take place in the substrate and not in the joint between the substrates.

Fig. 13 illustrates one embodiment of a micro-packaged device according to the present invention similar to the micro-packaged device in Fig. 12. In this case the packaged component 4 is formed in the same material as the first substrate 1. In this embodiment the first substrate 1 comprises a buried oxide layer dividing the first substrate 1 in a device layer and a bulk layer. The thickness of the device layer is usually thinner than the bulk layer, by way of example lOOμm and 300-400μm, respectively. The through connections 2 extend through the device layer and ends in the buried oxide layer which has been removed in an area about the through connections 2. A single crystalline micro-mechanic structure, such as a resonator structure or an accelerometer structure, formed by etching of the bulk layer and sacrificial etching of the buried oxide layer, is attached to the through connections 2. The micro-mechanic structure is formed, preferably in the same process step, in a depression 3 that is etched out in the bulk layer of the first substrate 1. Also in this embodiment of the present invention the first and second substrate 1 , 10 and the constituting parts thereof allow fusion bonding, which preferably is performed immediately after activation in the step of sacrificial etching of the buried oxide layer. A vapour of HF may be used for this activation. Furthermore, the bulk micromachined component is electrically anchored to the first substrate by a filled hole 20 extending entirely through the component 4 and the buried oxide layer between the component and the first substrate 1 down to the through wafer connections. In this embodiment the filled hole 20 is filled with polysilicon which provides an electrical connection between the component 4 and the through connections 2.

Fig. 14 illustrates a micro-packaged device according to the invention comprising a first substrate made of a semiconductor material such as monocrystalline silicon and a second substrate 10 made of glass. The first substrate 1 comprises an array of through connections 2 extending entirely through the first substrate 1 to form electrical connections between the bottom of a depression to a second (lower) side of the first substrate 1. The first and the second substrate 1, 10 are joined together to form a sealed compartment 3, wherein a microelectromechanical component 4 is integrated on the surface of the second substrate 10 within the compartment 3. The first and the second substrates 1, 10 each comprises e.g. a gold layer, which is patterned in order to connect at least one of the through connections 2 in the first substrate 1 with the microelectromechanical component 4 on the second substrate 10. This is accomplished by a strip of the gold layer extending from a through connection 2 along the bottom of the compartment 3 and up along the sidewall of the compartment 3 to the joint between the first and second wafers 1 , 10, wherein the gold layer of the first and second wafers are in contact. From there a strip of gold extends to the microelectromechanical component 4. The first and second substrates 1 , 10 are joined together using thermocompression bonding by applying a high pressure at about 400⁰C, whereby the gold layers adhere to each other. In one embodiment of the present invention the micro-packaged device 15 is formed using a first and a second substrate 1, 10 and at least one intermediate substrate 11. At least the first substrate 1 comprises through connections 2 extending entirely through the first substrate 1 into the compartment 3. The compartment 3 for the component 4 is formed by etching a hole through the intermediate substrate and joining the first, the second and the intermediate substrate. Fig. 15 illustrates one embodiment of this kind. The component 4 is monolithically integrated with the intermediate substrate 1 1 and is formed by bulk micromachining of the intermediate substrate 11. The bulk micromachining both defines the shape of the component 4 and defines at least a portion of the compartment wherein the component 4 is to be packaged. As illustrated in Fig. 15 the component (or the through wafer connections of the first substrate 1 ) is provided with bumps 5 before joining the substrates and sealing the compartment 3.

A micro-packaged device according to the invention can be made much smaller than a conventional micro-packaged device for a given component size. Usually ceramic materials are used to package and hermetically seal electrical and micromechanical components, but the smallest packages available are about 3x2 mm² and with a thickness of more than lmm. This technology does not allow substantial miniaturisation. The present invention provides substantially smaller packages. The thickness is preferably less than 0.6mm and the lateral dimensions are preferably less than lxlmm², depending on the size of the component.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, on the contrary, is intended to cover various modifications and equivalent arrangements within the appended claims.

Claims

CLAIMS:

1. A method of micro-packaging a component (4), comprising the steps of:

- providing a plurality of substrates (1, 10, 1 1) comprising at least a first and a second substrate (1, 10), the first substrate (1) being a semiconductor substrate and being provided with an electrical through connection (2);

- forming a compartment (3) in either one or a plurality of the substrates (1, 10, 1 1) by etching;

- providing the component (4) above the first semiconductor substrate (1) so that it covers at least the through connection (2);

- connecting the component (4) to the through connection (2); and

-joining the substrates (1, 10, 1 1) to form a sealed micro-packaged device (15).

2. The method of micro-packaging a component (4) according to claim 1 , wherein the first substrate (1) is provided with a plurality of through connections (2).

3. The method of micro-packaging a component (4) according to claim 1 or 2, wherein the second substrate (10) is a semiconductor substrate.

4. The method of micro-packaging a component (4) according to any of claims 1-3, wherein one of the plurality of substrates (1, 10, 1 1) is an intermediate semiconductor substrate (1 1).

5. The method of micro-packaging a component (4) according to any of claims 1-4, wherein the first substrate (1) which is provided with electrical through connections

(2) has a thickness of > 100μm, preferably >200μm, more preferably >300μm, still more preferred >400μm, and most preferred >500μm.

6. The method of micro-packaging a component (4) according to any of the preceding claims, wherein the step of providing the component (4) further comprises the step of attaching the component (4) directly to the through connections (2).

7. The method of micro-packaging a component (4) according to claim 6, further comprising the steps of: - etching a depression (3a) in the first substrate (1) which is provided with electrical through connections (2), the depression (3a) defining the compartment (3); and

- sealing the depression (3a) with the second substrate (10).

8. The method of micro-packaging a component (4) according to claim 6, further comprising the steps of:

- etching a depression (3a) in the second substrate (10), the depression (3a) defining the compartment (3); and

- sealing the depression (3a) with the first substrate (1).

9. The method of micro-packaging a component (4) according to claim 6, further comprising the steps of:

- etching a depression (4a) in each of the first and the second substrates (1 , 10), the depressions (3a) defining the compartment (3); and - sealing the depressions (4a) by joining the substrates (1, 10).

10. The method of micro-packaging a component (4) according to any of claims 6 further comprising the steps of:

- etching a hole (3b) in the intermediate substrate (1 1), the hole (3b) defining the compartment (3); and

- sealing the compartment (3) by joining the substrates (1 , 10, 1 1).

1 1. The method of micro-packaging a component (4) according to any of claims 7-9, further comprising the steps of: - etching a hole (3b) in the intermediate substrate (1 1), the depression

(3a)/depressions (3a) and the hole (3b) defining the compartment (3); and

- sealing the compartment (3) by joining the substrates (1 , 10, 1 1).

12. The method of micro-packaging a component (4) according to any of the preceding claims, wherein the compartment (3) is sealed under controlled ambient, e.g. vacuum.

13. The method of micro-packaging a component (4) according to any of the preceding claims, further comprising the step of thinning the sealed package (15) using e.g. grinding or polishing.

14. The method of micro-packaging a component (4) according to any of claims 6- 13, wherein the component (4) is a discrete component which is attached by surface mounting such as any of flip chip mounting, soldering, ultrasonic welding, thermocompression bonding, gluing, etc.

15. The method of micro-packaging a component (4) according to claim 14, wherein the sealed micro-package ( 15) has a thickness of <2mm, preferably < lmm and more preferably < 0.6mm.

16. The method of micro-packaging a component (4) according to claim 14, wherein the sealed micro-package ( 15) has lateral dimensions less than 2x2mm², preferably less than 1x1 mm².

17. The method of micro-packaging a component (4) according to any of claims 6- 13, wherein the component (4) is monolithically integrated in any of the substrates (1 , 10, 1 1) using surface micromachining or bulk micromachining.

18. The method of micro-packaging a component (4) according to claim 17, wherein the step of joining further comprises the step of fusion bonding the substrates.

19. The method of micro-packaging a component (4) according to claim 17, wherein the step of joining further comprises the step of anodic bonding the substrates.

20. The method of micro-packaging a component (4) according to claim 17, wherein the sealed micro-package ( 15) has a thickness of < lmm, preferably <0.5mm and more preferably < 0.25mm.

21. The method of micro-packaging a component (4) according to claim 20, wherein the sealed micro-package ( 15) has lateral dimensions less than 2x2mm², preferably less than lxlmm², more preferably less than 0.5x0.5mm².

22. The method of micro-packaging a component (4) according to claim 5, wherein the through connections (2) are extending entirely through the first substrate ( 1).

23. The method of micro-packaging a component (4) according to claim 5, wherein the through connections (2) are provided in a SOI substrate, the through connections (2) extending entirely through the device layer of the SOI substrate.

24. The method of micro-packaging a component (4) according to claim 22 or 23, wherein the through connections (2) are made of the substrate material.

25. The method of micro-packaging a component (4) according to claim 22 or 23, wherein the through connections (2) are made of a metal or a metal alloy.

26. The method of micro-packaging a component (4) according to claim 1 , further comprising the step of cutting up individual packages, e.g. by sawing.

27. The method of micro-packaging a component (4) according to any of claims 1-5, wherein the component (4) is provided on the second substrate ( 10)

28. The method of micro-packaging a component (4) according to any of claims 1-5, wherein the component (4) is integrated with the intermediate substrate (10).

29. The method of micro-packaging a component (4) according to claim 1 , further comprising the step of providing getter means ( 17) in the compartment (3).

30. A micro-packaged electronic or micromechanic device (15) comprising a casing ( 13) which encloses a compartment (3); electrical through connections (2) through the bottom of the casing ( 13); and an electronic or micromechanic component (4) connected to the electrical through connections (2), the micro-packaged device ( 15) being hermetically sealed for maintaining a desired atmosphere, suitable vacuum inside, characterised in that the casing ( 13) is made of a semiconducting material and the component (4) is located immediately above the through connections (2).

31. The micro-packaged electronic or micromechanic device ( 15) according to claim 30, wherein the component (4) is directly attached to the through connections (2).

32. The micro-packaged electronic or micromechanic device (15) according to claim 31 , wherein the component (4) is a discrete component attached by surface mounting such as any of flip chip mounting, soldering, ultrasonic welding, thermocompression bonding, gluing.

33. The micro-packaged electronic or micromechanic device (15) according to claim 31 , wherein the component (4) is monolithically integrated with the casing ( 13) by surface micromachining or bulk micromachining.

34. The micro-packaged electronic or micromechanic device (15) according to claim 33, wherein the casing ( 13) is bonded by fusion bonding or anodic bonding.

35. The micro-packaged electronic or micromechanic device (15) according to any of claims 30-34, wherein the casing ( 13) comprises large contact areas (8) for surface mounting on an outer bottom surface.

36. The micro-packaged electronic or micromechanic device (15) according to any of claims 30-35, wherein the electrical through connections (2) forms a through connection structure (51) comprising at least two insulating trenches (54) one of which surrounds the other, the inner trench defining the through connection, and a plurality of cross-connecting trenches between said two trenches (54).

37. The micro-packaged electronic or micromechanic device (15) according to any of claims 30-36, wherein the electrical through connections (2) form a high density through connection structure (53) comprising neighbouring electrical through connections (2) that share at least one insulating trench (54).

38. The micro-packaged electronic or micromechanic device (15) according to claim 36 or 37, wherein the micro-packaged device ( 15) comprises a plurality of components (4) in an array structure connected to the through connection structure (51 , 53).

39. The micro-packaged electronic or micromechanic device (15) according to claim 32, wherein the micro-packaged device ( 15) has a thickness of <2mm, preferably

< lmm and more preferably < 0.6mm.

40. The micro-packaged electronic or micromechanic device (15) according to claim 39, wherein the sealed micro-packaged device (15) has lateral dimensions less than 2x2 mm², preferably less than Ix lmm².

41. The micro-packaged electronic or micromechanic device ( 15) according to claim 33, wherein the sealed micro-packaged device (15) has a thickness of < lmm, preferably < 0.5mm and more preferably < 0.25mm.

42. The electronic or micromechanic micro-package ( 15) according to claim 41 , wherein the sealed micro-packaged device (15) has lateral dimensions less than 2x2mm², preferably less than lxlmm², more preferably less than 0.5x0.5mm².