WO2008099246A3 - Multilayer structure and its fabrication process - Google Patents

Multilayer structure and its fabrication process Download PDF

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Publication number
WO2008099246A3
WO2008099246A3 PCT/IB2008/000201 IB2008000201W WO2008099246A3 WO 2008099246 A3 WO2008099246 A3 WO 2008099246A3 IB 2008000201 W IB2008000201 W IB 2008000201W WO 2008099246 A3 WO2008099246 A3 WO 2008099246A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
growth
multilayer structure
pattern
fabrication process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2008/000201
Other languages
French (fr)
Other versions
WO2008099246A2 (en
Inventor
Fabrice Letertre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to EP08702336A priority Critical patent/EP2111633A2/en
Priority to CN2008800020084A priority patent/CN101584024B/en
Priority to JP2009549858A priority patent/JP5380306B2/en
Priority to KR1020097014816A priority patent/KR101301771B1/en
Publication of WO2008099246A2 publication Critical patent/WO2008099246A2/en
Publication of WO2008099246A3 publication Critical patent/WO2008099246A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H10P14/274—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition using seed materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3216—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)

Abstract

The invention relates to a process for fabricating a multilayer structure, comprising at least the following steps : a) epitaxial growth (S1) of a growth layer on a silicon substrate; b) formation of at least one pattern (S2, S3) in the growth layer,- c) deposition of an oxide layer (S5) on the silicon substrate; d) transfer of a silicon active layer (S7-S10) onto the oxide layer; e) formation of a cavity (S11, S12) in the silicon active layer and in the oxide layer above each pattern; and f) growth in the cavity of a III-V material (S14) from each exposed pattern of the growth layer.
PCT/IB2008/000201 2007-02-14 2008-01-28 Multilayer structure and its fabrication process Ceased WO2008099246A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP08702336A EP2111633A2 (en) 2007-02-14 2008-01-28 Multilayer structure and its fabrication process
CN2008800020084A CN101584024B (en) 2007-02-14 2008-01-28 Multilayer structure and its fabrication process
JP2009549858A JP5380306B2 (en) 2007-02-14 2008-01-28 Multilayer structure and manufacturing process thereof
KR1020097014816A KR101301771B1 (en) 2007-02-14 2008-01-28 Multilayer structure and its fabrication process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0753260 2007-02-14
FR0753260A FR2912552B1 (en) 2007-02-14 2007-02-14 MULTILAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Publications (2)

Publication Number Publication Date
WO2008099246A2 WO2008099246A2 (en) 2008-08-21
WO2008099246A3 true WO2008099246A3 (en) 2008-10-30

Family

ID=38565526

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/000201 Ceased WO2008099246A2 (en) 2007-02-14 2008-01-28 Multilayer structure and its fabrication process

Country Status (7)

Country Link
US (2) US7611974B2 (en)
EP (1) EP2111633A2 (en)
JP (1) JP5380306B2 (en)
KR (1) KR101301771B1 (en)
CN (1) CN101584024B (en)
FR (1) FR2912552B1 (en)
WO (1) WO2008099246A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2912552B1 (en) 2007-02-14 2009-05-22 Soitec Silicon On Insulator MULTILAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
US8299485B2 (en) 2008-03-19 2012-10-30 Soitec Substrates for monolithic optical circuits and electronic circuits
DE102009051520B4 (en) 2009-10-31 2016-11-03 X-Fab Semiconductor Foundries Ag Process for the production of silicon semiconductor wafers with layer structures for the integration of III-V semiconductor devices
US9190269B2 (en) * 2010-03-10 2015-11-17 Purdue Research Foundation Silicon-on-insulator high power amplifiers
FR2977069B1 (en) 2011-06-23 2014-02-07 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE USING TEMPORARY COLLAGE
US9329336B2 (en) 2012-07-06 2016-05-03 Micron Technology, Inc. Method of forming a hermetically sealed fiber to chip connection
EP2685297B1 (en) * 2012-07-13 2017-12-06 Huawei Technologies Co., Ltd. A process for manufacturing a photonic circuit with active and passive structures
JP6087192B2 (en) * 2013-04-03 2017-03-01 京セラ株式会社 Power generation system, power generation system control method, and fuel cell
US9698046B2 (en) 2015-01-07 2017-07-04 International Business Machines Corporation Fabrication of III-V-on-insulator platforms for semiconductor devices
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US10297445B2 (en) 2016-06-14 2019-05-21 QROMIS, Inc. Engineered substrate structure for power and RF applications
WO2017218536A1 (en) * 2016-06-14 2017-12-21 Quora Technology, Inc. Engineered substrate structure for power and rf applications
US10510582B2 (en) 2016-06-14 2019-12-17 QROMIS, Inc. Engineered substrate structure
CN114830332B (en) * 2019-10-18 2025-03-28 光量子计算公司 Electro-optical device fabricated on a substrate and comprising a ferroelectric layer epitaxially grown on the substrate
US12136682B2 (en) 2021-09-29 2024-11-05 International Business Machines Corporation Device integration using carrier wafer
US11677039B2 (en) 2021-11-18 2023-06-13 International Business Machines Corporation Vertical silicon and III-V photovoltaics integration with silicon electronics

Citations (4)

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EP0306153A1 (en) * 1987-08-08 1989-03-08 Canon Kabushiki Kaisha Method for growth of crystal
US4876210A (en) * 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
US20040012037A1 (en) * 2002-07-18 2004-01-22 Motorola, Inc. Hetero-integration of semiconductor materials on silicon
US20040232428A1 (en) * 2003-03-28 2004-11-25 Toyoda Gosei Co., Ltd. Semiconductor light emitting element and method of making same

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US3914137A (en) * 1971-10-06 1975-10-21 Motorola Inc Method of manufacturing a light coupled monolithic circuit by selective epitaxial deposition
JPS5116928B2 (en) * 1972-06-12 1976-05-28
JPS60210832A (en) * 1984-04-04 1985-10-23 Agency Of Ind Science & Technol Manufacture of compound semiconductor crystal substrate
US5286985A (en) * 1988-11-04 1994-02-15 Texas Instruments Incorporated Interface circuit operable to perform level shifting between a first type of device and a second type of device
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US4876210A (en) * 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
EP0306153A1 (en) * 1987-08-08 1989-03-08 Canon Kabushiki Kaisha Method for growth of crystal
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Also Published As

Publication number Publication date
US7863650B2 (en) 2011-01-04
FR2912552A1 (en) 2008-08-15
CN101584024B (en) 2011-11-30
US7611974B2 (en) 2009-11-03
JP2010519741A (en) 2010-06-03
JP5380306B2 (en) 2014-01-08
FR2912552B1 (en) 2009-05-22
US20100006857A1 (en) 2010-01-14
CN101584024A (en) 2009-11-18
EP2111633A2 (en) 2009-10-28
KR101301771B1 (en) 2013-09-02
WO2008099246A2 (en) 2008-08-21
KR20090110836A (en) 2009-10-22
US20080191239A1 (en) 2008-08-14

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