WO2008099657A1 - 半導体集積回路、デバッグ・トレース回路、および半導体集積回路動作観測方法 - Google Patents

半導体集積回路、デバッグ・トレース回路、および半導体集積回路動作観測方法 Download PDF

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Publication number
WO2008099657A1
WO2008099657A1 PCT/JP2008/051078 JP2008051078W WO2008099657A1 WO 2008099657 A1 WO2008099657 A1 WO 2008099657A1 JP 2008051078 W JP2008051078 W JP 2008051078W WO 2008099657 A1 WO2008099657 A1 WO 2008099657A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor integrated
integrated circuit
debug
trace
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/051078
Other languages
English (en)
French (fr)
Inventor
Noriaki Suzuki
Sunao Torii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to CN2008800046347A priority Critical patent/CN101606132B/zh
Priority to US12/525,953 priority patent/US7911216B2/en
Priority to EP08703905A priority patent/EP2124149A4/en
Priority to JP2008558029A priority patent/JP5151996B2/ja
Publication of WO2008099657A1 publication Critical patent/WO2008099657A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

　主機能構成部は、連続的な所定の動作を実行し、動作に伴うイベントを連続的に発生させる。デバッグ・トレース回路は、主機能構成部で発生するイベントと制御情報リストのいずれか１つのエントリの検出条件指示情報とを比較し、比較の結果に応じて、検出条件指示情報と対をなす動作指示情報に指定された動作を実行する。デバッグ・トレース回路は、これを制御情報リストに従って連続的に行い、事象を特定する。
PCT/JP2008/051078 2007-02-14 2008-01-25 半導体集積回路、デバッグ・トレース回路、および半導体集積回路動作観測方法 Ceased WO2008099657A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2008800046347A CN101606132B (zh) 2007-02-14 2008-01-25 半导体集成电路、调试/跟踪电路、以及半导体集成电路操作观测方法
US12/525,953 US7911216B2 (en) 2007-02-14 2008-01-25 Semiconductor integrated circuit, debug/trace circuit and semiconductor integrated circuit operation observing method
EP08703905A EP2124149A4 (en) 2007-02-14 2008-01-25 INTEGRATED SEMICONDUCTOR CIRCUIT, DEBUGGING CIRCUIT / ANOMALY DISCOVERY AND METHOD OF OBSERVING THE OPERATION OF AN INTEGRATED SEMICONDUCTOR CIRCUIT
JP2008558029A JP5151996B2 (ja) 2007-02-14 2008-01-25 半導体集積回路及びデバッグ・トレース回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007033340 2007-02-14
JP2007-033340 2007-12-05

Publications (1)

Publication Number Publication Date
WO2008099657A1 true WO2008099657A1 (ja) 2008-08-21

Family

ID=39689903

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/051078 Ceased WO2008099657A1 (ja) 2007-02-14 2008-01-25 半導体集積回路、デバッグ・トレース回路、および半導体集積回路動作観測方法

Country Status (6)

Country Link
US (1) US7911216B2 (ja)
EP (1) EP2124149A4 (ja)
JP (1) JP5151996B2 (ja)
KR (1) KR101090556B1 (ja)
CN (1) CN101606132B (ja)
WO (1) WO2008099657A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013175017A (ja) * 2012-02-24 2013-09-05 Nec Computertechno Ltd トランザクション処理装置及び不正トランザクション検出方法
JP2015516100A (ja) * 2012-05-07 2015-06-04 マイクロチップ テクノロジー インコーポレイテッドＭｉｃｒｏｃｈｉｐ Ｔｅｃｈｎｏｌｏｇｙ Ｉｎｃｏｒｐｏｒａｔｅｄ 命令トレース能力を有するプロセッサデバイス

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112011100807T5 (de) * 2010-03-05 2013-01-17 Mitsubishi Electric Corporation Programm-Ablaufverfolgungsvorrichtung
WO2011136212A1 (ja) * 2010-04-27 2011-11-03 日本電気株式会社 論理回路エミュレータ及び論理回路エミュレータの制御方法
JP2016025649A (ja) * 2014-07-24 2016-02-08 富士通株式会社 電子装置及び機器検知方法
KR102522154B1 (ko) * 2016-03-15 2023-04-17 에스케이하이닉스 주식회사 반도체 메모리 장치의 컨트롤러 및 이의 동작 방법
US12072378B2 (en) * 2019-12-09 2024-08-27 Advanced Micro Devices, Inc. Debug state machine triggered extended performance monitor counter

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001147836A (ja) * 1999-10-01 2001-05-29 Stmicroelectronics Inc マイクロコンピュータデバッグアーキテクチャ及び方法
JP2002024201A (ja) 2000-07-10 2002-01-25 Toshiba Corp 半導体集積回路
JP2006012017A (ja) * 2004-06-29 2006-01-12 Denso Corp 状態にアクションを割り当てた対応情報に基づいてプログラムを生成するプログラム生成プログラム、プログラム生成装置、およびプログラム生成方法，ならびに、この対応情報の生成プログラム、対応情報生成装置、および対応情報生成方法
JP2006338305A (ja) * 2005-06-01 2006-12-14 Toshiba Corp 監視装置及び監視プログラム
JP2007033340A (ja) 2005-07-28 2007-02-08 Nagano Keiki Co Ltd 測定器及びその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01288931A (ja) 1988-05-16 1989-11-21 Nec Corp Ｐｌ／ｉプログラムのデバック方式
JPH05100891A (ja) 1991-10-09 1993-04-23 Kobe Nippon Denki Software Kk プログラムデバツグ装置
JPH09305443A (ja) * 1996-05-13 1997-11-28 Omron Corp プロセス監視装置およびプロセス監視方法
JP3913470B2 (ja) * 2000-12-28 2007-05-09 株式会社東芝 システムｌｓｉ
JP2003263340A (ja) 2002-03-11 2003-09-19 Ricoh Co Ltd デバッグ装置
US7149926B2 (en) * 2003-05-22 2006-12-12 Infineon Technologies Ag Configurable real-time trace port for embedded processors
JP2006336305A (ja) 2005-06-02 2006-12-14 Shin Caterpillar Mitsubishi Ltd 作業機械
JP5067111B2 (ja) * 2007-10-18 2012-11-07 富士通セミコンダクター株式会社 半導体集積回路及びデバッグモード決定方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001147836A (ja) * 1999-10-01 2001-05-29 Stmicroelectronics Inc マイクロコンピュータデバッグアーキテクチャ及び方法
JP2002024201A (ja) 2000-07-10 2002-01-25 Toshiba Corp 半導体集積回路
JP2006012017A (ja) * 2004-06-29 2006-01-12 Denso Corp 状態にアクションを割り当てた対応情報に基づいてプログラムを生成するプログラム生成プログラム、プログラム生成装置、およびプログラム生成方法，ならびに、この対応情報の生成プログラム、対応情報生成装置、および対応情報生成方法
JP2006338305A (ja) * 2005-06-01 2006-12-14 Toshiba Corp 監視装置及び監視プログラム
JP2007033340A (ja) 2005-07-28 2007-02-08 Nagano Keiki Co Ltd 測定器及びその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2124149A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013175017A (ja) * 2012-02-24 2013-09-05 Nec Computertechno Ltd トランザクション処理装置及び不正トランザクション検出方法
JP2015516100A (ja) * 2012-05-07 2015-06-04 マイクロチップ テクノロジー インコーポレイテッドＭｉｃｒｏｃｈｉｐ Ｔｅｃｈｎｏｌｏｇｙ Ｉｎｃｏｒｐｏｒａｔｅｄ 命令トレース能力を有するプロセッサデバイス

Also Published As

Publication number Publication date
US7911216B2 (en) 2011-03-22
EP2124149A1 (en) 2009-11-25
JPWO2008099657A1 (ja) 2010-05-27
CN101606132B (zh) 2012-05-30
KR20090121321A (ko) 2009-11-25
CN101606132A (zh) 2009-12-16
JP5151996B2 (ja) 2013-02-27
US20100321051A1 (en) 2010-12-23
KR101090556B1 (ko) 2011-12-08
EP2124149A4 (en) 2012-11-14

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