WO2008151472A1 - Multilayer board surface-treated configuration and the producing method thereof - Google Patents

Multilayer board surface-treated configuration and the producing method thereof Download PDF

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Publication number
WO2008151472A1
WO2008151472A1 PCT/CN2007/001899 CN2007001899W WO2008151472A1 WO 2008151472 A1 WO2008151472 A1 WO 2008151472A1 CN 2007001899 W CN2007001899 W CN 2007001899W WO 2008151472 A1 WO2008151472 A1 WO 2008151472A1
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WO
WIPO (PCT)
Prior art keywords
layer
pad
solder resist
metal layer
cladding metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2007/001899
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English (en)
French (fr)
Inventor
Chih-Kuang Yang
Chieh-Lin Hsing
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Princo Corp
Original Assignee
Princo Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Princo Corp filed Critical Princo Corp
Priority to PCT/CN2007/001899 priority Critical patent/WO2008151472A1/zh
Priority to KR1020107001051A priority patent/KR101147398B1/ko
Priority to EP07721472.4A priority patent/EP2161976B1/en
Priority to JP2010511471A priority patent/JP2010530133A/ja
Publication of WO2008151472A1 publication Critical patent/WO2008151472A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099—Coating over pads, e.g. solder resist partly over pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/243—Reinforcing of the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Definitions

  • Multilayer substrate surface treatment layer structure and manufacturing method thereof Multilayer substrate surface treatment layer structure and manufacturing method thereof
  • the present invention relates to a multilayer substrate surface treatment layer structure and a method of fabricating the same, and more particularly to a surface treatment layer structure of a flexible multilayer substrate and a method of fabricating the same.
  • Pad definition (Pad)
  • This prior art is to apply a solder mask layer 104 after forming a pad layer 101 on a dielectric layer. Next, opening the pad layer 101. In order to remove the residual slag on the layer of the pad 101, there is a step of removing the Descum. Finally, a nickel metal layer 102 and a gold metal layer 103 are formed on the pad layer 101.
  • a solder resist layer 104 is applied.
  • opening is performed at the position of the pad layer 101.
  • a cladding metal layer such as a nickel metal layer 102 and a gold metal layer 103 is formed on the pad layer 101.
  • the hole area defined by the pad layer includes the entire area occupied by the pad layer 101, and the solder resist layer is defined in such a manner that the solder resist layer 104 covers a part of the pad layer 101.
  • the pad layer or the manner in which the solder resist layer is defined it is necessary to form a plurality of cladding metal layers after applying the solder resist layer 104 and performing the opening.
  • a solder or other solder or the like is used to bond the component and the pad layer 101.
  • the purpose of coating the metal layer is to avoid contact of the tin or other flux with the copper.
  • the definition of the pad layer or the definition of the solder resist layer is due to the moisture present in the environment or the stress caused by the material of the cladding metal layer and the dielectric layer and the solder resist layer.
  • the main object of the present invention is to provide a multilayer substrate surface treatment layer structure and a manufacturing method thereof, which embed a pad layer in a dielectric layer, thereby avoiding peeling or delamination of the pad layer, and improving package reliability. .
  • Another object of the present invention is to provide a multilayer substrate surface treatment layer structure and a manufacturing method thereof, which are formed by coating a metal layer before forming a solder resist layer, and can avoid tin or other flux when packaged. Contact of the pad to improve package reliability.
  • the multilayer substrate surface treatment layer structure of the present invention comprises a pad layer, at least one cladding metal layer and a solder resist layer.
  • the pad layer of the present invention is embedded in a plurality of opposite dielectric layers, and the metal layer is coated to cover the pad layer.
  • the solder resist layer has an opening that exposes the cladding metal layer.
  • the invention first forms a cladding metal layer on the surface of the pad layer, and then forms a solder resist layer, and then openings the solder resist layer at a position where the metal layer is coated, and exposes the metal layer.
  • the solder layer of the present invention may also be formed on the surface of a dielectric layer, but after forming a cladding metal layer on the surface of the pad layer, a solder resist layer is formed. Thereafter, the solder resist layer is further opened at a position where the metal layer is covered, and the metal layer is covered with a coating.
  • the present invention also provides a method of fabricating a surface treatment layer structure of a multilayer substrate, the manufacturing method of the present invention comprising the following steps:
  • the solder resist layer is opened at a position where the metal layer is coated, and the metal layer is covered with a coating.
  • the pad layer of the present invention is embedded in the surface of a dielectric layer of the multilayer substrate or formed on the surface of a dielectric layer of the multilayer substrate.
  • the multilayer of the invention can increase the adhesion between the pad layer and the dielectric layer by embedding the pad layer in the dielectric layer, so that the pad layer and the dielectric layer are not easily delaminated (Delamination), and the reinforcement is reliable. degree.
  • the cladding metal layer is formed as a barrier layer between the solder material or the solder layer and the solder layer, even if the moisture exists in the environment, or the metal layer and the cladding layer are coated.
  • the stress between the electric layer and the solder resist layer causes the cladding metal layer and the dielectric layer, or the delamination between the cladding metal layer and the solder resist layer, to ensure the barrier between the tin or other solder and the pad layer. Contact, which improves package reliability.
  • FIG. 1 is a prior art surface finish structure in a pad definition manner
  • Figure 3 is a schematic view showing a first embodiment of the multilayered surface treatment layer structure of the present invention.
  • Figure 4 is a schematic view showing a second embodiment of the surface treatment layer structure of the multilayer substrate of the present invention.
  • Figure 5 is a schematic view showing a third embodiment of the surface treatment layer structure of the multilayer substrate of the present invention
  • Figure 6 is a schematic view showing a fourth embodiment of the structure of the multi-layered surface treatment layer of the present invention
  • Figures 7A to 7E are flow charts showing a method of fabricating the structure of the multi-layered anti-surface treatment layer of the first embodiment according to the present invention
  • FIG. 8A through 8E are flow charts showing a method of fabricating a multilayer processing layer structure of a third embodiment in accordance with the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION Figure 3 is a schematic illustration of a first embodiment of a multilayer reverse surface treatment layer structure of the present invention.
  • a pad layer 301 (Pad) of the present invention is embedded in a dielectric layer.
  • the material shield of the dielectric layer can be polyimide.
  • a plurality of cladding metal layers i.e., a nickel cladding metal layer 302 and a gold cladding metal layer 303, are formed on the pad layer 301.
  • a solder resist layer 304 is further formed, and then the solder resist layer 304 is opened at a position where the gold material is covered with the metal layer 303, the metal strip is coated with the metal layer 303, and the solder resist layer 304 is covered with the nickel clad metal. Layer 302 and a portion of gold cladding metal layer 303.
  • the solder resist layer 304 covers a part of the nickel-clad metal layer 302 and the gold-clad metal layer 303, and ensures that the nickel material is coated with the metal layer 302 and gold.
  • FIG. 4 is a schematic illustration of a second embodiment of the multilayer anti-surface treatment layer structure of the present invention.
  • a pad layer 401 of the present invention is embedded in a dielectric layer.
  • This second embodiment is a manner defined by the solder resist layer. Therefore, after forming a solder resist layer 404, the solder resist layer 404 is opened at the position of the pad layer 401, the pad layer 401 is exposed, and solder resist is applied. Layer 404 covers a portion of pad layer 401. Further, on the pad layer 401, a plurality of cladding metal layers, that is, a nickel cladding metal layer 402 and a gold cladding metal layer 403 are formed. Different from the prior art technology shown in FIG. 2, since the pad layer 401 is embedded in the dielectric layer, the adhesion between the pad layer 401 and the dielectric layer can be increased, and the pad layer 401 and the dielectric layer can be formed. It is not easy to separate and separate, and enhance reliability.
  • Fig. 5 is a schematic view showing a third embodiment of the surface treatment layer structure of the multilayer substrate of the present invention.
  • a pad layer 501 of the multilayered surface layer of the present invention is embedded in a dielectric layer.
  • This third embodiment belongs to the pad definition. Therefore, in this embodiment, a plurality of cladding metal layers, that is, a nickel-clad metal layer 502 and a gold material package, may be formed on the pad layer 501.
  • a solder mask 504 is formed, and then the solder resist layer 504 is opened at the position of the pad layer 501, and the metal strip is covered with the metal layer 503, and the area of the opening is included and larger than the solder pad layer 501. Area.
  • the solder resist layer 504 may be formed first, and after the solder resist layer 504 is opened at the position of the pad layer 501, the nickel clad metal layer 302 and the gold clad metal layer 303 are formed.
  • the difference from the prior art shown in FIG. 1 is that since the pad layer 301 is embedded in the dielectric layer, the adhesion between the pad layer and the dielectric layer can be increased, and the pad layer and the dielectric layer are not easily delaminated. Separate and enhance reliability.
  • Fig. 6 is a schematic view showing a fourth embodiment of the surface treatment layer structure of the multilayer substrate of the present invention.
  • a pad layer 601 is formed on the surface of a dielectric layer.
  • the present invention first forms a plurality of cladding metal layers, i.e., a nickel cladding metal layer 602 and a gold cladding metal layer 603, on the pad layer 601.
  • the solder resist layer 604 is opened at a position where the gold material is covered with the metal layer 603, the metal strip is coated with a metal layer 603, and the solder resist layer 604 covers the nickel clad metal layer. 602 and a portion of the gold-clad metal layer 603.
  • the present invention causes the solder resist layer 604 to cover a portion of the nickel clad metal layer 602 and the gold clad metal layer 603, it is ensured that when the nickel clad metal layer 602, the gold clad metal layer 603 and the solder resist layer 604 or When delamination occurs between the electrical layers, the contact between the tin or other flux and the solder layer 601 can be blocked, thereby improving package reliability.
  • FIG. 7A to 7E are flow charts showing a method of fabricating the multi-layered reverse surface treatment layer structure of the first embodiment shown in Fig. 3 in accordance with the present invention.
  • Figure 7A shows the formation of a pad layer on the surface of a carrier 700. 301, to perform an adhesion strengthening treatment 305, for example: an oxygen or argon plasma process.
  • FIG. 7B shows the formation of a dielectric layer 702 that completely covers the carrier 700.
  • 7C shows that after the dielectric layer 702 and the pad layer 301 are separated from the carrier surface 700 and turned upside down, a nickel-clad metal layer 302 and a gold-clad metal layer 303 are formed on the surface of the pad layer 301.
  • the pad layer 301 is covered.
  • 7D shows the formation of a solder mask 304 that completely covers the gold clad metal layer 303 and the dielectric layer 702.
  • 7E shows that the solder resist layer 304 is opened at a position where the nickel-clad metal layer 302 and the gold-clad metal layer 303 are covered, and the gold-plated metal layer 303 is covered with the gold-plated metal layer 303.
  • a portion of the metal layer 303 that is, a surface treatment layer structure in which the pad layer 301 is embedded in the dielectric layer 702, and the solder resist layer 304 covers the portion of the gold-clad metal layer 303.
  • the pad layer 501 can also be formed by the same method.
  • the area of the opening is included and larger than the pad layer 301.
  • the area is fine. If the pad layer 401 of the second embodiment shown in FIG. 4 is to be formed, the steps of FIG. 7C and FIG. 7D can be sequentially changed, that is, the solder resist layer 304 is formed first and the holes are opened to cover the solder resist layer 304. After a part of the pad layer 301, a nickel-clad metal layer 302 and a gold-clad metal layer 303 may be formed.
  • FIG. 8A to 8E are flow charts showing a method of fabricating the structure of the multilayer shampoo surface treatment layer of the third embodiment shown in Fig. 5 in accordance with the present invention.
  • FIG. 8A shows that a solder resist layer 504 is first formed on the surface of a carrier 800.
  • 8B shows a pad layer 501 formed on the surface of the solder resist layer 504, and a dielectric layer 802 is formed.
  • An adhesion strengthening process 505 can be performed between the pad layer 501 and the dielectric layer 802, for example: an oxygen gas or Argon plasma processing.
  • Fig. 8C shows that the solder resist layer 504 is separated from the surface of the carrier plate 800 and turned upside down with the solder resist layer 504 facing upward to open the solder resist layer 504.
  • FIG. 8D shows the solder mask layer 504 being opened at the position of the in-line pad layer 501, and the pad layer 501 is exposed so that the area of the opening in FIG. 8D is larger than the area occupied by the pad layer 501.
  • FIG. 8E shows that a nickel-clad metal layer 502 and a gold-clad metal layer 503 are formed on the surface of the pad layer 501 to cover the pad layer 501. That is, the surface treatment layer structure in which the pad layer 501 is embedded in the dielectric layer 802 can be realized.
  • the pad layer 401 can also be formed by the same method.
  • the solder resist layer is formed. 504 may cover a portion of the pad layer 501.
  • an interface adhesion strengthening process 305, 405, 505, and 605 may be applied between the pad layers 301, 401, 501, and 601 and the dielectric layer.
  • an interface adhesion strengthening process 305, 405, 505, and 605 may be applied between the pad layers 301, 401, 501, and 601 and the dielectric layer.
  • Stripping or delamination of the pad layers 301, 401, 501, and 601 can be further avoided.
  • the present invention utilizes a carrier to fabricate a pad layer embedded in a dielectric layer, adhesion between the pad layer and the dielectric layer can be increased, peeling or delamination of the pad layer can be avoided, and reliability can be enhanced.
  • a process of coating the metal layer is first formed, so that the solder resist layer covers a part of the cladding metal layer, and the solder resist layer or the dielectric layer is ensured when the cladding metal layer is wet or stressed.
  • delamination occurs, the contact between the tin or other flux and the pad layer can be blocked, and the package reliability can be improved. As a result, the reliability of multi-layer anti-packaging and the yield of packaged products can be improved.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

多层基板表面处理层结构及其制造方法
技术领域 本发明是关于一种多层基板表面处理层结构及其制造方法，且特别是有关 于一种软性多层基板的表面处理层结构及其制造方法。
背景技术
1
现有的多层基板表面处理 (surface finish)可分为两大类： 焊垫层定义 (Pad
Figure imgf000002_0001
(Surface Finish Structure^ 该现有技术是在一介电层上形成焊垫层 (Pad)101后， 涂布一防焊层 104 (Solder Mask)。 接着， 在焊垫层 101的位置进行开孔， 为清 除焊垫 101层上残余的胶渣， 会有一去胶渣 (Descum)的步骤。 最后， 再在焊垫 层 101上形成镍材金属层 102以及金材金属层 103。
构。 在一介电层上形成焊垫层 101后， 涂布一层防焊层 104。 接着， 在焊垫层 101的位置进行开孔，为清除焊垫层 101上残余的胶渣，会有一去胶渣的步骤。 最后，再在焊垫层 101上形成镍材金属层 102以及金材金属层 103等包覆金属 层。 与焊垫层定义方式不同的是， 焊垫层定义方式的开孔面积包含焊垫层 101 所占的全部面积，而防焊层定义方式则使防焊层 104覆盖焊垫层 101的一部分。
无论是前述焊垫层定义或是防焊层定义的方式， 均必须在涂布防焊层 104 及进行开孔后， 再进行形成若干包覆金属层的步骤。 当后续将元件封装在一般 以铜为材质的焊垫层 101时， 会使用锡材或其它焊剂等， 来黏结封装该元件与 焊垫层 101。 然而， 由于锡材或其它焊剂与铜的接触会产生互熔的现象， 因此 包覆金属层的目的是避免锡材或其它焊剂与铜的接触。 然而， 前述焊垫层定义 或是防焊层定义的方式， 由于环境所存在的湿气或者因包覆金属层与介电层、 防焊层为相异的材质， 产生的应力的缘故， 在图 1或图 2中箭头所指之处均有 脱层的可能性， 而使锡材或其它焊剂与焊垫层 101接触， 产生互熔产生介金属 化合物 (IMC), 导致接点结构脆弱、 产品可靠度降低。
此外， 无论是焊垫层或是防焊层定:^的方式， 由于焊垫层 101均形成于介 电层表面上， 均有焊垫层 101剥离或脱层的可能， 使封装可靠度降低。
因此， 如果在进行封装时， 能避免锡材或其它焊剂与焊垫层的接触， 并强 化焊垫层对下方介电层的附着， 即可提高封装可靠度以及封装产品产出的良 率。 发明内容 本发明的主要目的在于提供一种多层基板表面处理层结构及其制造方法， 其将焊垫层内嵌于介电层， 能避免焊垫层的剥离或脱层， 提高封装可靠度。
本发明的另一目的在于提供一种多层基板表面处理层结构及其制造方法， 其在形成防焊层前， 先制作包覆金属层， 当进行封装时， 能避免锡材或其它焊 剂与焊垫层的接触， 提高封装可靠度。
为实现上述或是其它目的， 本发明采用如下技术方案： 本发明多层基板表 面处理层结构包含一焊垫层、 至少一包覆金属层以及一防焊层。 本发明的焊垫 层内嵌于多层 反的一介电层， 包覆金属层用以包覆焊垫层。 防焊层具有一棵 露包覆金属层的开孔。 本发明先形成包覆金属层于焊垫层表面后， 再形成防焊 层， 之后再在包覆金属层的位置对防焊层进行开孔， 棵露包覆金属层。
在本发明的焊藝层也可以形成于一介电层的表面，但仍先在焊垫层表面形 成包覆金属层后， 再形成防焊层。 之后， 再于包覆金属层的位置对防焊层进行 开孔， 棵露包覆金属层。 本发明也提供一种制造一多层基板的表面处理层结构的方法， 本发明的制 造方法包含下列步骤：
在焊垫层的表面形成包覆金属层， 包覆金属层完全覆盖于焊垫层； 形成防焊层在多层基板具有焊垫层的表面； 以及
在包覆金属层的位置对防焊层进行开孔， 棵露包覆金属层。 本发明的焊垫 层内嵌于多层基板的一介电层的表面， 或者， 形成于多层基板的一介电层的表 面。
本发明的多层！^反表面处理层结构因将焊垫层内嵌于介电层， 能增加焊垫 层与介电层间的附着力， 使焊垫层与介电层不易脱层分离 (Delamination)， 加强 可靠度。 且于形成防焊层前， 先制作包覆金属层作为锡材或其它焊剂与焊垫层 间的阻障层 (Barrier Layer), 即使由于环境所存在的湿气， 或者包覆金属层与介 电层、 防焊层间的应力， 导致包覆金属层与介电层， 或包覆金属层与防焊层间 发生脱层时， 仍能确保阻隔锡材或其它焊剂与焊垫层间的接触， 而能提高封装 可靠度。
为让本发明之上述和其它目的、 特征和优点能更明显易懂， 下文特举较佳 实施例， 并配合所附图式， 作详细说明如下。 附图说明 图 1 是现有技术以焊垫层定义 (Pad Definition)方式的表面处理层 (Surface Finish)结构；
图 1是现有技术以防焊层 (Solder Mask Definition)定义方式的表面处理层 结构；
图 3是本发明多层基 表面处理层结构第一实施例的示意图；
图 4是本发明多层基板表面处理层结构第二实施例的示意图；
图 5是本发明多层基板表面处理层结构第三实施例的示意图； 图 6是本发明多层羞 表面处理层结构第四实施例的示意图； 图 7A至图 7E是依据本发明制造第一实施例多层 反表面处理层结构的 方法流程图； 以及
图 8A至图 8E是依据本发明制造第三实施例多层 面处理层结构的 方法流程图。 具体实施方式 图 3所示的是本发明多层 反表面处理层结构的第一实施例的示意图。本 发明的一焊垫层 301(Pad)内嵌于一介电层。 该介电层的材盾可以是聚酰亚胺。 并且本发明的第一实施例先在焊垫层 301上形成若干包覆金属层， 即镍材包覆 金属层 302以及金材包覆金属层 303。 再形成一防焊层 304， 然后在金材包覆 金属层 303的位置对防焊层 304进行开孔， 棵露金材包覆金属层 303 , 并且使 防焊层 304覆盖镍材包覆金属层 302以及金材包覆金属层 303的一部分。
由于焊垫层 301内嵌于介电层， 能增加焊垫层 301与介电层间的附着力， 使焊垫层 301与介电层不易脱层分离 (Delamination), 加强可靠度。 并且， 以防 焊层定义 (Solder Mask Defmintion)的方式， 使防焊层 304覆盖镍材包覆金属层 302、金材包覆金属层 303的一部分， 确保当镍材包覆金属层 302、金材包覆金 属层 303因湿气或应力， 而与防焊层 304间或介电层间发生脱层时， 仍能阻隔 锡材或其它焊剂与焊垫层 301之间的接触， 而能提高封装可靠度。
图 4所示的是本发明多层 反表面处理层结构第二实施例的示意图。 与第 一实施例相同， 本发明的一焊垫层 401内嵌于一介电层。 此第二实施例属防焊 层定义的方式， 因此， 在形成一防焊层 404后， 在焊垫层 401的位置对防焊层 404进行开孔， 棵露焊垫层 401 , 且防焊层 404覆盖焊垫层 401的一部分。 再 在焊垫层 401上， 形成若干包覆金属层， 即镍材包覆金属层 402以及金材包覆 金属层 403。 与图 2所示的现有技术技术不同的是， 由于焊垫层 401内嵌于介电层， 能 增加焊垫层 401与介电层间的附着力， 使焊垫层 401与介电层不易脱层分离， 加强可靠度。
图 5所示为本发明多层基板表面处理层结构第三实施例的示意图。 与第一 实施例相同，本发明多层基^ ^面处理层结构的一焊垫层 501内嵌于一介电层。 此第三实施例属于焊垫层定义 (Pad Definition)的方式， 因此， 本实施例可先在 焊垫层 501上， 形成若干包覆金属层， 即镍材包覆金属层 502以及金材包覆金 属层 503。 接着， 形成一防焊^ 504， 然后在焊垫层 501的位置对防焊层 504 进行开孔， 棵露金材包覆金属层 503 , 并且开孔的面积包含且大于焊垫层 501 所占的面积。 或者， 本实施例也可先形成防焊层 504, 在焊垫层 501的位置对 防焊层 504进行开孔后，再形成镍材包覆金属层 302以及金材包覆金属层 303。
与图 1所示的现有技术不同的是： 由于焊垫层 301内嵌于介电层， 能增加 焊垫层与介电层间的附着力， 使焊垫层与介电层不易脱层分离， 加强可靠度。
图 6所示为本发明多层基板表面处理层结构第四实施例的示意图。一焊垫 层 601 , 形成在一介电层的表面。在第四实施例中， 本发明先在焊垫层 601上， 形成若干包覆金属层， 即镍材包覆金属层 602以及金材包覆金属层 603。 再形 成一防焊层 604后， 在金材包覆金属层 603的位置对防焊层 604进行开孔， 棵 露金材包覆金属层 603, 且防焊层 604覆盖镍材包覆金属层 602以及金材包覆 金属层 603的一部分。
由于本发明使防焊层 604覆盖镍材包覆金属层 602、 金材包覆金属层 603 的一部分， 确保当镍材包 金属层 602、 金材包覆金属层 603与防焊层 604或 介电层间发生脱层时， 仍能阻隔锡材或其它焊剂与焊藝层 601间的接触， 从而 能提高封装可靠度。
图 7A至 7E所示的是依据本发明制造图 3所示的笫一实施例多层 反表 面处理层结构的方法流程图。 图 7A表示在一载板 700 的表面先形成焊垫层 301 , 以进行一附着强化处理 305， 例如： 一氧气或氩气电浆制程处理。 图 7B 表示形成一介电层 702, 完全覆盖载板 700。 图 7C表示将介电层 702与焊垫层 301从载^ ^面 700分离并上下翻转后， 在焊垫层 301的表面形成镍材包覆金 属层 302以及金材包覆金属层 303 , 用以包覆焊垫层 301。 图 7D表示形成一防 焊层 304， 完全覆盖金材包覆金属层 303以及介电层 702。 图 7E表示在镍材包 覆金属层 302以及金材包覆金属层 303的位置对防焊层 304进行开孔，棵露金 材包覆金属层 303， 使防焊层 304覆盖金材包覆金属层 303的一部分， 即能实 现焊垫层 301内嵌于介电层 702的表面处理层结构，且防焊层 304覆盖金材包 覆金属层 303—部分的结构。 而在本发明图 5所示的第三实施例中， 也可用相 同的方法形成焊垫层 501 , 在图 7E中进行开孔时， 使开孔的面积包含且大于 焊垫层 301所占的面积即可。如果要形成本发明图 4所示的第二实施例中焊垫 层 401 , 则可将图 7C与图 7D的步骤顺序调换， 即先形成防焊层 304并开孔， 使防焊层 304覆盖焊垫层 301的一部分后，再形成镍材包覆金属层 302以及金 材包覆金属层 303即可。
图 8A至图 8E所示的是依据本发明制造图 5所示的第三实施例多层羞 ^反 表面处理层结构的方法流程图。 图 8A表示在一载板 800的表面先形成防焊层 504。图 8B表示在防焊层 504的表面，先形成焊垫层 501 ,再形成一介电层 802, 焊垫层 501与介电层 802之间可进行一附着强化处理 505 , 例如： 一氧气或氩 气电浆制程处理。图 8C表示将防焊层 504自载板 800的表面分离并上下翻转， 使防焊层 504朝上， 以对防焊层 504进行开孔。 图 8D表示在内嵌焊垫层 501 的位置对防焊层 504进行开孔， 棵露焊垫层 501， 使图 8D中开孔的面积包含 且大于焊垫层 501所占的面积。 图 8E表示在焊垫层 501的表面形成镍材包覆 金属层 502以及金材包覆金属层 503 , 用以包覆焊垫层 501。 即能实现焊垫层 501内嵌在介电层 802的表面处理层结构。 而在本发明第 4图所示的第二实施 例中， 也可用相同的方法形成焊垫层 401 , 在图 8D中进行开孔时， 使防焊层 504覆盖焊垫层 501的一部分即可。
并且，在前述本发明第一实施例至第四实施例中，均可在焊垫层 301、 401、 501以及 601与介电层之间施以一接口附着强化处理 305、 405、 505以及 605， 以增加悍垫层 301、 401、 501以及 601与介电层间的附着强度。 能更进一步避 免焊垫层 301、 401、 501以及 601的剥离或脱层。
总而言之， 由于本发明利用载板制造内嵌于介电层之焊垫层， 能增加焊垫 层与介电层间的附着力， 避免焊垫层的剥离或脱层， 加强可靠度。 同时由于形 成防焊层前， 先制作包覆金属层的制程， 使防焊层覆盖包覆金属层的一部分， 确保当包覆金属层因湿气或应力， 而与防焊层或介电层间发生脱层时， 仍能阻 隔锡材或其它焊剂与焊垫层间的接触， 而能提高封装可靠度。 因此， 能提高多 层 反封装的可靠度以及封装产品产出的良率。

Claims

权 利 要 求
1. 一种多层基板表面处理层结构， 包括： 一焊垫层、 一介电层、 至少一 包覆金属层以及一防焊层， .其中前述包覆金属层用以包覆该焊垫层， 防焊层 具有一棵露该包覆金属层的开孔， 其特征在于： 前述焊垫层内嵌于介电层。
2. 如权利要求 1所述的结构， 其特征在于： 该防焊层覆盖该包覆金属层 的一部分。
3. 如权利要求 1所述的结构， 其特征在于： 该开孔的面积包含该包覆金 属层所占的面积。
4. 如权利要求 1所述的结构， 其特征在于： 该包覆金属在该防焊层的开 孔形成后， 再包覆该焊垫层。
5. 如权利要求 4所述的结构， 其特征在于： 该防焊层覆盖该焊塾层的一 部分。
6. 如权利要求 1所述的结构，其特征在于：该介电层的材质为聚酰亚胺。
7. 如权利要求 1所述的结构， 其特征在于： 该焊垫层的材廣为铜。
8. 如权利要求 1所述的结构， 其特征在于： 该包覆金属层为镍。
9. 如权利要求 1所述的结构， 其特征在于： 该包覆金属层为金。
10. 如权利要求 1所述的结构， 其特征在于： 在该焊垫层与该介电层间 施以一接口附着强化处理， 以增加该焊垫层与该介电层的附着强度。
11. 一种多层基板表面处理层结构， 包括： 一介电层、 一形成在该介电 层表面的焊垫层、 至少一包覆金属层以及一防焊层， 其中包覆金属层用以包 覆该焊垫层， 其特征在于： 防焊层覆盖该包覆金属层的一部分。
12. 如权利要求 11所述的结构， 其特征在于： 在该焊垫层与该介电层表 面间施以一介面附着强化处理， 以增加该焊垫层与该介电层的附着强度。
13. 如权利要求 11所述的结构， 其特征在于： 该介 4层的材盾为聚酰亚 胺。
14.如权利要求 11所述的结构， 其特征在于： 该焊垫层的材质为铜。
15. 如权利要求 11所述的结构， 其特征在于： 该包覆金属层为镍。
16.如权利要求 11所述的结构， 其特征在于： 该包覆金属层为金。
17.一种制造一多层基板的表面处理层结构的方法， 该制造方法包含下 列步骤：
在一焊垫层的表面形成至少一包覆金属层， 该包覆金属层完全覆盖于该 焊垫层；
形成一防焊层在该多层基板具有该焊垫层的表面; 以及
在该包覆金属层的位置对该防焊层进行开孔， 棵露该包覆金属层。
18. 如权利要求 17所述的制造方法， 其特征在于： 该防焊层覆盖该包覆 金属层的一部分。
19. 如权利要求 17所述的制造方法， 其特征在于： 在该防焊层所开孔的 面积包含该包覆金属层所占的全部面积。
20. 如权利要求 17所述的制造方法， 其特征在于： 在形成该包覆金属层 的步骤前， 还包含一将该焊垫层内嵌于该多层基板一介电层内的步骤。
21. 如权利要求 20所述的制造方法， 其特征在于： 将该焊垫层内嵌于该 介电层内的步骤是在一载板表面先形成该焊垫层， 再形成该介电层， 再将该 介电层与该焊垫层从该载^^面分离， 使该焊垫层内嵌于该介电层。
22. 如权利要求 17所述的制造方法， 其特征在于： 在形成该包覆金属层 的步骤前， 还包含一将该焊垫层形成于该多层基板一介电层的该表面的步骤。
23. 一种制造一多层基板的表面处理层结构的方法， 该制造方法包含下 列步骤：
形成一防焊层；
在该多层基板的一介电层的表面所内嵌一焊垫层的位置对该防焊层进行 开孔， 棵露该焊垫层； 以及
于该焊垫层的表面形成至少一包覆金属层， 用以包覆该焊垫层。
24. 如权利要求 23所述的制造方法， 其特征在于： 该防焊层覆盖该焊垫 层的一部分。
25. 如权利要求 23所述的制造方法， 其特征在于： 在该防焊层所开孔的 面积包含该焊垫层所占的面积。
26. 如权利要求 23所述的制造方法， 其特征在于： 在形成该防焊层的步 骤前， 还包含一步骤， 在一载板表面先形成该焊垫层， 再形成该介电层， 再 将该介电层与该焊垫层从该载板表面分离， 使该焊垫层内嵌于该介电层。
27. 如权利要求 23所述的制造方法， 其特征在于： 该防焊层先形成在一 载板表面。
28. 如权利要求 27所述的制造方法， 其特征在于： 在该载板表面形成该 防焊层的步骤后， 还包含一步骤， 在该防焊层的表面先形成该焊垫层， 再形 成该介电层， 使该焊垫层内嵌于该介电层。
29. 如权利要求 27所述的制造方法， 其特征在于： 对该防焊层进行开孔 的步骤前， 还包含一将该防焊层从该载板表面分离的步骤。
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EP2161976A4 (en) 2011-07-13
KR20100043048A (ko) 2010-04-27
JP2010530133A (ja) 2010-09-02

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