WO2009060763A1 - クロックデータ復元装置 - Google Patents

クロックデータ復元装置 Download PDF

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Publication number
WO2009060763A1
WO2009060763A1 PCT/JP2008/069555 JP2008069555W WO2009060763A1 WO 2009060763 A1 WO2009060763 A1 WO 2009060763A1 JP 2008069555 W JP2008069555 W JP 2008069555W WO 2009060763 A1 WO2009060763 A1 WO 2009060763A1
Authority
WO
WIPO (PCT)
Prior art keywords
equalizer
clock
restoration device
sampler
data restoration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/069555
Other languages
English (en)
French (fr)
Inventor
Seiichi Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
THine Electronics Inc
Original Assignee
THine Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by THine Electronics Inc filed Critical THine Electronics Inc
Priority to KR1020097020489A priority Critical patent/KR101397741B1/ko
Priority to EP08847479.6A priority patent/EP2131523B1/en
Priority to US12/594,916 priority patent/US8331513B2/en
Priority to CN2008800116212A priority patent/CN101652955B/zh
Publication of WO2009060763A1 publication Critical patent/WO2009060763A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

　クロックデータ復元装置１は、入力したデジタル信号に基づいてクロック信号およびデータを復元する装置であって、イコライザ部１０，サンプラ部２０，クロック生成部３０，イコライザ制御部４０および位相モニタ部５０を備える。サンプラ部２０およびクロック生成部３０によるループ処理により、入力デジタル信号に基づいて復元されたクロック信号として、クロック信号ＣＫまたはＣＫＸが生成される。イコライザ部１０，サンプラ部２０およびイコライザ制御部３０によるループ処理により、イコライザ部１０におけるデジタル信号のうちの高周波成分のレベル調整量の制御が行われる。
PCT/JP2008/069555 2007-11-06 2008-10-28 クロックデータ復元装置 Ceased WO2009060763A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020097020489A KR101397741B1 (ko) 2007-11-06 2008-10-28 클록 데이터 복원 장치
EP08847479.6A EP2131523B1 (en) 2007-11-06 2008-10-28 Clock data restoration device
US12/594,916 US8331513B2 (en) 2007-11-06 2008-10-28 Clock data restoration device
CN2008800116212A CN101652955B (zh) 2007-11-06 2008-10-28 时钟数据恢复装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007289011A JP4558028B2 (ja) 2007-11-06 2007-11-06 クロックデータ復元装置
JP2007-289011 2007-11-06

Publications (1)

Publication Number Publication Date
WO2009060763A1 true WO2009060763A1 (ja) 2009-05-14

Family

ID=40625657

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/069555 Ceased WO2009060763A1 (ja) 2007-11-06 2008-10-28 クロックデータ復元装置

Country Status (7)

Country Link
US (1) US8331513B2 (ja)
EP (1) EP2131523B1 (ja)
JP (1) JP4558028B2 (ja)
KR (1) KR101397741B1 (ja)
CN (1) CN101652955B (ja)
TW (1) TWI405447B (ja)
WO (1) WO2009060763A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015156089A1 (ja) * 2014-04-10 2015-10-15 ザインエレクトロニクス株式会社 受信装置
US10148418B2 (en) 2014-04-09 2018-12-04 Thine Electronics, Inc. Receiving device

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US7639736B2 (en) * 2004-05-21 2009-12-29 Rambus Inc. Adaptive receive-side equalization
JP5540472B2 (ja) * 2008-06-06 2014-07-02 ソニー株式会社 シリアルデータ受信機、利得制御回路および利得制御方法
TWI451102B (zh) * 2009-09-24 2014-09-01 Hon Hai Prec Ind Co Ltd 對串列訊號進行測試的資料處理設備及方法
KR101161314B1 (ko) 2010-05-14 2012-07-02 전자부품연구원 비정수 샘플링 방식의 클록 데이터 복원장치
CN103053140B (zh) 2010-08-03 2015-01-28 松下电器产业株式会社 自适应型接收系统及自适应型收发系统
CN102594340B (zh) * 2011-01-17 2015-05-27 智原科技股份有限公司 相位检测器、相位检测方法以及时钟数据恢复装置
US8384421B1 (en) * 2011-04-21 2013-02-26 Applied Micro Circuits Corporation Digital CMOS circuit with noise cancellation
CN102299721A (zh) * 2011-09-22 2011-12-28 四川和芯微电子股份有限公司 均衡电路及均衡系统
US20140032743A1 (en) * 2012-07-30 2014-01-30 James S. Hiscock Selecting equipment associated with provider entities for a client request
CN104572543B (zh) * 2013-10-12 2019-04-09 成都信息工程大学 一种过采样高速串行接收器
JP5844832B2 (ja) * 2014-02-03 2016-01-20 日本電信電話株式会社 ディジタルコヒーレント光受信装置および周波数特性調整方法
US9356588B2 (en) 2014-06-09 2016-05-31 Qualcomm Incorporated Linearity of phase interpolators using capacitive elements
KR102326661B1 (ko) * 2015-08-13 2021-11-16 삼성전자주식회사 이퀄라이저 장치 및 이를 포함하는 메모리 장치
KR101748032B1 (ko) * 2015-09-03 2017-06-14 한국과학기술원 집적회로를 이용한 다중전극 신장신경절제 방법 및 시스템
US10791009B1 (en) * 2019-11-13 2020-09-29 Xilinx, Inc. Continuous time linear equalization (CTLE) adaptation algorithm enabling baud-rate clock data recovery(CDR) locked to center of eye

Citations (4)

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JPS6229236A (ja) * 1985-07-31 1987-02-07 ミシエル　セルヴル 局部クロック信号と受信データ信号とを再同期させる機構
JPH0575653A (ja) * 1991-02-12 1993-03-26 Shaye Commun Ltd デイジタル通信システム
JP2007151044A (ja) * 2005-11-30 2007-06-14 Fujitsu Ltd シリアル転送用インターフェース
WO2008044406A1 (en) * 2006-10-12 2008-04-17 Thine Electronics, Inc. Clock data restoring device

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JPH07221800A (ja) 1994-02-02 1995-08-18 Nec Corp データ識別再生回路
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US6298103B1 (en) * 1998-06-16 2001-10-02 Sorrento Networks Corporation Flexible clock and data recovery module for a DWDM optical communication system with multiple clock rates
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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6229236A (ja) * 1985-07-31 1987-02-07 ミシエル　セルヴル 局部クロック信号と受信データ信号とを再同期させる機構
JPH0575653A (ja) * 1991-02-12 1993-03-26 Shaye Commun Ltd デイジタル通信システム
JP2007151044A (ja) * 2005-11-30 2007-06-14 Fujitsu Ltd シリアル転送用インターフェース
WO2008044406A1 (en) * 2006-10-12 2008-04-17 Thine Electronics, Inc. Clock data restoring device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10148418B2 (en) 2014-04-09 2018-12-04 Thine Electronics, Inc. Receiving device
WO2015156089A1 (ja) * 2014-04-10 2015-10-15 ザインエレクトロニクス株式会社 受信装置
JP2015201809A (ja) * 2014-04-10 2015-11-12 ザインエレクトロニクス株式会社 受信装置
US10333692B2 (en) 2014-04-10 2019-06-25 Thine Electronics, Inc. Reception apparatus

Also Published As

Publication number Publication date
EP2131523B1 (en) 2021-04-28
US8331513B2 (en) 2012-12-11
TW200937925A (en) 2009-09-01
KR101397741B1 (ko) 2014-05-20
JP4558028B2 (ja) 2010-10-06
CN101652955A (zh) 2010-02-17
JP2009118186A (ja) 2009-05-28
US20110285432A1 (en) 2011-11-24
KR20100084974A (ko) 2010-07-28
TWI405447B (zh) 2013-08-11
EP2131523A1 (en) 2009-12-09
CN101652955B (zh) 2013-07-03
EP2131523A4 (en) 2014-07-02

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