WO2010008281A1 - A method of forming a high density structure - Google Patents
A method of forming a high density structure Download PDFInfo
- Publication number
- WO2010008281A1 WO2010008281A1 PCT/NL2009/050430 NL2009050430W WO2010008281A1 WO 2010008281 A1 WO2010008281 A1 WO 2010008281A1 NL 2009050430 W NL2009050430 W NL 2009050430W WO 2010008281 A1 WO2010008281 A1 WO 2010008281A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cavity
- substrate
- release liner
- high density
- filler material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1258—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K1/183—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components mounted in and supported by recessed areas of the PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
Definitions
- the further layer has to be adhered to an outer surface of the dielectric layer during a baking step.
- residuals of the semiconductor layer may be left behind when surface adherence between the dielectric layer and the substrate is stronger than surface adherence between the dielectric layer and the further layer.
- a release liner on a surface of the substrate prior to any substantial processing step, like cavity forming and cavity filling, the overall surface of the substrate is protected from deposition of undesirable material, like debris or contamination from the filler material. This improves operational properties of the high density structure, in particular of a high density electrical circuit.
- Squeegee processing may be preferable for enabling fast and reliable filling of the cavities provided in the substrate.
- Another possibility of cavity filling may relate to a processing using dispenser which represents a suitable low cost alternative.
- the release liner according to the invention is provided on the surface of the substrate prior to the filling step, no particular accuracy condition is put to the step of squeegee filling or dispensing, as any excessive material left will be removed together with the release liner, because it extends substantially over the whole surface area of the substrate.
- the filler material and/or the further filler material are provided in excess for excessively filling the at least one cavity and/or the at least one further cavity.
- the release liner as used in the method according to the invention has a further advantage. It is possible to use a substrate with pre- manufactured cavities which can be protected from material interference by the release liner during the step of filling. Such pre-manufactured cavities preferably relate to cavities wherein suitable devices are to be positioned, for example chips.
- the high density structure may relate to a suitable plurality of items.
- it may relate an electrical circuit, an optical structure, a fluidic interconnection, a magnetic structure.
- FIG. 1 presents in a schematic way an embodiment of the method according to the invention.
- the method 10 may comprise steps 10a — 1Od as will be described herein after.
- a suitable substrate 2 may be selected, said substrate may comprise a piece or a layer of a suitable material, for example a foil.
- the substrate 2 may comprise a piece or a layer of a suitable material provided with one or more pre-manufactured cavities of the type 2a.
- the cavity 2a is depicted as a relatively small structure with respect to both a thickness of the substrate and its lateral dimension, the cavity 2a may be of any desirable size and it may have any desirable depth.
- the pre-manufactured cavity 2a is used for housing a suitable device conceived to cooperate with a high density structure provided on the substrate according to the invention.
- the substrate 35 is provided with a suitable number of further cavities 33a, 33b, which are subsequently filled with a suitable further material.
- the cavities 31a', 31b', 31c', 31d', 31e', 31f , 31g' may be filled with a conductive material, for example, metal, while the cavities 33a, 33b may be field with a resistive material. It will be appreciated that the cavities 33a, 33b may be filled with a different material, or may be used to embed a further device in the substrate 35.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011518672A JP5442731B2 (en) | 2008-07-15 | 2009-07-14 | Method for forming high-density structure |
| US13/054,277 US8415246B2 (en) | 2008-07-15 | 2009-07-14 | Method of forming a high density structure |
| EP09788230.2A EP2308276B1 (en) | 2008-07-15 | 2009-07-14 | A method of forming a high density structure |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP08160452.2 | 2008-07-15 | ||
| EP08160452A EP2146559A1 (en) | 2008-07-15 | 2008-07-15 | A method of forming a high density structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2010008281A1 true WO2010008281A1 (en) | 2010-01-21 |
Family
ID=40088828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/NL2009/050430 Ceased WO2010008281A1 (en) | 2008-07-15 | 2009-07-14 | A method of forming a high density structure |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8415246B2 (en) |
| EP (2) | EP2146559A1 (en) |
| JP (1) | JP5442731B2 (en) |
| WO (1) | WO2010008281A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI556698B (en) * | 2014-08-12 | 2016-11-01 | 旭德科技股份有限公司 | Substrate structure and manufacturing method thereof |
| CN115190693A (en) | 2021-04-02 | 2022-10-14 | 奥特斯奥地利科技与系统技术有限公司 | Component carrier and method for producing the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3948706A (en) * | 1973-12-13 | 1976-04-06 | International Business Machines Corporation | Method for metallizing ceramic green sheets |
| US3956052A (en) * | 1974-02-11 | 1976-05-11 | International Business Machines Corporation | Recessed metallurgy for dielectric substrates |
| US4080513A (en) * | 1975-11-03 | 1978-03-21 | Metropolitan Circuits Incorporated Of California | Molded circuit board substrate |
| US4985601A (en) * | 1989-05-02 | 1991-01-15 | Hagner George R | Circuit boards with recessed traces |
| US5460921A (en) | 1993-09-08 | 1995-10-24 | International Business Machines Corporation | High density pattern template: materials and processes for the application of conductive pastes |
| US7014727B2 (en) * | 2003-07-07 | 2006-03-21 | Potomac Photonics, Inc. | Method of forming high resolution electronic circuits on a substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2697447B2 (en) * | 1992-01-17 | 1998-01-14 | 富士通株式会社 | Laser ablation processing method and electronic device |
| JP3956667B2 (en) * | 2001-10-23 | 2007-08-08 | 松下電器産業株式会社 | Circuit board and manufacturing method thereof |
| DE102004005300A1 (en) * | 2004-01-29 | 2005-09-08 | Atotech Deutschland Gmbh | Process for treating carrier material for the production of powder carriers and application of the process |
| JP4443349B2 (en) * | 2004-08-24 | 2010-03-31 | パナソニック株式会社 | Manufacturing method of multilayer wiring board |
-
2008
- 2008-07-15 EP EP08160452A patent/EP2146559A1/en not_active Withdrawn
-
2009
- 2009-07-14 JP JP2011518672A patent/JP5442731B2/en not_active Expired - Fee Related
- 2009-07-14 EP EP09788230.2A patent/EP2308276B1/en not_active Not-in-force
- 2009-07-14 US US13/054,277 patent/US8415246B2/en not_active Expired - Fee Related
- 2009-07-14 WO PCT/NL2009/050430 patent/WO2010008281A1/en not_active Ceased
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3948706A (en) * | 1973-12-13 | 1976-04-06 | International Business Machines Corporation | Method for metallizing ceramic green sheets |
| US3956052A (en) * | 1974-02-11 | 1976-05-11 | International Business Machines Corporation | Recessed metallurgy for dielectric substrates |
| US4080513A (en) * | 1975-11-03 | 1978-03-21 | Metropolitan Circuits Incorporated Of California | Molded circuit board substrate |
| US4985601A (en) * | 1989-05-02 | 1991-01-15 | Hagner George R | Circuit boards with recessed traces |
| US5460921A (en) | 1993-09-08 | 1995-10-24 | International Business Machines Corporation | High density pattern template: materials and processes for the application of conductive pastes |
| US5789121A (en) * | 1993-09-08 | 1998-08-04 | International Business Machines Corporation | High density template: materials and processes for the application of conductive pastes |
| US7014727B2 (en) * | 2003-07-07 | 2006-03-21 | Potomac Photonics, Inc. | Method of forming high resolution electronic circuits on a substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| US8415246B2 (en) | 2013-04-09 |
| JP2011528502A (en) | 2011-11-17 |
| EP2308276B1 (en) | 2016-10-26 |
| JP5442731B2 (en) | 2014-03-12 |
| EP2146559A1 (en) | 2010-01-20 |
| EP2308276A1 (en) | 2011-04-13 |
| US20110159683A1 (en) | 2011-06-30 |
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