WO2011085605A1 - 一种级联码的译码方法及装置 - Google Patents

一种级联码的译码方法及装置 Download PDF

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WO2011085605A1
WO2011085605A1 PCT/CN2010/077975 CN2010077975W WO2011085605A1 WO 2011085605 A1 WO2011085605 A1 WO 2011085605A1 CN 2010077975 W CN2010077975 W CN 2010077975W WO 2011085605 A1 WO2011085605 A1 WO 2011085605A1
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codeword
decoding
ldpc
information
module
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English (en)
French (fr)
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张涛
游月意
曹南山
姚扬中
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ZTE Corp
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ZTE Corp
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Priority to KR1020127014693A priority Critical patent/KR101351497B1/ko
Priority to AU2010342630A priority patent/AU2010342630B2/en
Priority to BR112012014031A priority patent/BR112012014031A2/pt
Priority to US13/512,196 priority patent/US8667378B2/en
Priority to EP10842888.9A priority patent/EP2501046A4/en
Publication of WO2011085605A1 publication Critical patent/WO2011085605A1/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1128—Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • H03M13/3715—Adaptation to the number of estimated errors or to the channel state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/373—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes

Definitions

  • the present invention relates to the field of China Mobile Multimedia Broadcasting (CMMB) technology, and in particular, to a method and a device for decoding a concatenated code.
  • CMMB China Mobile Multimedia Broadcasting
  • the effectiveness and reliability of information transmission are the two main indicators for evaluating communication systems.
  • the redundancy is not as good as possible.
  • the simulation model of the digital communication system is shown in Figure 1.
  • LDPC Low Density Parity Check
  • the LDPC code generated by the LDPC code can be divided into a regular code and an irregular code: if each row in the matrix H has a fixed r 1 and each column has a fixed c 1 , then The generated LDPC code is called a (c, r) rule code; if the number of elements 1 in the row and column of H is not fixed, the generated LDPC code is an irregular code.
  • the (3,6) rule code of 1/2 code rate and the (3, 12) rule code of 3/4 code rate are used as part of the channel coding, and the code word length is 9216.
  • the LDPC code check matrix H in the CMMB system can be created by cyclic shifting through a code table.
  • the code table is an 18 x 6 matrix, which stores the position of the first 18 rows of non-zero elements of the H matrix.
  • the code table can be rotated right by 36 bits every 18 lines to obtain the H matrix.
  • the code table is a 9 X 12 matrix, which stores the position of the first 9 rows of non-zero elements of the HH matrix. Every 9 lines, the code table can be rotated right by 36 bits to obtain the H matrix. Non-line Zero element position. This structure can greatly reduce the storage space of the H matrix.
  • the code table for generating the H matrix at 1/2 code rate is:
  • the code table for generating the H matrix at 3/4 code rate is:
  • the output code word of the LDPC ⁇ , ..., ⁇ consists of the input information bits ⁇ ..., ⁇ and the school horse ratio: ⁇ ,... ⁇ — ⁇ , as shown in the following equation:
  • the RS (Reed Solomon) code is used as the cascading code of the outer code and the LDPC code.
  • the encoding process is shown in Figure 2.
  • Each symbol of the RS code is taken from the finite field GF (256), which is a truncation code of (240, k), and k can take values of 176, 192, 224, and 240, and different values can be obtained according to different values.
  • RS code for error correction capability.
  • the decoding of LDPC codes generally uses a soft decision decoding algorithm based on BP algorithm, such as the normalized Min-Sum algorithm.
  • the decoding method of the RS code generally includes error correction decoding and erasure decoding, and the erasure decoding decoding has better decoding performance than the error correction decoding.
  • the conventional decoding algorithm only performs the RS decoding by directly storing the decoding result of the LDPC code into the byte interleaver, so the RS code can only perform error correction decoding. , which affects the decoupling of concatenated codes to a certain extent
  • the present invention provides a decoding method and apparatus for concatenated codes to improve the decoding performance of the concatenated codes of the RS code and the LDPC code, and to solve the problem of poor performance of concatenated codes in the prior art.
  • the present invention provides a decoding method for a concatenated code, which is used for decoding a concatenated code composed of a low density parity check code (LDPC) and a Reed-Solomon (RS) code, the method comprising: Performing LDPC soft decision iterative decoding on the bit deinterleaved data stream, and performing check verification on the decoded LDPC codeword by using the check matrix;
  • LDPC low density parity check code
  • RS Reed-Solomon
  • Decoding mode is selected according to the puncturing information of the RS codeword, and RS decoding is performed.
  • the step of performing a check decision on the decoded LDPC codeword by using the check matrix may include: multiplying the parity matrix of the decoded hard decision codeword C by the check matrix H, and if the product is zero, determining The codeword C is correctly verified, and the value of the error flag corresponding to the codeword C is recorded as correct; if the product is not zero, the codeword C is judged to be incorrect, and the value of the error flag corresponding to the codeword C is recorded. error.
  • the step of converting the check information of the LDPC codeword into the punctured information of the RS codeword may include: repeating the error flag corresponding to each LDPC codeword L times as the punctured information of the column corresponding to the LDPC codeword, where L is the ratio of the information bit length of the LDPC codeword to the interleaver column length, and L is a positive integer.
  • the step of selecting a coding mode according to the puncturing information of the RS codeword may include: if the number of the punctured positions of the RS codeword is within the correctable range of the RS erasure decoding, selecting the erasure decoding mode; If the number of punctured positions is not within the range, the error correction decoding mode is selected.
  • the number of punctured positions of the RS codeword in the correctable range of the RS erasure decoding may be: The number of punctured positions is less than or equal to the number of RS check bits.
  • the step of deinterleaving the decoded LDPC codeword may include: writing the decoded LDPC codeword to the interleaver in column order, and reading in a row order.
  • the present invention further provides a decoding device for a concatenated code, comprising an LDPC decoding module, a de-byte interleaving module and an RS decoding module, the device further comprising: an LDPC codeword check decision module and an RS decoding mode selection Module, where:
  • the LDPC decoding module is configured to: perform soft decision iterative decoding of the LDPC code, and output the information bits of the decoded LDPC codeword to the de-byte interleaving module, and decode the information bits of the decoded LDPC codeword.
  • the check bit is output to the LDPC codeword check decision module;
  • the LDPC codeword check decision module is configured to complete the verification decision of the decoded LDPC codeword, and output the check information of the LDPC codeword to the de-byte interleaving module;
  • the de-interleaving byte interleaving module is configured to: convert the information bits of the LDPC codeword into a byte de-interleaving output, and extract the RS codeword to the RS decoding module, and process the LDPC codeword verification information, and the LDPC
  • the parity information of the codeword is converted into the punctured information of the RS codeword, and output to the RS decoding mode selection module;
  • the RS decoding mode selection module is configured to complete the selection of the RS decoding mode according to the puncturing information of the RS codeword output by the de-byte interleaving module, and output the selection result to the RS decoding module;
  • the RS decoding module is configured to perform error correction decoding or erasure decoding decoding of the RS codeword according to the selection result output by the RS decoding mode selection module.
  • the LDPC codeword check decision module may be configured to perform a check decision on the decoded LDPC codeword according to the following manner: multiply the check matrix H by the transposed matrix of the decoded hard decision codeword C, if the product If it is zero, the codeword C is judged to be correct, and the value of the error flag corresponding to the code word C is recorded as correct; if not, the code word C is checked for error, and the error corresponding to the code word C is recorded. The value of the tag is incorrect.
  • the de-interleaving module may be configured to convert the check information of the LDPC codeword into the punctured information of the RS codeword in the following manner: repeating the error flag corresponding to each LDPC codeword L times as the deletion of the column corresponding to the LDPC The remaining information, where L is a ratio of the information bit length of the LDPC codeword to the interleaver column length, and L is a positive integer.
  • the RS coding mode selection module may be configured to perform selection of the RS coding mode according to the following manner: if the number of punctured positions of the RS codeword is within the correctable range of the RS erasure decoding, then the erasure decoding is selected.
  • the error correction decoding mode is selected.
  • the number of the to-be-punctured positions of the RS codeword may be within the correctable range of the RS erasure decoding, that is, the number of the to-be-punctured positions is less than or equal to the number of RS parity bits of the RS codeword.
  • the de-interleaving module may be arranged to convert the information bits of the LDPC codeword into a byte-de-interleaved output in the following manner:
  • the LDPC codewords are written to the interleaver in column order, and are read in line order.
  • the decoding scheme of the concatenated code composed of the RS code and the LDPC code according to the present invention can improve the performance of the RS decoding without increasing the computational complexity, so that the receiving performance of the CMMB terminal is compared with the conventional method. Greatly improved.
  • 1 is a simulation model diagram of a conventional digital communication system
  • FIG. 2 is a flow chart of channel coding in a prior art CMMB system
  • FIG. 3 is a schematic block diagram of a decoding apparatus for a concatenated code according to an embodiment of the present invention
  • the present invention provides a decoding method for a concatenated code, which is applied to the decoding of a concatenated code composed of an RS code and an LDPC code, and is applicable to a CMMB system, which mainly includes the following steps:
  • Step a performing LDPC soft decision iterative decoding on the bit deinterleaved data stream, and performing check verification on the decoded LDPC codeword by using the check matrix H;
  • Step b Deinterleave the information bits of the decoded LDPC codeword, and convert the check information of the LDPC codeword into the punctured information of the RS codeword;
  • Step c Select a decoding mode according to the puncturing information of the RS codeword, and perform RS decoding.
  • the LDPC decoding operation may select a soft decision decoding algorithm based on the BP algorithm, and may decode the obtained LDPC codeword by using the modulo 2 sum operation (ie, the hard decision codeword C, including information bits and Parity check: If the product of the check matrix H and the transposed matrix of the hard decision codeword C is zero, the codeword C is correctly verified. If the product is not zero, the codeword C checksum error. Specifically, it is assumed that the hard decision codeword C outputted after decoding is a row vector of length N, and the check matrix H is a matrix of M rows and N columns.
  • deinterleaving the LDPC codeword means: converting the information bits of the decoded LDPC codeword into bytes and deinterleaving the output.
  • the information bit length of each LDPC codeword is L times the length of the interleaver column (L is a positive integer), and therefore,
  • the parity information of the LDPC codeword is converted into the punctured information of the RS codeword in the following manner:
  • the error flag err_flag corresponding to each LDPC codeword is repeated L times as the punctured information of the corresponding column.
  • the process of selecting a coding mode according to the puncturing information of the RS codeword includes: if the number of the punctured positions of the RS codeword is within the correctable range of the RS erasure decoding, then selecting and correcting Deleting the decoding mode; if not within the range, selecting the error correction decoding mode.
  • the correctable range of the number of the punctured bits of the RS codeword in the RS erasure decoding refers to: the number of the punctured positions is less than or equal to the number of the RS check bits.
  • the above-mentioned to-be-punctured position refers to a position of an error flag (err_flag is 1) in a sequence obtained by err_flag, and the number of positions to be punctured refers to an error flag in the sequence. number.
  • the decoding device of the concatenated code provided by the embodiment of the present invention includes:
  • the LDPC decoding module is configured to: perform soft decision iterative decoding of the LDPC code, and output the information bits of the decoded LDPC codeword to the de-byte interleaving module, and decode the information bits of the decoded LDPC codeword.
  • the check bit is output to the LDPC codeword check decision module;
  • the LDPC codeword check decision module is configured to complete the verification decision of the decoded LDPC codeword, and output the check information of the LDPC codeword to the de-byte interleaving module;
  • the de-interleaving byte interleaving module is configured to: convert the information bits of the LDPC codeword into a byte de-interleaving output, and extract the RS codeword to the RS decoding module, and process the LDPC codeword verification information, and the LDPC
  • the codeword check information is converted into punctured information of the RS codeword, and output to the RS decoding mode selection module;
  • the RS decoding mode selection module is configured to complete the selection of the RS decoding mode according to the puncturing information of the RS codeword output by the de-byte interleaving module, and output the selection result to the RS decoding module;
  • the RS decoding module is configured to perform error correction or erasure decoding of the RS code according to the selection result output by the RS decoding mode selection module.
  • the LDPC decoding module is configured to perform soft decision iterative decoding of the LDPC code after the bit deinterleaving output of the receiving end, and output the hard decision codeword C.
  • the LDPC codeword check decision module performs the parity check on the codeword C by using the modulo 2 and the calculation according to the hard decision codeword C and the LDPC check matrix H output by the LDPC decoding module.
  • the solution byte interleaving module is respectively connected to the output of the LDPC decoding module and the LDPC codeword verification decision module, and is configured to convert the information bits of the LDPC decoding result into bytes.
  • the deinterleaving output is performed, and the verification information of the LDPC codeword is converted into the punctual information output of the RS codeword. Since the LDPC codewords are stored in columns in the byte interleaver, according to the CMMB protocol, the information bit length of each LDPC codeword is L times the interleaver column length (ie, the number of rows) (L is an integer value).
  • the error flag err_flag corresponding to each LDPC codeword is repeated L times as the puncturing information of the corresponding column.
  • the RS decoding mode selection module is determined according to the puncturing information output by the de-byte interleaving module, and selects a corresponding decoding mode: if the number of locations to be punctured is within the correctable range of the RS erasure decoding Then, the erasure decoding mode is selected; if not within the range, the error correction decoding mode is selected.
  • the number of positions to be punctured in the correction range of the RS erasure decoding means that the number of positions to be punctured of the RS code is less than or equal to the number of RS parity bits.
  • the RS decoding module is respectively connected to the de-byte interleaving module and the decoding mode selection module, and the RS decoding module can perform two decoding modes of error correction decoding and erasure decoding, and select according to the RS decoding mode.
  • the output of the module determines the operation of the corresponding decoding mode. Said.
  • the decoding method of this embodiment is applicable to the CMMB system, and the method mainly includes the following steps: Step 101: Perform LDPC decoding operation of the data stream after bit deinterleaving, and output a hard decision code word C;
  • the input of the LDPC decoding module is the log likelihood ratio information of the bit, and the LDPC decoding operation may select the existing soft decision decoding algorithm based on the BP algorithm, and the hard decision codeword C output after the LDPC decoding is completed.
  • the length is 9216 bits.
  • Step 102 Perform parity check on the hard decision codeword C by using the check matrix H.
  • H is a matrix of 4068 rows and 9216 columns; for a 3/4 code rate LDPC code, H is a matrix of 2304 rows and 9216 columns.
  • H - C T 0 T
  • Step 103 Convert the information bits of the LDPC decoding result into a byte deinterleaving output, and convert the verification information of the LDPC codeword into the punctured information of the RS codeword.
  • the byte conversion manner is as follows: the information bits of the LDPC codeword are grouped into 8 groups, and each group is converted into a representation form in the GF (256) domain in a lower priority order.
  • the deinterleaving method is as follows: The LDPC codewords are written to the interleaver in column order, and are read out in the row order.
  • the implementation step of converting the check information of the LDPC codeword into the punctured information of the RS codeword is: setting the information bit length of the LDPC codeword to M, and then the byte length is M/8;
  • the error flag err_flag corresponding to each LDPC code word is repeated L times as the puncturing information of the corresponding column.
  • Step 104 Perform judging according to the punctured information of the converted RS codeword, and select a corresponding RS decoding mode.
  • the implementation steps are as follows: According to the error flag err_flag obtained in the above step 103, the number E of the err_flag is 1 is calculated. For the RS code used in the system, the code length is assumed to be N bytes, and the information bit is The length is K bytes. If E is less than or equal to N - K (ie, the number of RS check bits), the erasure decoding mode selection flag is output; if E is greater than N - K, the error correction decoding mode is selected. Sign.
  • Step 105 Decode the RS codeword according to the RS code word obtained in step 103 and the decoding mode selection flag obtained in step 104.
  • FIG. 4 shows the performance comparison between the decoding scheme of the present invention and the conventional scheme when the maximum Doppler shift is 100 Hz, wherein the ordinate is BER (Bit Error Rate) and the abscissa is SNR. (Signal to Noise Ratio), as can be seen from Fig. 4, the decoding scheme can be improved by about 0.7 dB by using the present invention to provide a decoding scheme as compared with the conventional scheme.
  • BER Bit Error Rate
  • SNR Signal to Noise Ratio
  • the present invention can improve the performance of the RS decoding without increasing the computational complexity, so that the receiving performance of the CMMB terminal is greatly improved compared with the conventional method.

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Description

一种级联码的译码方法及装置
技术领域
本发明涉及中国移动多媒体广播 ( China Mobile Multimedia Broadcasting, 简称为 CMMB )技术领域， 尤其涉及一种级联码的译码方法及装置。
背景技术
信息传输的有效性和可靠性是评估通信系统的两个主要指标， 为了增加 信息传输的可靠性， 通常要对信息进行信道编码以增加一定的冗余度， 使得 码字具有自动检错和纠错的能力。 但是， 冗余度并不是越多越好， 为了兼顾 信息传输的有效性， 人们希望在冗余度一定的情况下， 通过设计优秀的编译 码方法， 使得在接收端获得良好的译码性能。 数字通信系统的仿真模型如图 1所示。
低密度奇偶校验 ( Low Density Parity Check, 简称为 LDPC )码是 1962 年由 Gallager提出的一种基于稀疏校验矩阵的线性分组码。 1996年， MacKay 和 Neal对 LDPC码进行了再发现， 证明其具有接近香农限的性能。 现有的一 些通信系统， 如 DVB ( Digital Video Broadcasting, 数字视频广播）、 WiMAX ( Worldwide Interoperability for Microwave Access, 全球微波互联接入)和 CMMB系统中都釆用 LDPC码作为信道编码。根据 LDPC码校验矩阵 H中元 素 1的分布， 可以将其生成的 LDPC码分为规则码与非规则码： 如果矩阵 H 中每行有固定 r个 1 , 每列有固定 c个 1 , 则其生成的 LDPC码称为 (c,r)规则 码；如果 H的行列中元素 1的个数不固定，则其生成的 LDPC码为非规则码。 在 CMMB系统中，釆用了 1/2码率的 (3,6)规则码和 3/4码率的 (3, 12)规则码作 为信道编码的一部分， 码字长度均为 9216。
CMMB系统中 LDPC码校验矩阵 H可以通过一个码表进行循环移位创 建。 釆用 1/2码率时， 码表为一 18 x 6的矩阵， 存放的是 H矩阵前 18行非零 元素的位置， 每隔 18行可将码表循环右移 36位得到 H矩阵其它行的非零元 素位置。 釆用 3/4码率时， 码表为一 9 X 12的矩阵， 存放的是 HH矩阵前 9 行非零元素的位置，每隔 9行可将码表循环右移 36位得到 H矩阵其它行的非 零元素位置。 这种结构可以大大减少 H矩阵的存储空间。
1/2码率时生成 H矩阵的码表为：
0， 6, 12, 18, 25， 30
0， 7, 19, 26， 31, 5664
0， 8, 13, 20， 32， 8270
1， 6, 14, 21， 3085， 8959
1， 15, 27, 33， 9128， 9188
1， 9, 16, 34, 8485， 9093
2， 6, 28， 35， 4156， 7760
2， 10, 17, 7335， 7545， 9138
2， 11, 22， 5278， 8728， 8962
3, 7, 2510， 4765， 8637， 8875
3, 4653， 4744， 7541， 9175， 9198
3, 23， 2349， 9012， 9107， 9168
4， 7, 29， 5921， 7774， 8946
4， 7224， 8074， 8339， 8725， 9212
4， 4169， 8650， 8780， 9023， 9159
5， 8, 6638， 8986， 9064， 9210
5， 2107， 7787， 8655， 9141， 9171
5， 24, 5939， 8507， 8906， 9173
3/4码率时生成 H矩阵的码表为：
0, 3, 6, 12, 16, 18, 21, 24, 27, 31, 34, 7494
0, 4, 10, 13, 25, 28, 5233, 6498, 7018, 8358, 8805, 9211
0, 7, 11, 19, 22, 6729, 6831, 7913, 8944, 9013, 9133, 9184
1, 3, 8, 14, 17, 20, 29, 32, 5000, 5985, 7189, 7906
1, 9, 4612, 5523, 6456, 7879, 8487, 8952, 9081, 9129, 9164, 9214
1, 5, 23, 26, 33, 35, 7135, 8525, 8983, 9015, 9048, 9154
2, 3, 30, 3652, 4067, 5123, 7808, 7838, 8231, 8474, 8791, 9162
2, 35, 3774, 4310, 6827, 6917, 8264, 8416, 8542, 8834, 9044, 9089 2, 15, 631, 1077, 6256, 7859, 8069, 8160, 8657, 8958, 9094, 9116
LDPC 的输出码字 ^^， …，^^由输入信息比特^^^^…，^^和校 马全比 ：^^ ，…^ —^组成， 如下式所示：
Figure imgf000005_0001
式中， COJ_ORZ)£R()为码字比特映射向量， K为信息比特长度（ 1/2码 率时 K = 4608, 3/4码率时 Κ = 6912) 。
CMMB系统中同时釆用了 RS (Reed Solomon, 里德-索洛蒙）码作为外 码与 LDPC码组成级联码， 编码流程如图 2所示。 RS码的每个码元取自有限 域 GF(256), 为一 (240,k)的截短码， k可以取值为 176、 192、 224和 240, 根 据不同的取值， 可以获得不同纠错能力的 RS码。
LDPC码的译码一般釆用基于 BP算法的软判决译码算法， 如归一化的 Min-Sum算法。 RS码的译码方法一般包括纠错译码和纠删译码， 纠删译码较 之纠错译码具有更好的译码性能。 目前， 针对 RS码和 LDPC码组成的级联 码， 传统的译码算法只是将 LDPC码的译码结果存入字节交织器后直接进行 RS译码， 因此 RS码只能做纠错译码， 这在一定程度上影响级联码的译码性
发明内容
本发明提供一种级联码的译码方法及装置， 以改善 RS码和 LDPC码的 级联码的译码性能， 解决现有技术中级联码性能不好的问题。
本发明提供了一种级联码的译码方法， 用于低密度奇偶校验码（LDPC) 和里德-索洛蒙（RS)码组成的级联码的译码， 所述方法包括： 对比特解交织后的数据流进行 LDPC软判决迭代译码， 并利用校验矩阵 对译码得到的 LDPC码字进行校验判决；
对译码得到的 LDPC码字的信息位进行解字节交织， 并将 LDPC码字的 校验信息转换成 RS码字的删余信息； 以及
根据所述 RS码字的删余信息选择译码模式， 进行 RS译码。 利用校验矩阵对译码得到的 LDPC码字进行校验判决的步骤可以包括： 利用校验矩阵 H与译码得到的硬判决码字 C的转置矩阵相乘， 若乘积为零， 则判决码字 C校验正确， 并记录该码字 C对应的错误标记的值为正确； 若乘 积不为零， 则判决码字 C校验错误， 并记录该码字 C对应的错误标记的值为 错误。 将 LDPC码字的校验信息转换成 RS码字的删余信息的步骤可以包括： 将每一个 LDPC码字对应的错误标记重复 L次作为该 LDPC码字所对应列的 删余信息， 其中， L为该 LDPC码字的信息位长度与交织器列长度的比值， L 为正整数。 根据 RS码字的删余信息选择译码模式的步骤可以包括： 如果 RS 码字的待删余位置的个数在 RS 纠删译码的可纠正范围内， 则选择纠删译码 模式； 若待删余位置的个数不在该范围内， 则选择纠错译码模式。 RS码字的 待删余位置的个数在 RS 纠删译码的可纠正范围可以是指： 待删余位置的个 数小于等于 RS校验位的个数。
对译码得到的 LDPC码字进行解字节交织的步骤可以包括： 将译码得到 的 LDPC码字按列顺序写入交织器， 按行顺序读出。
本发明还提供一种级联码的译码装置， 包括 LDPC译码模块、 解字节交 织模块和 RS译码模块， 所述装置还包括： LDPC码字校验判决模块和 RS译 码模式选择模块， 其中：
LDPC译码模块设置成： 完成 LDPC码的软判决迭代译码， 并将完成译 码后的 LDPC码字的信息位输出给解字节交织模块， 将译码后的 LDPC码字 的信息位和校验位输出给 LDPC码字校验判决模块；
LDPC码字校验判决模块设置成完成译码后的 LDPC码字的校验判决， 并将 LDPC码字的校验信息输出给解字节交织模块；
解字节交织模块设置成： 将 LDPC码字的信息位转换为字节的形式解交 织输出， 并提取 RS码字给 RS译码模块， 以及， 对 LDPC码字校验信息进行 处理， 将 LDPC码字的校验信息转换成 RS码字的删余信息， 并输出给 RS译 码模式选择模块；
RS译码模式选择模块设置成根据解字节交织模块输出的 RS码字的删余 信息完成 RS译码模式的选择， 并将选择结果输出给 RS译码模块； RS译码模块设置成根据 RS译码模式选择模块输出的选择结果完成 RS 码字的纠错译码或纠删译码。
LDPC码字校验判决模块可设置成对译码后的 LDPC码字按照以下方式 进行校验判决： 利用校验矩阵 H与译码后的硬判决码字 C的转置矩阵相乘， 若乘积为零， 则判决码字 C校验正确， 并记录该码字 C对应的错误标记的值 为正确； 若不为零， 则判决码字 C校验错误， 并记录该码字 C对应的错误标 记的值为错误。 解字节交织模块可设置成按照以下方式将 LDPC码字的校验 信息转换成 RS码字的删余信息：将每一个 LDPC码字对应的错误标记重复 L 次作为该 LDPC所对应列的删余信息， 其中， L为该 LDPC码字的信息位长 度与交织器列长度的比值， L为正整数。 RS译码模式选择模块可设置成按照 以下方式完成 RS译码模式的选择： 如果 RS码字的待删余位置的个数在 RS 纠删译码的可纠正范围内， 则选择纠删译码模式； 若待删余位置的个数不在 该可纠正范围内， 则选择纠错译码模式。 其中， RS码字的待删余位置的个数 在 RS纠删译码的可纠正范围内可以是指：待删余位置的个数小于等于 RS码 字的 RS校验位的个数。
解字节交织模块可设置成按照以下方式将 LDPC码字的信息位转换为字 节的形式解交织输出： 将所述 LDPC码字按列顺序写入交织器， 按行顺序读 出。
釆用本发明所述的 RS码与 LDPC码组成的级联码的译码方案， 可以在 不增加计算复杂度的情况下提高 RS译码的性能， 从而使 CMMB终端接收性 能较之传统方法有很大提高。 附图概述
图 1是现有数字通信系统的仿真模型图；
图 2是现有技术的 CMMB系统中信道编码流程图；
图 3是本发明实施例的级联码的译码装置的示意框图；
图 4是本发明译码方法与传统译码方法的性能对比仿真图。 本发明的较佳实施方式
本发明提供了一种级联码的译码方法， 应用于 RS码和 LDPC码组成的 级联码的译码， 可适用于 CMMB系统中， 其主要包括如下步骤：
步骤 a, 对比特解交织后的数据流进行 LDPC软判决迭代译码， 并利用 校验矩阵 H对译码得到的 LDPC码字进行校验判决；
步骤 b,对译码得到的 LDPC码字的信息位进行解字节交织， 并将 LDPC 码字的校验信息转换成 RS码字的删余信息；
步骤 c, 根据 RS码字的删余信息选择译码模式， 进行 RS译码。
其中，步骤 a中， LDPC译码操作可选择基于 BP算法的软判决译码算法， 并可通过模 2和的运算对译码得到的 LDPC码字 （即硬判决码字 C, 包括信 息位和校验位 )进行奇偶校验： 如果校验矩阵 H与硬判决码字 C的转置矩阵 的乘积为零， 则码字 C校验正确， 若该乘积不为零， 则码字 C校验错误。 具 体地， 假设译码后输出的硬判决码字 C为一长度为 N的行向量， 校验矩阵 H 为 M行 N列的矩阵， 如果 H · CT = 0Τ , 则码字 C校验正确， 同时将其对应的 错误标记 err— flag设为 0, 表示码字 C译码正确； 若上述乘积不为 0, 则设 err— flag的值为 1 , 表示码字 C译码错误。
进一步地， 步骤 b中， 对 LDPC码字进行解字节交织是指： 将译码得到 的 LDPC码字的信息位转换成字节的形式解交织输出。
由于 LDPC码字在字节交织器中是按列存放的， 根据 CMMB协议可知， 每一个 LDPC码字的信息位长度都是交织器列长度的 L倍（L为正整数） ， 因此， 可釆用如下方式将 LDPC码字的校验信息转换成 RS码字的删余信息： 将每一个 LDPC码字对应的错误标记 err— flag重复 L次作为其所对应列的删余 信息。
进一步地，步骤 c中，根据 RS码字的删余信息选择译码模式的过程包括： 如果 RS码字的待删余位置的个数在 RS纠删译码的可纠正范围内，则选 择纠删译码模式； 若不在该范围内， 则选择纠错译码模式。 其中， RS码字的待删余位置的个数在 RS纠删译码的可纠正范围是指： 待删余位置的个数小于等于 RS校验位的个数。 进一步地，上述的待删余位置是指通过 err— flag得到的一个序列中错误标 记（err— flag为 1 ) 的位置， 而待删余位置的个数则是指这个序列中错误标记 的个数。
下面结合附图及具体实施例对本发明技术方案的实施作进一步详细描 述。
如图 2所示， 本发明实施例提供的级联码的译码装置包括：
LDPC译码模块设置成： 完成 LDPC码的软判决迭代译码， 并将完成译 码后的 LDPC码字的信息位输出给解字节交织模块， 将译码后的 LDPC码字 的信息位和校验位输出给 LDPC码字校验判决模块；
LDPC码字校验判决模块设置成完成译码后的 LDPC码字的校验判决， 并将 LDPC码字的校验信息输出给解字节交织模块；
解字节交织模块设置成： 将 LDPC码字的信息位转换为字节的形式解交 织输出， 并提取 RS码字给 RS译码模块， 以及， 对 LDPC码字校验信息进行 处理， 将 LDPC码字校验信息转换成 RS码字的删余信息， 并输出给 RS译码 模式选择模块；
RS译码模式选择模块设置成根据解字节交织模块输出的 RS码字的删余 信息完成 RS译码模式的选择， 并将选择结果输出给 RS译码模块；
RS译码模块设置成根据 RS译码模式选择模块输出的选择结果完成 RS 码的纠错或纠删译码。
其中，上述的 LDPC译码模块是设置成在接收端的比特解交织输出之后， 完成 LDPC码的软判决迭代译码， 并且输出硬判决码字 C。
其中， 上述的 LDPC码字校验判决模块根据 LDPC译码模块输出的硬判 决码字 C和 LDPC校验矩阵 H, 通过模 2和计算完成对码字 C的奇偶校验判 决。 H没 C为一长度为 N的行向量， H为 M行 N列的矩阵， 如果 H . CT = 0T , 则码字 C校验正确， 同时将其对应的错误标记 err— flag设为 0; 若上述乘积不 为 0, 则设 err— flag=l , 表示码字 C译码错误。
其中， 上述的解字节交织模块分别与 LDPC译码模块及 LDPC码字校验 判决模块的输出相连， 并设置成将 LDPC译码结果的信息位转换成字节的形 式解交织输出， 同时将 LDPC码字的检验信息转换成 RS码字的删余信息输 出。 由于 LDPC码字在字节交织器中是按列存放的， 根据 CMMB协议可知， 每一个 LDPC码字的信息位长度都是交织器列长度（即行数） 的 L倍（L为 一整数值 ) ,将每一个 LDPC码字对应的错误标记 err— flag重复 L次作为其所 对应列的删余信息。
其中， 上述的 RS译码模式选择模块是根据解字节交织模块输出的删余 信息进行判断， 选择对应的译码模式： 如果待删余位置的个数在 RS 纠删译 码可纠正范围内， 则选择纠删译码模式； 若不在该范围内， 则选择纠错译码 模式。待删余位置的个数在 RS纠删译码的纠正范围是指 RS码的待删余位置 的个数小于等于 RS校验位的个数。
其中， 上述的 RS译码模块分别与解字节交织模块和译码模式选择模块 相连， RS译码模块可进行纠错译码及纠删译码两种译码模式， 根据 RS译码 模式选择模块的输出决定相应译码模式的运算。 述。
本实施例的译码方法可适用于 CMMB系统， 其主要包括以下步骤： 步骤 101 , 完成比特解交织后数据流的 LDPC译码操作， 并输出硬判决 码字 C;
其中， LDPC译码模块的输入为比特的对数似然比信息， LDPC译码操作 可选择目前已有的基于 BP算法的软判决译码算法， LDPC译码完成后输出的 硬判决码字 C的长度为 9216比特。
步骤 102, 利用校验矩阵 H对硬判决码字 C进行奇偶校验；
对于 1/2码率的 LDPC码， H为一 4068行 9216列的矩阵； 对于 3/4码率 的 LDPC码， H为一 2304行 9216列的矩阵。
如果 H - CT = 0T , 则码字 C校验正确， 同时将其对应的错误标记 err— flag 设为 0; 若上述乘积不为 0, 则设 err— flag=l , 表示码字 C译码错误。 其中， H与 C的乘积可以看作一系列模 2和的运算， 其计算方式为： 将 H的每一行 非零元素的位置所对应的码字 C的值求和并做模 2运算， 如果所有行的计算 结果都为 0 , 则 H . CT = 0T ; 如果运算过程中出现某一行计算结果不为 0的情 况， 则码字 C译码错误， 随之可以停止后续的模 2和运算。
步骤 103 , 将 LDPC译码结果的信息位转换成字节的形式解交织输出， 同时将 LDPC码字的检验信息转换成 RS码字的删余信息；
其中所述的字节转换方式为：将 LDPC码字的信息位每 8比特分为一组， 将每一组按照低位优先的次序转换为 GF(256)域中的表示形式。
其中所述的解交织方式为： LDPC码字按列顺序写入交织器， 按行顺序 读出。
其中所述的 LDPC码字的校验信息转换成 RS码字的删余信息的实现步 骤为： 设 LDPC码字的信息位比特长度为 M, 则字节长度为 M/8; 设字节交 织器的行数为 R, —个 LDPC所占用的字节交织器的列数为 L= M/(8R)。 将每 一个 LDPC码字对应的错误标记 err— flag重复 L次作为其所对应列的删余信 息。
步骤 104 , 根据转换的 RS码字的删余信息进行判断， 选择对应的 RS译 码模式；
其实现步骤为： 根据上述步骤 103 中得到的错误标记 err— flag, 计算 err— flag为 1的个数 E,对于系统中使用的 RS码来说，假设其码长为 N字节， 信息位长度为 K字节， 如果 E小于或等于 N - K (即 RS校验位的个数）， 则 输出纠删译码模式选择标志； 若 E大于 N - K, 则输出纠错译码模式选择标 志。
步骤 105 ,根据步骤 103得到的 RS码字以及步骤 104得到的译码模式选 择标志， 对 RS码字进行译码操作。
图 4中示出了当最大多普勒频移为 100Hz时， 本发明的译码方案与传统 方案的性能对比， 其中， 纵坐标为 BER ( Bit Error Rate, 误码率） , 横坐标 为 SNR ( Signal to Noise Ratio, 信噪比 ) , 从图 4中可以看出， 与传统方案相 比， 釆用本发明提供译码方案， 可将译码性能提高约 0.7dB。
当然， 本发明还可以有其他多种实施例， 在不违背本发明实质的情况下， 应的改变和变形都应属于本发明所附的权利要求的保护范围内。
工业实用性
与现有技术相比， 本发明可以在不增加计算复杂度的情况下提高 RS译 码的性能， 从而使 CMMB终端接收性能较之传统方法有很大提高。

Claims

权 利 要 求 书
1、 一种级联码的译码方法， 其特征在于， 该方法用于低密度奇偶校验码 LDPC和里德-索洛蒙 RS码组成的级联码的译码， 所述方法包括：
对比特解交织后的数据流进行 LDPC软判决迭代译码， 并利用校验矩阵 对译码得到的 LDPC码字进行校验判决；
对译码得到的 LDPC码字的信息位进行解字节交织， 并将所述 LDPC码 字的校验信息转换成 RS码字的删余信息； 以及
根据所述 RS码字的删余信息选择译码模式， 进行 RS译码。
2、 如权利要求 1所述的方法， 其中， 利用校验矩阵对译码得到的 LDPC 码字进行校验判决的步骤包括：
利用校验矩阵 H与译码得到的硬判决码字 C的转置矩阵相乘， 若乘积为 零， 则判决码字 C校验正确， 并记录该码字 C对应的错误标记的值为正确； 若所述乘积不为零， 则判决码字 C校验错误， 并记录该码字 C对应的错误标 记的值为错误。
3、 如权利要求 2所述的方法， 其中， 将 LDPC码字的校验信息转换成
RS码字的删余信息的步骤包括：
将每一个 LDPC码字对应的错误标记重复 L次作为该 LDPC码字所对应 列的删余信息， 其中， L为该 LDPC码字的信息位长度与交织器列长度的比 值， L为正整数。
4、 如权利要求 3所述的方法， 其中， 根据 RS码字的删余信息选择译码 模式的步骤包括：
如果 RS码字的待删余位置的个数在 RS纠删译码的可纠正范围内，则选 择纠删译码模式； 若所述待删余位置的个数不在 RS 纠删译码的可纠正范围 内， 则选择纠错译码模式。
5、 如权利要求 4所述的方法， 其中， RS码字的待删余位置的个数在 RS 纠删译码的可纠正范围内是指： 所述待删余位置的个数小于等于 RS码字的 RS校验位的个数。
6、 如权利要求 1所述的方法， 其中， 对译码得到的 LDPC码字进行解字 节交织的步骤为：
将所述译码得到的 LDPC码字按列顺序写入交织器， 按行顺序读出。
7、 一种级联码的译码装置， 包括低密度奇偶校验码 LDPC译码模块、 解 字节交织模块和里德-索洛蒙 RS译码模块， 其特征在于， 所述装置还包括
LDPC码字校验判决模块和 RS译码模式选择模块， 其中：
所述 LDPC译码模块设置成： 完成 LDPC码的软判决迭代译码， 并将译 码后的 LDPC码字的信息位输出给解字节交织模块， 将译码后的 LDPC码字 的信息位和校验位输出给 LDPC码字校验判决模块；
所述 LDPC码字校验判决模块设置成对译码后的 LDPC码字进行校验判 决， 并将校验信息输出给解字节交织模块；
所述解字节交织模块设置成： 将 LDPC码字的信息位转换为字节的形式 解交织输出， 并提取 RS码字给 RS译码模块， 以及， 将 LDPC码字的校验信 息转换成 RS码字的删余信息， 并输出给 RS译码模式选择模块；
所述 RS译码模式选择模块设置成根据解字节交织模块输出的 RS码字的 删余信息完成 RS译码模式的选择， 并将选择结果输出给 RS译码模块；
所述 RS译码模块设置成根据 RS译码模式选择模块输出的选择结果完成 RS码字的纠错译码或纠删译码。
8、 如权利要求 7所述的装置， 其中， 所述 LDPC码字校验判决模块是设 置成对译码后的 LDPC码字按照以下方式进行校验判决：
利用校验矩阵 H与译码后的硬判决码字 C的转置矩阵相乘，若乘积为零， 则判决码字 C校验正确， 并记录该码字 C对应的错误标记的值为正确； 若乘 积不为零， 则判决码字 C校验错误， 并记录该码字 C对应的错误标记的值为 错误。
9、 如权利要求 8所述的装置， 其中， 所述解字节交织模块是设置成按照 以下方式将 LDPC码字的校验信息转换成 RS码字的删余信息：
将每一个 LDPC码字对应的错误标记重复 L次作为该 LDPC码字所对应 列的删余信息， 其中， 所述 L为 LDPC码字的信息位长度与交织器列长度的 比值， L为正整数。
10、 如权利要求 9所述的装置， 其中， 所述 RS译码模式选择模块设置 成按照以下方式完成 RS译码模式的选择：
如果所述 RS码字的待删余位置的个数在 RS纠删译码的可纠正范围内， 则选择纠删译码模式； 若所述待删余位置的个数不在所述可纠正范围内， 则 选择纠错译码模式。
11、 如权利要求 10所述的装置， 其中， RS码字的待删余位置的个数在 RS纠删译码的可纠正范围内是指： 所述待删余位置的个数小于等于 RS码字 的 RS校验位的个数。
12、 如权利要求 7所述的装置， 其中， 所述解字节交织模块是设置成按 照以下方式将 LDPC码字的信息位转换为字节的形式解交织输出： 将所述 LDPC码字按列顺序写入交织器， 按行顺序读出。
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