WO2011134390A1 - Ffs型tft-lcd阵列基板的制造方法 - Google Patents

Ffs型tft-lcd阵列基板的制造方法 Download PDF

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Publication number
WO2011134390A1
WO2011134390A1 PCT/CN2011/073336 CN2011073336W WO2011134390A1 WO 2011134390 A1 WO2011134390 A1 WO 2011134390A1 CN 2011073336 W CN2011073336 W CN 2011073336W WO 2011134390 A1 WO2011134390 A1 WO 2011134390A1
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WIPO (PCT)
Prior art keywords
photoresist
film
region
electrode
array substrate
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Ceased
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PCT/CN2011/073336
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English (en)
French (fr)
Inventor
宋泳錫
崔承镇
刘圣烈
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Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Priority to JP2013506472A priority Critical patent/JP5770831B2/ja
Priority to US13/499,353 priority patent/US8609477B2/en
Priority to EP11774381.5A priority patent/EP2565917B1/en
Priority to KR1020127003099A priority patent/KR101274628B1/ko
Publication of WO2011134390A1 publication Critical patent/WO2011134390A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • Embodiments of the present invention relate to a method of fabricating an FFS type TFT-LCD array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • FPD main flat panel display
  • the TFT-LCD is divided into a vertical electric field type and a horizontal electric field type.
  • the vertical electric field type TFT-LCD needs to form a pixel electrode on the array substrate to form a common electrode on the color filter substrate; however, the horizontal electric field type TFT-LCD needs to simultaneously form the pixel electrode and the common electrode on the array substrate. Therefore, when fabricating an array substrate of a horizontal electric field type TFT-LCD, it is necessary to additionally increase the patterning process for forming a common electrode with respect to the vertical electric field type TFT-LCD.
  • the vertical electric field type TFT-LCD includes: Twist Nematic (TN) type TFT-LCD;
  • the horizontal electric field type TFT-LCD includes: Fringe Field Switching (FFS) type TFT-LCD, In-Plane Switching (referred to as IPS) type TFT-LCD.
  • FFS Fringe Field Switching
  • IPS In-Plane Switching
  • the horizontal electric field type TFT-LCD, especially the FFS type TFT-LCD has the advantages of wide viewing angle and high aperture ratio, and is widely used in the field of liquid crystal displays.
  • the FFS type TFT-LCD array substrate is formed by forming a structural pattern by a plurality of patterning processes, and each of the patterning processes includes respectively exposing, developing, etching, and stripping the remaining photoresist by using a mask.
  • the etching process includes dry etching and wet etching.
  • the number of patterning processes can measure the complexity of fabricating a TFT-LCD array substrate, and reducing the number of patterning processes means a reduction in manufacturing cost.
  • the six-time patterning process of the prior art FFS type TFT-LCD array substrate includes: common electrode patterning, gate line and gate electrode patterning, active layer patterning, source/drain electrode patterning, via patterning, and pixel electrode patterning.
  • the existing four-time patterning process for manufacturing an array substrate of an FFS type liquid crystal display is as follows: Step 1. Depositing a first metal thin film, and forming a pattern of a gate line, a common electrode line, and a gate electrode by using a common mask by a first patterning process ; Step 2, depositing a gate insulating film, an active layer (semiconductor layer and a doped semiconductor layer) film, and forming a pattern of an active layer (ACTIVE) by using a common mask plate by a second patterning process;
  • Step 3 sequentially depositing a first transparent conductive film and a second metal film, and forming a pixel electrode, a source electrode, a drain electrode, and a TFT channel by using a double adjustment mask through a third patterning process;
  • Step 4 depositing a passivation layer and a second transparent conductive layer, forming a passivation layer, a connection hole (for connecting the common electrode and the common electrode line), and a PAD region connection hole by using a double adjustment mask through a fourth patterning process (The PAD area is a region where the lead of the driving circuit board and the array substrate are crimped, the lead wire is electrically connected to the gate line, the data line, and the common electrode line on the array substrate through the PAD area connection hole) and the pattern of the common electrode.
  • An embodiment of the present invention provides a method for fabricating an FFS type TFT-LCD array substrate, including: Step 1. sequentially forming a first transparent conductive film and a first metal film on a transparent substrate, and then pairing the first Forming a laminate of the transparent conductive film and the first metal film to form a pattern including a gate line, a gate electrode, a common electrode, and a common electrode line; Step 2, sequentially forming a gate insulating film, a semiconductor film, and a doped semiconductor film, Patterning a gate insulating film, a semiconductor film, and a doped semiconductor film to form a gate line connecting hole including a PAD region and a pattern of the semiconductor layer; Step 3, forming a second metal film, and patterning the second metal film Forming a second transparent conductive film, performing a ground lift-off process to remove the second transparent conductive film on the photoresist, and etching the exposed second metal film and the doped semiconductor film to form a source electrode, a drain electrode, The pattern of the
  • Step 100 sequentially forming a first transparent conductive film and a first metal film on a transparent substrate, Forming a stack of a transparent conductive film and a first metal film to form a pattern including a gate line, a gate electrode, a pixel electrode, and a common electrode line;
  • Step 200 sequentially forming a gate insulating film, a semiconductor film, and a doped semiconductor film, Forming a stack of the gate insulating film, the semiconductor film, and the doped semiconductor film to form a pattern including a via hole, a gate connection hole of the PAD region, and a semiconductor layer;
  • Step 300 depositing a second metal film, for the second The metal film is patterned, and then a second transparent conductive film is deposited, and a ground stripping process is performed to remove the second transparent conductive film on the photoresist, and then the exposed second metal film and the doped semiconductor film are etched.
  • 1A is a schematic plan view of an FFS type TFT-LCD array substrate
  • Figure 1B is a cross-sectional view taken along line A-A of Figure 1A;
  • Embodiment 1 is a flow chart showing Embodiment 1 of a method for manufacturing an FFS type TFT-LCD array substrate according to the present invention
  • FIG. 3A-3C are cross-sectional views showing a first transparent conductive film and a first metal thin film deposited on a transparent substrate, wherein FIG. 3A is a cross-sectional view of a pixel region, and FIG. 3B is a cross-sectional view of a gate line of the PAD region.
  • Figure 3C is a cross-sectional view of the data line of the PAD region;
  • FIGS. 4A to 4C are cross-sectional views after exposure and development processing after applying a photoresist on the structure of Figs. 3A to 3C;
  • FIGS. 5A-5C are cross-sectional views showing the structure of FIGS. 4A-4C after the first etching process
  • FIGS. 6A-6C are cross-sectional views of the photoresist of FIG. 5A to FIG. 5C after the ashing process
  • 7A-7C are cross-sectional views of the structure of FIGS. 6A-6C after a second etching process
  • FIGS. 8A-8C are cross-sectional views of the photoresist of FIGS. 7A-7C after peeling off;
  • FIGS. 8A-8C are cross-sectional views showing the deposition of a gate insulating film, a semiconductor film, and a doped semiconductor film on the structures of FIGS. 8A-8C;
  • FIGS. 10A-10C are cross-sectional views after exposure and development processing after applying a photoresist on the structure of Figs. 9A to 9C;
  • FIGS. 10A-10C are cross-sectional views showing the structure of FIGS. 10A-10C after a third etching process
  • FIGS. 12A to 12C are cross-sectional views showing the photoresist of Figs. 11A to 11C after ashing; and Figs. 13A to 13C are cross sections after the fourth etching process is performed on the structures of Figs. 12A to 12C.
  • FIGS. 14A to 14C are cross-sectional views after peeling off the photoresist of Figs. 13A to 13C;
  • FIGS. 15A to 15C are cross-sectional views showing a structure in which a second metal thin film is deposited on the structure of Figs. 14A to 14C; and Figs. 16A to 16C are a photoresist coated on the structure of Figs. 15A to 15C and exposed and a cross-sectional view after development processing;
  • 17A-17C are cross-sectional views after the fifth etching process is performed on the structures of FIGS. 16A-16C.
  • FIGS. 18A to FIG. 18C are cross-sectional views showing the photoresist of FIGS. 17A to 17C after ashing;
  • FIG. 19A to FIG. 19C are cross-sectional views showing the second transparent conductive film deposited on the structure of FIGS. 18A to 18C;
  • 20A to 20C are cross-sectional views showing the structure of Figs. 19A to 19C after lift off;
  • 21A-21C are cross-sectional views showing the sixth and seventh etching processes of the structures of Figs. 20A to 20C;
  • Figure 22 is a flow chart showing the second embodiment of the method for fabricating the FFS type TFT-LCD array substrate of the present invention.
  • FIG. 23A-23C are cross-sectional views showing a first transparent conductive film and a first metal thin film deposited on a transparent substrate, wherein FIG. 23A shows a cross-sectional view of a pixel region, and FIG. 23B shows a cross section of a gate line of the PAD region.
  • Figure 23C is a cross-sectional view of the data line of the PAD region;
  • 24A to 24C are cross-sectional views after exposure and development processing after applying a photoresist on the structure of Figs. 23A to 23C;
  • 25A-25C are cross-sectional views showing the structure of Figs. 24A to 24C after the first etching process
  • FIGS. 26A to FIG. 26C are cross-sectional views showing the photoresist of FIGS. 25A to 25C after the ashing process; and FIGS. 27A to 27C are diagrams showing the second etching process of the structures of FIGS. 26A to 26C. Sectional view
  • 28A to 28C are cross-sectional views after peeling off the photoresist of Figs. 27A to 27C;
  • 29A to 29C are cross-sectional views showing the deposition of a gate insulating film, a semiconductor film, and a doped semiconductor film on the structures of Figs. 28A to 28C;
  • FIGS. 29A to 29C are cross-sectional views after exposure and development processing after applying a photoresist on the structure of Figs. 29A to 29C;
  • 31A to 31C are cross-sectional views showing the structure of Figs. 30A to 30C after the third etching process;
  • FIGS. 32A to 32C are cross-sectional views showing the photoresist of FIGS. 31A to 31C after the ashing process; and FIGS. 33A to 33C are cross sections after the fourth etching process is performed on the structures of FIGS. 32A to 312C.
  • Figure 34A-34C are cross-sectional views after the photoresist of FIGS. 33A-33C is peeled off;
  • 35A to 35C are cross-sectional views showing a structure in which a second metal thin film is deposited on the structure of Figs. 34A to 34C; and Figs. 36A to 36C are a photoresist coated on the structure of Figs. 35A to 35C and exposed. a cross-sectional view after development processing;
  • FIGS. 36A to 36C are cross-sectional views showing the fifth etching process performed on the structures of Figs. 36A to 36C;
  • FIGS. 38A-38C are cross-sectional views of the photoresist of FIGS. 37A-37C after the ashing process;
  • FIGS. 39A-39C are cross-sectional views of the structure of FIGS. 38A-38C after depositing a second transparent conductive film;
  • 40A to 40C are cross-sectional views showing the structure of Figs. 39A to 39C after lift off;
  • 41A to 41C are cross-sectional views showing the sixth and seventh etching processes of the structures of Figs. 40A to 40C. detailed description
  • Figure 1A is a plan view of a conventional FFS type TFT-LCD array substrate.
  • Fig. 1B is a cross-sectional view taken along line A-A of Fig. 1.
  • an FFS type TFT-LCD array substrate (Array Substrate) includes: a gate line 1, a data line 2, a thin film transistor (Thin Firm Transistor), a pixel electrode 4, and a common electrode 6. And a common electrode line 5.
  • the gate line 1 is laterally disposed on the transparent substrate 10, and the data line 2 is longitudinally disposed on the transparent substrate 10, and the intersection of the gate line 1 and the data line 2 is disposed TFT3.
  • TFT3 is an active switching element.
  • the pixel electrode 4 is a plate electrode, and the common electrode 6 is a slit electrode.
  • the common electrode 6 is located above and overlaps the pixel electrode 4, and forms an electric field for driving the liquid crystal with the pixel electrode 4.
  • the common electrode line 5 and the common electrode 6 are connected by a connection hole.
  • the reference numeral "4" refers to a slit which is not a long strip, but a plate-like pixel electrode below the slit.
  • the FFS type TFT-LCD array substrate further includes: a transparent substrate 10, a pixel electrode 4, a common electrode 6, a gate electrode 11, a gate insulating layer 12, an active layer (including a semiconductor layer 13 and a doped semiconductor) The layer 14), the first transparent conductive portion 15, the source electrode 16, the drain electrode 17, the TFT channel 18, and the passivation layer 19.
  • the gate electrode 11 is integrally formed with the gate line 1, the source electrode 16 and the data line 2 are integrally formed, and the drain electrode 17 is directly connected to the pixel electrode 4.
  • the active layer becomes conductive, and the data signal on the data line 2 can pass from the source electrode 16 through the TFT channel 18 to the drain electrode 17, and finally to the pixel electrode 4.
  • the pixel electrode 4 obtains a signal and forms an electric field for driving the liquid crystal to rotate with the common electrode 6. Since the common electrode 6 has a slit, the electric field formed with the pixel electrode 4 is a horizontal electric field.
  • a transparent conductive portion 15 (a portion remaining when the transparent conductive film is formed to form a pixel electrode) deposited by the pixel electrode.
  • the pixel electrode is formed by ITO or IZO, but this material is less conductive than metal, thus hindering the transmission of signals from the source electrode to the active layer, affecting the response time of the liquid crystal display, and displaying the quality of the liquid crystal display. Influential.
  • Fig. 2 is a flow chart showing the first embodiment of the method of manufacturing the FFS type TFT-LCD array substrate of the present invention.
  • a method for manufacturing an FFS type TFT-LCD array substrate according to a first embodiment of the present invention includes:
  • Step 1 Form a first transparent conductive film and a first metal film on the transparent substrate, and then pattern the first transparent conductive film and the first metal film to form a gate line, a gate electrode, and a common electrode. And a pattern of common electrode lines;
  • Step 2 sequentially forming a gate insulating film, a semiconductor film, and a doped semiconductor film, and then patterning the gate insulating film, the semiconductor film, and the doped semiconductor film layer to form a gate connection hole including the PAD region and a pattern of the semiconductor layer;
  • Step 3 forming a second metal film, patterning the second metal film, and then forming a second transparent conductive film, performing a ground stripping process to remove the second transparent conductive film on the photoresist, and then etching the exposed
  • the second metal film and the semiconductor film are formed to include a source electrode, a drain electrode, The pattern of the TFT channel and the pixel electrode.
  • the FFS type TFT-LCD array substrate is manufactured by the three-time patterning process, the number of processes is reduced, the cost is greatly saved, and the market competitiveness is improved.
  • the FFS type TFT-LCD array substrate embodiment of the present invention will be described in detail below with reference to FIG. 3A to FIG. 21C.
  • the first patterning process of Embodiment 1 of the method of manufacturing the FFS type TFT-LCD array substrate of the present invention will be described in detail based on Figs. 3A to 8C.
  • the first patterning process includes the following steps.
  • Step 11 The first transparent conductive film 100 and the first metal thin film 200 are sequentially deposited on the transparent substrate 10, as shown in Figs. 3A to 3C.
  • the first transparent conductive film 100 and the first metal film may be sequentially deposited on the transparent substrate 10 (such as a glass substrate or a quartz substrate) by plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods. 200.
  • the first transparent conductive film 100 may be a transparent conductive material such as ruthenium or iridium.
  • the first metal thin film 200 may be a single-layer thin film formed of a metal such as molybdenum, aluminum, an aluminum-niobium alloy, tungsten, chromium, or copper, or may be a multilayer thin film formed by depositing the above metal layers.
  • Step 12 In the structure of FIG. 3A to FIG. 3C, the photoresist 1000 is first coated on the substrate, and the first halftone mask is used for exposure and development processing, as shown in FIG. 4A- The photoresist pattern shown in 4C.
  • the halftone mask can be classified into a complete light leakage region, a partial light leakage region, and a non-light leakage region depending on the degree of light transmission or intensity.
  • the photoresist 1000 forms a fully exposed region, a partially exposed region, and a non-exposed region, and then subjected to development processing, and the photoresist in the fully exposed region is washed away by the agent; In the photoresist of the exposed region, the upper layer is exposed and washed away, leaving the underlying photoresist, whereby the thickness of the photoresist layer is lowered; the thickness of the photoresist in the unexposed regions remains unchanged.
  • the non-exposed areas correspond to the areas of the gate lines, the gate electrodes, and the common electrode lines of the array substrate, and the partially exposed areas correspond to the common electrode areas of the array substrate, and the fully exposed areas correspond to the remaining areas.
  • Step 13 On the structure of FIGS. 4A-4C, a first etching process is performed to form a pattern including the gate line 1, the gate electrode 11, the common electrode 6, and the common electrode line (not shown), as shown in FIG. 5A. - Figure 5C.
  • the first etching process includes a two-step etching.
  • the first step is to etch the first metal thin film 200 with a metal material etching solution (for example, a mixture of phosphoric acid and nitric acid) to obtain a pattern of the gate line 1, the gate electrode 11, and the common electrode line (not shown).
  • a metal material etching solution for example, a mixture of phosphoric acid and nitric acid
  • wet etching of large area graphics The etch is to put the etched material into the etchant, so that the etchant etches away the exposed etched material.
  • the metal material etching solution can only etch away the metal, that is, the first metal film, and therefore, the region covered by the photoresist, that is, the first metal film of the partially exposed region and the non-exposed region is not corroded. Only the first metal thin film 200 in the completely exposed region is etched away by direct contact with the etching liquid, and the remaining first metal thin film forms a pattern of the gate line, the gate electrode, and the common electrode line.
  • the second step is to remove the first transparent conductive film 100 by using an etching solution of ITO or IZO, to form a pattern of the common electrode 6, and to avoid forming the gate line, the gate electrode and the common electrode line through the first transparent conductive film 100. Sexual connection.
  • Step 14 The photoresist 1000 of FIGS. 5A-5C is subjected to an ashing process to expose the first metal film 200 of the partially exposed region, as shown in FIGS. 6A-6C.
  • the role of the ashing process is to remove a certain thickness of photoresist.
  • the thickness of the photoresist removed is the same as the thickness of the exposed portion of the photoresist in step 12, that is, after the ashing process, the photoresist remains only in the unexposed areas, and no photoresist remains in other areas.
  • Step 15 A second etching process is performed on the structures of Figs. 6A - 6C, and the first metal film 200 exposed in the step 14 is removed, as shown in Figs. 7A - 7C. The second metal film 200 above the common electrode 6 is removed, and the common electrode 6 is exposed.
  • Step 16 Remove the remaining photoresist 1000 in the structure of Figures 7A-7C, as shown in Figures 8A-8C.
  • the first patterning process is completed through steps 11-16.
  • the second patterning process includes the following steps.
  • Step 21 sequentially depositing a gate insulating film 300, a semiconductor film on the structures of FIGS. 8A-8C
  • Step 22 In the structure of FIG. 9A to FIG. 9C, the photoresist 2000 is first coated, and the second halftone mask is used for exposure and development processing to obtain a photoresist as shown in FIGS. 10A-10C. pattern.
  • the unexposed area corresponds to the area of the TFT channel
  • the fully exposed area corresponds to the area of the gate line of the PAD area of the array substrate
  • the partially exposed area corresponds to the remaining area.
  • the PAD region is a crimping region, and is a region in which a signal line such as a gate line, a data line, and a common electrode line on the array substrate to be formed is crimped to a lead of an external driving circuit board, and includes a gate line of the PAD region, The data line of the PAD area and the common electrode line of the PAD area.
  • the PAD region is located on one of the four sides of the array substrate or on two adjacent sides. In order to electrically connect the leads and the signal lines, the signal lines above the PAD area must be covered with no insulating layer, usually by etching the connection holes above the signal lines. The signal line is exposed or the signal line is connected to the conductive element.
  • Step 23 performing a third etching process on the structure of FIGS. 10A-10C, removing the doped semiconductor film 500, the semiconductor film 400, and the gate insulating film 300 in the fully exposed region of the photoresist 2000, exposing the gate of the PAD region.
  • Line 1 forms a pattern of the PAD region gate line connection holes and the gate insulating layer 12, as shown in FIGS. 11A-11C.
  • the third etching process includes a three-step etching. In the first step, the exposed doped semiconductor film 500 is removed, the second step removes the exposed semiconductor film 400, and the third step removes the exposed gate insulating film 300 to form a pattern of the gate insulating layer 12.
  • the reagents and methods used in the etching process can be conventional methods in the art, and a detailed description thereof will be omitted.
  • Step 24 In order to etch the photoresist 2000 of FIGS. 11A to 11C, the doped semiconductor film 500 of the partially exposed region is exposed, as shown in FIGS. 12A to 12C.
  • the gray chemical removes the thickness of the partially exposed region corresponding to the photoresist 2000 in step 22, so that the doped semiconductor film 500 of the exposed portion is exposed, and the photoresist remains in the unexposed region.
  • Step 25 performing a fourth etching process on the structure of FIGS. 12A to 12C, removing the doped semiconductor film 500, the semiconductor film 400, and the gate insulating film 300 of the partially exposed regions, forming a pattern including the semiconductor layer 13, as shown in 13A - Figure 13C.
  • Step 26 The remaining photoresist 2000 in FIGS. 13A- 13C is peeled off, as shown in FIGS. 14A-14C.
  • the second patterning process is completed by steps 21-26.
  • the third patterning process includes the following steps.
  • Step 31 A second metal film 600 is deposited on the structure of Figs. 14A - 14C, as shown in Figs. 15A - 15C.
  • Step 32 On the structure of FIG. 15A to FIG. 15C, the photoresist 3000 is first coated, and the third halftone mask is used for exposure and development processing to obtain a photoresist as shown in FIGS. 16A to 16C. pattern.
  • the fully exposed area corresponds to the area of the pixel electrode 4 (see FIG. 1) of the array substrate
  • the partially exposed area corresponds to the source electrode 16 (see FIG. 1B), the drain electrode 17 and the gate line 1, PAD of the PAD area.
  • the data line 2 of the area (see Fig. 1A) and the area of the common electrode line of the PAD area, the unexposed areas correspond to the remaining areas.
  • Step 33 A fifth etching process is performed on the structure of Figs. 16A to 16C to remove the second metal thin film 600 of the completely exposed region, as shown in Figs. 17A to 17C.
  • Step 34 The ashing process of the photoresist 3000 of FIGS. 17A-17C is performed, and the part is exposed.
  • the second metal film 600 of the exposed region is as shown in Figs. 18A to 18C.
  • the ashing process removes the thickness of the partially exposed region corresponding to the photoresist 3000 in the step 32, so that the second metal film 600 of the partially exposed region is exposed, and the photoresist layer remains in the unexposed region.
  • Step 35 A second transparent conductive film 700 is deposited on the structure of Figs. 18A - 18C, as shown in Figs. 19A - 19C.
  • Step 36 Lifting off the structure of FIGS. 19A to 19C, and removing the second transparent conductive film on the photoresist while stripping the photoresist, forming the pixel electrode 4 Graphic, as shown in Figures 20A-20C.
  • Step 37 A sixth etching process is performed on the structures of FIGS. 20A-20C, and the exposed second metal film 600 and the doped semiconductor film 500 are removed, and the TFT channel 18, the source electrode 16, and the drain electrode are formed.
  • Figure 17 is shown in Figures 21A-21C.
  • the sixth etching process includes two-step etching. First, in the first step, the metal material etching solution is used to remove the second metal film 600 not covered by the second transparent conductive film 700, and the source electrode 16 and the drain electrode 17 are formed; Etching, the exposed doped semiconductor film 500 is etched using a gas etchant to form a pattern of the TFT channel 18.
  • steps 31 - 37 of the third patterning process of the embodiment of the present invention that the second metal film is deposited first, and then the second transparent conductive layer is deposited, that is, the source electrode and the drain electrode are formed on the TFT channel.
  • a pixel electrode is formed on the drain electrode. Therefore, no transparent conductive portion is formed between the source electrode and the active layer (doped semiconductor layer and the semiconductor layer), so that the signal from the data line can directly enter the TFT channel through the source electrode without being hindered by the transparent conductive portion.
  • Fig. 22 is a flow chart showing the second embodiment of the method of manufacturing the FFS type TFT-LCD array substrate of the present invention.
  • a method for manufacturing an FFS type TFT-LCD array substrate according to an embodiment of the present invention includes:
  • Step 100 sequentially forming a first transparent conductive film and a first metal film on the transparent substrate, and then patterning the first transparent conductive film and the first metal film stack to form a gate line, a gate electrode, and a pixel electrode. And a pattern of common electrode lines;
  • Step 200 sequentially forming a gate insulating film, a semiconductor film, and a doped semiconductor film, patterning the stack of the gate insulating film, the semiconductor film, and the doped semiconductor film, forming a gate connection hole including a via, a PAD region, and a semiconductor Layer graphics Step 300, depositing a second metal film, patterning the second metal film, and then depositing a second transparent conductive film, performing a ground stripping process to remove the second transparent conductive film on the photoresist, and then etching the exposed
  • the second metal film and the doped semiconductor film form a pattern including a source electrode, a drain electrode, a TFT channel, and a common electrode.
  • the FFS type TFT-LCD array substrate is manufactured by the three-time patterning process, thereby reducing the number of processes, greatly saving the cost, and improving the market competitiveness. .
  • the first patterning process of Embodiment 2 of the method of manufacturing the FFS type TFT-LCD array substrate of the present invention will be described in detail based on Figs. 23A to 28C.
  • the first patterning process includes the following steps.
  • Step 1100 sequentially depositing a first transparent conductive film 100 and a first metal film 200 on the transparent substrate 10, as shown in FIG. 23A-FIG. 23C.
  • the first transparent conductive film 100 and the first metal film may be sequentially deposited on the transparent substrate 10 (such as a glass substrate or a quartz substrate) by plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods. 200.
  • the first transparent conductive film 100 may be ruthenium, iridium or the like.
  • the first metal thin film 200 may be a single-layer thin film formed of a metal such as molybdenum, aluminum, aluminum bismuth alloy, tungsten, chromium, copper or the like, or may be a multilayer thin film formed by depositing the above metal layers.
  • Step 1200 In the structure of FIG. 23A to FIG. 23C, the photoresist 1000 is first coated, and the first halftone mask is used for exposure and development processing to obtain light as shown in FIGS. 24A to 24C. Engraved pattern.
  • the halftone mask can be classified into a complete light leakage region, a partial light leakage region, and a non-light leakage region depending on the degree of light transmission or intensity. Therefore, after exposure processing by the first halftone mask, the photoresist 1000 forms a fully exposed region, a partially exposed region, and a non-exposed region.
  • the photoresist in the fully exposed region is washed away by the agent; in the photoresist in the partially exposed region, the upper layer is exposed and washed away, leaving the underlying photoresist, thereby reducing the thickness of the photoresist layer; The thickness of the photoresist in the exposed area remains unchanged.
  • the non-exposed areas correspond to the areas of the gate lines, the gate electrodes, and the common electrode lines of the array substrate, and the partially exposed areas correspond to the pixel electrode areas of the array substrate, and the fully exposed areas correspond to the remaining areas.
  • the positions of the formed pixel electrodes and the common electrodes are interchanged.
  • Step 1300 On the structure of FIGS. 24A to 24C, a first etching process is performed to form a pattern including the gate line 1, the gate electrode 11, the pixel electrode 4, and the common electrode line, as shown in FIGS. 25A to 25C.
  • the first etching process actually includes a two-step etching.
  • the first step is to etch the first metal thin film 200 with a metal material etching solution (for example, a mixture of phosphoric acid and nitric acid) to obtain a pattern of the gate line 1, the gate electrode 11, and the common electrode line (not shown).
  • a metal material etching solution for example, a mixture of phosphoric acid and nitric acid
  • the wet etching for etching a large-area pattern is to put the object to be etched into the etching liquid, so that the etching liquid etches away the exposed object to be etched.
  • the metal material etching solution can only etch away the metal, that is, the first metal film, and therefore, the region covered by the photoresist, that is, the first metal film of the partially exposed region and the non-exposed region is not corroded. Only the first metal thin film 200 of the completely exposed region is etched away by direct contact with the etching liquid, and the remaining first metal thin film 200 forms a pattern of the gate line 1, the gate electrode 11, and the common electrode line.
  • the second step is to remove the first transparent conductive film 100 by using an etching solution of ITO or IZO to form a pattern of the pixel electrode 4, and to prevent the formation of the gate line 1, the gate electrode 11 and the common electrode line from passing through the first transparent
  • the conductive film 100 is electrically connected.
  • Step 1400 The photoresist 1000 of FIGS. 25A to 25C is subjected to an ashing process to expose the first metal thin film 200 of the partially exposed region, as shown in FIGS. 26A to 26C.
  • the role of the ashing process is to remove a certain thickness of photoresist.
  • the thickness of the removed photoresist is the same as the thickness of the exposed portion of the photoresist in step 12, that is, after the ashing process, the photoresist is retained only in the non-exposed areas, and no photoresist remains in the other areas.
  • Step 1500 A second etching process is performed on the structures of Figs. 26A to 26C, and the first metal thin film 200 exposed in the step 14 is removed, as shown in Figs. 27A-27C.
  • the second metal thin film 200 above the pixel electrode 4 is removed, and the pixel electrode 4 is exposed.
  • Step 1600 The photoresist 1000 in the structure of Figs. 27A-27C is removed, as shown in Figs. 28A-28C.
  • the first patterning process is completed via steps 1100-1600.
  • Embodiment 2 of the method of manufacturing the FFS type TFT-LCD array substrate of the present invention will be described in detail with reference to Figs. 29A to 34C.
  • the second patterning process includes the following steps.
  • Step 2100 A gate insulating film 300, a semiconductor film 400, and a doped semiconductor film 500 are sequentially deposited on the structures of FIGS. 28A to 28C, as shown in FIGS. 29A to 29C.
  • Step 2200 On the structure of FIGS. 29A-29C, the photoresist 2000 is first coated, and the second halftone mask is used for exposure and development processing to obtain a photoresist pattern as shown in FIGS. 30A to 30C.
  • the unexposed area corresponds to the area of the TFT channel 18 (see FIG. 21A), and is completely exposed.
  • the light area corresponds to the via of the array substrate [the area for passing the connection line 4' (see FIG. 41A) so that the drain electrode is electrically connected to the pixel electrode] and the area of the gate line 1 of the PAD area, and the partial exposure area corresponds to the rest region.
  • Step 2300 Performing a third etching process on the structure of FIGS. 30A to 30C, removing the doped semiconductor film 500, the semiconductor film 400, and the gate insulating film 300 in the fully exposed region of the photoresist 2000, exposing part of the pixel electrode 4 and the gate line 1 of the PAD region form a pattern including the via hole, the PAD region gate line connection hole, and the gate insulating layer 12, as shown in FIGS. 31A to 31C.
  • the third etching process includes a three-step etching.
  • the exposed doped semiconductor film 500 is removed in the first step
  • the exposed semiconductor film 400 is removed in the second step
  • the exposed gate insulating film 300 is removed in the third step.
  • the reagents and methods used in the etching process can be carried out by a conventional method in the art, and a detailed description thereof will be omitted.
  • Step 2400 In order to etch the photoresist 2000 of FIGS. 31A-31C, the doped semiconductor film 500 of the partially exposed region is exposed, as shown in FIGS. 32A-32C. In this step, the ashing process removes the thickness of the partially exposed region corresponding to the photoresist 2000 in step 22, so that the doped semiconductor film 500 of the partially exposed region is exposed, and the photoresist in the unexposed region is partially retained.
  • Step 2500 performing a fourth etching process on the structure of FIGS. 32A-32C, removing the doped semiconductor film 500, the semiconductor film 400, and the gate insulating film 300 of the partially exposed regions, forming a pattern including the semiconductor layer 13, as shown in 33A- Figure 33C.
  • Step 2600 Stripping the photoresist 2000 of Figures 33A-33C, as shown in Figures 34A-34C.
  • the second patterning process is completed by steps 2100-2600.
  • the third patterning process includes the following steps.
  • Step 3100 depositing a second metal film 600 on the structure of Figs. 34A-34C, as shown in Figs. 35A-35C.
  • Step 3200 In the structure of FIGS. 35A-35C, the photoresist 3000 is first coated, and the third halftone mask is used for exposure and development processing to obtain a photoresist pattern as shown in FIGS. 36A to 36C.
  • the fully exposed region corresponds to the region of the common electrode 6 of the array substrate
  • the partially exposed region corresponds to the source electrode 16 (see FIG. 21A), the drain electrode 17 and the gate line 1 of the PAD region, and the data line 2 of the PAD region. (See FIG. 1A) and the area of the common electrode line of the PAD area, the unexposed area corresponding to the remaining area.
  • Step 3300 Perform a fifth etching process on the structure of FIGS. 36A-36C to remove the second metal film 600 of the fully exposed region, as shown in FIGS. 37A-37C.
  • Step 3400 The photoresist 3000 of FIGS. 37A-37C is subjected to an ashing process to expose the second metal film 600 of the partially exposed region, as shown in FIGS. 38A-38C.
  • the ashing process removes the thickness of the partially exposed region corresponding to the photoresist 3000 in step 32, so that the second metal film 600 of the partially exposed region is exposed, and the photoresist in the unexposed region is partially retained.
  • Step 3500 Depositing a second transparent conductive film 700 on the structure of Figs. 38A-38C, as shown in Figs. 39A-39C.
  • Step 3600 Lifting off the structure of FIGS. 39A-39C, forming a pattern for connecting the drain electrode and the pixel electrode connecting line 4' and the common electrode 6, as shown in FIG. 40A- 40C.
  • Step 3700 Performing a sixth etching process on the structures of FIGS. 40A-40C, removing the exposed second metal film 600 and the doped semiconductor film 500, forming the TFT channel 18, the source electrode 16, and the drain electrode Figure 17 is shown in Figure 41A-41C:.
  • the sixth etching process includes a two-step etching. First, in the first step, the second metal thin film 600 not covered by the second transparent conductive film 700 is removed by the etching solution of the metal material, and the source electrode 16 and the drain electrode 17 are formed; then, the second step is passed through the thousand steps. Etching, the exposed doped semiconductor film 500 is etched using a gas etchant to form a pattern of the TFT channel 18. Complete the third composition process through steps 3100-3700
  • the passivation layer is not formed, the material is reduced, and the array substrate is thinner and lighter.
  • the resulting liquid crystal display can achieve a predetermined rotation requirement of the liquid crystal material with less driving voltage.
  • the patterning or patterning process referred to herein includes photoresist coating, exposure of the photoresist using a mask, development of a photoresist pattern, etching using a photoresist pattern, and residual photoresist. Stripping and other processes.
  • the photoresist is exemplified by a positive photoresist. If a negative photoresist is used, the photoresist in the fully exposed region of the photoresist after development is completely retained, and the photoresist in the non-exposed region is completely removed, and the photolithography in the partially exposed region is performed. The glue is still partially retained.
  • the "area of a certain area” described in this article is the area where a certain figure is mapped on a transparent substrate, that is, This area has the same shape as a certain figure, for example, the area of the gate line, that is, the area where the pattern of the gate line is mapped on the transparent substrate, and can also be understood as the area on the transparent substrate where the gate line pattern is to be set.

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Description

FFS型 TFT-LCD阵列 的制造方法 技术领域
本发明的实施例涉及一种 FFS型 TFT-LCD阵列基板的制造方法。 背景技术
薄膜晶体管液晶显示装置 ( Thin Film Transistor Liquid Crystal Display, 简称 TFT-LCD )是一种主要的平板显示装置 （Flat Panel Display, 简称为 FPD ) 。
才艮据驱动液晶的电场方向， TFT-LCD分为垂直电场型和水平电场型。垂 直电场型 TFT-LCD需要在阵列基板上形成像素电极， 在彩膜基板上形成公 共电极； 然而， 水平电场型 TFT-LCD需要在阵列基板上同时形成像素电极 和公共电极。 因此， 制作水平电场型 TFT-LCD的阵列基板时， 相对于垂直 电场型 TFT-LCD, 需要额外增加一次形成公共电极的构图工艺。垂直电场型 TFT-LCD包括： 扭曲向列 （ Twist Nematic, 简称为 TN )型 TFT-LCD; 水平 电场型 TFT-LCD包括： 边缘电场切换（Fringe Field Switching, 简称为 FFS ) 型 TFT-LCD, 共平面切换（In-Plane Switching, 简称为 IPS )型 TFT-LCD。 水平电场型 TFT-LCD, 尤其是 FFS型 TFT-LCD, 具有广视角、 开口率高等 优点， 广泛应用于液晶显示器领域。
目前, FFS型 TFT-LCD阵列基板是通过多次构图工艺形成结构图形来完 成， 每一次构图工艺中又分别包括使用掩膜对光刻胶曝光、 显影、 刻蚀和剥 离剩余的光刻胶等工艺。 刻蚀工艺包括干法刻蚀和湿法刻蚀。 构图工艺的次 数可以衡量制造 TFT-LCD阵列基板的繁简程度， 减少构图工艺的次数就意 味着制造成本的降低。 现有技术的 FFS型 TFT-LCD阵列基板六次构图工艺 包括： 公共电极构图、 栅线和栅电极构图、 有源层构图、 源电极 /漏电极构 图、 过孔构图和像素电极构图。
现有的 4次构图工艺制造 FFS型液晶显示器的阵列基板的方法如下： 步骤 1、 沉积第一金属薄膜， 通过第一构图工艺利用普通掩膜板形成栅 线、 公共电极线和栅电极的图形； 步骤 2、 沉积栅绝缘薄膜、 有源层 （半导体层和掺杂半导体层） 薄膜， 通过第二构图工艺利用普通掩膜板形成有源层（ACTIVE ) 的图形；
步骤 3、 依次沉积第一透明导电薄膜和第二金属薄膜， 通过第三次构图 工艺利用双调掩膜板形成像素电极、 源电极、 漏电极及 TFT沟道；
步骤 4、 沉积钝化层及第二透明导电层， 通过第四次构图工艺利用双调 掩膜板形成钝化层、 连接孔（用于将公共电极与公共电极线连接） 、 PAD区 域连接孔（ PAD区域为将驱动电路板的引线和阵列基板进行压接的区域， 通 过 PAD 区域连接孔将引线与阵列基板上的栅线、 数据线及公共电极线等电 连接） 以及公共电极的图形。 发明内容
本发明的一个实施例提供了一种 FFS型 TFT-LCD阵列基板的制造方法， 包括： 步骤 1、 在透明基板上依次形成第一透明导电薄膜及第一金属薄膜， 然后对对所述第一透明导电薄膜及第一金属薄膜的叠层进行构图， 形成包括 栅线、 栅电极、 公共电极以及公共电极线的图形； 步骤 2、 依次形成栅绝缘 薄膜、 半导体薄膜及掺杂半导体薄膜， 对对栅绝缘薄膜、 半导体薄膜及掺杂 半导体薄膜的叠层进行构图， 形成包括 PAD 区域的栅线连接孔以及半导体 层的图形； 步骤 3、 形成第二金属薄膜， 对所述第二金属薄膜进行构图， 然 后形成第二透明导电薄膜， 进行离地剥离工艺以除去光刻胶上的第二透明导 电薄膜， 并刻蚀暴露的第二金属薄膜及掺杂半导体薄膜， 形成包括源电极、 漏电极、 TFT沟道以及像素电极的图形。
本发明的另一个实施例提供了一种一种 FFS型 TFT-LCD阵列基板的制 造方法， 包括： 步骤 100、 在透明基板上依次形成第一透明导电薄膜及第一 金属薄膜， 对所述第一透明导电薄膜及第一金属薄膜的叠层进行构图， 形成 包括栅线、 栅电极、 像素电极以及公共电极线的图形； 步骤 200、 依次形成 栅绝缘薄膜、 半导体薄膜及掺杂半导体薄膜， 对所述栅绝缘薄膜、 半导体薄 膜及掺杂半导体薄膜的叠层进行构图， 形成包括过孔、 PAD区域的栅连接孔 以及半导体层的图形； 步骤 300、 沉积第二金属薄膜， 对所述第二金属薄膜 进行构图， 然后沉积第二透明导电薄膜， 进行离地剥离工艺以除去光刻胶上 的第二透明导电薄膜， 之后刻蚀暴露的第二金属薄膜及掺杂半导体薄膜， 形 成包括源电极、 漏电极、 TFT沟道以及公共电极的图形。 附图说明
图 1A为一种 FFS型 TFT-LCD阵列基板的平面示意图；
图 1B为图 1A的 A-A向剖面图；
图 2为本发明 FFS型 TFT-LCD阵列基板的制造方法的实施例 1的流程 图；
图 3A-图 3C为在透明基板上沉积第一透明导电薄膜及第一金属薄膜后 的剖面图， 其中图 3A所示为像素区域的截面图， 图 3B所示为 PAD区域的 栅线的截面图 , 图 3C所示为 PAD区域的数据线的截面图；
图 4A-图 4C为在图 3A-图 3C的结构上涂覆光刻胶后进行了曝光和显影 处理后的剖面图；
图 5A-图 5C为对图 4A-图 4C的结构进行了第一刻蚀工艺后的剖面图； 图 6A-图 6C为对图 5A-图 5C的光刻胶进行了灰化工艺后的剖面图； 图 7A-图 7C为对图 6A-图 6C的结构进行了第二刻蚀工艺后的剖面图； 图 8A-图 8C为剥离掉图 7A-图 7C的光刻胶后的剖面图；
图 9A-图 9C为在图 8A-图 8C的结构上沉积栅绝缘薄膜、 半导体薄膜及 掺杂半导体薄膜后的剖面图；
图 10A-图 10C为在图 9A-图 9C的结构上涂覆光刻胶后进行了曝光和显 影处理后的剖面图；
图 11A-图 11C为对图 10A-图 10C的结构进行了第三刻蚀工艺后的剖面 图；
图 12A-图 12C为对图 11A-图 11C的光刻胶进行了灰化工艺后的剖面图； 图 13A-图 13C为在图 12A-图 12C的结构进行了第四刻蚀工艺后的剖面 图；
图 14A-图 14C为剥离图 13A-图 13C的光刻胶后的剖面图；
图 15A-图 15C为对图 14A-图 14C的结构沉积第二金属薄膜后的剖面图； 图 16A-图 16C为在图 15A-图 15C的结构上涂覆了光刻胶并进行了曝光 和显影处理后的剖面图；
图 17A-图 17C为在图 16A-图 16C的结构上进行了第五刻蚀工艺后的剖 面图；
图 18A-图 18C对图 17A-图 17C的光刻胶进行了灰化工艺后的剖面图； 图 19A-图 19C为对图 18A-图 18C的结构沉积第二透明导电薄膜后的剖 面图；
图 20A-图 20C为对图 19A-图 19C的结构进行了离地剥离工艺 （ lift off ) 后的剖面图；
图 21A-图 21C为在图 20A-图 20C的结构进行了第六及第七刻蚀工艺后 的剖面图；
图 22为本发明 FFS型 TFT-LCD阵列基板的制造方法的实施例 2的流程 图；
图 23A-图 23C为在透明基板上沉积第一透明导电薄膜及第一金属薄膜 后的剖面图,其中图 23A所示为像素区域的截面图， 图 23B所示为 PAD区域 的栅线的截面图， 图 23C所示为 PAD区域的数据线的截面图；
图 24A-图 24C为在图 23A-图 23C的结构上涂覆光刻胶后进行了曝光和 显影处理后的剖面图；
图 25A-图 25C为对图 24A-图 24C的结构进行了第一刻蚀工艺后的剖面 图；
图 26A-图 26C为对图 25 A-图 25C的光刻胶进行了灰化工艺后的剖面图； 图 27A-图 27C为对图 26A-图 26C的结构进行了第二刻蚀工艺后的剖面 图；
图 28A-图 28C为剥离掉图 27 A-图 27C的光刻胶后的剖面图；
图 29A-图 29C为在图 28A-图 28C的结构上沉积栅绝缘薄膜、 半导体薄 膜及掺杂半导体薄膜后的剖面图；
图 30A-图 30C为在图 29A-图 29C的结构上涂覆光刻胶后进行了曝光和 显影处理后的剖面图；
图 31A-图 31C为对图 30A-图 30C的结构进行了第三刻蚀工艺后的剖面 图；
图 32A-图 32C为对图 31A-图 31C的光刻胶进行了灰化工艺后的剖面图； 图 33A-图 33C为在图 32A-图 312C的结构进行了第四刻蚀工艺后的剖面 图； 图 34A-图 34C为剥离图 33A-图 33C的光刻胶后的剖面图；
图 35A-图 35C为对图 34A-图 34C的结构沉积第二金属薄膜后的剖面图； 图 36A-图 36C为在图 35A-图 35C的结构上涂覆了光刻胶并进行了曝光 和显影处理后的剖面图；
图 37A-图 37C为在图 36A-图 36C的结构上进行了第五刻蚀工艺后的剖 面图；
图 38A-图 38C对图 37A-图 37C的光刻胶进行了灰化工艺后的剖面图； 图 39A-图 39C为对图 38A-图 38C的结构沉积第二透明导电薄膜后的剖 面图；
图 40A-图 40C为对图 39A-图 39C的结构进行了离地剥离工艺 （lift off ) 后的剖面图；
图 41A-图 41C为在图 40A-图 40C的结构进行了第六及第七刻蚀工艺后 的剖面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是全部的实施例。 基于 本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
虽然， 现有的 4次构图的液晶显示器的阵列基板的制造方法中， 虽然仅 通过一次构图工艺就完成了像素电极、 源电极、 漏电极及 TFT沟道的图形， 节省了成本， 但是本发明的发明人在实践中发现， 这种现有的方法的到的会 导致液晶显示器的显示性能降低的缺陷。
下面结合附图 1A和图 1B详述此缺陷。 参阅图 1A、 图 1B， 图 1A为传 统 FFS型 TFT-LCD阵列基板的平面示意图。 图 1B为图 1的 A-A向剖面图。
如图 1A所示， 一种 FFS型 TFT-LCD阵列基板 ( Array Substrate ) 包括： 栅线 1、 数据线 2、 薄膜晶体管（Thin Firm Transistor, 筒称为 TFT ) 3、 像素 电极 4、 公共电极 6以及公共电极线 5。 栅线 1横向设置在透明基板 10上， 数据线 2纵向设置在透明基板 10之上， 栅线 1与数据线 2的交叉处设置有 TFT3。 TFT3为有源开关元件。 像素电极 4为板状电极， 公共电极 6为狭缝 电极。 公共电极 6位于像素电极 4的上方且与之重叠， 与像素电极 4形成用 于驱动液晶的电场。 公共电极线 5与公共电极 6通过连接孔连接。 图 1A中， 附图标记 "4" 所指并非是长条状的狭缝， 而是狭缝的下方的板状像素电极。
如图 1B所示， 该 FFS型 TFT-LCD阵列基板还包括： 透明基板 10、 像 素电极 4、 公共电极 6、 栅电极 11、 栅绝缘层 12、 有源层（包括半导体层 13 和掺杂半导体层 14 )、 第一透明导电部 15、 源电极 16、 漏电极 17、 TFT沟 道（channel ) 18 以及钝化层 19。 栅电极 11与栅线 1一体成型， 源电极 16 与数据线 2—体成型， 漏电极 17与像素电极 4直接连接。 当栅线 1中输入导 通信号时， 有源层变得导电， 数据线 2上的数据信号可从源电极 16经 TFT 沟道 18到达漏电极 17 , 最终输入至像素电极 4。像素电极 4得到信号后与公 共电极 6形成用于驱动液晶转动的电场。 由于公共电极 6具有狭缝， 因此与 像素电极 4形成的电场为水平电场。
从图 1B可知， 在源电极 16与有源层之间， 具有形成像素电极所沉积的 透明导电部 15 (刻蚀透明导电薄膜形成像素电极时所残留的部分）。 液晶显 示器领域中，像素电极采用 ITO或 IZO形成，但是这种材料比金属导电性差， 因此会阻碍信号从源电极传输至有源层中， 影响液晶显示器的响应时间， 对 液晶显示器的显示品质照成影响。
图 2为本发明 FFS型 TFT-LCD阵列基板的制造方法的实施例 1的流程 图。 如图 2所示， 本发明实施 1的 FFS型 TFT-LCD阵列基板的制造方法， 包括：
步骤 1、 在透明基板上依次形成第一透明导电薄膜及第一金属薄膜， 然 后对所述第一透明导电薄膜及第一金属薄膜的叠层进行构图，形成包括栅线、 栅电极、 公共电极以及公共电极线的图形；
步骤 2、 依次形成栅绝缘薄膜、 半导体薄膜及掺杂半导体薄膜， 然后对 栅绝缘薄膜、 半导体薄膜及掺杂半导体薄膜的叠层进行构图， 形成包括 PAD 区域的栅连接孔以及半导体层的图形；
步骤 3、 形成第二金属薄膜， 对所述第二金属薄膜进行构图， 然后形成第 二透明导电薄膜， 进行离地剥离工艺以除去光刻胶上的第二透明导电薄膜， 之后刻蚀暴露的第二金属薄膜及捧杂半导体薄膜， 形成包括源电极、 漏电极、 TFT沟道以及像素电极的图形。
本发明上述实施例的 FFS型 TFT-LCD阵列基板的制造方法，通过 3次构 图工艺制造了 FFS型 TFT-LCD阵列基板，减少了工艺数，极大地节省了成本， 提高了市场竟争力。
下面结合图 3A-图 21C详细说明本发明 FFS型 TFT-LCD阵列基板实施例
1的一个示例。
首先， 根据图 3A-图 8C详细说明本发明 FFS型 TFT-LCD阵列基板的制 造方法的实施例 1的第一构图工艺。 该第一构图工艺包括如下步骤。
步骤 11 :在透明基板 10上依次沉积第一透明导电薄膜 100和第一金属薄 膜 200, 如图 3A-图 3C。
可采用等离子增强化学气相沉积（ PECVD )、 磁控溅射、 热蒸发或其它成 膜方法， 在透明基板 10 (如玻璃基板或石英基板）上依次沉积第一透明导电 薄膜 100和第一金属薄膜 200。 第一透明导电薄膜 100可以为 ΙΤΟ、 ΙΖΟ等透 明导电材料。 第一金属薄膜 200 可以是钼、 铝、 铝钕合金、 钨、 铬、 铜等金 属形成的单层薄膜， 也可以是以上金属多层沉积形成的多层薄膜。
步骤 12: 在图 3Α-图 3C的结构上， 先在基板上涂覆光刻胶 1000, 并采 用第一半色调掩膜板（half tone mask )进行曝光及显影处理， 得到如图 4A- 图 4C所示的光刻胶图案。 半色调掩膜板根据光的透过程度或强度， 可分为完 全漏光区域、 部分漏光区域及不漏光区域。 因此， 经第一半色调掩膜板进行 曝光处理后， 光刻胶 1000形成完全曝光区域、 部分曝光区域及不曝光区域， 然后经显影处理， 完全曝光区域的光刻胶被药剂洗去； 部分曝光区域的光刻 胶中， 上层被曝光而洗去， 留下下层光刻胶， 由此光刻胶层的厚度降低； 不 曝光区域的光刻胶厚度保持不变。 在光刻胶 1000中， 不曝光区域对应阵列基 板的栅线、 栅电极以及公共电极线的区域， 部分曝光区域对应阵列基板的公 共电极区域， 完全曝光区域对应其余区域。
步骤 13: 在图 4A-图 4C的结构上， 进行了第一刻蚀工艺， 形成了包括栅 线 1、 栅电极 11、 公共电极 6及公共电极线 (未图示)的图形， 如图 5A-图 5C。 第一刻蚀工艺包括两步骤的刻蚀。 第一步是采用金属材料刻蚀液（例如磷酸 和硝酸的混合物）对第一金属薄膜 200进行了刻蚀， 得到了栅线 1、 栅电极 11及公共电极线（未图示） 的图形。 实际生产中， 刻蚀大面积图形的湿法刻 蚀是将被刻蚀物投入刻蚀液中， 使得刻蚀液腐蚀掉暴露出的被刻蚀物。 金属 材料刻蚀液仅能刻蚀掉金属， 即第一金属薄膜， 因此， 被光刻胶覆盖的区域， 也就是部分曝光区域及不曝光区域的第一金属薄膜没有被腐蚀。 仅是完全曝 光区域的第一金属薄膜 200 , 由于直接与刻蚀液接触被腐蚀掉， 而残留的第一 金属薄膜形成栅线、 栅电极及公共电极线的图形。 第二步是用 ITO或 IZO的 刻蚀液， 去掉第一透明导电薄膜 100, 形成了公共电极 6的图形， 另外避免形 成的栅线、 栅电极及公共电极线通过第一透明导电薄膜 100电性连接。
步骤 14: 对图 5A-图 5C的光刻胶 1000进行灰化工艺， 暴露出了部分曝 光区域的第一金属薄膜 200, 如图 6A-图 6C。 灰化工艺的作用为去掉一定厚 度的光刻胶。 此步骤中， 去掉的光刻胶厚度与步骤 12中光刻胶部分曝光区域 的厚度相同， 即灰化工艺后， 光刻胶仅在不曝光区域还有保留， 其他区域无 光刻胶剩余。
步骤 15: 对图 6A-图 6C的结构进行了第二刻蚀工艺， 去掉了步骤 14中 暴露出的第一金属薄膜 200, 如图 7A-图 7C。 去掉了公共电极 6上方的第二 金属薄膜 200, 暴露出了公共电极 6。
步骤 16: 去掉图 7A-图 7C的结构中剩余的光刻胶 1000, 如图 8A-图 8C。 经步骤 11-16完成第一构图工艺。
下面根据图 9A-图 14C详细说明本发明 FFS型 TFT-LCD阵列基板的制造 方法的第二构图工艺。 该第二构图工艺包括如下步骤。
步 21： 在图 8A-图 8C的结构上依次沉积栅绝缘薄膜 300、 半导体薄膜
400及掺杂半导体薄膜 500， 如图 9A-图 9C。
步骤 22: 在图 9A-图 9C的结构上， 先涂覆光刻胶 2000， 并釆用第二半 色调掩膜板进行曝光及显影处理， 得到如图 10A-图 10C所示的光刻胶图案。 在光刻胶 2000中， 不曝光区域对应 TFT沟道的区域， 完全曝光区域对应阵列 基板的 PAD区域的栅线的区域， 部分曝光区域对应其余区域。 所谓 PAD区 域即为压接区域， 是将待形成的阵列基板上的栅线、 数据线及公共电极线等 信号线与外部的驱动电路板的引线压接的区域， 包括 PAD区域的栅线、 PAD 区域的数据线以及 PAD区域的公共电极线。 PAD区域位于阵列基板的四个边 中的其中一个或相邻的两个边上。 为了将引线和信号线电连接， PAD 区域的 信号线上方必须没有绝缘层覆盖， 通常是在信号线上方刻蚀形成连接孔， 将 信号线暴露或将信号线与导电元件连接。
步骤 23：对图 10A-图 10C的结构进行了第三刻蚀工艺，去掉光刻胶 2000 完全曝光区域的掺杂半导体薄膜 500、半导体薄膜 400及栅绝缘薄膜 300,暴 露出了 PAD区域的栅线 1 , 形成了 PAD区域栅线连接孔及栅绝缘层 12的图 形， 如图 11A-图 11C。 第三刻蚀工艺包括三步骤刻蚀。 第一步去掉了暴露出 的掺杂半导体薄膜 500, 第二步去掉了暴露出的半导体薄膜 400,第三步去掉 了暴露出的栅绝缘薄膜 300, 形成了栅绝缘层 12的图形。 刻蚀工艺所采用的 试剂及方法可为本领域常规方法， 故省略对其的详细描述。
步骤 24: 为对图 11A-图 11C的光刻胶 2000进行了灰化工艺， 暴露出了 部分曝光区域的掺杂半导体薄膜 500, 如图 12A-图 12C。 本步骤中， 灰化工 艺去掉相当于步骤 22中光刻胶 2000的部分曝光区域的厚度， 使得暴露出部 分曝光区域的掺杂半导体薄膜 500, 而不曝光区中还保留有光刻胶。
步骤 25: 在图 12A-图 12C的结构进行第四刻蚀工艺， 去掉了部分曝光 区域的掺杂半导体薄膜 500、半导体薄膜 400及栅绝缘薄膜 300,形成了包括 半导体层 13的图形， 如图 13A-图 13C。
步骤 26: 剥离图 13A-图 13C中剩余的光刻胶 2000, 如图 14A-图 14C。 通过步骤 21-26， 完成了第二构图工艺。
下面根据图 15A-图 21C详细说明本发明 FFS型 TFT-LCD阵列基板的制 造方法的实施例 1的第三构图工艺。 该第三构图工艺包括如下步骤。
步 31： 在图 14A-图 14C的结构上沉积第二金属薄膜 600, 如图 15A- 图 15C。
步骤 32: 在图 15A-图 15C的结构上， 先涂覆光刻胶 3000， 并釆用第三 半色调掩膜板进行曝光及显影处理， 得到如图 16A-图 16C所示的光刻胶图 案。 在光刻胶 3000中， 完全曝光区域对应阵列基板的像素电极 4 (参见图 1 ) 的区域， 部分曝光区域对应源电极 16 (参见图 1B )、 漏电极 17及 PAD区域 的栅线 1、 PAD区域的数据线 2 (参见图 1A ) 以及 PAD区域的公共电极线 的区域， 不曝光区域对应其余区域。
步骤 33: 对图 16A-图 16C的结构进行第五刻蚀工艺， 去掉完全曝光区 域的第二金属薄膜 600, 如图 17A-图 17C。
步骤 34: 对图 17A-图 17C的光刻胶 3000进行了灰化工艺， 暴露出了部 分曝光区域的第二金属薄膜 600, 如图 18A-图 18C。 本步骤中， 灰化工艺去 掉相当于步骤 32中光刻胶 3000的部分曝光区域的厚度， 使得暴露出部分曝 光区域的第二金属薄膜 600, 而不曝光区域中还保留有光刻胶层。
步骤 35:对图 18A-图 18C的结构沉积第二透明导电薄膜 700,如图 19A- 图 19C。
步骤 36: 对图 19A-图 19C的结构进行了离地剥离工艺 （lift off ), 在剥 离光刻胶的同时一并除去了光刻胶上的第二透明导电薄膜， 形成了像素电极 4的图形， 如图 20A-图 20C。
步骤 37: 在图 20A-图 20C的结构上进行了第六刻蚀工艺， 去掉了暴露 出的第二金属薄膜 600及掺杂半导体薄膜 500， 形成了 TFT沟道 18、 源电极 16和漏电极 17的图形， 如图 21A-图 21C。 本步骤中， 第六刻蚀工艺包括两 步骤刻蚀。 首先， 第一步骤中以金属材料刻蚀液， 去掉了没有被第二透明导 电薄膜 700覆盖的第二金属薄膜 600, 形成了源电极 16和漏电极 17; 然后， 第二步骤中通过千法刻蚀， 采用气体刻蚀剂对暴露出的掺杂半导体薄膜 500 进行刻蚀， 形成了 TFT沟道 18的图形。
从本发明实施例的第三构图工艺的步骤 31 -37可以看出， 本发明先沉积 了第二金属薄膜， 后沉积了第二透明导电层， 即 TFT沟道上形成了源电极和 漏电极， 像素电极形成于漏电极上。 因此， 没有在源电极和有源层 （摻杂半 导体层和半导体层）之间形成透明导电部， 所以从数据线的信号可以直接通 过源电极进入 TFT沟道， 不受透明导电部的阻碍， 提高了液晶显示器的显示 品质
图 22为本发明 FFS型 TFT-LCD阵列基板的制造方法的实施例 2的流程 图。 如图 22所示， 本发明实施例的 FFS型 TFT-LCD阵列基板的制造方法， 包括：
步骤 100、 在透明基板上依次形成第一透明导电薄膜及第一金属薄膜， 然后对所述第一透明导电薄膜及第一金属薄膜的叠层进行构图， 形成包括栅 线、 栅电极、 像素电极以及公共电极线的图形；
步骤 200、 依次形成栅绝缘薄膜、 半导体薄膜及掺杂半导体薄膜， 对所 述栅绝缘薄膜、 半导体薄膜及掺杂半导体薄膜的叠层进行构图， 形成包括过 孔、 PAD区域的栅连接孔以及半导体层的图形； 步骤 300、 沉积第二金属薄膜， 对所述第二金属薄膜进行构图， 然后沉积 第二透明导电薄膜， 进行离地剥离工艺以除去光刻胶上的第二透明导电薄膜， 之后刻蚀暴露的第二金属薄膜及摻杂半导体薄膜， 形成包括源电极、 漏电极、 TFT沟道以及公共电极的图形。
本发明实施例的 FFS型 TFT-LCD阵列基板的制造方法，通过 3次构图工 艺制造了 FFS型 TFT-LCD阵列基板，由此减少了工艺数，极大地节省了成本， 提高了市场竟争力。
下面结合图 23 A-图 41C详细说明本发明 FFS型 TFT-LCD阵列基板实施 例 2的一个示例的制造方法。
首先根据图 23 A-图 28C详细说明本发明 FFS型 TFT-LCD阵列基板的制 造方法的实施例 2的第一构图工艺。 该第一构图工艺包括如下步骤。
步骤 1100:在透明基板 10上依次沉积第一透明导电薄膜 100和第一金属 薄膜 200, 如图 23 A-图 23C„
可采用等离子增强化学气相沉积（PECVD )、 磁控溅射、 热蒸发或其它成 膜方法， 在透明基板 10 (如玻璃基板或石英基板）上依次沉积第一透明导电 薄膜 100和第一金属薄膜 200。 第一透明导电薄膜 100可以为 ΙΤΟ、 ΙΖΟ等。 第一金属薄膜 200 可以是钼、 铝、 铝钕合金、 钨、 铬、 铜等金属形成的单层 薄膜， 也可以是以上金属多层沉积形成的多层薄膜。
步驟 1200: 在图 23Α-图 23C的结构上， 先涂覆光刻胶 1000, 并采用第 一半色调掩膜板（ half tone mask )进行曝光及显影处理，得到如图 24A-图 24C 的光刻胶图案。 半色调掩膜板根据光的透过程度或强度， 可分为完全漏光区 域、 部分漏光区域及不漏光区域。 因此， 经第一半色调掩膜板进行曝光处理 后， 光刻胶 1000形成完全曝光区域、 部分曝光区域及不曝光区域。 经显影处 理， 完全曝光区域的光刻胶被药剂洗去； 部分曝光区域的光刻胶中， 上层被 曝光而洗去， 留下下层光刻胶， 由此光刻胶层的厚度降低； 不曝光区域的光 刻胶的厚度保持不变。 在光刻胶 1000中， 不曝光区域对应阵列基板的栅线、 栅电极以及公共电极线的区域， 部分曝光区域对应阵列基板的像素电极区域， 完全曝光区域对应其余区域。 在实施例 2与实施例 1相比， 所形成的像素电 极与公共电极的位置互换。 另外， 实施例 1 中狭缝设置在像素电极上， 而实 施例 2中， 狭缝设置在公共电极上。 步骤 1300: 在图 24A-图 24C的结构上， 进行了第一刻蚀工艺， 形成了包 括栅线 1、 栅电极 11、 像素电极 4及公共电极线的图形， 如图 25A-图 25C。 第一刻蚀工艺， 实际上包括两步骤刻蚀。 第一步是采用金属材料刻蚀液（例 如磷酸和硝酸的混合物 )对第一金属薄膜 200进行了刻蚀， 得到了栅线 1、 栅 电极 11及公共电极线（未图示）的图形。 刻蚀大面积图形的湿法刻蚀是将被 刻蚀物投入刻蚀液中， 使得刻蚀液腐蚀掉暴露出的被刻蚀物。 金属材料刻蚀 液仅能刻蚀掉金属， 即第一金属薄膜， 因此， 被光刻胶覆盖的区域， 也就是 部分曝光区域及不曝光区域的第一金属薄膜没有被腐蚀。 仅是完全曝光区域 的第一金属薄膜 200, 由于直接与刻蚀液接触被腐蚀掉， 残留的第一金属薄膜 200形成栅线 1、 栅电极 11及公共电极线的图形。 第二步是用 ITO或 IZO的 刻蚀液， 去掉第一透明导电薄膜 100 , 形成了像素电极 4的图形， 另外还能避 免形成的栅线 1、 栅电极 11及公共电极线通过第一透明导电薄膜 100电性连 接。
步骤 1400: 对图 25A-图 25C的光刻胶 1000进行灰化工艺， 暴露出了部 分曝光区域的第一金属薄膜 200, 如图 26A-图 26C。 灰化工艺的作用为去掉 一定厚度的光刻胶。 此步骤中， 去掉的光刻胶厚度与步骤 12中光刻胶部分曝 光区域的厚度相同， 即灰化工艺后， 光刻胶仅在不曝光区域有保留， 其他区 域无光刻胶剩余。
步骤 1500: 对图 26A-图 26C的结构进行了第二刻蚀工艺， 去掉了步骤 14中暴露出的第一金属薄膜 200, 如图 27A-图 27C。 去掉了像素电极 4上方 的第二金属薄膜 200， 暴露出了像素电极 4。
步骤 1600:去掉图 27 A-图 27C的结构中的光刻胶 1000，如图 28A-图 28C。 经步骤 1100-1600完成第一构图工艺。
下面根据图 29A-图 34C详细说明本发明 FFS型 TFT-LCD阵列基板的制 造方法的实施例 2的第二构图工艺。 该第二构图工艺包括如下步骤。
步骤 2100: 在图 28A-图 28C的结构上依次沉积栅绝缘薄膜 300、 半导体 薄膜 400及掺杂半导体薄膜 500， 如图 29A-图 29C。
步骤 2200: 在图 29A-图 29C的结构上， 先涂覆光刻胶 2000, 并采用第 二半色调掩膜板进行曝光及显影处理， 得到如图 30A-图 30C的光刻胶图案。 在光刻胶 2000中， 不曝光区域对应 TFT沟道 18(参见图 21A)的区域， 完全曝 光区域对应阵列基板的过孔 [用于使连接线 4' (参见图 41A ) 穿过， 使得漏电 极与像素电极电连接]的区域及 PAD区域的栅线 1的区域，部分曝光区域对应 其余区域。
步骤 2300: 对图 30A-图 30C的结构进行了第三刻蚀工艺， 去掉光刻胶 2000 完全曝光区域的掺杂半导体薄膜 500、 半导体薄膜 400 及栅绝缘薄膜 300, 暴露出了部分的像素电极 4和 PAD区域的栅线 1 , 形成了包括过孔、 PAD区域栅线连接孔及栅绝缘层 12的图形， 如图 31A-图 31C。 第三刻蚀工 艺包括三步骤刻蚀。 第一步去掉了暴露出的掺杂半导体薄膜 500, 第二步去 掉了暴露出的半导体薄膜 400,第三步去掉了暴露出的栅绝缘薄膜 300。刻蚀 工艺所采用的试剂及方法可采用本领域常规方法，故省略了对其的详细描述。
步骤 2400: 为对图 31 A-图 31C的光刻胶 2000进行了灰化工艺， 暴露出 了部分曝光区域的掺杂半导体薄膜 500, 如图 32A-图 32C。 本步骤中， 灰化 工艺去掉相当于步骤 22中光刻胶 2000的部分曝光区域的厚度， 使得暴露出 部分曝光区域的摻杂半导体薄膜 500, 而不曝光区域中的光刻胶得到部分保 留。
步骤 2500: 在图 32A-图 32C的结构进行第四刻蚀工艺， 去掉了部分曝 光区域的掺杂半导体薄膜 500、半导体薄膜 400及栅绝缘薄膜 300,形成了包 括半导体层 13的图形， 如图 33A-图 33C。
步骤 2600: 剥离图 33 A-图 33C的光刻胶 2000, 如图 34A-图 34C。
通过步骤 2100-2600, 完成了第二构图工艺。
下面根据图 35A-图 41C详细说明本发明 FFS型 TFT-LCD阵列基板的制 造方法的实施例 2的第三构图工艺。 该第三构图工艺包括如下步骤。
步骤 3100:在图 34A-图 34C的结构上沉积第二金属薄膜 600，如图 35A- 图 35C。
步骤 3200: 在图 35A-图 35C的结构上， 先涂覆光刻胶 3000， 并釆用第 三半色调掩膜板进行曝光及显影处理， 得到如图 36A-图 36C的光刻胶图案。 在光刻胶 3000中， 完全曝光区域对应阵列基板的公共电极 6的区域，部分曝 光区域对应源电极 16 (参见图 21A )、 漏电极 17及 PAD区域的栅线 1、 PAD 区域的数据线 2(参见图 1A)以及 PAD区域的公共电极线的区域，不曝光区域 对应其余区域。 步骤 3300: 对图 36A-图 36C的结构进行第五刻蚀工艺， 去掉完全曝光 区域的第二金属薄膜 600, 如图 37A-图 37C。
步骤 3400: 对图 37A-图 37C的光刻胶 3000进行了灰化工艺， 暴露出了 部分曝光区域的第二金属薄膜 600, 如图 38A-图 38C。 本步骤中， 灰化工艺 去掉相当于步骤 32中光刻胶 3000的部分曝光区域的厚度， 使得暴露出部分 曝光区域的第二金属薄膜 600 , 而不曝光区域中的光刻胶得到部分保留。
步骤 3500: 对图 38A-图 38C的结构沉积第二透明导电薄膜 700, 如图 39A-图 39C。
步骤 3600: 对图 39A-图 39C的结构进行了离地剥离工艺 （lift off ), 形 成了用于连接漏电极和像素电极的连接线 4'以及公共电极 6 的图形， 如图 40 A-图 40C。
步骤 3700: 在图 40A-图 40C的结构上进行了第六刻蚀工艺， 去掉了暴 露出的第二金属薄膜 600及掺杂半导体薄膜 500, 形成了 TFT沟道 18、 源电 极 16和漏电极 17的图形， 如图 41A-图 41C：。 本步骤中， 第六刻蚀工艺包括 两步骤刻蚀。 首先， 第一步骤中以金属材料刻蚀液， 去掉了没有被第二透明 导电薄膜 700覆盖的第二金属薄膜 600,形成了源电极 16和漏电极 17;然后， 第二步骤中通过千法刻蚀， 采用气体刻蚀剂对暴露出的掺杂半导体薄膜 500 进行刻蚀， 形成了 TFT沟道 18的图形。 经步骤 3100-3700完成第三构图工 艺
本发明实施例的 FFS型 TFT-LCD阵列基板的制造方法， 没有形成钝化 层， 减少了用料， 且阵列基板更加轻薄。 另外， 由于阵列基板上没有钝化层， 所得到的液晶显示器可以用较少的驱动电压即可完成液晶材料的既定的旋转 要求。
这里， 需要说明的是， 本文所称的构图或构图工艺包括光刻胶涂覆、 使 用掩模对光刻胶曝光、 显影得到光刻胶图案、 使用光刻胶图案刻蚀、 剩余光 刻胶的剥离等工艺。 上述说明书中， 光刻胶以正性光刻胶为例。 如果釆用负 性光刻胶， 则显影之后光刻胶的完全曝光区域中的光刻胶是完全保留的， 而 非曝光区域中的光刻胶被全部去除， 而部分曝光区域中的光刻胶仍然是部分 保留的。
本文中所述的 "某某的区域" 是某某图形在透明基板上映射的区域， 即 该区域与某某图形具有相同的形状， 例如栅线的区域， 即为栅线的图形在透 明基板上的映射的区域，也可以理解为透明基板上将要设置栅线图形的区域。
最后应说明的是： 以上实施例仅用以说明本发明的技术方案， 而非对其 限制； 尽管参照前述实施例对本发明进行了详细的说明， 本领域的普通技术 人员应当理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或 者对其中部分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技 术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1、 一种 FFS型 TFT-LCD阵列基板的制造方法， 包括：
步骤 1、 在透明基板上依次形成第一透明导电薄膜及第一金属薄膜， 然 后对对所述第一透明导电薄膜及第一金属薄膜的叠层进行构图， 形成包括栅 线、 栅电极、 公共电极以及公共电极线的图形；
步骤 2、 依次形成栅绝缘薄膜、 半导体薄膜及掺杂半导体薄膜， 对对栅 绝缘薄膜、 半导体薄膜及掺杂半导体薄膜的叠层进行构图， 形成包括 PAD 区域的栅线连接孔以及半导体层的图形；
步骤 3、 形成第二金属薄膜， 对所述第二金属薄膜进行构图， 然后形成 第二透明导电薄膜,进行离地剥离工艺以除去光刻胶上的第二透明导电薄膜， 并刻蚀暴露的第二金属薄膜及掺杂半导体薄膜， 形成包括源电极、 漏电极、 TFT沟道以及像素电极的图形。
2、根据权利要求 1所述的 FFS型 TFT-LCD阵列基板的制造方法， 其中 所述步骤 1包括：
步骤 11 : 在透明基板上依次沉积所述第一透明导电薄膜和第一金属薄 膜；
步驟 12: 涂覆第一光刻胶， 并采用第一半色调掩膜板进行曝光及显影处 理， 使得所述第一光刻胶的光刻胶完全保留区域对应阵列基板的栅线、 栅电 极以及公共电极线的区域， 光刻胶部分保留区域对应阵列基板的公共电极的 区域， 光刻胶完全去除区域对应其余区域；
步骤 13: 进行第一刻蚀工艺， 去掉所述光刻胶完全去除区域的第一金属 薄膜及第一透明导电薄膜， 形成了包括栅线、 栅电极、 公共电极及公共电极 线的图形；
步骤 14: 对第一光刻胶进行灰化工艺， 暴露出了光刻胶部分保留区域的 第一金属薄膜；
步骤 15:进行第二刻蚀工艺，去掉光刻胶部分保留区域的第一金属薄膜， 暴露出了公共电极；
步骤 16: 剥离剩余的第一光刻胶。
3、根据权利要求 1所述的 FFS型 TFT-LCD阵列基板的制造方法， 其中 所述步骤 2包括：
步骤 21 : 在步骤 1的得到的结构上沉积所述栅绝缘薄膜、 半导体薄膜及 掺杂半导体薄膜；
步骤 22: 涂覆第二光刻胶， 并采用第二半色调掩膜板进行曝光及显影处 理， 使得所述第二光刻胶的光刻胶完全保留区域对应 TFT沟道的区域， 光刻 胶完全去除区域对应阵列基板的 PAD 区域的栅线的区域， 光刻胶部分保留 区域对应其余区域；
步骤 23: 进行第三刻蚀工艺， 去掉所述光刻胶完全去除区域的掺杂半导 体薄膜、半导体薄膜及栅绝缘薄膜，暴露出了 PAD区域的栅线，形成了 PAD 区域栅线连接孔及栅绝缘层的图形；
步骤 24: 对所述第二光刻胶进行灰化工艺， 暴露出光刻胶部分保留区域 的掺杂半导体薄膜；
步骤 25: 在进行第四刻蚀工艺， 去掉了所述光刻胶部分保留区域的掺杂 半导体薄膜、 半导体薄膜及栅绝缘薄膜， 形成了包括半导体层的图形； 步骤 26: 剥离剩余的第二光刻胶。
4、根据权利要求 1所述的 FFS型 TFT-LCD阵列基板的制造方法， 其中 所述步骤 3包括：
步驟 31 : 在步骤 2得到的结构上沉积所述第二金属薄膜；
步骤 32: 涂覆第三光刻胶， 并釆用第三半色调掩膜板进行曝光及显影处 理， 使得光刻胶的光刻胶完全去除区域对应阵列基板的像素电极的区域， 光 刻胶部分保留区域对应源电极、 漏电极及 PAD区域的栅线、 PAD区域的数 据线以及 PAD 区域的公共电极线的区域， 光刻胶完全保留区域对应其余区 域；
步骤 33: 进行第五刻蚀工艺， 去掉所述光刻胶完全去除区域的所述第二 金属薄膜 600;
步骤 34: 对所述第三光刻胶进行灰化工艺， 暴露出了所述光刻胶部分保 留区域的第二金属薄膜；
步骤 35: 沉积第二透明导电薄膜；
步骤 36: 进行离地剥离工艺以除去剩余的第三光刻胶之上的第二透明导 电薄膜， 形成像素电极的图形； 步骤 37: 进行第六刻蚀工艺， 去掉暴露出的第二金属薄膜及掺杂半导体 薄膜， 形成了源电极、 漏电极以及 TFT沟道的图形。
5、 一种 FFS型 TFT-LCD阵列基板的制造方法， 包括：
步骤 100、 在透明基板上依次形成第一透明导电薄膜及第一金属薄膜， 对所述第一透明导电薄膜及第一金属薄膜的叠层进行构图， 形成包括栅线、 栅电极、 像素电极以及公共电极线的图形；
步骤 200、 依次形成栅绝缘薄膜、 半导体薄膜及掺杂半导体薄膜， 对所 述栅绝缘薄膜、 半导体薄膜及掺杂半导体薄膜的叠层进行构图， 形成包括过 孔、 PAD区域的栅连接孔以及半导体层的图形；
步骤 300、 沉积第二金属薄膜， 对所述第二金属薄膜进行构图， 然后沉 积第二透明导电薄膜， 进行离地剥离工艺以除去光刻胶上的第二透明导电薄 膜， 之后刻蚀暴露的第二金属薄膜及掺杂半导体薄膜， 形成包括源电极、 漏 电极、 TFT沟道以及公共电极的图形。
6、根据权利要求 5所述的 FFS型 TFT-LCD阵列基板的制造方法， 其中 所述步骤 100包括：
步骤 1100: 在透明基板上依次沉积所述第一透明导电薄膜和第一金属薄 膜；
步驟 1200: 涂覆第一光刻胶， 并采用第一半色调掩膜板进行曝光及显影 处理， 使得所述第一光刻胶的光刻胶完全保留区域对应阵列基板的栅线、 栅 电极以及公共电极线的区域， 光刻胶部分保留区域对应阵列基板的像素电极 的区域， 光刻胶完全去除区域对应其余区域；
步骤 1300: 进行第一刻蚀工艺， 去掉所述光刻胶完全去除区域的第一金 属薄膜及第一透明导电薄膜， 形成了包括栅线、 栅电极、 像素电极及公共电 极线的图形；
步骤 1400: 对所述第一光刻胶进行灰化工艺， 暴露出了光刻胶部分保留 区域的第一金属薄膜；
步骤 1500: 进行第二刻蚀工艺， 去掉光刻胶部分保留区域的第一金属薄 膜， 暴露出了像素电极；
步骤 1600: 剥离所述第一光刻胶。
7、根据权利要求 5所述的 FFS型 TFT-LCD阵列基板的制造方法， 其中 所述步骤 200包括：
步骤 2100: 在步骤 100的得到的结构上沉积所述栅绝缘薄膜、 半导体薄 膜及掺杂半导体薄膜；
步骤 2200: 涂覆第二光刻胶， 并采用第二半色调掩膜板进行曝光及显影 处理， 使得所述第二光刻胶的光刻胶完全保留区域对应 TFT沟道的区域， 光 刻胶完全去除区域对应阵列基板的过孔的区域及 PAD 区域的栅线的区域， 光刻胶部分保留区域对应其余区域；
步骤 2300: 进行第三刻蚀工艺， 去掉所述光刻胶完全去除区域的掺杂半 导体薄膜、 半导体薄膜及栅绝缘薄膜， 暴露出了暴露出了部分的像素电极和 PAD 区域的栅线， 形成了包括过孔、 PAD 区域栅线连接孔及栅绝缘层的图 形；
步骤 2400: 对所述第二光刻胶进行灰化工艺， 暴露出光刻胶部分保留区 域的掺杂半导体薄膜；
步骤 2500: 在进行第四刻蚀工艺， 去掉了所述光刻胶部分保留区域的掺 杂半导体薄膜、 半导体薄膜及栅绝缘薄膜， 形成了包括半导体层的图形； 步骤 2600: 剥离所述第二光刻胶。
8、根据权利要求 5所述的 FFS型 TFT-LCD阵列基板的制造方法， 其中 所述步驟 300包括：
步骤 3100: 在步驟 200得到的结构上沉积第二金属薄膜；
步骤 3200: 涂覆第三光刻胶， 并采用第三半色调掩膜板进行曝光及显影 处理， 使得所述第三光刻胶的光刻胶完全去除区域对应阵列基板的公共电极 的区域， 光刻胶部分保留区域对应源电极、 漏电极及 PAD区域的栅线、 PAD 区域的数据线以及 PAD 区域的公共电极线的区域， 光刻胶完全保留区域对 应其余区域；
步骤 3300: 进行第五刻蚀工艺， 去掉所述光刻胶完全去除区域的所述第 二金属薄膜 600;
步骤 3400: 对所述第三光刻胶进行灰化工艺， 暴露出了所述光刻胶部分 保留区域的第二金属薄膜；
步骤 3500: 沉积第二透明导电薄膜；
步骤 3600: 进行离地剥离工艺以除去剩余的第三光刻胶之上的第二透明 导电薄膜， 形成公共电极及连接线的图形， 所述连接线用于连接漏电极与像 素电极；
步骤 3700: 进行第六刻蚀工艺， 去掉暴露出的第二金属薄膜及掺杂半导 体薄膜， 形成了包括源电极、 漏电极以及 TFT沟道的图形。
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