WO2012009103A3 - Method and apparatus for training a memory signal via an error signal of a memory - Google Patents

Method and apparatus for training a memory signal via an error signal of a memory Download PDF

Info

Publication number
WO2012009103A3
WO2012009103A3 PCT/US2011/041050 US2011041050W WO2012009103A3 WO 2012009103 A3 WO2012009103 A3 WO 2012009103A3 US 2011041050 W US2011041050 W US 2011041050W WO 2012009103 A3 WO2012009103 A3 WO 2012009103A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
error
signal
memory module
training
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/041050
Other languages
French (fr)
Other versions
WO2012009103A2 (en
Inventor
Santanu Chaudhuri
Joseph H. Salmon
Kuljit S. Bains
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP11807237.0A priority Critical patent/EP2586031B1/en
Priority to CN201180031921.9A priority patent/CN102959639B/en
Publication of WO2012009103A2 publication Critical patent/WO2012009103A2/en
Publication of WO2012009103A3 publication Critical patent/WO2012009103A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface.
PCT/US2011/041050 2010-06-28 2011-06-20 Method and apparatus for training a memory signal via an error signal of a memory Ceased WO2012009103A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP11807237.0A EP2586031B1 (en) 2010-06-28 2011-06-20 Method and apparatus for training a memory signal via an error signal of a memory
CN201180031921.9A CN102959639B (en) 2010-06-28 2011-06-20 The method and apparatus training memory signals via the error signal of memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/824,675 US8533538B2 (en) 2010-06-28 2010-06-28 Method and apparatus for training a memory signal via an error signal of a memory
US12/824,675 2010-06-28

Publications (2)

Publication Number Publication Date
WO2012009103A2 WO2012009103A2 (en) 2012-01-19
WO2012009103A3 true WO2012009103A3 (en) 2012-04-12

Family

ID=45353741

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/041050 Ceased WO2012009103A2 (en) 2010-06-28 2011-06-20 Method and apparatus for training a memory signal via an error signal of a memory

Country Status (4)

Country Link
US (1) US8533538B2 (en)
EP (1) EP2586031B1 (en)
CN (1) CN102959639B (en)
WO (1) WO2012009103A2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110100467A (en) * 2010-03-04 2011-09-14 삼성전자주식회사 A method for optimizing data training of a system having a memory device
US8760945B2 (en) 2011-03-28 2014-06-24 Samsung Electronics Co., Ltd. Memory devices, systems and methods employing command/address calibration
JP2013073653A (en) 2011-09-28 2013-04-22 Elpida Memory Inc Semiconductor device
KR101750215B1 (en) * 2012-03-31 2017-06-22 인텔 코포레이션 Delay-compensated error indication signal
US20140089573A1 (en) * 2012-09-24 2014-03-27 Palsamy Sakthikumar Method for accessing memory devices prior to bus training
US9299400B2 (en) 2012-09-28 2016-03-29 Intel Corporation Distributed row hammer tracking
US9607714B2 (en) 2012-12-26 2017-03-28 Nvidia Corporation Hardware command training for memory using write leveling mechanism
US9824772B2 (en) * 2012-12-26 2017-11-21 Nvidia Corporation Hardware chip select training for memory using read commands
US20140181452A1 (en) * 2012-12-26 2014-06-26 Nvidia Corporation Hardware command training for memory using read commands
US9026725B2 (en) 2012-12-27 2015-05-05 Intel Corporation Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals
US9378169B2 (en) 2012-12-31 2016-06-28 Nvidia Corporation Method and system for changing bus direction in memory systems
US9021154B2 (en) * 2013-09-27 2015-04-28 Intel Corporation Read training a memory controller
US9025399B1 (en) * 2013-12-06 2015-05-05 Intel Corporation Method for training a control signal based on a strobe signal in a memory module
KR20160107685A (en) * 2015-03-05 2016-09-19 에스케이하이닉스 주식회사 Semiconductor system and method for testing semiconductor device
US10585672B2 (en) * 2016-04-14 2020-03-10 International Business Machines Corporation Memory device command-address-control calibration
KR102536657B1 (en) * 2016-07-12 2023-05-30 에스케이하이닉스 주식회사 Semiconductor device and semiconductor system
KR102340446B1 (en) 2017-09-08 2021-12-21 삼성전자주식회사 Storage device and data training method thereof
US10720197B2 (en) * 2017-11-21 2020-07-21 Samsung Electronics Co., Ltd. Memory device for supporting command bus training mode and method of operating the same
TWI715095B (en) * 2018-07-03 2021-01-01 聯發科技股份有限公司 Methods and memory systems of parity training for a dram
US10810078B2 (en) * 2018-07-03 2020-10-20 Mediatek Inc. Method of parity training for a DRAM supporting a link error checking and correcting functionality
KR20200043017A (en) 2018-10-17 2020-04-27 삼성전자주식회사 Memory modules, memory systems and methods of operating memory modules
CN116092544A (en) * 2021-09-02 2023-05-09 爱思开海力士有限公司 Command address control circuit and semiconductor device and semiconductor system including same
US12334186B2 (en) 2022-06-10 2025-06-17 Samsung Electronics Co., Ltd. Memory device, memory system and method for operating memory system including command and address training

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004152378A (en) * 2002-10-30 2004-05-27 Elpida Memory Inc Semiconductor integrated circuit device
JP2008192309A (en) * 2008-05-12 2008-08-21 Elpida Memory Inc Semiconductor integration circuit device
JP2008234699A (en) * 2007-03-16 2008-10-02 Fujitsu Ltd Semiconductor memory, memory controller, system, and operation method of semiconductor memory
JP2010009642A (en) * 2008-06-24 2010-01-14 Toshiba Corp Semiconductor memory device and test method thereof

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6026621U (en) * 1983-07-28 1985-02-22 アルプス電気株式会社 Optical head position control device
WO2001097215A1 (en) * 2000-06-09 2001-12-20 Seagate Technology Llc Reducing actuator arm oscillation during settle mode in a disc drive servo system
JP4092877B2 (en) * 2001-01-26 2008-05-28 株式会社日立プラントテクノロジー Adaptive control device and shaking table
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
JP2003050738A (en) * 2001-08-03 2003-02-21 Elpida Memory Inc Calibration method and memory system
US7646835B1 (en) * 2003-11-17 2010-01-12 Rozas Guillermo J Method and system for automatically calibrating intra-cycle timing relationships for sampling signals for an integrated circuit device
US7106021B2 (en) * 2004-05-04 2006-09-12 International Business Machines Corporation Method, system, and program product for feedback control of a target system utilizing imposition of a periodic modulating signal onto a command signal
US7126874B2 (en) * 2004-08-31 2006-10-24 Micron Technology, Inc. Memory system and method for strobing data, command and address signals
DE102005001894A1 (en) * 2005-01-14 2006-08-03 Infineon Technologies Ag Synchronous parallel-to-serial converter
US7321524B2 (en) * 2005-10-17 2008-01-22 Rambus Inc. Memory controller with staggered request signal output
US7783954B2 (en) * 2006-09-11 2010-08-24 Globalfoundries Inc. System for controlling high-speed bidirectional communication
US7694031B2 (en) * 2006-10-31 2010-04-06 Globalfoundries Inc. Memory controller including a dual-mode memory interconnect
WO2008063199A1 (en) * 2006-11-20 2008-05-29 Rambus Inc. Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
KR101533120B1 (en) * 2006-12-14 2015-07-01 램버스 인코포레이티드 Multi-die memory device
KR101308047B1 (en) * 2007-02-08 2013-09-12 삼성전자주식회사 Memory system, memory for the same, and command decoding method of the memory
EP2153525B1 (en) * 2007-05-29 2017-04-05 Rambus Inc. Adjusting clock error across a circuit interface
US8359521B2 (en) * 2008-01-22 2013-01-22 International Business Machines Corporation Providing a memory device having a shared error feedback pin
US8255783B2 (en) * 2008-04-23 2012-08-28 International Business Machines Corporation Apparatus, system and method for providing error protection for data-masking bits
KR101407362B1 (en) * 2008-06-23 2014-06-16 삼성전자주식회사 Phase change memory device
JP4517312B2 (en) * 2008-07-08 2010-08-04 ソニー株式会社 Memory access control device and imaging device
US8161313B2 (en) * 2008-09-30 2012-04-17 Mosaid Technologies Incorporated Serial-connected memory system with duty cycle correction
US20100162037A1 (en) * 2008-12-22 2010-06-24 International Business Machines Corporation Memory System having Spare Memory Devices Attached to a Local Interface Bus
US8412987B2 (en) * 2009-06-30 2013-04-02 Micron Technology, Inc. Non-volatile memory to store memory remap information

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004152378A (en) * 2002-10-30 2004-05-27 Elpida Memory Inc Semiconductor integrated circuit device
JP2008234699A (en) * 2007-03-16 2008-10-02 Fujitsu Ltd Semiconductor memory, memory controller, system, and operation method of semiconductor memory
JP2008192309A (en) * 2008-05-12 2008-08-21 Elpida Memory Inc Semiconductor integration circuit device
JP2010009642A (en) * 2008-06-24 2010-01-14 Toshiba Corp Semiconductor memory device and test method thereof

Also Published As

Publication number Publication date
CN102959639A (en) 2013-03-06
EP2586031A4 (en) 2017-08-23
US20110320867A1 (en) 2011-12-29
EP2586031B1 (en) 2018-09-12
US8533538B2 (en) 2013-09-10
EP2586031A2 (en) 2013-05-01
WO2012009103A2 (en) 2012-01-19
CN102959639B (en) 2016-08-24

Similar Documents

Publication Publication Date Title
WO2012009103A3 (en) Method and apparatus for training a memory signal via an error signal of a memory
WO2010096153A3 (en) Data integrity in memory controllers and methods
EP2472508A3 (en) Method and apparatus for transmitting data
WO2011062424A3 (en) Method and apparatus for transmitting and receiving data in a communication system
WO2011159805A3 (en) Apparatus, system, and method for providing error correction
WO2011041262A3 (en) Real-time feedback of task performance
WO2011118943A3 (en) Method and device for transmitting control information
WO2012124969A3 (en) Method for transmitting/receiving signal and device therefor
WO2010140039A8 (en) Electro-biometric methods and apparatus
WO2012014211A3 (en) Interactive toy apparatus and method of using same
GB201302029D0 (en) Electronic apparatus, control method and recording medium
WO2013019879A3 (en) Asset model import connector
WO2009031860A3 (en) Control apparatus and method
WO2009117431A3 (en) Multi-resolution beamforming with feedback in mimo systems
WO2007117426A3 (en) Glucose meter communication method and system
WO2011017365A3 (en) Methods and apparatus for facilitating application inter-communications
WO2011016672A3 (en) Home appliance and method for operating the same
WO2007028081A3 (en) Remote control media player
WO2012087729A3 (en) Remote vehicle programming system and method
WO2010090697A3 (en) Solid state memory formatting
WO2010107176A3 (en) Apparatus and method for managing a dram buffer
WO2012097372A3 (en) Door-mounted 3d video messaging system
WO2012045998A3 (en) Detector system
TW200951712A (en) Multi-channel hybrid density memory storage device and control method thereof
WO2010129255A3 (en) Mobile communication device and communication method

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180031921.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11807237

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2011807237

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE