WO2012175048A1 - 磨损均衡方法、存储装置及信息系统 - Google Patents

磨损均衡方法、存储装置及信息系统 Download PDF

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Publication number
WO2012175048A1
WO2012175048A1 PCT/CN2012/077403 CN2012077403W WO2012175048A1 WO 2012175048 A1 WO2012175048 A1 WO 2012175048A1 CN 2012077403 W CN2012077403 W CN 2012077403W WO 2012175048 A1 WO2012175048 A1 WO 2012175048A1
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Prior art keywords
storage
remapping
subspace
key
address
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English (en)
French (fr)
Inventor
龚皓
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Tsinghua University
Huawei Technologies Co Ltd
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Tsinghua University
Huawei Technologies Co Ltd
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Priority to EP12802379.3A priority Critical patent/EP2626792A4/en
Publication of WO2012175048A1 publication Critical patent/WO2012175048A1/zh
Priority to US13/903,774 priority patent/US9189420B2/en
Anticipated expiration legal-status Critical
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7211Wear leveling

Definitions

  • Embodiments of the present invention relate to the field of storage technologies, and in particular, to a wear leveling method, a storage device, and an information system.
  • phase change memory has two major advantages: one is high integration and scalability, and the other is energy saving.
  • phase change memory cells can only withstand a certain number of write operations, typically around 105-108 times. After this number is exceeded, a lock error (Stuck-at Fault) occurs in the memory cell, so that the new write request cannot change the original write state, and thus the memory cell is permanently locked in the original write data state.
  • a lock error (Stuck-at Fault) occurs in the memory cell, so that the new write request cannot change the original write state, and thus the memory cell is permanently locked in the original write data state.
  • the main reason is that after a certain number of write operations, due to frequent expansion and contraction, the heating resistor will fall off, resulting in the memory unit can no longer change the phase, that is, write new data, and the original data is still written. You can continue with the read operation.
  • Embodiments of the present invention provide a wear leveling method, a storage device, and an information system, which can map a logical address of a data block with too many local write operations to an entire physical storage space, thereby avoiding overheating of local data and prolonging the use of phase change storage. life.
  • An embodiment of the present invention provides a wear leveling method, in which a storage space is divided into a plurality of storage subspaces of the same size, and each storage subspace is divided into a plurality of storage blocks of the same size, each storage block.
  • the logical address and the physical address correspond to a logical address and a physical address, the logical address and the physical address have a unique mapping relationship; the method comprises: recording the cumulative number of write operations of each storage subspace; when any one of the plurality of storage subspaces When the number of accumulated write operations of the space reaches a predetermined remapping rate, the logical address of the storage subspace is mapped to the remapping physical address.
  • An embodiment of the present invention provides a storage device, including a storage space, where the storage space includes a plurality of storage subspaces of the same size, each storage subspace includes a plurality of storage blocks of the same size, and each storage block corresponds to one logical address. And a physical address, a logical address and a physical address have a unique mapping relationship; a recording unit for recording the cumulative number of write operations per storage subspace; a remapping unit for storing any one of the plurality of storage subspaces When the number of accumulated write operations of the subspace reaches a predetermined remapping rate, the logical address of the storage subspace is mapped to the remapping physical address.
  • An embodiment of the present invention provides an information system, including a central processing unit and at least one of the foregoing storage devices; wherein, the central processing unit is configured to control the storage device; and the storage device is configured to store or access information according to instructions of the central processing unit. .
  • the logical address of the data block with too many local write operations can be mapped to the full physical storage space, thereby avoiding overheating of the local data and prolonging the service life of the storage medium.
  • Embodiment 1 is a flowchart of a wear leveling method according to Embodiment 1 of the present invention.
  • FIG. 2 is a flowchart of a wear leveling method according to Embodiment 2 of the present invention.
  • Embodiment 3 is a flowchart of a wear leveling method according to Embodiment 3 of the present invention.
  • FIG. 4 is a flowchart of a wear leveling method according to Embodiment 4 of the present invention
  • FIG. 5 is a schematic structural diagram of a storage device according to Embodiment 5 of the present invention
  • FIG. 5 is a schematic structural diagram of a storage device according to Embodiment 5 of the present invention
  • FIG. 6 is a schematic structural diagram of a storage device according to Embodiment 6 of the present invention.
  • FIG. 7 is a schematic structural diagram of an information system according to Embodiment 7 of the present invention. detailed description
  • the wear leveling method proposed in the embodiment of the present invention divides a logical address space of a storage space into a plurality of storage subspaces of the same size, each storage subspace includes a plurality of storage blocks, and each storage subspace can be remapped to Full physical address space.
  • the remapping of multiple storage subspaces can be done simultaneously. If all of the memory blocks in a storage subspace have been remapped, then the storage subspace will immediately proceed to the next remapping round to continue remapping.
  • This parallel wear leveling approach enables the remapping of memory blocks to occur as quickly as possible at the most "need" locations, ie, the most frequently written or worn out memory block logical addresses, and the physical address to which each memory block logical address can be mapped.
  • the address is not limited to any physical sub-address space.
  • FIG. 1 is a flow chart of the wear leveling method provided in the first embodiment of the present invention.
  • the method is applied to a storage medium such as phase change storage, flash memory, and the like.
  • the storage space of the storage medium is divided into a plurality of storage subspaces of the same size, each storage subspace is divided into a plurality of storage blocks of the same size, each storage block corresponding to one logical address and one physical address, the logical address
  • the physical address has a uniquely mapped relationship; a plurality of storage subspaces of the same size may be contiguous; a plurality of storage blocks of the same size may be contiguous.
  • the partitioning operation of the storage space may be that the storage medium is completed at the time of production, and the parameters of the storage space are initialized, for example:
  • the method in this embodiment includes:
  • Step S101 Record the number of accumulated write operations of each storage subspace WC;
  • Step S103 When the number of accumulated write operations of any one of the plurality of storage subspaces reaches a predetermined remapping rate, for example, 100, mapping the logical address of the storage subspace to the remapped physical address;
  • Step S105 Zero the cumulative number of write operations WC of the storage subspace, and the storage subspace enters the next remapping wheel.
  • the step S101 may be: setting a counter for each storage subspace, for recording the number of accumulated write operations of each storage subspace; according to the storage block address (logical address or physical address) corresponding to each write operation Determining the storage subspace to which the storage block belongs, adding 1 to the counter corresponding to the storage subspace, thereby recording the cumulative number of write operations of the storage subspace.
  • the step S103 may include: generating a remapping key for the storage subspace; performing an exclusive OR operation on the logical address of the storage subspace and the remapping key to obtain a remapping physical of the storage subspace Address, thereby mapping the logical address of the storage subspace to the remapped physical address.
  • address remapping of multiple storage subspaces can be performed simultaneously. If all of the memory blocks in a storage subspace have been remapped, then the storage subspace will immediately proceed to the next remapping round to continue remapping.
  • the address remapping of the plurality of storage subspaces is performed in multiple parallel manners, which can make the wear leveling speed faster.
  • FIG. 2 is a flowchart of a wear leveling method according to Embodiment 2 of the present invention. This method is applied to storage media such as phase change storage, flash flash, and the like.
  • the storage block logical address of the storage subspace includes a storage subspace key and a storage block key
  • the storage subspace key is used to identify the storage subspace
  • the storage block key is used to identify the storage block of the storage subspace.
  • Step S201 Record the number of accumulated write operations of each storage subspace
  • Step S203 When the number of accumulated write operations of any one of the plurality of storage subspaces reaches a predetermined remapping rate, a remapping key is generated for the storage subspace, and the number of bits of the remapping key and the storage subspace The number of bits in the logical address of the memory block is the same;
  • the logical block of the storage block in the storage subspace is represented by a binary number string MA of length Log2N, and the consecutive Log2 (N/n) bits in the MA are storage subspace keys, and the consecutive Log2n bits in the MA are stored.
  • Block key for example, the former Log2 (N/n) bit in the MA is the storage subspace key Region key, and the Log2 (N/n) bit in the MA is the storage subspace key Block key, where N is the storage block of the storage space.
  • the total number, n is the number of storage blocks per storage subspace.
  • Step S205 XORing each memory block logical address of the storage subspace with the remapping key to obtain a remapping physical address of each memory block, thereby mapping the logical address of the storage subspace to the remapping physical address.
  • address remapping of multiple storage subspaces can be performed simultaneously. If all of the memory blocks in a storage subspace have been remapped, then the storage subspace will immediately proceed to the next remapping round to continue remapping. In the embodiment of the present invention, the address remapping of the plurality of storage subspaces is performed in multiple parallel manners, which can make the wear leveling speed faster.
  • FIG. 3 is a flowchart of a wear leveling method according to Embodiment 3 of the present invention. This method is applied to storage media such as phase change storage, flash flash, and the like. As shown in FIG. 1, the method in this embodiment includes: Step S301. Record the number of accumulated write operations of each storage subspace;
  • Step S303 When the number of accumulated write operations of any one of the plurality of storage subspaces reaches a predetermined remapping rate, the logical address of the storage subspace is mapped to the remapping physical address;
  • the method further includes:
  • Step S305 Zero the number of accumulated write operations of the storage subspace, and the storage subspace enters the next remapping wheel; Step S307. After the storage subspace enters the next remapping round, generate a new remapping key of the local remapping wheel for the storage subspace;
  • Step S309 Determine whether the new remapping key is the same as the remapping key of the previous remapping wheel; when the two are the same, step S311 is performed, and when the two are not the same, step S313 is performed;
  • Step S311 Perform an exclusive OR operation on the logical address of the storage subspace and the remapping key to obtain a remapping physical address of the storage subspace in the local remapping round, complete remapping of the local remapping round, and enter the next remapping round;
  • Step S313. It is determined whether the remapping physical address of the storage subspace in the local remapping round is the same as the remapping physical address of the buddy storage subspace of the storage subspace; if they are the same, step S315 is performed, if not, step S311 is performed; If the two logical subspaces are mapped to the same physical address by XOR mapping, the two logical subspaces are said to be partner storage subspaces respectively; Step S315. Update the buddy storage subspace according to the remapping key of the storage subspace. The remapping key of the space obtains a remapping key of the updated buddy storage subspace; and the remapping physical address of the buddy storage subspace is determined according to the updated remapping key of the buddy storage subspace.
  • address remapping of multiple storage subspaces can be performed simultaneously. If all of the memory blocks in a storage subspace have been remapped, then the storage subspace will immediately proceed to the next remapping round to continue remapping. In the embodiment of the present invention, the address remapping of the plurality of storage subspaces is performed in multiple parallel manners, which can make the wear leveling speed faster.
  • the logical address of the subspace is stored. Mapping to the remapping physical address can map the logical address of the data block with too many local write operations to the full physical storage space, thereby avoiding overheating of the local data and prolonging the service life of the storage medium.
  • 4 is a flow chart of a wear leveling method according to Embodiment 4 of the present invention. The method is applied to a storage medium such as phase change storage, flash memory, and the like. As shown in FIG. 4, the method in this embodiment includes: Step S401. Record the number of accumulated write operations of each storage subspace;
  • Step S403. When the number of accumulated write operations of any one of the plurality of storage subspaces reaches a predetermined remapping rate, mapping the logical address of the storage subspace to the remapping physical address;
  • Step S405. When the storage subspace is accessed, the logical address of the storage subspace is translated into a corresponding remapped physical address, which specifically includes:
  • step S405 may include:
  • Lb.pbp lb XOR lsr.keys.pr;
  • the translated physical block address is the physical address lb.pbc to which the current remapping round is mapped; otherwise, after translation
  • the physical block address is the physical address lb.pbp mapped to in the previous remapping round.
  • address remapping of multiple storage subspaces can be performed simultaneously. If all of the memory blocks in a storage subspace have been remapped, then the storage subspace will immediately proceed to the next remapping round to continue remapping. In the embodiment of the present invention, the address remapping of the plurality of storage subspaces is performed in multiple parallel manners, which can make the wear leveling speed faster.
  • the logical address of the subspace is stored. Map to the remapping physical address, when the storage subspace is accessed, The logical address of the storage subspace is translated into a corresponding remapping physical address, and the translation of the logical space of the storage subspace after the remapping is implemented, and the access operation is completed.
  • the address remapping algorithm and the address translation algorithm of the wear leveling method of the embodiment of the present invention will be described in detail below. The first is the definition of the data structure:
  • the storage subspace data structure includes a wheel number cr of a current remapping wheel and a wheel number lr of a previous remapping wheel, and a mapping key for extracting a current remapping wheel and a previous remapping wheel; a current remapping pointer crp; a storage subspace The accumulated write operand wc; the remapping key of the storage subspace, and the like.
  • the data structure of the physical address of the storage subspace includes the current logical address number clsr, which is used to find the logical address corresponding to the physical address of the storage subspace.
  • the multipath wear leveling global structure includes the logical address array of the storage subspace *lsrs, the physical address array of the storage subspace *psrs, the total number of write operations writes, the total number of block swaps, and the total number of remapping refreshes.
  • PSR FIND - PSR (PHY - ADD)
  • VICTIM - PHY - ADD LOG - ADD XOR LSR -> KEYS [LR]
  • VICTIM - PSR FIND - PSR (VICTIM - PHY - ADD)
  • VICTIM - PSR - CLSR VICTIM - PSR -> CLSR
  • VICTIM — LSR VICTIM — PSR — CLSR
  • VICTIM—LR VICTIM— LSR -> LR
  • VICTIM—CR VICTIM— LSR -> CR
  • VICTIM — LOG — ADD PHY — ADD XOR VICTIM — LSR --> KEYS [VICTIM — LR] IF VICTIM — LOG — ADD ⁇ VICTIM — LSR --> CRP) ⁇
  • VICTIM — LSR PSR — CLSR
  • VICTIM—LR VICTIM— LSR -> LR
  • VICTIM—CR (VICTIM—LR + 1) % 2
  • VICTIM- LSR -> CR VICTIM-CR
  • VICTIM— LSR -> KEYS [VICTIM— CR] LSR -> KEYS [CR] XOR LSR -> KEYS [LR] VICTIM— LSR -> KEYS [VICTIM—LR]
  • VICTIM - LSR -> CRP FIRST ADDRESS IN THE VICTIM LSR
  • VICTIM - LSR -> LR (VICTIM - LSR -> LR + 1) % 2
  • PHY_ADD_ PRE LOG— ADD XOR LSR -> KEYS [LSR -> LR]
  • PSR - CUR F ⁇ - PSR (PHY - ADD - CUR)
  • PSR— PRE F ⁇ — PSR (PHY— ADD— PRE)
  • VICTIM — LOG — ADD PHY — ADD — CUR XOR
  • VICTIM-LSR -> KEYS [VICTIM-LSR -> LR]
  • FIG. 5 is a schematic structural diagram of a storage device according to Embodiment 5 of the present invention. As shown in FIG. 5, the storage device 500 can include:
  • the storage space includes a plurality of storage subspaces of the same size, each storage subspace includes a plurality of storage blocks of the same size, each storage block corresponding to one logical address and one physical address, the logical address and physical
  • the address has a unique mapping relationship;
  • the storage medium of the storage space may be phase change storage, flash memory, etc.;
  • a recording unit 503 configured to record the number of accumulated write operations of each storage subspace
  • a remapping unit 505 configured to accumulate storage space of any one of the plurality of storage subspaces When the number of write operations reaches a predetermined remapping rate, the logical address of the storage subspace is mapped to the remapping physical address.
  • the remapping unit 505 can include:
  • a generating unit 5051 configured to generate a remapping key for the storage subspace
  • the operation unit 5053 is configured to perform an exclusive OR operation on the logical address of the storage subspace and the remapping key to obtain a remapping physical address of the storage subspace, thereby implementing mapping the logical address of the storage subspace to the remapping physical address.
  • the storage block logical address of the storage subspace may include a storage subspace key and a storage block key
  • the storage subspace key may be used to identify a storage subspace
  • the storage block key may be used to identify a storage block of the storage subspace
  • the generating unit 5051 may include:
  • a first generating subunit 50511 configured to generate a remapping key for the storage subspace, where the number of bits of the remapping key is the same as the number of bits of the logical block of the storage block of the storage subspace;
  • the operation unit 5053 may include:
  • the operation subunit 50531 is configured to perform an exclusive OR operation on each storage block logical address of the storage subspace and the remapping key to obtain a remapping physical address of each storage block, thereby realizing mapping the logical address of the storage subspace to the heavy Map physical addresses.
  • the logical block address of the storage block in the storage subspace can be represented by a binary number string MA of length Log2N, and the consecutive Log2 (N/n) bits in the binary number string MA are storage subspace keys Region key, binary number string MA The consecutive Log2n bits are the block key Block, where N is the total number of memory blocks in the storage space, and n is the number of memory blocks in each storage subspace;
  • the recording unit 503 can include:
  • a determining unit 5031 configured to determine, according to a storage block address corresponding to each write operation, a storage subspace to which the storage block belongs;
  • the counting unit 5033 is configured to record the number of accumulated write operations of the storage subspace.
  • the storage device 500 further includes:
  • the zeroing unit 507 is configured to zero the number of accumulated write operations of the storage subspace 501, indicating that the storage subspace 501 enters the next remapping wheel.
  • the remapping unit 505 is further configured to generate a new remapping key of the local remapping wheel to the storage subspace 501 after the storage subspace 501 enters the next remapping round, when the new remapping key is the same as the previous remapping key.
  • the remapping keys of the mapping wheel are the same, the logical address of the storage subspace 501 is XORed with the remapping key to obtain the remapping physical address of the storage subspace 501 in the local remapping round.
  • the remapping unit 505 is further configured to: when the storage subspace enters the next remapping round, generate a new remapping key for the storage subspace; when the remapping key of the new remapping key and the previous remapping wheel is not When the same, it is determined whether the remapping physical address of the storage subspace in the remapping wheel is the same as the remapping physical address of the buddy storage subspace of the storage subspace; if the same, the buddy storage is updated according to the remapping key of the storage subspace The remapping key of the space is obtained by the remapping key of the updated buddy storage subspace; and the remapping physical address of the buddy storage subspace is determined according to the remapping key of the updated buddy storage subspace.
  • address remapping of multiple storage subspaces can be performed simultaneously. If all of the memory blocks in a storage subspace have been remapped, then the storage subspace will immediately proceed to the next remapping round to continue remapping. In the embodiment of the present invention, the address remapping of the plurality of storage subspaces is performed in multiple parallel manners, which can make the wear leveling speed faster.
  • FIG. 6 is a schematic structural diagram of a storage device according to Embodiment 6 of the present invention.
  • the storage device of the sixth embodiment of the present invention is improved based on the storage device of the fifth embodiment.
  • the storage device 600 may further include: a logical address determining unit 607 for determining a storage subspace 601 to which the access operation address belongs, in addition to the storage space 601, the recording unit 603, and the remapping unit 605.
  • the translation unit 609 is configured to translate the logical address of the storage subspace 601 into a physical block address.
  • the translation unit 609 can include:
  • the first physical address determining unit 6091 is configured to determine a physical address to which the storage subspace logical address is mapped in the last remapping round;
  • the second physical address determining unit 6093 is configured to determine a physical address to which the storage subspace logical address is mapped in the current remapping wheel;
  • the translation subunit 6095 is configured to: when the storage subspace or the buddy storage subspace of the storage subspace has completed address remapping in the current remapping round, determine that the translated physical block address is mapped to the current remapping wheel Physical address; otherwise it is determined that the translated physical block address is the physical address mapped in the previous remapping round.
  • FIG. 7 is a schematic structural diagram of an information system according to Embodiment 6 of the present invention.
  • the information system 700 can include a central processing unit 701 and at least one storage device 7031, . . . , 703n as described in Embodiments 5 and 6.
  • the storage medium of the storage device can be phase change storage, Flash memory, etc.;
  • the central processing unit 701 is configured to control the storage devices 7031, . . . , 703 ⁇ ;
  • the storage devices 7031, ..., 703n are used to store or access information according to an instruction of the central processing unit 701.
  • the information system can be integrated into servers, telecommunications systems, network systems, data centers, and consumer electronics such as computers and mobile terminals.
  • address remapping of multiple storage subspaces can be performed simultaneously. If all of the memory blocks in a storage subspace have been remapped, then the storage subspace will immediately proceed to the next remapping round to continue remapping. In the embodiment of the present invention, the address remapping of the plurality of storage subspaces is performed in multiple parallel manners, which can make the wear leveling speed faster.
  • the logical address of the data block with too many local write operations can be mapped to the full physical storage space, thereby avoiding overheating of the local data and prolonging the service life of the storage device.
  • all or part of the steps of implementing the above method embodiments may be completed by using hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

提供一种磨损均衡方法、存储装置及信息系统,存储空间被分割成多个大小相同的存储子空间,每个存储子空间被分割成多个大小相同的存储块,每个存储块对应一个逻辑地址和一个物理地址,所述逻辑地址和物理地址具有唯一映射的关系;该方法包括:记录所述每个存储子空间的累积写操作次数;当所述多个存储子空间中的任意一个存储子空间的累积写操作次数达到预定的重映率时,将所述存储子空间的逻辑地址映射到重映射物理地址。可以将局部的写操作过多的数据块的逻辑地址均衡映射到全物理存储空间,从而避免局部数据过热,延长存储介质的使用寿命。

Description

磨损均衡方法、 存储装置及信息系统
技术领域
本发明实施例涉及存储技术领域, 尤其涉及一种磨损均衡方法、 存储装 置及信息系统。
背景技术
近年来,一种新型存储技术——相变存储(Phase-Change Memory, PCM ) 逐渐展露出替代动态随机访问内存的潜力, 从而引起了业界的高度重视。 相 对于动态随机访问内存, 相变存储主要有两大优势: 一是集成度高和可扩展 性强, 二是节约能耗。
然而, 相变存储的存储单元只能承受一定数目的写操作, 一般在 105-108 次左右。 在超过这个数目后存储单元会发生锁定错误(Stuck-at Fault ), 使得 新的写请求不能改变原先的写入状态, 因而存储单元永久被锁在原写入数据 状态。 其主要原因是在超过一定数目的写操作之后, 由于频繁的膨胀和收缩, 加热电阻会发生脱落, 从而导致存储单元再也无法改变相态, 即写入新数据, 而原先写入的数据还可以继续进行读操作。
发明内容
本发明实施例提供一种磨损均衡方法、 存储装置及信息系统, 可以将局 部的写操作过多的数据块的逻辑地址映射到全物理存储空间, 从而避免局部 数据过热, 延长相变存储的使用寿命。
本发明实施例提供一种磨损均衡方法, 存储空间被分割成多个大小相同 的存储子空间,每个存储子空间被分割成多个大小相同的存储块, 每个存储块 对应一个逻辑地址和一个物理地址, 所述逻辑地址和物理地址具有唯一映射 的关系; 该方法包括: 记录每个存储子空间的累积写操作次数; 当多个存储 子空间中的任意一个存储子空间的累积写操作次数达到预定的重映射率时, 将存储子空间的逻辑地址映射到重映射物理地址。
本发明实施例提供一种存储装置, 包括存储空间, 所述存储空间包括多 个大小相同的存储子空间,每个存储子空间包括多个大小相同的存储块, 每个 存储块对应一个逻辑地址和一个物理地址, 逻辑地址和物理地址具有唯一映 射的关系; 记录单元, 用于记录每个存储子空间的累积写操作次数; 重映射 单元, 用于当多个存储子空间中的任意一个存储子空间的累积写操作次数达 到预定的重映射率时, 将存储子空间的逻辑地址映射到重映射物理地址。
本发明实施例提供一种信息系统, 包括中央处理器以及至少一个上述的 存储装置; 其中, 中央处理器用于对存储装置进行控制; 存储装置用于根据 中央处理器的指令对信息进行存储或访问。
通过本发明实施例的磨损均衡方法、 存储装置及信息系统, 可以将局部 的写操作过多的数据块的逻辑地址映射到全物理存储空间, 从而避免局部数 据过热, 延长存储介质的使用寿命。 附图说明
为了更清楚地说明本发明实施例中的技术方案, 下面将对实施例描述中 所需要使用的附图作一筒单地介绍, 显而易见地, 下面描述中的附图是本发 明的一些实施例, 对于本领域普通技术人员来讲, 在不付出创造性劳动性的 前提下, 还可以根据这些附图获得其他的附图。
图 1为本发明实施例一提供的磨损均衡方法的流程图;
图 2为本发明实施例二提供的磨损均衡方法的流程图;
图 3为本发明实施例三提供的磨损均衡方法的流程图;
图 4为本发明实施例四提供的磨损均衡方法的流程图; 图 5为本发明实施例五提供的存储装置的结构示意图;
图 6为本发明实施例六提供的存储装置的结构示意图;
图 7为本发明实施例七提供的信息系统的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚, 下面将结合本发 明实施例中的附图, 对本发明实施例中的技术方案进行清楚、 完整地描述, 显然, 所描述的实施例是本发明一部分实施例, 而不是全部的实施例。 基于 本发明中的实施例, 本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例, 都属于本发明保护的范围。
本发明实施例提出的磨损均衡方法将存储空间的逻辑地址空间分割成多 个相同大小的存储子空间, 每个存储子空间包含多个存储块, 并且每个存储 子空间都能够被重映射到全物理地址空间。 多个存储子空间的重映射可以同 时进行。 如果一个存储子空间其中的所有存储块完成了重映射, 那么该存储 子空间将立即进入下一个重映射轮继续进行重映射。 这种并行的磨损均衡方 法使得存储块的重映射能够尽快在最 "需要" 的部位发生, 即写操作最多或 者磨损最多的存储块逻辑地址, 并且每个存储块逻辑地址可以被映射到的物 理地址并不会被限定在任意一个物理子地址空间。
中文参数 英文对照参数
存储空间大小 Region Size
子存储空间大小 Sub-region Size
子存储空间数目 Sub-region Number
块大小 Block Size
每存储空间块数目 Block Number per Region
每子存储空间块数目 Block Number per Sub-region 表 1 存储配置参数中英文对照表 图 1 为本发明实施例一提供的磨损均衡方法的流程图。 该方法应用于存 储介质, 比如相变存储、 闪存 flash等。 存储介质的存储空间被分割成多个大 小相同的存储子空间,每个存储子空间被分割成多个大小相同的存储块, 每个 存储块对应一个逻辑地址和一个物理地址, 所述逻辑地址和物理地址具有唯 一映射的关系; 多个大小相同的存储子空间可以是连续的; 多个大小相同的 存储块可以是连续的。 存储空间的分割操作可以是存储介质在生产时完成, 同时对存储空间的参数进行初始化, 比如:
总存储块数: N
每个逻辑子空间包含的存储块数: n
逻辑子空间: IsrO, lsrl , lsr2, lsr3, ……, lsr(N/n- 1 )
物理子空间: psrO, psrl , psr2, psr3, ……, psr(N/n-l)
如图 1所示, 本实施例的方法包括:
步骤 S101.记录每个存储子空间的累积写操作次数 WC;
步骤 S103.当多个存储子空间中的任意一个存储子空间的累积写操作次 数达到预定的重映射率时, 比如 100, 将该存储子空间的逻辑地址映射到重映 射物理地址;
步骤 S105.将该存储子空间的累积写操作次数 WC归零,该存储子空间进 入下一个重映射轮。
具体的, 步骤步骤 S101可以是: 对每个存储子空间分别设置计数器, 用 于记录每个存储子空间的累积写操作次数; 根据每一次写操作对应的存储块 地址(逻辑地址或物理地址)确定该存储块所属的存储子空间, 对该存储子 空间对应的计数器加 1 , 从而记录该存储子空间的累积写操作次数。
具体的, 步骤步骤 S103可以包括: 对存储子空间生成重映射键; 将存储 子空间的逻辑地址与重映射键进行异或操作, 得到存储子空间的重映射物理 地址, 从而实现将存储子空间的逻辑地址映射到重映射物理地址。 在本发明实施例中, 多个存储子空间的地址重映射可以同时进行。 如果 一个存储子空间其中的所有存储块完成了重映射, 那么该存储子空间将立即 进入下一个重映射轮继续进行重映射。 本发明实施例中, 多个存储子空间的 地址重映射是多路并行进行的, 可以使得磨损均衡速度更快。
本发明实施例通过记录每个存储子空间的累积写操作次数, 当多个存储 子空间中的任意一个存储子空间的累积写操作次数达到预定的重映射率时, 将存储子空间的逻辑地址映射到重映射物理地址, 可以将局部的写操作过多 的数据块的逻辑地址均衡映射到全物理存储空间, 从而避免局部数据过热, 延长存储介质的使用寿命。 图 2为本发明实施例二提供的磨损均衡方法的流程图。 该方法应用于存 储介质, 比如相变存储、 闪存 flash等。 在本发明实施例中, 存储子空间的存 储块逻辑地址包括存储子空间键和存储块键, 存储子空间键用于标识存储子 空间, 存储块键用于标识存储子空间的存储块。 本实施例的磨损均衡方法包 括:
步骤 S201.记录每个存储子空间的累积写操作次数;
步骤 S203.当多个存储子空间中的任意一个存储子空间的累积写操作次 数达到预定的重映射率时, 对存储子空间生成重映射键, 该重映射键的位数 与存储子空间的存储块逻辑地址的位数相同;
具体的, 存储子空间中的存储块逻辑地址以长度为 Log2N的二进制数串 MA表示, MA中连续的 Log2(N/n)位为存储子空间键 Region key, MA中连 续的 Log2n位为存储块键 Block key, 比如 MA中前 Log2(N/n)位为存储子空 间键 Region key, MA中后 Log2(N/n)位为存储子空间键 Block key, 其中 N为 存储空间的存储块总数, n为每个存储子空间的存储块数量。
具体的, 步骤 S203 包括: 对存储子空间生成重映射键 Key, 重映射键 Key的长度 KeySize = Log2N;
步骤 S205.将存储子空间的每一存储块逻辑地址与重映射键进行异或操 作, 得到每一存储块的重映射物理地址, 从而实现将存储子空间的逻辑地址 映射到重映射物理地址。
具体的, 步骤 S205包括: 将存储子空间中的每一存储块逻辑地址 MA与 重映射键 Key进行异或操作, 得到每一存储块的重映射物理地址 RMA, 即 RMA = MA XOR Key, 其中 XOR表示异或操作。
在本发明实施例中, 多个存储子空间的地址重映射可以同时进行。 如果 一个存储子空间其中的所有存储块完成了重映射, 那么该存储子空间将立即 进入下一个重映射轮继续进行重映射。 本发明实施例中, 多个存储子空间的 地址重映射是多路并行进行的, 可以使得磨损均衡速度更快。
本发明实施例通过记录每个存储子空间的累积写操作次数, 当多个存储 子空间中的任意一个存储子空间的累积写操作次数达到预定的重映射率时, 将存储子空间的逻辑地址映射到重映射物理地址, 可以将局部的写操作过多 的数据块的逻辑地址均衡映射到全物理存储空间, 从而避免局部数据过热, 延长存储介质的使用寿命。 图 3 为本发明实施例三提供的磨损均衡方法的流程图。 该方法应用于存 储介质, 比如相变存储、 闪存 flash等。 如图 1所示, 本实施例的方法包括: 步骤 S301.记录每个存储子空间的累积写操作次数;
步骤 S303.当多个存储子空间中的任意一个存储子空间的累积写操作次 数达到预定的重映射率时, 将该存储子空间的逻辑地址映射到重映射物理地 址;
完成本重映射轮后, 该方法还包括:
步骤 S305.将该存储子空间的累积写操作次数归零, 该存储子空间进入下 一个重映射轮; 步骤 S307. 当该存储子空间进入下一个重映射轮后, 对该存储子空间生 成本重映射轮新的重映射键;
步骤 S309.判断新的重映射键与上一个重映射轮的重映射键是否相同; 当 两者相同时, 执行步骤 S311 , 当两者不相同时, 执行步骤 S313;
步骤 S311.将存储子空间的逻辑地址与重映射键进行异或操作, 得到本重 映射轮中存储子空间的重映射物理地址, 完成本重映射轮的重映射, 进入下 一个重映射轮;
步骤 S313. 判断本重映射轮中存储子空间的重映射物理地址是否与存储 子空间的伙伴存储子空间的重映射物理地址相同; 如果相同, 则执行步骤 S315 , 如果不相同, 执行步骤 S311 ; 其中, 如果两个逻辑子空间通过异或映 射后映射到同一块物理地址, 则称该两块逻辑子空间互为伙伴存储子空间; 步骤 S315.根据存储子空间的重映射键更新伙伴存储子空间的重映射键, 得到更新后的伙伴存储子空间的重映射键; 根据更新后的所述伙伴存储子空 间的重映射键, 确定伙伴存储子空间的重映射物理地址。
在本发明实施例中, 多个存储子空间的地址重映射可以同时进行。 如果 一个存储子空间其中的所有存储块完成了重映射, 那么该存储子空间将立即 进入下一个重映射轮继续进行重映射。 本发明实施例中, 多个存储子空间的 地址重映射是多路并行进行的, 可以使得磨损均衡速度更快。
本发明实施例通过记录每个存储子空间的累积写操作次数, 当多个存储 子空间中的任意一个存储子空间的累积写操作次数达到预定的重映射率时, 将存储子空间的逻辑地址映射到重映射物理地址, 可以将局部的写操作过多 的数据块的逻辑地址均衡映射到全物理存储空间, 从而避免局部数据过热, 延长存储介质的使用寿命。 图 4为本发明实施例四提供的磨损均衡方法的流程图。 该方法应用于存 储介质, 比如相变存储、 闪存 flash等。 如图 4所示, 本实施例的方法包括: 步骤 S401.记录每个存储子空间的累积写操作次数;
步骤 S403.当多个存储子空间中的任意一个存储子空间的累积写操作次 数达到预定的重映射率时, 将该存储子空间的逻辑地址映射到重映射物理地 址;
步骤 S405. 当该存储子空间被访问时, 将该存储子空间的逻辑地址翻译 成对应的重映射物理地址, 具体包括:
确定访问操作地址所属的存储子空间逻辑地址;
将存储子空间逻辑地址翻译成物理块地址。
具体的, 步骤 S405可以包括:
首先, 确定该存储子空间逻辑地址 LBA在上一重映射轮中映射到的物理 地址 lb.pbp:
lb.pbp = lb XOR lsr.keys.pr;
其中, lb是逻辑块的逻辑地址, lsr.keys.pr是前一重映射轮的映射键值。 确定该存储子空间逻辑地址在当前重映射轮映射到的物理地址 lb.pbc: lb.pbc = lb XOR lsr.keys.cr
所以, 如果该存储子空间或者它的伙伴存储子空间已经在当前重映射轮 完成了地址重映射, 那么翻译后的物理块地址为当前重映射轮映射到的物理 地址 lb.pbc; 否则翻译后的物理块地址为上一重映射轮中映射到的物理地址 lb.pbp。
在本发明实施例中, 多个存储子空间的地址重映射可以同时进行。 如果 一个存储子空间其中的所有存储块完成了重映射, 那么该存储子空间将立即 进入下一个重映射轮继续进行重映射。 本发明实施例中, 多个存储子空间的 地址重映射是多路并行进行的, 可以使得磨损均衡速度更快。
本发明实施例通过记录每个存储子空间的累积写操作次数, 当多个存储 子空间中的任意一个存储子空间的累积写操作次数达到预定的重映射率时, 将存储子空间的逻辑地址映射到重映射物理地址, 当该存储子空间被访问时, 将该存储子空间的逻辑地址翻译成对应的重映射物理地址, 实现对重映射后 存储子空间逻辑地址的翻译, 完成访问操作。 下面将详细说明本发明实施例的磨损均衡方法的地址重映射算法和地址 翻译算法。 首先是对数据结构的定义:
存储子空间的逻辑地址:
struct lsr {
uint64_t cr;
uint64_t lr;
uint64_t crp;
uint64_t wc;
uint64_t keys [2];
uint64_t total— round ;
};
存储子空间数据结构包括当前重映射轮的轮号 cr和上一重映射轮的轮号 lr, 用于提取当前重映射轮和上一重映射轮的映射键; 当前重映射指针 crp; 存储子空间的累积写操作数 wc; 该存储子空间的重映射键 keys等。
存储子空间的物理地址:
struct psr {
uint64_t clsr;
};
存储子空间的物理地址的数据结构包括当前逻辑地址号 clsr,用于找到该 存储子空间的物理地址当前所对应的逻辑地址。
多路磨损均衡全局结构:
struct mult i way {
struct lsr 氺 lsrs ; struct psr 氺 psrs ;
uint64_t writes;
uint64_t swaps;
uint64_t refreshes;
} mw ;
多路磨损均衡全局结构包括存储子空间的逻辑地址数组 *lsrs、存储子空间 的物理地址数组 *psrs、 写操作总数 writes, 块交换总数 swaps和重映射总数 refreshes等。 本发明实施例的磨损均衡方法的地址重映射算法如下伪代码所示: REMAP ALGORITHM CR = LSR -〉 CR
LR = LSR -〉 LR
IF CR = LR
CR = (LR + 1) % 2
LSR -〉 KEYS [CR] = RANDOMLY GENERATED KEY
ENDIF
LOG— ADD = LSR -〉 CRP
PHY— ADD = LOG— ADD XOR LSR -〉 KEYS [CR]
PSR = FIND— PSR (PHY— ADD)
PSR— CLSR = PSR -〉 CLSR
VICTIM— PHY— ADD = LOG— ADD XOR LSR -〉 KEYS [LR]
VICTIM— PSR = FIND— PSR (VICTIM— PHY— ADD)
VICTIM— PSR— CLSR = VICTIM— PSR -〉 CLSR
PSR— CLSR— PSR— CLSR = PSR— CLSR XOR
PSR— CLSR -〉 KEYS [PSR— CLSR -〉 CR] -〉 CLSR IF PSR— CLSR = LSR
VICTIM— LSR = VICTIM— PSR— CLSR
VICTIM—LR = VICTIM— LSR -〉 LR
VICTIM—CR = VICTIM— LSR -〉 CR
VICTIM— LOG— ADD = PHY— ADD XOR VICTIM— LSR -〉 KEYS [VICTIM— LR] IF VICTIM— LOG— ADD < VICTIM— LSR -〉 CRP) {
/* ALREADY REMAPPED */
UPDATE LSR AND VICTIM— LSR
ELSE
SWAP PHY— ADD AND VICTIM— PHY— ADD
UPDATE LSR AND VICTIM— LSR
ENDIF
ELSE IF PSR— CLSR -〉 LR = PSR— CLSR -〉 CR OR (PSR— CLSR -〉 CRP = PSR— CLSRLOCK— NUM— PER— SUBREGION AND PSR— CLSR IS NOT PSR— CLSR— PSR— CLSR) PSR -〉 CLSR = LSR
VICTIM— LSR = PSR— CLSR
VICTIM—LR = VICTIM— LSR -〉 LR
VICTIM—CR = (VICTIM—LR + 1) % 2
VICTIM— LSR -〉 CR = VICTIM—CR
VICTIM— LSR -〉 KEYS [VICTIM— CR] = LSR -〉 KEYS [CR] XOR LSR -〉 KEYS [LR] VICTIM— LSR -〉 KEYS [VICTIM—LR]
VICTIM— LOG— ADD = PHY— ADD XOR VICTIM— LSR -〉 KEYS [VICTIM— LR] VICTIM— PSR -〉 CLSR = VICTIM— LSR
SWAP PHY— ADD AND VICTIM— PHY— ADD
UPDATE LSR AND VICTIM— LSR
ELSE REFRESH PSR— CLSR
ENDIF 其中 UPDATE算法描述如下:
UPDATE ALGORITHM LSR -〉 CRP++ ;
IF LSR -〉 CRP = LSR OVERFLOW
LSR -〉 CRP = FIRST ADDRESS IN THE LOGICAL SUB-REGION
LSR -〉 LR = (LSR -〉 LR + 1) % 2
IF LSR IS NOT VICTIM— LSR
VICTIM— LSR -〉 CRP = FIRST ADDRESS IN THE VICTIM LSR VICTIM— LSR -〉 LR = (VICTIM— LSR -〉 LR + 1) % 2
ENDIF 本发明实施例的磨损均衡方法的地址翻译算法描述如下所示: TRANSLATE ALGORITHM LSR = FIND— LSR (LOG— ADD)
PHY— ADD— CUR = LOG— ADD XOR LSR -〉 KEYS [LSR -〉 CR]
PHY— ADD— PRE = LOG— ADD XOR LSR -〉 KEYS [LSR -〉 LR]
IF LSR -〉 LR = LSR -〉 CR
RETURN PHY— ADD— PRE
ELSE
PSR— CUR = F誦— PSR (PHY— ADD— CUR)
PSR— CUR— CLSR = PSR— CUR -〉 CLSR
IF PSR— CUR— CLSR = LSR
IF LOG— ADD < LSR -〉 CRP RETURN PHY— ADD— CUR
ELSE
PSR— PRE = F誦— PSR (PHY— ADD— PRE)
PSR— PRE— CLSR = PSR— PRE -〉 CLSR
VICTIM—LSR = PSR— PRE— CLSR
VICTIM— LOG— ADD = PHY— ADD— CUR XOR
VICTIM—LSR -〉 KEYS [VICTIM—LSR -〉 LR]
IF VICTIM— LOG— ADD < VICTIM— LSR -〉 CRP
RETURN PHY— ADD— CUR
ELSE
RETURN PHY— ADD— PRE
ENDIF ENDIF ELSE
RETURN PHY— ADD— PRE
ENDIF ENDIF 图 5为本发明实施例五提供的存储装置的结构示意图。 如图 5所示, 该 存储装置 500可以包括:
存储空间 501 , 该存储空间包括多个大小相同的存储子空间,每个存储子 空间包括多个大小相同的存储块, 每个存储块对应一个逻辑地址和一个物理 地址, 所述逻辑地址和物理地址具有唯一映射的关系; 该存储空间的存储介 质可以是相变存储、 闪存 flash等;
记录单元 503 , 用于记录每个存储子空间的累积写操作次数;
重映射单元 505 ,用于当多个存储子空间中的任意一个存储子空间的累积 写操作次数达到预定的重映射率时, 将存储子空间的逻辑地址映射到重映射 物理地址。
具体的, 重映射单元 505可以包括:
生成单元 5051 , 用于对存储子空间生成重映射键;
运算单元 5053 ,用于将存储子空间的逻辑地址与重映射键进行异或操作, 得到存储子空间的重映射物理地址, 从而实现将存储子空间的逻辑地址映射 到重映射物理地址。
具体的, 存储子空间的存储块逻辑地址可以包括存储子空间键和存储块 键, 存储子空间键可以用于标识存储子空间, 存储块键可以用于标识存储子 空间的存储块;
具体的, 生成单元 5051可以包括:
第一生成子单元 50511 , 用于对存储子空间生成重映射键, 重映射键的位 数与存储子空间的存储块逻辑地址的位数相同;
运算单元 5053可以包括:
运算子单元 50531 ,用于将存储子空间的每一存储块逻辑地址与重映射键 进行异或操作, 得到每一存储块的重映射物理地址, 从而实现将存储子空间 的逻辑地址映射到重映射物理地址。
具体的, 存储子空间中的存储块逻辑地址可以以长度为 Log2N的二进制 数串 MA表示,二进制数串 MA中连续的 Log2(N/n)位为存储子空间键 Region key, 二进制数串 MA中连续的 Log2n位为存储块键 Block key, 其中 N为存 储空间的存储块总数, n为每个存储子空间的存储块数量;
第一生成子单元 50511可以具体用于对存储子空间生成重映射键 Key,重 映射键 Key的长度 KeySize = Log2N;
运算子单元 50531 可以具体用于将存储子空间中的每一存储块逻辑地址 MA与重映射键 Key进行异或操作,得到每一存储块的重映射物理地址 RMA, 即 RMA = MA XOR Key, 其中 XOR表示异或操作。 具体的, 记录单元 503可以包括:
确定单元 5031 , 用于根据每一次写操作对应的存储块地址确定存储块所 属的存储子空间;
计数单元 5033 , 用于记录该存储子空间的累积写操作次数。
具体的, 该存储装置 500还包括:
归零单元 507, 用于将存储子空间 501的累积写操作次数归零, 指示存储 子空间 501进入下一个重映射轮。
具体的, 重映射单元 505还可以用于当存储子空间 501进入下一个重映 射轮后, 对存储子空间 501 生成本重映射轮新的重映射键, 当新的重映射键 与上一个重映射轮的重映射键相同时, 将存储子空间 501 的逻辑地址与重映 射键进行异或操作, 得到本重映射轮中存储子空间 501的重映射物理地址。
具体的, 重映射单元 505还可以用于当存储子空间进入下一个重映射轮 后, 对存储子空间生成新的重映射键; 当新的重映射键与上一重映射轮的重 映射键不相同时, 判断本重映射轮中存储子空间的重映射物理地址是否与存 储子空间的伙伴存储子空间的重映射物理地址相同; 如果相同, 则根据存储 子空间的重映射键更新伙伴存储子空间的重映射键, 得到更新后的伙伴存储 子空间的重映射键; 根据更新后的伙伴存储子空间的重映射键, 确定伙伴存 储子空间的重映射物理地址。
在本发明实施例中, 多个存储子空间的地址重映射可以同时进行。 如果 一个存储子空间其中的所有存储块完成了重映射, 那么该存储子空间将立即 进入下一个重映射轮继续进行重映射。 本发明实施例中, 多个存储子空间的 地址重映射是多路并行进行的, 可以使得磨损均衡速度更快。
通过本发明实施例存储装置, 可以将局部的写操作过多的数据块的逻辑 地址映射到全物理存储空间, 从而避免局部数据过热, 延长存储介质的使用 寿命。 图 6 为本发明实施例六提供的存储装置的结构示意图。 本发明实施例六 的存储装置是基于实施例五的存储装置改进的。如图 6所示, 该存储装置 600 除了包括存储空间 601、 记录单元 603和重映射单元 605之外, 还可以包括: 逻辑地址确定单元 607,用于确定访问操作地址所属的存储子空间 601的 逻辑地址;
翻译单元 609, 用于将存储子空间 601的逻辑地址翻译成物理块地址。 具体的, 翻译单元 609可以包括:
第一物理地址确定单元 6091 , 用于确定该存储子空间逻辑地址在上一重 映射轮中映射到的物理地址;
第二物理地址确定单元 6093 , 用于确定该存储子空间逻辑地址在当前重 映射轮映射到的物理地址;
翻译子单元 6095 , 用于当该存储子空间或者该存储子空间的伙伴存储子 空间已经在当前重映射轮完成了地址重映射时, 确定翻译后的物理块地址为 当前重映射轮映射到的物理地址; 否则确定翻译后的物理块地址为上一重映 射轮中映射到的物理地址。
本发明实施例通过记录每个存储子空间的累积写操作次数, 当多个存储 子空间中的任意一个存储子空间的累积写操作次数达到预定的重映射率时, 将存储子空间的逻辑地址映射到重映射物理地址, 当该存储子空间被访问时, 将该存储子空间的逻辑地址翻译成对应的重映射物理地址, 实现对重映射后 存储子空间逻辑地址的翻译, 完成访问操作。 图 7为本发明实施例六提供的信息系统的结构示意图。 如图 6所示, 该 信息系统 700可以包括中央处理器 701以及至少一个如实施例五和六所描述 的存储装置 7031 , ··. , 703η; 该存储装置的存储介质可以是相变存储、 闪存 flash等; 其中:
中央处理器 701用于对存储装置 7031 , ··. , 703η进行控制; 存储装置 7031 , …, 703η用于根据中央处理器 701的指令对信息进行存 储或访问。
该信息系统可以集成在服务器、 电信系统、 网络系统、 数据中心, 以及 计算机、 移动终端等消费电子中。
在本发明实施例中, 多个存储子空间的地址重映射可以同时进行。 如果 一个存储子空间其中的所有存储块完成了重映射, 那么该存储子空间将立即 进入下一个重映射轮继续进行重映射。 本发明实施例中, 多个存储子空间的 地址重映射是多路并行进行的, 可以使得磨损均衡速度更快。
通过本发明实施例信息系统中的存储装置, 可以将局部的写操作过多的 数据块的逻辑地址映射到全物理存储空间, 从而避免局部数据过热, 延长存 储装置的使用寿命。 本领域普通技术人员可以理解: 实现上述方法实施例的全部或部分步骤 可以通过程序指令相关的硬件来完成, 前述的程序可以存储于一计算机可读 取存储介质中, 该程序在执行时, 执行包括上述方法实施例的步骤; 而前述 的存储介质包括: ROM、 RAM, 磁碟或者光盘等各种可以存储程序代码的介 质。
最后应说明的是: 以上实施例仅用以说明本发明的技术方案, 而非对其 限制; 尽管参照前述实施例对本发明进行了详细的说明, 本领域的普通技术 人员应当理解: 其依然可以对前述各实施例所记载的技术方案进行修改, 或 者对其中部分技术特征进行等同替换; 而这些修改或者替换, 并不使相应技 术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1、 一种磨损均衡方法, 其特征在于, 存储空间被分割成多个大小相同的存 储子空间,每个存储子空间被分割成多个大小相同的存储块, 每个存储块对应一 个逻辑地址和一个物理地址, 所述逻辑地址和物理地址具有唯一映射的关系; 所述方法包括:
记录所述每个存储子空间的累积写操作次数;
当所述多个存储子空间中的任意一个存储子空间的累积写操作次数达到预 定的重映射率时, 将所述存储子空间的逻辑地址映射到重映射物理地址。
2、 根据权利要求 1所述的方法, 其特征在于, 所述将存储子空间的逻辑地 址映射到重映射物理地址包括:
对所述存储子空间生成重映射键;
将所述存储子空间的逻辑地址与所述重映射键进行异或操作, 得到所述存 储子空间的重映射物理地址, 从而实现将所述存储子空间的逻辑地址映射到重 映射物理地址。
3、 根据权利要求 2所述的方法, 其特征在于, 所述存储子空间的存储块逻 辑地址包括存储子空间键和存储块键, 所述存储子空间键用于标识所述存储子 空间, 所述存储块键用于标识所述存储子空间的存储块;
所述对存储子空间生成重映射键包括:
对所述存储子空间生成重映射键, 所述重映射键的位数与所述存储子空间 的存储块逻辑地址的位数相同;
所述将存储子空间的逻辑地址与所述重映射键进行异或操作, 得到所述存 储子空间的重映射物理地址包括:
将所述存储子空间的每一存储块逻辑地址与所述重映射键进行异或操作, 得到所述每一存储块的重映射物理地址, 从而实现将所述存储子空间的逻辑地 址映射到重映射物理地址。
4、 根据权利要求 3所述的方法, 其特征在于, 所述存储子空间中的存储块 逻辑地址以长度为 Log2N的二进制数串 MA表示, 所述二进制数串 MA中连续 的 Log2(N/n)位为存储子空间键 Region key,所述二进制数串 MA中连续的 Log2n 位为存储块键 Block key, 其中 N为所述存储空间的存储块总数, n为每个存储 子空间的存储块数量;
所述对存储子空间生成重映射键包括:
对所述存储子空间生成重映射键 Key, 所述重映射键 Key的长度 KeySize = Log2N;
所述将所述存储子空间的每一存储块逻辑地址与所述重映射键进行异或操 作, 得到所述每一存储块的重映射物理地址包括:
将所述存储子空间中的每一存储块逻辑地址 MA与所述重映射键 Key进行 异或操作, 得到所述每一存储块的重映射物理地址 RMA, 即 RMA = MA XOR Key, 其中 XOR表示异或操作。
5、 根据权利要求 1 - 4 中任一项的所述方法, 其特征在于, 所述记录所述 每个存储子空间的累积写操作次数包括:
根据每一次写操作对应的存储块地址确定所述存储块所属的存储子空间, 记录该存储子空间的累积写操作次数。
6、 根据权利要求 1 - 4 中任一项的所述方法, 其特征在于, 在将所述存储 子空间的逻辑地址映射到重映射物理地址之后, 还包括:
将所述存储子空间的累积写操作次数归零, 所述存储子空间进入下一个重 映射轮。
7、 根据权利要求 6的所述方法, 其特征在于, 还包括:
当所述存储子空间进入下一个重映射轮后, 对所述存储子空间生成本重映 射轮新的重映射键, 当所述新的重映射键与上一个重映射轮的重映射键相同时, 将所述存储子空间的逻辑地址与所述重映射键进行异或操作, 得到本重映射轮 中所述存储子空间的重映射物理地址。
8、 根据权利要求 6的所述方法, 其特征在于, 还包括: 当所述存储子空间进入下一个重映射轮后, 对所述存储子空间生成新的重 映射键;
当所述新的重映射键与上一重映射轮的重映射键不相同时, 判断本重映射 轮中所述存储子空间的重映射物理地址是否与所述存储子空间的伙伴存储子空 间的重映射物理地址相同;
如果相同, 则根据所述存储子空间的重映射键更新所述伙伴存储子空间的 重映射键, 得到更新后的所述伙伴存储子空间的重映射键;
根据所述更新后的所述伙伴存储子空间的重映射键, 确定所述伙伴存储子 间的重映射物理地址。
9、 根据权利要求 1 - 4任一项所述的方法, 其特征在于, 在对所述存储子 空间进行地址重映射之后, 还包括:
确定访问操作地址所属的存储子空间逻辑地址;
将所述存储子空间逻辑地址翻译成物理块地址。
10、 根据权利要求 9所述的方法, 其特征在于, 所述将存储子空间逻辑地 址翻译成物理块地址包括:
确定该存储子空间逻辑地址在上一重映射轮中映射到的物理地址; 确定该存储子空间逻辑地址在当前重映射轮映射到的物理地址;
当该存储子空间或者该存储子空间的伙伴存储子空间已经在当前重映射轮 完成了地址重映射时, 翻译后的物理块地址为当前重映射轮映射到的物理地址; 否则, 翻译后的物理块地址为上一重映射轮中映射到的物理地址。
11、 一种存储装置, 其特征在于, 包括:
存储空间,所述存储空间包括多个大小相同的存储子空间, 所述每个存储子 空间包括多个大小相同的存储块, 所述每个存储块对应一个逻辑地址和一个物 理地址, 所述逻辑地址和物理地址具有唯一映射的关系;
记录单元, 用于记录所述每个存储子空间的累积写操作次数;
重映射单元, 用于当所述多个存储子空间中的任意一个存储子空间的累积 写操作次数达到预定的重映射率时, 将所述存储子空间的逻辑地址映射到重映 射物理地址。
12、根据权利要求 11所述的存储装置, 其特征在于, 所述重映射单元包括: 生成单元, 用于对所述存储子空间生成重映射键;
运算单元, 用于将所述存储子空间的逻辑地址与所述重映射键进行异或操 作, 得到所述存储子空间的重映射物理地址, 从而实现将所述存储子空间的逻 辑地址映射到重映射物理地址。
13、 根据权利要求 12所述的存储装置, 其特征在于, 所述存储子空间的存 储块逻辑地址包括存储子空间键和存储块键, 所述存储子空间键用于标识所述 存储子空间, 所述存储块键用于标识所述存储子空间的存储块;
所述生成单元包括:
第一生成子单元, 用于对所述存储子空间生成重映射键, 所述重映射键的 位数与所述存储子空间的存储块逻辑地址的位数相同;
所述运算单元包括:
运算子单元, 用于将所述存储子空间的每一存储块逻辑地址与所述重映射 键进行异或操作, 得到所述每一存储块的重映射物理地址, 从而实现将所述存 储子空间的逻辑地址映射到重映射物理地址。
14、 根据权利要求 13所述的存储装置, 其特征在于, 所述存储子空间中的 存储块逻辑地址以长度为 Log2N的二进制数串 MA表示, 所述二进制数串 MA 中连续的 Log2(N/n)位为存储子空间键 Region key, 所述二进制数串 MA中连续 的 Log2n位为存储块键 Block key, 其中 N为所述存储空间的存储块总数, n为 每个存储子空间的存储块数量;
所述第一生成子单元具体用于对所述存储子空间生成重映射键 Key,所述重 映射键 Key的长度 KeySize = Log2N;
所述运算子单元具体用于将所述存储子空间中的每一存储块逻辑地址 MA 与所述重映射键 Key 进行异或操作, 得到所述每一存储块的重映射物理地址 RMA, 即 RMA = MA XOR Key, 其中 XOR表示异或操作。
15、 根据权利要求 11 - 14中任一项的所述存储装置, 其特征在于, 所述记 录单元包括:
确定单元, 用于根据每一次写操作对应的存储块地址确定所述存储块所属 的存储子空间;
计数单元, 用于记录该存储子空间的累积写操作次数。
16、根据权利要求 11 - 14中任一项的所述存储装置, 其特征在于,还包括: 归零单元, 用于将所述存储子空间的累积写操作次数归零, 指示所述存储 子空间进入下一个重映射轮。
17、 根据权利要求 16的所述存储装置, 其特征在于,
所述重映射单元还用于当所述存储子空间进入下一个重映射轮后, 对所述 存储子空间生成本重映射轮新的重映射键, 当所述新的重映射键与上一个重映 射轮的重映射键相同时, 将所述存储子空间的逻辑地址与所述重映射键进行异 或操作, 得到本重映射轮中所述存储子空间的重映射物理地址。
18、 根据权利要求 16的所述存储装置, 其特征在于, 所述重映射单元还用 于当所述存储子空间进入下一个重映射轮后, 对所述存储子空间生成新的重映 射键; 当所述新的重映射键与上一重映射轮的重映射键不相同时, 判断本重映 射轮中所述存储子空间的重映射物理地址是否与所述存储子空间的伙伴存储子 空间的重映射物理地址相同; 如果相同, 则根据所述存储子空间的重映射键更 新所述伙伴存储子空间的重映射键, 得到更新后的所述伙伴存储子空间的重映 射键; 根据所述更新后的所述伙伴存储子空间的重映射键, 确定所述伙伴存储 子空间的重映射物理地址。
19、 根据权利要求 11 - 14所述的存储装置, 其特征在于, 还包括: 逻辑地址确定单元, 用于确定访问操作地址所属的存储子空间逻辑地址; 翻译单元, 用于将所述存储子空间逻辑地址翻译成物理块地址。
20、 根据权利要求 19所述的存储装置, 其特征在于, 所述翻译单元包括: 第一物理地址确定单元, 用于确定该存储子空间逻辑地址在上一重映射轮 中映射到的物理地址;
第二物理地址确定单元, 用于确定该存储子空间逻辑地址在当前重映射轮 映射到的物理地址;
翻译子单元, 用于当该存储子空间或者该存储子空间的伙伴存储子空间已 经在当前重映射轮完成了地址重映射时, 确定翻译后的物理块地址为当前重映 射轮映射到的物理地址; 否则确定翻译后的物理块地址为上一重映射轮中映射 到的物理地址。
21、 一种信息系统, 其特征在于, 包括中央处理器以及至少一个如权利要 求 11 - 20所述的存储装置; 其中,
所述中央处理器用于对存储装置进行控制; 所述存储装置用于根据中央处 理器的指令对信息进行存储或访问。
PCT/CN2012/077403 2011-06-24 2012-06-25 磨损均衡方法、存储装置及信息系统 Ceased WO2012175048A1 (zh)

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