WO2013060285A1 - 栅线驱动方法、移位寄存器、栅线驱动装置及显示设备 - Google Patents

栅线驱动方法、移位寄存器、栅线驱动装置及显示设备 Download PDF

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Publication number
WO2013060285A1
WO2013060285A1 PCT/CN2012/083558 CN2012083558W WO2013060285A1 WO 2013060285 A1 WO2013060285 A1 WO 2013060285A1 CN 2012083558 W CN2012083558 W CN 2012083558W WO 2013060285 A1 WO2013060285 A1 WO 2013060285A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
shift register
gate
node
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PCT/CN2012/083558
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English (en)
French (fr)
Inventor
曹昆
胡明
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Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Priority to EP12790780.6A priority Critical patent/EP2772902B1/en
Priority to US13/805,414 priority patent/US20140050294A1/en
Priority to JP2014537480A priority patent/JP2015502564A/ja
Priority to KR1020127032628A priority patent/KR101459521B1/ko
Publication of WO2013060285A1 publication Critical patent/WO2013060285A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • Gate line driving method shift register, gate line driving device and display device
  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a gate line driving method, a shift register, a gate line driving device, and a display device. Background technique
  • the pixel array of the liquid crystal display includes staggered multi-row gate lines and multi-column data lines.
  • the driving of the gate line can be realized by the attached integrated driving circuit.
  • the gate line driving circuit can be integrated on the thin film transistor array substrate to form a shift register to drive the gate line.
  • a gate line driving device composed of a plurality of shift registers provides a switching signal for the plurality of rows of gate lines of the pixel array, thereby controlling the plurality of rows of gate lines to be sequentially turned on, and charging the pixel electrodes of the corresponding rows in the pixel array by the data lines to A gray voltage required to display each gray scale of the image is formed, and each frame image is displayed.
  • the turn-on and turn-off of the thin film transistors are required to turn on or off the gate lines of the corresponding rows.
  • the thin film transistor cannot be turned on normally due to a wide-voltage voltage shift (here, a positive offset, that is, an increase in the threshold voltage).
  • the increase in the threshold voltage of the open thin film transistor is related to the voltage applied to its source and gate.
  • Embodiments of the present invention provide a gate line driving method, a shift register, a gate line driving device, and a display device, which can improve the stability of the operation of the shift register.
  • a gate line driving method including:
  • a shift register including:
  • a first thin film transistor having a gate and a source connected together and connected to an upper trigger signal terminal, and a drain connected to a first node as a pull-up node;
  • a second thin film transistor having a gate connected to the first node, a source connected to the clock signal end, and a drain connected to the output end of the current stage;
  • a reset module connected between the second node as the pull-down node, the clock signal end and the low-level signal end, for loading the drain and the gate of the second thin film transistor with a low level after the output of the current stage is completed ;
  • a feedback receiving module is connected between the first node, the low-level signal end and the output end of the current stage, and is connected to the lower-level feedback signal end for receiving the lower-level feedback signal to output the first node and the current stage The level of the terminal is pulled low.
  • a gate line driving device comprising a plurality of shift registers as described above connected in series.
  • a display device comprising a pixel array and a gate line driving device as described above.
  • Embodiments of the present invention provide a gate line driving method, a shift register, a gate line driving device, and a display device. If a gate of a thin film transistor is pressed for a long time, it is easily formed in a gate insulating layer of the thin film transistor. And accumulating electrons, resulting in a threshold voltage shift of the thin film transistor. By loading a high level at the source of the thin film transistor and a low level of the gate loading, according to the tunneling effect and the principle of quantum mechanics, electrons formed and accumulated in the gate insulating layer can pass through the barrier to reach the source of the thin film transistor.
  • FIG. 1 is a schematic diagram of a gate line driving method according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a specific embodiment of a shift register of the present invention.
  • FIG. 4 is a timing control diagram of the shift register shown in FIG. 3;
  • 5 is a schematic diagram of the operation of the shift register shown in FIG. 3 in the tl phase
  • 6 is a schematic diagram of the operation of the shift register shown in FIG. 3 in the t2 phase
  • Figure 7 is a schematic diagram of the operation of the shift register shown in Figure 3 in the t3 phase
  • Figure 8 is a schematic diagram of the operation of the shift register shown in Figure 3 in the t4 phase
  • FIG. 9 is a schematic diagram of a gate line driving device according to an embodiment of the present invention. detailed description
  • source and drain names defined in the embodiments of the present invention are interchangeable, and the direction of the arrow in the figure only indicates that the TFT is turned on, and does not indicate the conduction direction.
  • FIG. 1 is a schematic diagram of a gate line driving method according to the present invention.
  • the gate line driving method includes: Step 11: reducing a threshold voltage shift of a thin film transistor in a shift register corresponding to a row of gate lines;
  • Step 12 Apply a voltage to a gate of the thin film transistor in the shift register to turn on the thin film transistor, thereby providing a row scan signal to the row gate line to drive the row gate line to open.
  • the shift register circuit can be operated normally, the stability of the shift register operation is improved, and the working life of the shift register is prolonged.
  • the threshold voltage offset of the inner thin film transistor can include:
  • Step 111 The electrons accumulated on the gate insulating layer of the thin film transistor reach the source of the thin film transistor to reduce the threshold voltage shift of the thin film transistor.
  • the threshold voltage shift of the inner thin film transistor may include not only the above step 111 but also other steps such as bringing the electrons accumulated on the passivation layer to the source of the thin film transistor and the like.
  • the electrons accumulated on the gate insulating layer of the thin film transistor reach the source of the thin film transistor, including: loading a high level of the source of the thin film transistor, and a gate loading low level, so as to insulate the gate of the thin film transistor
  • the electrons accumulated on the layer reach the source of the thin film transistor.
  • the source of the thin film transistor is loaded with a high level and the gate is loaded with a low level, according to the tunneling effect and the quantum mechanical principle, electrons formed and accumulated in the gate insulating layer of the thin film transistor can pass through the barrier to reach the thin film transistor.
  • the source thereby reducing the threshold voltage shift of the thin film transistor due to the accumulation of electrons in the gate insulating layer of the thin film transistor.
  • the shift register in this embodiment includes three thin film transistors, a storage capacitor, a reset module, a feedback receiving module, and corresponding input and output terminals. Specifically include:
  • a first thin film transistor M1 having a gate and a source connected together and connected to the upper trigger signal terminal Input (n), and a drain connected to the first node PU as a pull-up node, the function of which is to be triggered by the upper stage
  • the high-level signal sent by the signal terminal Input ( n ) controls the shift register to start working, wherein the upper-level trigger signal terminal Input ( n ) is in the output terminal of the upper-stage shift register (ie, the n-1th-stage shift register).
  • Output (n-1) receives a high level signal when it is a high level output;
  • the second thin film transistor M2 has a gate connected to the first node PU, a source connected to the clock signal end, and a drain connected to the output terminal Output (n) of the current stage, and the function is to provide the output (Out) of the stage a high level output to drive a row of gate lines corresponding to the shift register of the stage (ie, the nth stage shift register) to be turned on;
  • a third thin film transistor M3 having a gate connected to the first node PU, a source connected to the clock signal terminal, and a drain connected to the lower trigger signal terminal Input (n+1), the role of which is a lower shift register (ie, The n+1 stage shift register provides a trigger signal to control the operation of the lower shift register; the capacitor C1 is connected between the first node PU and the output of the stage (Out); the reset module 1 is connected as a pulldown
  • the second node PL of the node, the clock signal terminal and the low-level signal terminal Vss are used for the drain and gate forces of the second thin film transistor M2 after the output of the current stage is completed. Load low level;
  • the feedback receiving module 2 is connected to the first node PU, the low-level signal terminal Vss, and the output of the current stage.
  • the signal is fed to lower the level of the first node PU and the output terminal Output (n), wherein the lower feedback signal end Reset (n+1) is in the lower shift register (ie, the n+1th shift register)
  • the output of the current stage, Output (n+1) receives a high level signal when it is a high level output.
  • the lower feedback signal end Reset (n+1) may be connected to the output terminal Output (n+1) of the lower stage shift register (ie, the n+1th stage shift register), or may be connected to the lower stage shift register ( That is, the lower trigger signal terminal Input (n+2) of the n+1th shift register is connected.
  • the shift register includes three thin film transistors in Fig. 2, the embodiment of the present invention is not limited thereto.
  • the third thin film transistor M3 may not be included, and the output terminal Output (n) connected to the drain of the second thin film transistor M2 is directly used as the lower level trigger signal. End Input ( n+1 ).
  • a shift register includes two thin film transistors, a storage capacitor, a reset module, a feedback receiving module, and corresponding input and output terminals. Specifically include:
  • the first thin film transistor M1 has a gate and a source connected together and connected to the upper trigger signal terminal Input (n), and a drain connected to the first node PU as a pull-up node, and the function is to receive the trigger from the upper stage.
  • the high-level signal sent by the signal terminal Input (n) controls the shift register to start working, wherein the upper-level trigger signal terminal Input (n) is at the output terminal of the upper-stage shift register (ie, the n-1th-stage shift register).
  • Output (n-1) receives a high level signal when it is a high level output;
  • a second thin film transistor M2 having a gate connected to the first node PU, a source connected to the clock signal terminal, a drain connected to the output terminal Output (n), and connected to the lower trigger signal terminal Input (n+1). Its function is to provide a high level output for the output (Out) of the stage to drive a row of gate lines corresponding to the shift register of the stage (ie, the nth stage shift register) to be turned on, and is a lower shift register (ie The n+1th shift register provides a trigger signal to control the operation of the lower shift register;
  • the capacitor C1 is connected between the first node PU and the output terminal Output (n) of the current stage; the reset module 1 is connected between the second node PL as a pull-down node, the clock signal end and the low-level signal end Vss, After the output of this stage is completed, it is the drain and gate force of the second thin film transistor M2. Load low level;
  • the feedback receiving module 2 is connected between the first node PU, the low-level signal terminal Vss and the output terminal Output(n) of the current stage, and is connected with the lower-level feedback signal end Reset (n+1) for receiving the lower-level feedback signal.
  • the feed signal Reset (n+1) receives a high level signal when the output terminal Output (n+1) of the lower stage shift register (i.e., the n+1th stage shift register) is a high level output.
  • the lower feedback signal end Reset (n+1) may be connected to the lower stage shift register (ie, the n+1th stage shift register) of the present stage output terminal Output (n+1), or may be used according to the present embodiment.
  • Other thin film transistors such as M3 in FIG. 2 are added to the lower shift register (ie, the n+1th shift register) to provide the lower feedback signal end Reset (n+1).
  • the shift register provided by the embodiment of the present invention, if a thin film transistor is always pressurized, electrons are easily formed and accumulated in the gate insulating layer of the thin film transistor, thereby causing a threshold voltage shift of the thin film transistor.
  • a threshold voltage shift of the thin film transistor By loading a high level at the source of the thin film transistor and a low level of the gate loading, according to the tunneling effect and the principle of quantum mechanics, electrons formed and accumulated in the gate insulating layer of the thin film transistor can pass through the barrier to reach the thin film.
  • the source of the transistor thereby reducing the threshold voltage shift of the thin film transistor in the shift register corresponding to each row of gate lines, finally enabling the shift register circuit to work normally, improving the stability of the shift register operation, and extending the shift The working life of the bit register.
  • the threshold voltage of the corresponding thin film transistor is shifted, so that each thin film transistor in the shift register can be used.
  • the reset module 1 is set to apply a high level to the source of the thin film transistor after the output of the shift register is completed, and the gate is loaded with a low level, so that the electrons in the gate insulating layer of the thin film transistor reach the source of the thin film transistor.
  • the pole is used to reduce the threshold voltage shift of the thin film transistor.
  • the second thin film transistor M2 in the shift register, can turn on the clock signal end and the output terminal of the current stage, so that a row of gate lines corresponding to the shift register is turned on, so the second thin film transistor M2 is in the shift register. It has a very important role. Once the second thin film transistor M2 cannot be normally turned on due to the threshold voltage shift, the display effect will be affected. In addition, the operating current on the second thin film transistor M2 is generally large, which easily causes a threshold voltage shift. Therefore, in the embodiment, the second thin film transistor M2 is taken as an example to explain how to reduce the threshold voltage offset by the reset module 1. It should be understood that the description is illustrative and not restrictive.
  • the shift register includes fourteen thin film transistors, a storage capacitor, and corresponding input and output terminals.
  • the fourteen thin film transistors are: a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, and a seventh thin film transistor.
  • the storage capacitor is capacitor C1.
  • the input and output terminals include: an upper trigger signal terminal Input (n) that receives the trigger signal of the upper shift register, an output terminal Output (n) of the current stage output level signal of the shift register, and a trigger signal for the lower shift register.
  • the lower trigger signal terminal Input (n+1), the lower feedback signal terminal Reset (n+1) receiving the lower shift register feedback signal, the low level signal terminal Vss, and the clock signal end, the clock signal end includes the first The clock signal terminal CLK and the second clock signal terminal CLKB, the clock signal of the first clock signal terminal CLK and the clock signal of the second clock signal terminal CLKB are exactly the same, and only the phases are 180° out of phase.
  • the first thin film transistor M1 has a gate and a source connected together and connected to the upper trigger signal terminal Input ( n ), and a drain connected to the first node PU as a pull-up node;
  • the second thin film transistor M2 The gate is connected to the first node PU, the source is connected to the first clock signal terminal CLK, and the drain is connected to the output terminal Output (n) of the current stage;
  • the third thin film transistor M3 has a gate connected to the first node PU, The source is connected to the first clock signal terminal CLK, and the drain is connected to the lower trigger signal terminal Input (n+1);
  • the fourth thin film transistor M4 has a gate connected to the lower feedback signal terminal Reset (n+1), and the source Connected to the output of the current stage, Output (n), and the drain and low level signal terminal Vss;
  • the tenth thin film transistor M10 has a gate connected to the drain of the fourth reset thin film transistor T4 in the reset module 1, the source output terminal Output (n), and the drain The low level signal terminal Vss is connected.
  • a first reset thin film transistor T1 having a gate connected to the second node PL, a source connected to the drain of the third reset thin film transistor T3, and a drain connected to the low level signal terminal Vss; and a second reset thin film transistor T2
  • the gate is connected to the second node PL, the source is connected to the drain of the fourth reset thin film transistor T4, and the drain is connected to the low level signal terminal Vss;
  • the third reset thin film transistor T3 has the gate and the source and the first
  • the clock signal terminal CLK is connected, the drain is connected to the source of the first reset thin film transistor T1, and the fourth reset thin film transistor T4 has a gate and a third reset film.
  • the drain of the transistor T3 is connected, the source is connected to the first clock signal terminal CLK, and the drain is connected to the source of the second reset thin film transistor T2.
  • the storage capacitor C1 is connected between the first node PU and the output of the stage (Out).
  • the structures of the first reset thin film transistor T1, the second reset thin film transistor ⁇ 2, the third reset thin film transistor ⁇ 3, and the fourth reset thin film transistor ⁇ 4 are the same as those of the first thin film transistor M1 to the tenth thin film transistor M10, etc.
  • a reset thin film transistor T1, a second reset thin film transistor ⁇ 2, a third reset thin film transistor ⁇ 3, and a fourth reset thin film transistor ⁇ 4 constitute the reset module 1 in the present embodiment, and thus the first thin film transistor M1 to the tenth thin film Transistor M10 is distinguished by name.
  • the first reset thin film transistor T1, the second reset thin film transistor ⁇ 2, the third reset thin film transistor ⁇ 3, and the fourth reset thin film transistor ⁇ 4 constitute the reset module 1 in this embodiment, and the reset module 1 is used at this level.
  • the source of the second thin film transistor ⁇ 2 is loaded with a high level and the gate is loaded with a low level, so that according to the tunneling effect and the principle of quantum mechanics, the second thin film transistor ⁇ 2 can be formed and accumulated in the gate insulating layer.
  • Electrons pass through the barrier to reach the source of the second thin film transistor T2, thereby reducing the threshold voltage shift of the second thin film transistor T2 in the shift register corresponding to each row of gate lines, and finally enabling the shift register circuit to work normally. , improve the stability of the shift register operation, and extend the working life of the shift register.
  • the fourth thin film transistor ⁇ 4 and the fifth thin film transistor ⁇ 5 constitute a feedback receiving module 2.
  • the feedback receiving module 2 is configured to keep the output terminal Output(n) of the current stage and the first node PU as the pull-up node low when the shift register of the stage is not working and the lower shift register operates, thereby avoiding the following Situation: Output (n) of this stage becomes high level under the action of other interference signals, and its controlled gate line is opened under the action of high level, which eventually causes the gate line to open incorrectly.
  • the fourth thin film transistor M4 is configured to maintain the output terminal Output (n) of the current stage as a low level by the lower feedback signal end Reset (n+1), and the fifth thin film transistor M5 is used for the lower feedback signal end.
  • the first node PU is kept low by the action of Reset (n+1) to prevent the second thin film transistor M2 from being erroneously turned on.
  • the shift register further includes a sixth thin film transistor M6.
  • the sixth thin film transistor M6 is configured to pull the second node PL as a pull-down node low by receiving a high level signal of the second clock signal terminal CLKB when the shift register of the stage is not operating, thereby avoiding the following situation:
  • the output Output (n) turns to a high level under the action of other interfering signals, and causes a row of gate lines controlled by it to open at a high level, eventually causing a gate line opening error.
  • the shift register further includes a seventh thin film transistor M7.
  • the seventh thin film transistor M7 is configured to accelerate the storage capacitor C1 when the upper trigger signal terminal Input (n) is at a high level and the second clock signal terminal CLKB is at a high level.
  • the shift register further includes an eighth thin film transistor M8.
  • the eighth thin film transistor M8 is used for the time when the output terminal Output(n) of the current stage is at a high level (that is, during the working time of the shift register of the current stage), and the first node PU is maintained in a high level state, and continues to be
  • the capacitor C1 is charged to further increase the opening capability of the second thin film transistor M2.
  • the shift register further includes a ninth thin film transistor M9 and a tenth thin film transistor M10, which are combined with the reset module 1 such that the gate of the second thin film transistor M2 is reset when the second thin film transistor M2 is reset. And the drain are both low, wherein the ninth thin film transistor M9 is used to pull the first node PU low to avoid the second thin film transistor M2 from being turned on by mistake, and the tenth thin film transistor M10 is used for outputting the current level The output (n) is pulled low to avoid the output (Out) of this stage becoming high.
  • the shift register includes fourteen thin film transistors in Fig. 3, the embodiment of the present invention is not limited thereto.
  • the third thin film transistor M3 may not be included in the shift register according to the embodiment of the present invention, and the output terminal Output (n) connected to the drain of the second thin film transistor M2 is directly used as the lower level trigger signal. End Input ( n+1 ).
  • a shift register includes thirteen thin film transistors, a storage capacitor, and corresponding input and output terminals.
  • the thirteen thin film transistors are: a first thin film transistor M1, a second thin film transistor M2, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, and an eighth thin film transistor.
  • the storage capacitor is capacitor C1.
  • the input and output terminals include: an upper-level trigger signal terminal Input (n) that receives a trigger signal of the upper-stage shift register, an output output signal that is a level-level shift register output level signal, and a trigger signal is sent to the lower-stage shift register.
  • an upper-level trigger signal terminal Input (n) that receives a trigger signal of the upper-stage shift register
  • a trigger signal is sent to the lower-stage shift register.
  • Receiving a lower feedback signal end Reset (n+1), a low level signal terminal Vss, and a clock signal end of the lower stage shift register feedback signal the clock signal end comprising a first clock signal terminal CLK and a second clock signal terminal CLKB
  • the clock signal of the first clock signal terminal CLK and the clock signal of the second clock signal terminal CLKB are exactly the same, and only the phases are 180° out of phase.
  • each of the thin film transistors in the above technical solution of the present embodiment may be a hydrogenated amorphous thin film transistor, but may be other types of thin film transistors.
  • the control timing chart of the shift register in this embodiment can be divided into four stages: t1, t2, t3, and t4.
  • the first clock signal terminal CLK and the second clock signal terminal CLKB are alternately used periodically.
  • the STV is a switching signal, that is, the upper trigger signal terminal Input ( n ), which is used to receive a high level signal from the upper shift register. Among them, 1 indicates a high level signal, and 0 indicates a low level signal. Further, in the following Figs. 5 to 8, the conduction of the thin film transistor is indicated by an arrow, and the turn-off of the thin film transistor is indicated by a cross.
  • the STV signal of the shift register of this stage is provided by the upper shift register through the upper trigger signal input Input ( n ).
  • Input ( n ) 1
  • the first thin film transistor M1 is turned on and controls the shift register of the current stage to start working, and the upper trigger signal terminal Input ( n ) passes through the first thin film transistor M1 as the storage capacitor C1.
  • CLKB 1, the seventh thin film transistor M7 is turned on, and the second clock signal terminal CLKB is accelerated by the seventh thin film transistor M7 to charge the storage capacitor C1.
  • the first node PU is pulled high to have a high level, and the second thin film transistor M2 is turned on.
  • the low level of the first clock signal terminal CLK is output to the present through the second thin film transistor M2.
  • the output terminal Output (n) the low level of the output makes the row line corresponding to the shift register of the current stage in a low state.
  • CLKB 1
  • the sixth thin film transistor M6 is turned on. The sixth thin film transistor M6 pulls the second node PL down to Vss when the shift register of the stage is not operating, and prevents the output (n) of the output of the stage from becoming high level by other interference signals.
  • the tl phase is the charging phase of the storage capacitor C1.
  • the second thin film transistor M2 is turned on by the storage capacitor CI, and outputs the high level on the first clock signal terminal CLK to the output terminal Output(n) of the current stage, and is further outputted by the output of the current stage ( n) outputting the high level to a row of gate lines corresponding to the shift register of the current stage, so that all thin film transistors located on the row gate line in the display area of the liquid crystal panel are turned on, and the data line starts to write signals.
  • the eighth thin film transistor M8 is turned on and feeds the high level on the output terminal (n) of the current stage to the first node PU, ensuring that the first node PU continues to be in a high state, continuing to be the capacitor C1.
  • the ninth thin film transistor M9 and the tenth thin film transistor M10 are turned off to ensure that the first node PU and the output terminal Output (n) of the current stage are continuously in a high state, and are not pulled low. .
  • the third thin film transistor M3 is also turned on by the storage capacitor C1, so that the lower-level trigger signal terminal Input (n+1) becomes a high level, and the trigger signal is sent to the lower-stage shift register.
  • the t2 phase outputs a high level phase of the output (Out) of the current stage of the shift register of the stage.
  • the reset signal of the shift register of this stage is passed by the lower stage shift register through the lower feedback signal end
  • the output (Out) of the current stage becomes high level under the action of other interference signals, and makes it The gate line of the control is turned on under the high level, which eventually causes the gate line to open incorrectly.
  • the t3 phase is a phase in which the output of the lower stage of the lower stage shift register Output (n+1) outputs a high level.
  • the third reset thin film transistor T3 is turned on, thereby making the fourth The gate of the reset thin film transistor T4 becomes a high level, thereby turning on the fourth reset thin film transistor T4.
  • the conduction of the fourth reset thin film transistor T4 causes the gates of the ninth thin film transistor M9 and the tenth thin film transistor M10 to become a high level, thereby turning on the ninth thin film transistor M9 and the tenth thin film transistor M10.
  • the ninth thin film transistor M9 pulls the first node PU down to Vss, and the tenth thin film transistor M10 pulls the output terminal Output(n) of the current stage to Vss, so that the second thin film transistor is reset when the second thin film transistor M2 is reset.
  • the t4 phase is a phase in which the reset module 1 operates to make the second thin film transistor M2, that is, a reset phase of the shift register of the present stage.
  • the shift register in this embodiment can reduce the threshold voltage shift of the thin film transistor in the shift register corresponding to each row of gate lines, and finally can make the shift register circuit work normally and improve the shift.
  • the stability of the register operation extends the operating life of the shift register.
  • the embodiment of the invention further provides a gate line driving device.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the gate line driving device includes a plurality of shift registers connected in series.
  • the clock signal CLK and the clock signal CLKB are alternately used periodically.
  • the clock signal terminal of the Nth stage shift register is shown as receiving the clock signal CLK
  • the clock signal terminals of the N-1th stage and the N+1th stage shift register are shown as receiving the clock signal CLKB, Therefore, the clock signal for the Nth stage shift register is completely opposite to the phase of the clock signal for the Nth - 1st and N+1th stage shift registers, that is, the phases are 180° out of phase.
  • the clock signal CLK and the clock signal CLKB are also alternately used periodically for each stage of the shift register.
  • the first clock signal terminal receives the clock signal CLK
  • the second clock signal terminal receives the clock signal CLKB.
  • the first clock signal terminal receives the clock signal CLKB
  • the second clock signal terminal receives the clock signal CLK.
  • each stage of the shift register includes three thin film transistors, a storage capacitor, a reset module, a feedback receiving module and corresponding input and output terminals. Specifically include:
  • the first thin film transistor M1 has a gate and a source connected together and connected to the upper trigger signal terminal Input (n), and a drain connected to the first node PU as a pull-up node. Its function is to control the shift register to start working when receiving a high level signal sent by the upper trigger signal terminal Input (n).
  • the upper trigger signal terminal Input (n) receives a high level signal when the output of the previous stage of the upper shift register (ie, the n-1th shift register) is output (n-1).
  • the second thin film transistor M2 has a gate connected to the first node PU, a source connected to the clock signal terminal, and a drain connected to the output terminal Output (n).
  • the third thin film transistor M3 has a gate connected to the first node PU, a source connected to the clock signal terminal, and a drain connected to the lower trigger signal terminal Input (n+1). Its role is to provide a trigger signal for the lower shift register (ie, the n+1th shift register) to control the operation of the lower shift register.
  • Capacitor C1 is connected between the first node PU and the output of the stage (Out).
  • the reset module 1 is connected between the second node PL as a pull-down node, a clock signal terminal and a low-level signal terminal Vss for loading a high level of the source of the second thin film transistor M2 after the output of the current stage is completed.
  • the gate is loaded with a low level;
  • the feedback receiving module 2 is connected between the first node PU, the low level signal terminal Vss and the output terminal Output (n) of the current stage, and is connected with the lower feedback signal end Reset (n+1) And receiving the lower feedback signal to lower the level of the first node PU and the output terminal Output (n).
  • the output Output (n) of the Nth stage shift register is fed back to the N-1th stage shift register (ie, as a lower stage).
  • the feedback signal terminal Reset (n-1) is turned off to turn off the N-1th shift register, and the lower trigger signal terminal Input (n+1) of the Nth shift register is output to the N+1th shift register. Take the trigger signal as the N+1th shift register.
  • the third thin film transistor M3 is not included in each stage shift register in the gate line driving device according to the other embodiment of the present invention, and the current connected to the drain of the second thin film transistor M2 is directly connected.
  • the stage output Output (n) is also used as the lower level trigger signal input Input (n+l).
  • the operation of the shift register is performed in accordance with an embodiment of the present invention, except that the third thin film transistor M3 is not included
  • the operation of the shift register in the gate line driving device is the same and will not be described here.
  • the gate line driving device provided by the embodiment of the present invention, since a thin film transistor is always pressurized, electrons are easily formed and accumulated in the gate insulating layer of the thin film transistor, thereby causing a threshold voltage shift of the thin film transistor.
  • a thin film transistor is always pressurized, electrons are easily formed and accumulated in the gate insulating layer of the thin film transistor, thereby causing a threshold voltage shift of the thin film transistor.
  • the source of the transistor thereby reducing the threshold voltage shift of the thin film transistor in the shift register corresponding to each row of gate lines, finally enabling the shift register circuit to work normally, improving the stability of the shift register operation, and extending the shift The working life of the bit register.
  • the shift register used in the gate line driving device of this embodiment is the same in function and structure as the shift register used in the shift register embodiment, so that the same technical problem can be solved. The same expected effect.
  • the present invention also provides a display device comprising a pixel array and a gate line driving device as described above.
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Abstract

本发明公开了一种栅线驱动方法、移位寄存器及栅线驱动装置，涉及液晶显示技术领域，为提高移位寄存器的工作稳定性而发明。所述栅线驱动方法包括：降低与每行栅线对应的移位寄存器内薄膜晶体管（M2）的阈值电压偏移；为所述移位寄存器内的薄膜晶体管（M2）的栅极加载电压以开启薄膜晶体管（M2），从而为与所述移位寄存器对应的各行栅线提供行扫描信号以驱动该行栅线打开或关闭。所述移位寄存器包括：第一薄膜晶体管（M1）、第二薄膜晶体管（M2）、第三薄膜晶体管（M3）、电容（C1）、复位模块（1）和反馈模块（2）。本发明可用于对栅线进行驱动。

Description

栅线驱动方法、 移位寄存器、 栅线驱动装置及显示设备 技术领域
本发明涉及液晶显示技术领域， 尤其涉及一种栅线驱动方法、 移位寄存 器、 栅线驱动装置及显示设备。 背景技术
液晶显示的像素阵列包括交错的多行栅线和多列数据线。 其中， 对栅线 的驱动可以通过贴附的集成驱动电路实现。 然而近几年随着非晶硅薄膜工艺 的不断提高， 也可以将栅线驱动电路集成在薄膜晶体管阵列基板上构成移位 寄存器来对栅线进行驱动。
由多个移位寄存器构成的栅线驱动装置为像素阵列的多行栅线提供开关 信号， 从而控制多行栅线依序打开， 并由数据线向像素阵列中对应行的像素 电极充电， 以形成显示图像的各灰阶所需要的灰度电压， 进而显示每一帧图 像。
在每个移位寄存器中， 需要薄膜晶体管的开启和关断来实现对应行的栅 线的打开或关闭。 但在实际工作过程中， 使用一段时间后薄膜晶体管会因为 发生阔值电压偏移（这里指正向偏移， 即阔值电压的增加）而无法正常开启。
开启薄膜晶体管的阔值电压的增加与其源极和栅极上加载的电压有关， 源极和栅极上加载的电压越大、 时间越长， 开启薄膜晶体管的阔值电压的增 加就越大。 因此如果一直为一个薄膜晶体管加压， 则该薄膜晶体管的阔值电 压偏移也会一直增大， 使得该薄膜晶体管无法正常打开， 最终导致移位寄存 器电路无法正常工作。 发明内容
本发明的实施例提供一种栅线驱动方法、 移位寄存器、 栅线驱动装置及 显示设备， 能够提高移位寄存器工作的稳定性。
根据本发明实施例， 提供了一种栅线驱动方法， 包括：
降低与一行栅线对应的移位寄存器内薄膜晶体管的阔值电压偏移； 为所述移位寄存器内的薄膜晶体管的栅极加载电压以开启薄膜晶体管， 从而为该行栅线提供行扫描信号以驱动该行栅线打开。 根据本发明实施例， 还提供了一种移位寄存器， 包括：
第一薄膜晶体管， 其栅极和源极连接在一起并与上级触发信号端连接、 漏极与作为上拉节点的第一节点连接；
第二薄膜晶体管， 其栅极与所述第一节点连接、 源极与时钟信号端连接、 漏极与本级输出端连接；
电容， 连接在所述第一节点与本级输出端之间；
复位模块， 连接在作为下拉节点的第二节点、 时钟信号端和低电平信号 端之间， 用于在本级输出完成后为所述第二薄膜晶体管的漏极和栅极加载低 电平；
反馈接收模块， 连接在所述第一节点、 低电平信号端和本级输出端之间， 并与下级反馈信号端连接， 用于接收下级反馈信号以将所述第一节点和本级 输出端的电平拉低。
根据本发明实施例， 还提供了一种栅线驱动装置， 包括相互串联的多个 如上所述的移位寄存器。
此外， 根据本发明实施例， 还提供了一种显示设备， 包括像素阵列和如 上所述的栅线驱动装置。
本发明实施例提供了一种栅线驱动方法、 移位寄存器、 栅线驱动装置和 显示设备， 如果长时间为一个薄膜晶体管的栅极加压， 则容易在该薄膜晶体 管的栅绝缘层中形成并积累电子， 从而导致该薄膜晶体管的阔值电压偏移。 通过在薄膜晶体管的源极加载高电平、 栅极加载低电平， 根据隧道效应和量 子力学的原理， 能够使栅绝缘层中形成并积累的电子穿过势垒而到达薄膜晶 体管的源极， 从而降低与每行栅线对应的移位寄存器内薄膜晶体管的阔值电 压偏移， 最终能够使移位寄存器电路正常工作， 提高了移位寄存器工作的稳 定性， 延长了移位寄存器的工作寿命。 附图说明
图 1为本发明实施例中栅线驱动方法的示意图；
图 2为本发明实施例移位寄存器的示意图；
图 3为本发明移位寄存器的一个具体实施例的示意图；
图 4为图 3所示移位寄存器的时序控制图；
图 5为图 3所示移位寄存器在 tl阶段的工作示意图； 图 6为图 3所示移位寄存器在 t2阶段的工作示意图；
图 7为图 3所示移位寄存器在 t3阶段的工作示意图；
图 8为图 3所示移位寄存器在 t4阶段的工作示意图；
图 9为本发明实施例栅线驱动装置的示意图。 具体实施方式
下面结合附图对本发明实施例栅线驱动方法、 移位寄存器、 栅线驱动装 置和显示设备进行详纟田; ^述。
应当明确， 所描述的实施例仅仅是本发明的一部分实施例， 而不是全部 的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创造性 劳动前提下所获得的所有其它实施例， 都属于本发明保护的范围。
需要说明的是： 本发明实施例中定义的源极、 漏极其实名称是可以互换 的， 而且图中的箭头方向仅表示 TFT导通， 并不表示导通方向。
如图 1所示， 为本发明栅线驱动方法的示意图。所述栅线驱动方法包括： 步骤 11 , 降低与一行栅线对应的移位寄存器内薄膜晶体管的阔值电压偏 移；
步骤 12, 为所述移位寄存器内的薄膜晶体管的栅极加载电压以开启薄膜 晶体管， 从而为与该行栅线提供行扫描信号以驱动该行栅线打开。
本发明实施例提供的栅线驱动方法， 由于如果一直为一个薄膜晶体管加 压， 则容易在该薄膜晶体管的栅绝缘层中形成并积累电子， 从而导致该薄膜 晶体管的阔值电压偏移。 通过降低与每行栅线对应的移位寄存器内薄膜晶体 管的阔值电压偏移， 能够使移位寄存器电路正常工作， 提高了移位寄存器工 作的稳定性， 延长了移位寄存器的工作寿命。
由上面所述可知， 薄膜晶体管上阔值电压的偏移一般是由于在该薄膜晶 体管的栅绝缘层上形成和积累的电子造成的， 因此上述步骤 11 , 降低与一行 栅线对应的移位寄存器内薄膜晶体管的阔值电压偏移可以包括：
步骤 111 , 使在该薄膜晶体管的栅绝缘层上积累的电子到达该薄膜晶体 管的源极， 以降低该薄膜晶体管的阔值电压偏移。
需要说明的是， 除了在薄膜晶体管的栅绝缘层上形成并积累电子能够造 成薄膜晶体管的阔值电压偏移之外， 其它原因也能造成阔值电压偏移， 如钝 化层上的电子积累等。 为此， 本实施例中降低与每行栅线对应的移位寄存器 内薄膜晶体管的阔值电压偏移不仅可以包括如上步骤 111 ,还可以包括其它的 步骤， 如使钝化层上积累的电子达到薄膜晶体管的源极等。
上述步骤 111 , 使在薄膜晶体管的栅绝缘层上积累的电子到达薄膜晶体 管的源极包括： 为薄膜晶体管的源极加载高电平、 栅极加载低电平， 以使在 薄膜晶体管的栅绝缘层上积累的电子到达薄膜晶体管的源极。
为薄膜晶体管的源极加载高电平、 栅极加载低电平后， 根据隧道效应和 量子力学原理， 能够使在薄膜晶体管的栅绝缘层中形成并积累的电子穿过势 垒而到达薄膜晶体管的源极， 从而减小由于薄膜晶体管的栅绝缘层中电子的 积累而造成的薄膜晶体管阔值电压偏移。
下面， 利用所述的栅线驱动方法， 设计制作了一种移位寄存器， 该移位 寄存器具有较高的工作稳定性。 举例而言， 如图 2所示， 本实施例中的移位 寄存器包括三个薄膜晶体管、 一个存储电容、 一个复位模块、 一个反馈接收 模块和相应的输入输出端。 具体包括：
第一薄膜晶体管 Ml , 其栅极和源极连接在一起并与上级触发信号端 Input ( n )连接、 漏极与作为上拉节点的第一节点 PU连接， 其作用是当接收 到由上级触发信号端 Input ( n )发送的高电平信号时控制移位寄存器开始工 作， 其中上级触发信号端 Input ( n )在上级移位寄存器（即第 n-1级移位寄存 器） 的本级输出端 Output ( n-1 )为高电平输出时接收到高电平信号；
第二薄膜晶体管 M2, 其栅极与第一节点 PU连接、 源极与时钟信号端连 接、 漏极与本级输出端 Output ( n )连接， 其作用是为本级输出端 Output ( n ) 提供高电平输出， 以驱动与本级移位寄存器（即第 n级移位寄存器）对应的 一行栅线打开；
第三薄膜晶体管 M3 , 其栅极与第一节点 PU连接、 源极与时钟信号端连 接、 漏极与下级触发信号端 Input ( n+1 )连接， 其作用是为下级移位寄存器 (即第 n+1级移位寄存器 )提供触发信号， 以控制下级移位寄存器开始工作； 电容 C1 , 连接在第一节点 PU与本级输出端 Output ( n )之间； 复位模块 1 , 连接在作为下拉节点的第二节点 PL、 时钟信号端和低电平 信号端 Vss之间， 用于在本级输出完成后为第二薄膜晶体管 M2的漏极和栅 极力。载低电平；
反馈接收模块 2, 连接在第一节点 PU、 低电平信号端 Vss和本级输出端
Output ( n )之间， 并与下级反馈信号端 Reset ( n+1 )连接， 用于接收下级反 馈信号以将第一节点 PU和本级输出端 Output (n)的电平拉低， 其中下级反 馈信号端 Reset (n+1 )在下级移位寄存器 (即第 n+1级移位寄存器） 的本级 输出端 Output (n+1 )为高电平输出时接收到高电平信号。 所述下级反馈信号 端 Reset (n+1 )可以与下级移位寄存器 (即第 n+1级移位寄存器） 的本级输 出端 Output (n+1 )连接， 或者可以与下级移位寄存器（即第 n+1级移位寄存 器 ) 的下级触发信号端 Input ( n+2 )连接。
应注意， 尽管在图 2中移位寄存器包括三个薄膜晶体管， 然而本发明实 施例并不限于此。 例如， 在根据本发明实施例的移位寄存器中可以不包括第 三薄膜晶体管 M3,而直接将与第二薄膜晶体管 M2的漏极连接的本级输出端 Output (n) 同时用作下级触发信号端 Input ( n+1 )。
因此， 根据本发明另一实施例的移位寄存器包括两个薄膜晶体管、 一个 存储电容、 一个复位模块、 一个反馈接收模块和相应的输入输出端。 具体包 括：
第一薄膜晶体管 Ml, 其栅极和源极连接在一起并与上级触发信号端 Input (n)连接、 漏极与作为上拉节点的第一节点 PU连接， 其作用是当接收 到由上级触发信号端 Input (n)发送的高电平信号时控制移位寄存器开始工 作， 其中上级触发信号端 Input (n)在上级移位寄存器（即第 n-1级移位寄存 器） 的本级输出端 Output (n-1 )为高电平输出时接收到高电平信号；
第二薄膜晶体管 M2, 其栅极与第一节点 PU连接、 源极与时钟信号端连 接、 漏极与本级输出端 Output ( n )连接并且与下级触发信号端 Input ( n+1 ) 连接， 其作用是为本级输出端 Output (n)提供高电平输出， 以驱动与本级移 位寄存器 （即第 n级移位寄存器）对应的一行栅线打开， 并且为下级移位寄 存器 (即第 n+1级移位寄存器）提供触发信号， 以控制下级移位寄存器开始 工作；
电容 C1, 连接在第一节点 PU与本级输出端 Output (n)之间； 复位模块 1, 连接在作为下拉节点的第二节点 PL、 时钟信号端和低电平 信号端 Vss之间， 用于在本级输出完成后为第二薄膜晶体管 M2的漏极和栅 极力。载低电平；
反馈接收模块 2, 连接在第一节点 PU、 低电平信号端 Vss和本级输出端 Output ( n )之间， 并与下级反馈信号端 Reset ( n+1 )连接， 用于接收下级反 馈信号以将第一节点 PU和本级输出端 Output (n)的电平拉低， 其中下级反 馈信号端 Reset ( n+1 )在下级移位寄存器（即第 n+1级移位寄存器） 的本级 输出端 Output ( n+1 )为高电平输出时接收到高电平信号。 所述下级反馈信号 端 Reset ( n+1 )可以与下级移位寄存器 (即第 n+1级移位寄存器） 的本级输 出端 Output( n+l )连接，或者可以通过在根据本实施例的下级移位寄存器（即 第 n+1级移位寄存器）中添加其它薄膜晶体管 (例如图 2中的 M3 )来提供所 述下级反馈信号端 Reset ( n+1 )。
本发明实施例提供的移位寄存器，由于如果一直为一个薄膜晶体管加压， 则容易在薄膜晶体管的栅绝缘层中形成并积累电子， 从而导致该薄膜晶体管 的阔值电压偏移。 通过在薄膜晶体管的源极加载高电平、 栅极加载低电平， 根据隧道效应和量子力学的原理， 能够使在薄膜晶体管的栅绝缘层中形成并 积累的电子穿过势垒而到达薄膜晶体管的源极， 从而降低与每行栅线对应的 移位寄存器内薄膜晶体管的阔值电压偏移， 最终能够使移位寄存器电路正常 工作， 提高了移位寄存器工作的稳定性， 延长了移位寄存器的工作寿命。 这 里需要说明的是， 由于移位寄存器中各薄膜晶体管的栅绝缘层上电子的形成 和积累， 使得相应薄膜晶体管的阔值电压均产生了偏移， 因此可以为移位寄 存器中的各薄膜晶体管设置复位模块 1 , 以在移位寄存器的本级输出完成后 在薄膜晶体管的源极加载高电平、 栅极加载低电平， 从而使薄膜晶体管的栅 绝缘层中的电子到达薄膜晶体管的源极，以降低薄膜晶体管的阔值电压偏移。 其中由于在移位寄存器中， 第二薄膜晶体管 M2能够导通时钟信号端和本级 输出端， 从而使与该移位寄存器对应的一行栅线打开， 因此该第二薄膜晶体 管 M2在移位寄存器中具有非常重要的作用， 一旦该第二薄膜晶体管 M2由 于阔值电压偏移而无法正常开启， 则将影响显示效果。 此外， 该第二薄膜晶 体管 M2上的工作电流一般较大， 容易引起阔值电压偏移。 因此本实施例中 以第二薄膜晶体管 M2为例说明如何通过复位模块 1来降低其阔值电压偏移。 应当理解， 本说明是示例性的， 而不是限制性的。
如图 3所示， 为本发明移位寄存器一个具体实施例的示意图。 由图 3可 知所述移位寄存器包括十四个薄膜晶体管、 一个存储电容和相应的输入输出 端。 其中该十四个薄膜晶体管分别为： 第一薄膜晶体管 Ml、 第二薄膜晶体管 M2、 第三薄膜晶体管 M3、 第四薄膜晶体管 M4、 第五薄膜晶体管 M5、 第六 薄膜晶体管 M6、 第七薄膜晶体管 M7、 第八薄膜晶体管 M8、 第九薄膜晶体 管 M9、 第十薄膜晶体管 M10和第一复位薄膜晶体管 Tl、 第二复位薄膜晶体 管 T2、 第三复位薄膜晶体管 Τ3和第四复位薄膜晶体管 Τ4。 存储电容为电容 Cl。 输入输出端包括： 接收上级移位寄存器触发信号的上级触发信号端 Input ( n )、 为本级移位寄存器输出电平信号的本级输出端 Output ( n )、 为下级移 位寄存器发送触发信号的下级触发信号端 Input ( n+1 )、 接收下级移位寄存器 反馈信号的下级反馈信号端 Reset ( n+1 )、 低电平信号端 Vss、 以及时钟信号 端， 该时钟信号端包括第一时钟信号端 CLK和第二时钟信号端 CLKB, 第一 时钟信号端 CLK的时钟信号与第二时钟信号端 CLKB的时钟信号的频率和占 空比完全相同， 而仅仅相位相差 180°。
具体地， 第一薄膜晶体管 Ml , 其栅极和源极连接在一起并与上级触发 信号端 Input ( n )连接、 漏极与作为上拉节点的第一节点 PU连接； 第二薄膜 晶体管 M2, 其栅极与第一节点 PU连接、 源极与第一时钟信号端 CLK连接、 漏极与本级输出端 Output ( n )连接； 第三薄膜晶体管 M3 , 其栅极与第一节 点 PU连接、 源极与第一时钟信号端 CLK连接、漏极与下级触发信号端 Input ( n+1 )连接； 第四薄膜晶体管 M4, 其栅极与下级反馈信号端 Reset ( n+1 ) 连接、 源极与本级输出端连接 Output ( n )、 漏极与低电平信号端 Vss连接； 第五薄膜晶体管 M5, 其栅极与下级反馈信号端 Reset ( n+1 )连接、 源极与第 一节点 PU连接、 漏极与低电平信号端 Vss连接； 第六薄膜晶体管 M6, 其栅 极与第二时钟信号端 CLKB连接、 源极与第二节点 PL连接、 漏极与低电平 信号端 Vss连接； 第七薄膜晶体管 M7 , 其栅极与第二时钟信号端 CLKB连 接、 源极与上级触发信号端 Input ( n )连接、 漏极与第一节点 PU连接； 第八 薄膜晶体管 M8, 其栅极与第一时钟信号端 CLK连接、 源极与第一节点 PU 连接、 漏极与第二节点 PL连接； 第九薄膜晶体管 M9, 其栅极与复位模块 1 中的第四复位薄膜晶体管 T4的漏极连接、 源极与第一节点 PU连接、 漏极与 低电平信号端 Vss连接； 第十薄膜晶体管 M10, 其栅极与复位模块 1中的第 四复位薄膜晶体管 T4的漏极连接、 源极本级输出端 Output ( n )连接、 漏极 与低电平信号端 Vss连接。 第一复位薄膜晶体管 T1 , 其栅极与第二节点 PL 连接、 源极与第三复位薄膜晶体管 T3的漏极连接、 漏极与低电平信号端 Vss 连接； 第二复位薄膜晶体管 T2, 其栅极与第二节点 PL连接、 源极与第四复 位薄膜晶体管 T4的漏极连接、 漏极与低电平信号端 Vss连接； 第三复位薄膜 晶体管 T3 , 其栅极和源极与第一时钟信号端 CLK连接、 漏极与第一复位薄 膜晶体管 T1的源极连接； 第四复位薄膜晶体管 T4, 其栅极与第三复位薄膜 晶体管 T3的漏极连接、 源极与第一时钟信号端 CLK连接、 漏极与第二复位 薄膜晶体管 T2的源极连接。 存储电容 C1则连接在第一节点 PU和本级输出 端 Output ( n )之间。
其中， 第一复位薄膜晶体管 Tl、 第二复位薄膜晶体管 Τ2、 第三复位薄 膜晶体管 Τ3和第四复位薄膜晶体管 Τ4的结构与第一薄膜晶体管 Ml至第十 薄膜晶体管 M10等的结构相同， 由于第一复位薄膜晶体管 Tl、 第二复位薄 膜晶体管 Τ2、第三复位薄膜晶体管 Τ3和第四复位薄膜晶体管 Τ4组成了本实 施例中的复位模块 1 ,因此将其与第一薄膜晶体管 Ml至第十薄膜晶体管 M10 在名称上作以区分。
由上述可知， 第一复位薄膜晶体管 Tl、 第二复位薄膜晶体管 Τ2、 第三 复位薄膜晶体管 Τ3和第四复位薄膜晶体管 Τ4组成了本实施例中的复位模块 1 , 复位模块 1用于在本级输出完成后为第二薄膜晶体管 Μ2的源极加载高电 平、 栅极加载低电平， 这样根据隧道效应和量子力学的原理， 能够使第二薄 膜晶体管 Μ2 的栅绝缘层中形成并积累的电子穿过势垒而到达第二薄膜晶体 管 Μ2的源极，从而降低与每行栅线对应的移位寄存器内第二薄膜晶体管 Μ2 的阔值电压偏移， 最终能够使移位寄存器电路正常工作， 提高了移位寄存器 工作的稳定性， 延长了移位寄存器的工作寿命。
第四薄膜晶体管 Μ4和第五薄膜晶体管 Μ5组成了反馈接收模块 2。该反 馈接收模块 2用于在本级移位寄存器不工作且下级移位寄存器工作时， 保持 本级输出端 Output ( n )和作为上拉节点的第一节点 PU为低电平， 从而避免 以下情况： 本级输出端 Output ( n )在其他干扰信号的作用下变为高电平， 并 使其所控制的一行栅线在高电平作用下打开， 最终造成栅线打开错误。 其中， 第四薄膜晶体管 M4用于在下级反馈信号端 Reset ( n+1 ) 的作用下保持本级 输出端 Output ( n )为低电平， 而第五薄膜晶体管 M5用于在下级反馈信号端 Reset ( n+1 ) 的作用下保持第一节点 PU为低电平， 以防止第二薄膜晶体管 M2被误打开。
由图 3可知， 所述移位寄存器还包括第六薄膜晶体管 M6。 第六薄膜晶 体管 M6用于在本级移位寄存器不工作时， 通过接收第二时钟信号端 CLKB 的高电平信号而将作为下拉节点的第二节点 PL拉低，从而避免以下情况： 本 级输出端 Output ( n )在其他干扰信号的作用下变为高电平， 并使其所控制的 一行栅线在高电平作用下打开， 最终造成栅线打开错误。 所述移位寄存器还包括第七薄膜晶体管 M7。第七薄膜晶体管 M7用于在 上级触发信号端 Input ( n ) 为高电平， 且第二时钟信号端 CLKB变为高电平 时， 加速为存储电容 C1充电。
所述移位寄存器还包括第八薄膜晶体管 M8。第八薄膜晶体管 M8用于本 级输出端 Output( n )为高电平的时间内（即在本级移位寄存器的工作时间内 ), 保证第一节点 PU持续为高电平状态， 继续为电容 C1充电， 进一步提高第二 薄膜晶体管 M2的开启能力。
此外， 所述移位寄存器还包括第九薄膜晶体管 M9 和第十薄膜晶体管 M10, 二者与复位模块 1相结合， 以使得在对第二薄膜晶体管 M2复位时使 第二薄膜晶体管 M2的栅极和漏极均为低电平， 其中第九薄膜晶体管 M9用 于将第一节点 PU拉低到低电平， 以避免第二薄膜晶体管 M2误打开，第十薄 膜晶体管 M10用于将本级输出端 Output ( n )拉低到低电平， 以避免本级输 出端 Output ( n ) 变为高电平。
应注意， 尽管在图 3中移位寄存器包括十四个薄膜晶体管， 然而本发明 实施例并不限于此。 例如， 在根据本发明实施例的移位寄存器中可以不包括 第三薄膜晶体管 M3 ,而直接将与第二薄膜晶体管 M2的漏极连接的本级输出 端 Output ( n ) 同时用作下级触发信号端 Input ( n+1 )。
因此， 根据本发明另一实施例的移位寄存器包括十三个薄膜晶体管、 一 个存储电容和相应的输入输出端。 其中该十三个薄膜晶体管分别为： 第一薄 膜晶体管 Ml、 第二薄膜晶体管 M2、 第四薄膜晶体管 M4、 第五薄膜晶体管 M5、 第六薄膜晶体管 M6、 第七薄膜晶体管 M7、 第八薄膜晶体管 M8、 第九 薄膜晶体管 M9、 第十薄膜晶体管 M10和第一复位薄膜晶体管 Tl、 第二复位 薄膜晶体管 Τ2、 第三复位薄膜晶体管 Τ3和第四复位薄膜晶体管 Τ4。 存储电 容为电容 Cl。 输入输出端包括： 接收上级移位寄存器触发信号的上级触发信 号端 Input ( n )、 为本级移位寄存器输出电平信号并为下级移位寄存器发送触 发信号的本级输出端 Output ( n )、 接收下级移位寄存器反馈信号的下级反馈 信号端 Reset ( n+1 )、 低电平信号端 Vss、 以及时钟信号端， 该时钟信号端包 括第一时钟信号端 CLK和第二时钟信号端 CLKB, 第一时钟信号端 CLK的 时钟信号与第二时钟信号端 CLKB的时钟信号的频率和占空比完全相同， 而 仅仅相位相差 180°。 所述十三个薄膜晶体管的操作与上面结合图 3所述的实 施例中相应薄膜晶体管的操作相同， 在此不再进行赞述。 在实际使用中， 本实施例上述技术方案中的各薄膜晶体管可以为氢化非 晶薄膜晶体管， 但也可以为其他类型的薄膜晶体管。
下面结合图 3所示的移位寄存器以及图 4所示的控制时序对本实施例移 位寄存器的工作过程作以描述。
如图 4所示， 为本实施例中移位寄存器的控制时序图， 可以分为 tl、 t2、 t3和 t4四个阶段。 其中第一时钟信号端 CLK和第二时钟信号端 CLKB周期 性交替使用。 STV为开关信号， 即上级触发信号端 Input ( n ), 用于接收来自 上级移位寄存器的高电平信号。 其中以 1表示高电平信号， 0表示低电平信 号。 并且在以下图 5至图 8中， 以箭头表示薄膜晶体管的导通， 以叉号表示 薄膜晶体管的关闭。
在 tl阶段， Input ( n ) =1 , CLK=0, CLKB=1 , Reset ( n+1 ) =0。
本级移位寄存器的 STV 信号由上级移位寄存器通过上级触发信号端 Input ( n )提供。 如图 5所示， 由于 Input ( n ) =1 , 因此第一薄膜晶体管 Ml 导通并控制本级移位寄存器开始工作， 上级触发信号端 Input ( n )通过第一 薄膜晶体管 Ml为存储电容 C1充电。 由于 CLKB=1 , 因此第七薄膜晶体管 M7导通， 第二时钟信号端 CLKB通过第七薄膜晶体管 M7加速为存储电容 C1充电。 此时， 第一节点 PU被拉高而具有高电平， 第二薄膜晶体管 M2导 通， 由于 CLK=0, 因此第一时钟信号端 CLK的低电平通过第二薄膜晶体管 M2而输出到本级输出端 Output ( n ),该输出的低电平使与本级移位寄存器对 应的一行栅线处于低电平状态。 进一步地， 由于 CLKB=1 , 第六薄膜晶体管 M6导通。 第六薄膜晶体管 M6在本级移位寄存器不工作时将第二节点 PL拉 低至 Vss,避免本级输出端 Output ( n )在其他干扰信号的作用下变为高电平。 此外， 由于第一节点 PU被拉高至高电平， 因此第三薄膜晶体管 M3导通， 又 由于第一时钟信号端 CLK=0, 因此下级触发信号端 Input ( n+1 )被拉低至低 电平， 即本级移位寄存器在 tl阶段内未向下级移位寄存器发送触发信号。 综 上所述可知， tl阶段为存储电容 C1的充电阶段。
在 t2阶段， Input ( n ) =0, CLK=1 , CLKB=0, Reset ( n+1 ) =0。
如图 6所示， 由于在 Input ( n ) =0、 CLKB=0, 因此第一薄膜晶体管 Ml 和第七薄膜晶体管 M7关闭， t2阶段内不再通过上级触发信号端 Input ( n ) 和第二时钟信号端 CLKB为存储电容 C1充电。 由于 CLKB=0, 第六薄膜晶 体管 M6 关闭， 从而第六薄膜晶体管 M6 不会将第二节点 PL拉低。 由于 CLK=1,第二薄膜晶体管 M2在存储电容 CI的作用下导通后将第一时钟信号 端 CLK上的高电平输出到本级输出端 Output (n), 进而由本级输出端 Output (n)将该高电平输出到与本级移位寄存器对应的一行栅线上， 使液晶面板的 显示区域内位于该行栅线上的所有薄膜晶体管开启， 数据线开始写入信号。 由于 CLK=1, 第八薄膜晶体管 M8导通并将本级输出端 Output (n)上的高 电平反馈到第一节点 PU, 保证第一节点 PU持续为高电平状态， 继续为电容 C1充电， 进一步提高第二薄膜晶体管 M2的开启能力。 在 Output(n)=l后， 第二节点 PL被拉高， 从而使第一复位薄膜晶体管 T1和第二复位薄膜晶体管 T2导通。 此外， 由于 CLK=1, 第三复位薄膜晶体管 T3导通， 通过合理设 置第一复位薄膜晶体管 T1的沟道宽长比和第三复位薄膜晶体管 T3的沟道宽 长比， 使得第一复位薄膜晶体管 T1保持第四复位薄膜晶体管 T4的栅极为低 电平。 此外， 第二复位薄膜晶体管 T2保持第四复位薄膜晶体管 T4的漏极为 低电平。 由于第四复位薄膜晶体管 T4关闭， 因此第九薄膜晶体管 M9和第十 薄膜晶体管 M10关闭， 以保证第一节点 PU和本级输出端 Output ( n )持续处 于高电平状态， 不会被拉低。 而且此时第三薄膜晶体管 M3也在存储电容 C1 的作用下导通， 使下级触发信号端 Input (n+1) 变为高电平， 以向下级移位 寄存器发送触发信号。 综上所述， t2 阶段为本级移位寄存器的本级输出端 Output ( n )输出高电平的阶段。
在 t3阶段， Input (n) =0, CLK=0, CLKB=1, Reset (n+1) =1。
本级移位寄存器的 Reset信号由下级移位寄存器通过下级反馈信号端
Reset (n+1 )提供。 如图 7所示， 由于 Reset (n+1 ) =1, 第四薄膜晶体管 M4 和第五薄膜晶体管 M5导通，第四薄膜晶体管 M4导通后将本级输出端 Output (n)拉低到 Vss, 第五薄膜晶体管 M5导通后将第一节点 PU拉低到 Vss, 从 而避免以下情况： 本级输出端 Output (n)在其他干扰信号的作用下变为高电 平， 并使其所控制的一行栅线在高电平作用下打开， 最终造成栅线打开错误。 进一步地， 由于 CLKB=1, 第六薄膜晶体管 M6导通， 第六薄膜晶体管 M6 在本级移位寄存器不工作时将第二节点 PL 拉低至 Vss, 避免本级输出端 Output (n)在其他干 4尤信号的作用下变为高电平。 综上所述， t3阶段为下级 移位寄存器的本级输出端 Output (n+1 )输出高电平的阶段。
在 t4阶段， Input (n) =0, CLK=1 , CLKB=0, Reset ( n+1 ) =0。
如图 8所示， 由于 CLK=1, 第三复位薄膜晶体管 T3导通， 从而使第四 复位薄膜晶体管 T4的栅极变为高电平，由此使第四复位薄膜晶体管 T4导通。 此外，第四复位薄膜晶体管 T4的导通又使第九薄膜晶体管 M9和第十薄膜晶 体管 M10的栅极变为高电平， 从而使第九薄膜晶体管 M9和第十薄膜晶体管 M10导通。 第九薄膜晶体管 M9将第一节点 PU拉低至 Vss, 第十薄膜晶体管 M10将本级输出端 Output ( n )拉低至 Vss, 以使得在对第二薄膜晶体管 M2 复位时使第二薄膜晶体管 M2的栅极和漏极均为低电平。 此时， 对于第二薄 膜晶体管 M2 而言， 其源极上加载高电平、 栅极加载低电平， 因此在栅绝缘 层上积累的电子能够穿越势垒而到达第二薄膜晶体管 M2的源极， 从而降低 第二薄膜晶体管 M2的阔值电压偏移。 综上所述， t4阶段为复位模块 1工作 以使第二薄膜晶体管 M2的阶段， 即本级移位寄存器的复位阶段。
由上面的描述可知， 本实施例中的移位寄存器能够降低与每行栅线对应 的移位寄存器内薄膜晶体管的阔值电压偏移， 最终能够使移位寄存器电路正 常工作， 提高了移位寄存器工作的稳定性， 延长了移位寄存器的工作寿命。
同理， 对于不包括第三薄膜晶体管 M3的实施例， 上述的操作过程同样 适用， 在此不再赘述。
除此之外， 本发明实施例还提供了一种栅线驱动装置。 如图 9所示， 所 述栅线驱动装置包括串联的多个移位寄存器， 为方便说明图 9中仅显示了五 个移位寄存器， 分别为第 N-2级移位寄存器、 第 N-1级移位寄存器、 第 N级 移位寄存器、 第 N+1级移位寄存器和第 N+2级移位寄存器。 其中， 第 N级 移位寄存器的输出 Output( n ),不仅向第 N-1级移位寄存器反馈以关断第 N-1 级移位寄存器，同时还向第 N+1级移位寄存器输出以作为该第 N+1级移位寄 存器的触发信号。
此外， 如图 9所示， 对于各级移位寄存器而言， 时钟信号 CLK和时钟信 号 CLKB是周期性交替使用的。 具体地， 第 N级移位寄存器的时钟信号端被 示出为接收时钟信号 CLK, 而第 N - 1级和第 N+1级移位寄存器的时钟信号 端被示出为接收时钟信号 CLKB, 因此， 用于第 N级移位寄存器的时钟信号 与用于第 N _ 1级和第 N+1级移位寄存器的时钟信号的相位完全相反， 即相 位相差 180°。
在另一情况下， 即在时钟信号端包括第一时钟信号端和第二时钟信号端 的情况下，对于各级移位寄存器而言， 时钟信号 CLK和时钟信号 CLKB也是 周期性交替使用的。 对于第 N级移位寄存器， 第一时钟信号端接收时钟信号 CLK, 第二时钟信号端接收时钟信号 CLKB, 然而对于第 N- 1级和第 N+1 级移位寄存器， 第一时钟信号端接收时钟信号 CLKB, 第二时钟信号端接收 时钟信号 CLK。
结合图 2所示，每级移位寄存器均包括三个薄膜晶体管，一个存储电容， 一个复位模块、 一个反馈接收模块和相应的输入输出端。 具体包括：
第一薄膜晶体管 Ml, 其栅极和源极连接在一起并与上级触发信号端 Input (n)连接、 漏极与作为上拉节点的第一节点 PU连接。 其作用是当接收 到由上级触发信号端 Input (n)发送的高电平信号时控制移位寄存器开始工 作。 其中上级触发信号端 Input (n)在上级移位寄存器（即第 n-1级移位寄存 器）的本级输出端 Output (n-1)为高电平输出时接收到高电平信号。 第二薄 膜晶体管 M2, 其栅极与第一节点 PU连接、 源极与时钟信号端连接、 漏极与 本级输出端 Output (n)连接。 其作用是为本级输出端 Output (n)提供高电 平输出， 以驱动与本级移位寄存器（即第 n级移位寄存器）对应的一行栅线 打开。 第三薄膜晶体管 M3, 其栅极与第一节点 PU连接、 源极与时钟信号端 连接、 漏极与下级触发信号端 Input (n+1 )连接。 其作用是为下级移位寄存 器（即第 n+1级移位寄存器）提供触发信号， 以控制下级移位寄存器开始工 作。 电容 C1, 连接在第一节点 PU与本级输出端 Output (n)之间。 复位模 块 1, 连接在作为下拉节点的第二节点 PL、 时钟信号端和低电平信号端 Vss 之间， 用于在本级输出完成后为第二薄膜晶体管 M2 的源极加载高电平、 栅 极加载低电平； 反馈接收模块 2, 连接在第一节点 PU、 低电平信号端 Vss和 本级输出端 Output (n)之间， 并与下级反馈信号端 Reset (n+1 )连接， 用于 接收下级反馈信号以将第一节点 PU和本级输出端 Output (n) 的电平拉低。
此外， 根据本发明另一实施例的栅线驱动装置， 结合图 2和 3的说明可 知， 第 N级移位寄存器的输出 Output (n) 向第 N-1级移位寄存器反馈 (即 作为下级反馈信号端 Reset (n-1 ))以关断第 N-1级移位寄存器， 同时第 N级 移位寄存器的下级触发信号端 Input (n+1 ) 向第 N+1级移位寄存器输出以作 为该第 N+1级移位寄存器的触发信号。
如前所述， 在根据本发明该另一实施例的栅线驱动装置中的每级移位寄 存器中不包括第三薄膜晶体管 M3,而直接将与第二薄膜晶体管 M2的漏极连 接的本级输出端 Output (n) 同时用作下级触发信号端 Input (n+l)。 除了不 包括第三薄膜晶体管 M3之外， 该移位寄存器的操作与根据本发明实施例的 栅线驱动装置中的移位寄存器的操作相同， 在此不再进行赞述。
本发明实施例提供的栅线驱动装置中， 由于如果一直为一个薄膜晶体管 加压， 则容易在该薄膜晶体管的栅绝缘层中形成并积累电子， 从而导致该薄 膜晶体管的阔值电压偏移。 通过在薄膜晶体管的源极加载高电平、 栅极加载 低电平， 根据隧道效应和量子力学的原理， 能够使该薄膜晶体管的栅绝缘层 中形成并积累的电子穿过势垒而到达薄膜晶体管的源极， 从而降低与每行栅 线对应的移位寄存器内薄膜晶体管的阔值电压偏移， 最终能够使移位寄存器 电路正常工作， 提高了移位寄存器工作的稳定性， 延长了移位寄存器的工作 寿命。
需要说明的是， 本实施例栅线驱动装置中所使用的移位寄存器与上述移 位寄存器实施例中所使用的移位寄存器在功能和结构上均相同， 因此能够解 决同样的技术问题， 达到相同的预期效果。
本发明还提供了一种显示设备， 其包括像素阵列以及如上所述的栅线驱 动装置。
尽管上面在液晶显示技术领域描述了本发明实施例， 然而本发明实施例 不限于此， 而且还可以应用于其它的基于像素阵列的显示技术领域， 诸如
AMOLED (有源矩阵有机发光二极体面板）等。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权 利 要 求 书
1. 一种栅线驱动方法， 其特征在于， 包括：
降低与一行栅线对应的移位寄存器内薄膜晶体管的阔值电压偏移； 为所述移位寄存器内的薄膜晶体管的栅极加载电压以开启薄膜晶体 管， 从而为该行栅线提供行扫描信号以驱动该行栅线打开。
2. 根据权利要求 1所述的栅线驱动方法， 其特征在于， 所述降低与一 行栅线对应的移位寄存器内薄膜晶体管的阔值电压偏移包括：
使在所述薄膜晶体管的栅绝缘层上积累的电子到达所述薄膜晶体管的 源极， 以降低所述薄膜晶体管的阔值电压偏移。
3. 根据权利要求 2所述的栅线驱动方法， 其特征在于， 所述使在所述 薄膜晶体管的栅绝缘层上积累的电子到达薄膜晶体管的源极包括：
为所述薄膜晶体管的源极加载高电平、 栅极加载低电平， 以使在所述 薄膜晶体管的栅绝缘层上积累的电子到达所述薄膜晶体管的源极。
4. 一种移位寄存器， 其特征在于， 包括：
第一薄膜晶体管，其栅极和源极连接在一起并与上级触发信号端连接、 漏极与作为上拉节点的第一节点连接；
第二薄膜晶体管， 其栅极与所述第一节点连接、 源极与时钟信号端连 接、 漏极与本级输出端连接；
电容， 连接在所述第一节点与本级输出端之间；
复位模块， 连接在作为下拉节点的第二节点、 时钟信号端和低电平信 号端之间， 用于在本级输出完成后为所述第二薄膜晶体管的漏极和栅极加 载低电平；
反馈接收模块， 连接在所述第一节点、 低电平信号端和本级输出端之 间， 并与下级反馈信号端连接， 用于接收下级反馈信号以将所述第一节点 和本级输出端的电平拉低。
5. 根据权利要求 4所述的移位寄存器， 其特征在于， 所述复位模块包 括：
第一复位薄膜晶体管， 其栅极与所述第二节点连接、 源极与第三复位 薄膜晶体管的漏极连接、 漏极与低电平信号端连接；
第二复位薄膜晶体管， 其栅极与所述第二节点连接、 源极与第四复位 薄膜晶体管的漏极连接、 漏极与低电平信号端连接；
第三复位薄膜晶体管， 其栅极和源极与时钟信号端连接、 漏极与第一 复位薄膜晶体管的源极连接； 以及
第四复位薄膜晶体管， 其栅极与第三复位薄膜晶体管的漏极连接、 源 极与时钟信号端连接、 漏极与第二复位薄膜晶体管的源极连接，
所述移位寄存器还包括：
第九薄膜晶体管， 其栅极与所述复位模块中第二复位薄膜晶体管的源 极连接、 源极与所述第一节点连接、 漏极与低电平信号端连接； 以及
第十薄膜晶体管， 其栅极与所述复位模块第二复位薄膜晶体管的源极 连接、 源极本级输出端连接、 漏极与低电平信号端连接。
6. 根据权利要求 4所述的移位寄存器， 其特征在于， 所述反馈接收模 块包括：
第四薄膜晶体管， 其栅极与下级反馈信号端连接、 源极与本级输出端 连接、 漏极与低电平信号端连接； 以及
第五薄膜晶体管， 其栅极与下级反馈信号端连接、 源极与所述第一节 点连接、 漏极与低电平信号端连接。
7. 根据权利要求 4所述的移位寄存器， 其特征在于， 所述移位寄存器 还包括：
第六薄膜晶体管， 其栅极与第二时钟信号端连接、 源极与所述第二节 点连接、 漏极与低电平信号端连接， 其中， 所述第二时钟信号端处的时钟 信号与所述时钟信号端处的时钟信号完全反相。
8. 根据权利要求 4所述的移位寄存器， 其特征在于， 所述移位寄存器 还包括：
第七薄膜晶体管， 其栅极与第二时钟信号端连接、 源极与上级触发信 号端连接、 漏极与所述第一节点连接， 其中， 所述第二时钟信号端处的时 钟信号与所述时钟信号端处的时钟信号完全反相。
9. 根据权利要求 4所述的移位寄存器， 其特征在于， 所述移位寄存器 还包括：
第八薄膜晶体管， 其栅极与时钟信号端连接、 源极与所述第一节点连 接、 漏极与所述第二节点连接。
10. 根据权利要求 4所述的移位寄存器，其特征在于，所述移位寄存器 还包括：
第三薄膜晶体管， 其栅极与所述第一节点连接、 源极与时钟信号端连 接、 漏极与下级触发信号端连接。
11. 一种栅线驱动装置，其特征在于， 包括相互串联的多个如权利要求 4 至 10中任一项所述的移位寄存器。
12. 一种显示设备， 其特征在于， 包括像素阵列和如权利要求 11所述的 栅线驱动装置。
PCT/CN2012/083558 2011-10-26 2012-10-26 栅线驱动方法、移位寄存器、栅线驱动装置及显示设备 Ceased WO2013060285A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3086312A4 (en) * 2013-12-20 2017-07-26 Boe Technology Group Co. Ltd. Shift register unit, gate drive circuit and display device
CN110556154A (zh) * 2018-05-31 2019-12-10 爱思开海力士有限公司 包括多输入移位寄存器电路的半导体器件

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102629459A (zh) * 2011-10-26 2012-08-08 北京京东方光电科技有限公司 栅线驱动方法、移位寄存器及栅线驱动装置
CN102682689B (zh) * 2012-04-13 2014-11-26 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN102867475A (zh) * 2012-09-13 2013-01-09 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN102915714B (zh) * 2012-10-11 2015-05-27 京东方科技集团股份有限公司 一种移位寄存器、液晶显示栅极驱动装置和液晶显示装置
TWI500265B (zh) * 2012-11-22 2015-09-11 Au Optronics Corp 移位暫存器
CN103021466B (zh) * 2012-12-14 2016-08-03 京东方科技集团股份有限公司 移位寄存器及其工作方法、栅极驱动装置、显示装置
CN103021318B (zh) * 2012-12-14 2016-02-17 京东方科技集团股份有限公司 移位寄存器及其工作方法、栅极驱动装置、显示装置
CN103985341B (zh) * 2014-04-30 2016-04-20 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
KR102367484B1 (ko) * 2014-09-30 2022-02-28 엘지디스플레이 주식회사 표시장치 및 이의 구동방법
WO2016018105A1 (ko) 2014-07-31 2016-02-04 엘지디스플레이 주식회사 표시장치
CN104200769B (zh) * 2014-08-19 2016-09-28 上海和辉光电有限公司 扫描信号产生电路
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CN113056783B (zh) * 2019-10-28 2022-12-13 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN110867157A (zh) * 2019-11-29 2020-03-06 昆山国显光电有限公司 显示面板及像素驱动方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1445862A2 (en) * 2003-02-10 2004-08-11 Samsung Electronics Co., Ltd. Method of driving transistor and shift register performing the same
CN101089939A (zh) * 2006-06-12 2007-12-19 三星电子株式会社 栅极驱动电路和具有该栅极驱动电路的显示装置
CN101677021A (zh) * 2008-09-19 2010-03-24 北京京东方光电科技有限公司 移位寄存器的级、栅线驱动器、阵列基板和液晶显示装置
CN102012591A (zh) * 2009-09-04 2011-04-13 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
CN102629459A (zh) * 2011-10-26 2012-08-08 北京京东方光电科技有限公司 栅线驱动方法、移位寄存器及栅线驱动装置

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100797522B1 (ko) * 2002-09-05 2008-01-24 삼성전자주식회사 쉬프트 레지스터와 이를 구비하는 액정 표시 장치
KR100551729B1 (ko) * 2003-03-19 2006-02-13 비오이 하이디스 테크놀로지 주식회사 액정표시장치의 게이트 라인 구동방법 및 그 구동회로
KR20060123913A (ko) * 2005-05-30 2006-12-05 삼성전자주식회사 쉬프트 레지스터 및 이를 갖는 표시장치
KR20070013013A (ko) * 2005-07-25 2007-01-30 삼성전자주식회사 표시 장치
US8174478B2 (en) * 2006-06-12 2012-05-08 Samsung Electronics Co., Ltd. Gate driving circuit and display apparatus having the same
US7936332B2 (en) * 2006-06-21 2011-05-03 Samsung Electronics Co., Ltd. Gate driving circuit having reduced ripple effect and display apparatus having the same
KR101217177B1 (ko) * 2006-06-21 2012-12-31 삼성디스플레이 주식회사 게이트 구동회로 및 이를 갖는 표시 장치
TWI349906B (en) * 2006-09-01 2011-10-01 Au Optronics Corp Shift register, shift register array circuit, and display apparatus
JP5079301B2 (ja) * 2006-10-26 2012-11-21 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
TWI385624B (zh) * 2007-04-11 2013-02-11 Wintek Corp 移位暫存器及其位準控制器
KR101617215B1 (ko) * 2007-07-06 2016-05-03 삼성디스플레이 주식회사 액정 표시 장치 및 그의 구동 방법
KR101415562B1 (ko) * 2007-08-06 2014-07-07 삼성디스플레이 주식회사 게이트 구동회로 및 이를 가지는 표시장치
CN101546607B (zh) * 2008-03-26 2012-02-29 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
KR101472513B1 (ko) * 2008-07-08 2014-12-16 삼성디스플레이 주식회사 게이트 드라이버 및 이를 갖는 표시장치
KR101502361B1 (ko) * 2008-08-06 2015-03-16 삼성디스플레이 주식회사 액정 표시 장치
KR101471553B1 (ko) * 2008-08-14 2014-12-10 삼성디스플레이 주식회사 게이트 구동 회로 및 이를 갖는 표시 장치
KR101579842B1 (ko) * 2008-10-30 2015-12-24 삼성디스플레이 주식회사 게이트 라인 구동 방법, 이를 수행하기 위한 게이트 구동회로 및 이를 구비한 표시 장치
CN102224539B (zh) * 2008-12-10 2013-10-23 夏普株式会社 扫描信号线驱动电路、移位寄存器和移位寄存器的驱动方法
KR101579082B1 (ko) * 2008-12-23 2015-12-22 삼성디스플레이 주식회사 게이트 구동회로 및 이의 구동 방법
KR101520807B1 (ko) * 2009-01-05 2015-05-18 삼성디스플레이 주식회사 게이트 구동회로 및 이를 갖는 표시장치
TWI402814B (zh) * 2009-01-16 2013-07-21 Chunghwa Picture Tubes Ltd 可抑制臨界電壓漂移之閘極驅動電路
KR101543281B1 (ko) * 2009-02-19 2015-08-11 삼성디스플레이 주식회사 게이트 구동회로 및 이를 구비한 표시 장치
CN101847445B (zh) * 2009-03-27 2012-11-21 北京京东方光电科技有限公司 移位寄存器及其栅线驱动装置
KR101573460B1 (ko) * 2009-04-30 2015-12-02 삼성디스플레이 주식회사 게이트 구동회로
KR101587610B1 (ko) * 2009-09-21 2016-01-25 삼성디스플레이 주식회사 구동회로
KR101605433B1 (ko) * 2009-11-26 2016-03-23 삼성디스플레이 주식회사 표시 패널
WO2011092924A1 (ja) * 2010-01-29 2011-08-04 シャープ株式会社 シフトレジスタおよび表示装置
KR101641721B1 (ko) * 2010-06-24 2016-07-25 삼성디스플레이 주식회사 표시장치의 구동회로
TWI409528B (zh) * 2010-07-02 2013-09-21 Chunghwa Picture Tubes Ltd 顯示面板
CN102467890B (zh) * 2010-10-29 2014-05-07 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动装置及液晶显示器
KR101810517B1 (ko) * 2011-05-18 2017-12-20 삼성디스플레이 주식회사 게이트 구동회로 및 이를 구비한 표시 장치
CN102654986A (zh) * 2011-11-25 2012-09-05 京东方科技集团股份有限公司 移位寄存器的级、栅极驱动器、阵列基板以及显示装置
CN102708779B (zh) * 2012-01-13 2014-05-14 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN102708926B (zh) * 2012-05-21 2015-09-16 京东方科技集团股份有限公司 一种移位寄存器单元、移位寄存器、显示装置和驱动方法
CN102945657B (zh) * 2012-10-29 2014-09-10 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、阵列基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1445862A2 (en) * 2003-02-10 2004-08-11 Samsung Electronics Co., Ltd. Method of driving transistor and shift register performing the same
CN101089939A (zh) * 2006-06-12 2007-12-19 三星电子株式会社 栅极驱动电路和具有该栅极驱动电路的显示装置
CN101677021A (zh) * 2008-09-19 2010-03-24 北京京东方光电科技有限公司 移位寄存器的级、栅线驱动器、阵列基板和液晶显示装置
CN102012591A (zh) * 2009-09-04 2011-04-13 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
CN102629459A (zh) * 2011-10-26 2012-08-08 北京京东方光电科技有限公司 栅线驱动方法、移位寄存器及栅线驱动装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2772902A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3086312A4 (en) * 2013-12-20 2017-07-26 Boe Technology Group Co. Ltd. Shift register unit, gate drive circuit and display device
US9865211B2 (en) 2013-12-20 2018-01-09 Boe Technology Group Co., Ltd. Shift register unit, gate driving circuit and display device
CN110556154A (zh) * 2018-05-31 2019-12-10 爱思开海力士有限公司 包括多输入移位寄存器电路的半导体器件
CN110556154B (zh) * 2018-05-31 2023-01-24 爱思开海力士有限公司 包括多输入移位寄存器电路的半导体器件

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