WO2013104236A1 - 一种像素电路及其驱动方法 - Google Patents

一种像素电路及其驱动方法 Download PDF

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Publication number
WO2013104236A1
WO2013104236A1 PCT/CN2012/086799 CN2012086799W WO2013104236A1 WO 2013104236 A1 WO2013104236 A1 WO 2013104236A1 CN 2012086799 W CN2012086799 W CN 2012086799W WO 2013104236 A1 WO2013104236 A1 WO 2013104236A1
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WO
WIPO (PCT)
Prior art keywords
tube
switch tube
switch
gate
pole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/086799
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English (en)
French (fr)
Inventor
祁小敬
周全国
邱云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to KR1020137015437A priority Critical patent/KR101485278B1/ko
Priority to EP12852436.0A priority patent/EP2804170B1/en
Priority to US13/996,152 priority patent/US9030388B2/en
Priority to JP2014551503A priority patent/JP6039690B2/ja
Publication of WO2013104236A1 publication Critical patent/WO2013104236A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/60—Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/088—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements using a non-linear two-terminal element

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • An Organic Light Emitting Diode is a current-driven active light-emitting device that has the unique advantages of self-illumination, fast response, wide viewing angle, and fabrication on a flexible substrate.
  • the OLED-based organic light-emitting display is expected to become the mainstream in the display field in the next few years.
  • Each display unit of the organic light emitting display is composed of an OLED.
  • the OLED can be divided into a passive matrix driving organic light emitting diode (PMOLED) and an active matrix driving organic light emitting diode (Active Matrix Driving). OLED, AMOLED).
  • PMOLED passive matrix driving organic light emitting diode
  • Active Matrix Driving Active Matrix Driving
  • the active matrix driving method is widely used in large information display because it can realize high quality display.
  • each OLED has a Thin Film Transistor (TFT) circuit to control the current flowing through the OLED, and the OLED and the TFT circuit for driving the OLED constitute a pixel circuit, thereby ensuring active organic light emission.
  • TFT Thin Film Transistor
  • the uniformity of the brightness of the display panel requires consistency in the characteristics of the TFTs for driving the OLEDs located in different regions of the backplane.
  • the threshold voltage of a TFT is related to many factors, including the doping of the first pole of the TFT, the thickness of the dielectric, the gate material, and the excess charge in the dielectric.
  • the threshold voltage offset of each TFT is inconsistent; Problems such as decreased TFT stability may also cause the threshold voltage offset of the TFT to be inconsistent, and the inconsistent threshold voltage offset of the TFT may cause a difference in current flowing through each OLED, thereby causing the OLED to be driven by the current to emit light. Poor hooking.
  • Embodiments of the present invention provide a pixel circuit, a driving method thereof, and a display device, which effectively improve the uniformity of the luminance of the light emitting device.
  • the embodiments of the present invention provide the following technical solutions:
  • a pixel circuit comprising:
  • a light emitting device a driving tube, a storage capacitor, a first switching tube, a second switching tube, a compensation tube, and a fifth switching tube;
  • the driving tube, the first switching tube, the second switching tube, the compensation tube, and the fifth switching tube each include a gate, a first pole and a second pole;
  • One end of the light emitting device is connected to a power source
  • a first pole of the driving tube is connected to the other end of the light emitting device, a second pole is connected to the first pole of the fifth switching tube, and a gate is connected to the first pole of the first switching tube;
  • the second pole of the first switch tube is connected to the data line, the gate is connected to the scan line, and the first pole is connected to the gate of the drive tube;
  • the gate of the second switch tube is connected to the control line, the first pole is connected to the power source, and the second pole is connected to the second pole of the compensation tube;
  • the first pole of the compensating tube is connected to the first pole of the driving tube
  • the second pole is connected to the second pole of the second switching tube
  • the gate and the first pole or the second pole of the compensating tube Connected
  • the gate of the fifth switch tube is connected to the control line, the first pole is connected to the second pole of the drive tube, and the second pole is connected to the ground;
  • the first plate of the storage capacitor is connected to the gate of the drive tube, and the second plate is connected to the second pole of the compensation tube.
  • a driving method for the pixel circuit comprising:
  • a display device includes a pixel circuit provided by an embodiment of the present invention.
  • the pixel circuit, the driving method thereof and the display device provided by the embodiment of the invention enable the switching of the circuit and the charging and discharging control of the circuit by the compensation tube, the capacitor and the plurality of switching tubes, so that the voltage across the compensation tube can also act on the driving tube, thereby enabling
  • the drive current of the drive tube is independent of the threshold voltage of the drive tube.
  • the difference in current flowing through the light emitting device due to the inconsistency or offset of the threshold voltage of the driving tube is compensated, so that the uniformity of the light emitting luminance of the light emitting device can be effectively improved.
  • FIG. 1 is a circuit diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 2 is a timing chart of each signal line when the pixel circuit shown in FIG. 1 is driven;
  • FIG. 3 is a schematic diagram of an equivalent circuit of the pixel circuit shown in FIG. 1 in a compensation phase
  • FIG. 4 is a schematic diagram of an equivalent circuit of the pixel circuit of the first embodiment of the present invention
  • FIG. 5 is a circuit diagram of another pixel circuit according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of another pixel circuit according to an embodiment of the present invention.
  • FIG. 7 is a circuit diagram of another pixel circuit according to an embodiment of the present invention.
  • FIG. 8 is a circuit diagram of another pixel circuit according to an embodiment of the present invention.
  • FIG. 9 is an equivalent circuit diagram of the pixel circuit shown in FIG. 8 in a compensation phase
  • FIG. 10 is a schematic diagram of an equivalent circuit of the pixel circuit of FIG. 8 in a transitional illumination phase
  • FIG. 11 is a flow chart of a method for driving a pixel circuit according to an embodiment of the present invention.
  • an embodiment of the present invention provides a pixel circuit, including:
  • Light emitting device OLED driving transistor DTFT, storage capacitor Cst, first switching transistor T1, second The switch tube T2, the compensation tube ⁇ 3 and the fifth switch tube ⁇ 5.
  • the driving transistor DTFT, the first switching transistor T1, the second switching transistor 2, the compensation transistor 3, and the fifth switching transistor 5 are all ⁇ -type thin film transistors, and each includes a source, a drain, and a gate.
  • One end of the OLED is connected to the power supply VDD;
  • a drain (first pole) of the driving transistor DTFT is connected to the other end of the light emitting device OLED, and a source (second pole) is connected to a drain (first pole) of the fifth switching transistor 5, a pole connected to a drain (first pole) of the first switching transistor T1;
  • the source (second pole) of the first switch T1 is connected to the data line, the gate is connected to the scan line, and the drain (first pole) is connected to the gate of the drive transistor DTFT;
  • the gate of the second switch T2 is connected to the control line, the drain (first pole) is connected to the power source VDD, and the source (second pole) is connected to the source (second pole) of the compensation tube T3;
  • the gate of the compensation tube T3 is connected to the drain (first pole), the drain (first pole) is connected to the drain (first pole) of the driving transistor DTFT, and the source (second pole) and the The source (second pole) of the second switch tube T2 is connected;
  • the gate of the fifth switching transistor T5 is connected to the control line, the drain (first pole) is connected to the source (second pole) of the driving transistor DTFT, and the source (second pole) is connected to the ground;
  • the first plate of the storage capacitor Cst is connected to the gate of the drive transistor DTFT, and the second plate is connected to the source (second pole) of the compensation transistor T3.
  • the compensation tube T3 is equivalent to a diode
  • the drain (first pole) is connected to the gate and is equivalent to the anode of the diode, and is connected to the drain of the driving transistor DTFT (first pole) ), whose source is equivalent to the cathode of the diode, and is connected to the source (second pole) of the second switching transistor T2.
  • the scan line, the control line, and the data line are respectively used to transmit different signals, wherein the scan line transmits the scan signal Vscan, the control line transmits the control signal EM, and the data line transmits the data signal. Vdata.
  • Fig. 1 is a timing chart of each signal line when the pixel circuit shown in Fig. 1 is driven. As shown in Fig. 2, the compensation phase and the hopping illuminating phase are correspondingly represented by 1 and 2, respectively.
  • the driving method of the pixel circuit shown in FIG. 1 is as follows:
  • Phase 1 The compensation phase.
  • the scan signal Vscan is at a high level
  • the control signal EM is at a low level.
  • the first switching transistor T1 is turned on according to the input scan signal Vscan, and the second switching transistor T2 and the fifth switching transistor T5 are turned off according to the control signal EM being at a low level.
  • the compensation tube T3 is in a forward conduction state during the compensation phase.
  • the pixel circuit shown in FIG. 1 can be equivalent to the circuit structure shown in FIG.
  • the data signal Vdata can be input to the gate of the driving transistor DTFT through the first switching transistor T1, and the storage capacitor Cst is charged to input to the driving transistor.
  • the data signal Vdata of the gate of the DTFT is maintained. After charging,
  • the voltage at point A VA is equal to the data signal Vdata
  • the voltage at point B is the power supply voltage.
  • VDD minus the threshold voltage of the OLED.
  • the Voth is subtracted from the threshold voltage Vth3 of the compensation tube T3.
  • the second switching transistor T2 since the control signal EM input to the gate of the second switching transistor T2 is at a low level, the second switching transistor T2 is turned off, so that the storage capacitor Cst can be disconnected from the power supply VDD, and the OLED and the compensation of the light-emitting device are ensured.
  • the data signal Vdata to the gate of the driving transistor DTFT is lost by the connection of the fifth switching transistor T5 to the ground GND.
  • the second stage the transitional lighting stage.
  • the scan signal Vscan is low and the control signal EM is high.
  • the first switching transistor T1 is turned off according to the input scanning signal Vscan, and the second switching transistor T2 and the fifth switching transistor T5 are turned on according to the control signal EM being at a high level.
  • the compensating tube T3 is in the reverse-off state during the hopping illumination phase.
  • the pixel circuit shown in Fig. 1 can be equivalent to the circuit structure shown in Fig. 4.
  • the scan signal Vscan input to the gate of the first switch transistor T1 is at a low level, and the first switch transistor T1 is turned off, so that the gate of the drive transistor DTFT is isolated from the data line, and the drive transistor DTFT is illuminated.
  • the driving of the device OLED is not affected by the number of sources input to the first switching transistor T1. According to the influence of the change of signal Vdata.
  • the control signal EM input to the gate of the fifth switching transistor T5 is at a high level, and the fifth switching transistor T5 is turned on, the source of the driving transistor DTFT is directly connected to the ground GND.
  • the driving transistor DTFT operates in a saturated state, and the current I flowing through the source and the drain of the driving transistor DTFT, that is, the driving current I for driving the light emitting device OLED to emit light, the voltage Vgs between the gate and the source of the driving transistor DTFT Change and change, the specific relationship is shown in equation (5).
  • the drive tube DTFT starts to drive the OLED to emit light.
  • Vgs is the gate-source voltage of the driving transistor DTFT.
  • K eff *Cox*(W/L)/2, where ⁇ ⁇ represents the carrier effective mobility of the DTFT, Cox represents the dielectric constant of the gate insulating layer of the driving transistor DTFT, and W/L represents the trench of the driving transistor DTFT
  • the values of W, L, Cox, and ⁇ ⁇ are relatively stable in the same structure, so ⁇ can be considered as a constant.
  • the current I flowing through the driving transistor DTFT is related to the data signal Vdata and the constant K, and also to the threshold voltage Vth3 of the compensation tube T3, the threshold voltage Vth of the driving transistor DTFT, and the width of the light emitting device OLED.
  • the value voltage Voth is related.
  • LTPS Low Temperature Poly-silicon
  • the current I flowing through the driving transistor DTFT is only related to the data signal Vdata and the threshold voltage Voth of the light emitting device OLED.
  • the driving current I is independent of the threshold voltage Vth of the driving transistor DTFT, thereby avoiding the threshold voltage bias of the driving transistor DTFT caused by the manufacturing process of the backplane and the long-time operation.
  • the driving current I caused by the shift that is, the difference in current flowing through the light emitting device OLED, effectively improves the uniformity of the light emitting luminance of the light emitting device.
  • the pixel circuit provided by the embodiment of the present invention can not only compensate for the difference of the driving current I due to the offset of the threshold voltage Vth of the driving transistor DTFT, but also, due to the driving current I and the light emission
  • the Voth correlation of the OLED of the device OLED can also compensate for the difference in current flowing through the OLED of the OLED due to the high or low value of the threshold voltage Voth of the OLED of the OLED, thereby further improving the brightness of the illuminating device. Sex.
  • the driving current I increases as the threshold voltage Voth of the light emitting device OLED increases, with the threshold voltage of the light emitting device OLED.
  • the Voth is reduced by a decrease, so that when the OLED ages to cause the threshold voltage Voth to rise, the drive current I also rises accordingly to compensate for the decrease in the drive current I due to the rise of the threshold voltage Voth.
  • the driving transistor DTFT does not drive the light emitting device OLED to emit light
  • the light emitting device OLED is in the charging loop of the storage capacitor Cst, so the data signal Vdata is input to the driving transistor DTFT.
  • the gate is charged to the storage capacitor Cst, the OLED still emits a certain amount of light.
  • the driving transistor DTFT, the compensation transistor T3, and each of the switching transistors are ⁇ -type thin film transistors, but the present invention is not limited thereto.
  • Each of the above-mentioned ⁇ -type thin film transistors may be replaced in whole or in part by a ⁇ -type thin film transistor as long as the following conditions are satisfied.
  • the compensation tube 3 and the driving tube DTFT are the same type of thin film transistor, that is, the same type N or the same type P.
  • the compensation tube T3 is used to provide a compensation voltage so that the drive current I of the drive transistor DTFT is independent of the turn-on voltage Vth of the drive transistor DTFT.
  • Vth3 is equal to the turn-on voltage Vth of the driving transistor DTFT.
  • the compensation tube T3 and the driving transistor DTFT need to have the same structure and close distance to meet the short-range order condition of the LTPS process.
  • the second switching transistor T2 and the fifth switching transistor T5 are the same type of thin film transistor, that is, the same type N or the same P type. Since the second switch tube T2 and the fifth switch tube T5 need to be turned on or off at the same time, the on or off is controlled by the control signal EM on the control line.
  • a signal input to the gate of the corresponding thin film transistor such as a scan signal Vscan input to the first switching transistor T1, a control signal EM input to the gates of the second switching transistor T2 and the fifth switching transistor T5, and an input
  • the data signal Vdata to the gate of the drive transistor DTFT may need to be adjusted accordingly. The details are described below by way of specific examples.
  • the pixel circuit includes:
  • the driving transistor DTFT and the compensation transistor T3 are P-type thin film transistors
  • the first switching transistor T1, the second switching transistor ⁇ 2, and the fifth switching transistor ⁇ 5 are all ⁇ -type thin film transistors, and each thin film transistor includes a source and a drain. And the gate.
  • One end of the OLED is connected to the power supply VDD;
  • a source (first pole) of the driving transistor DTFT is connected to the other end of the light emitting device OLED, and a drain (second pole) is connected to a drain (first pole) of the fifth switching transistor T5. a pole connected to a drain (first pole) of the first switching transistor T1;
  • the source (second pole) of the first switch T1 is connected to the data line, the gate is connected to the scan line, and the drain (first pole) is connected to the gate of the drive transistor DTFT;
  • the gate of the second switching transistor T2 is connected to the control line, the drain (first pole) is connected to the power source VDD, and the source (second pole) is connected to the drain (second pole) of the compensation tube T3;
  • the gate of the compensation tube T3 is connected to the drain (second pole), the source (first pole) is connected to the source (first pole) of the driving transistor DTFT, and the drain (second pole) and the The source (second pole) of the second switch tube T2 is connected;
  • a gate of the fifth switching transistor T5 is connected to the control line, a drain (first pole) is connected to a drain (second pole) of the driving transistor DTFT, and a source (second pole) is connected to the ground;
  • the first plate of the storage capacitor Cst is connected to the gate of the driving tube DTFT, and the second plate is connected to the drain (second pole) of the compensation tube T3.
  • the driving transistor DTFT is N-type, and the current I flowing through the source and the drain of the N-type driving transistor DTFT increases as the data signal Vdata increases, along with the data signal Vdata.
  • the driving transistor DTFT is P-type, and the current I flowing through the source and the drain of the P-type driving transistor DTFT decreases as the data signal Vdata increases, along with the data.
  • the signal Vdata is decreased by increasing. Therefore, the data signal Vdata in the embodiment shown in Fig. 1 may be different from the data signal Vdata in the present embodiment, corresponding to the same current I flowing through the driving transistor DTFT.
  • the pixel circuit provided in this embodiment can achieve the same technical effect as the embodiment shown in FIG. 1 by replacing the N-type driving tube DTFT and the N-type compensation tube T3 with the corresponding P-type tube, and details are not described herein again. .
  • FIG. 6 is still another circuit diagram of a pixel circuit according to an embodiment of the present invention.
  • the present embodiment is different from the embodiment shown in Fig. 1 in that the second switching transistor T2 and the fifth switching transistor T5 are not N-type thin film transistors but P-type thin film transistors. Accordingly, the control signal EM input to the gate of the second switching transistor T2 and the gate of the fifth switching transistor T5 is also different from the embodiment shown in FIG.
  • the pixel circuit provided in this embodiment includes: a light emitting device OLED, a driving transistor DTFT, a storage capacitor Cst, a first switching transistor T1, a second switching transistor T2, a compensation tube T3, and a fifth switching tube. T5.
  • the driving transistor DTFT, the first switching transistor T1, and the compensation transistor ⁇ 3 are all ⁇ -type thin film transistors
  • the second switching transistor ⁇ 2 and the fifth switching transistor ⁇ 5 are ⁇ -type thin film transistors
  • each of the thin film transistors includes a source and a drain. Pole and gate.
  • One end of the OLED is connected to the power supply VDD;
  • a drain (first pole) of the driving transistor DTFT is connected to the other end of the light emitting device OLED, and a source (second pole) is connected to a source (first pole) of the fifth switching transistor T5.
  • the source (second pole) of the first switch tube T1 is connected to the data line, the gate is connected to the scan line, and the drain (first pole) is connected to the gate of the drive tube DTFT;
  • the gate of the second switching transistor T2 is connected to the control line, the source (first pole) is connected to the power source VDD, and the drain (second pole) is connected to the source (second pole) of the compensation tube T3;
  • the gate of the compensation tube T3 is connected to the drain (first pole), the drain (first pole) is connected to the drain (first pole) of the driving transistor DTFT, and the source (second pole) and the The drain (second pole) of the two switching tubes T2 is connected;
  • the gate of the fifth switching transistor T5 is connected to the control line, the source (first pole) is connected to the source (second pole) of the driving transistor DTFT, and the drain (second pole) is connected to the ground;
  • the first plate of the storage capacitor Cst is connected to the gate of the drive transistor DTFT, and the second plate is connected to the source (second pole) of the compensation transistor T3.
  • the working process of the pixel circuit is similar to the working process of the pixel circuit in the embodiment shown in FIG. 1, except that the control signal EM controls the opening or closing of the second switching transistor T2 and the fifth switching transistor T5, and The embodiment shown in 1 is different.
  • the control signal EM is at a high level to turn off the second switching transistor T2 and the fifth switching transistor T5.
  • the working process of the pixel circuit provided in this embodiment in the compensation phase is similar to the embodiment shown in Figures 1-4, and will not be described here.
  • the control signal EM is at a low level to turn on the second switching transistor T2 and the fifth switching transistor T5. .
  • the working process of the pixel circuit in the hopping illuminating stage is similar to the embodiment shown in FIG. 1-4, and details are not described herein again.
  • the pixel circuit includes: a light emitting device OLED, a driving transistor DTFT, a storage capacitor Cst, a first switching transistor T1, a second switching transistor T2, a compensation tube T3, and a fifth Switch tube T5.
  • the driving transistor DTFT, the compensation tube T3, the second switching transistor 2, and the fifth switching transistor ⁇ 5 are all ⁇ -type thin film transistors
  • the first switching transistor T1 is a ⁇ -type thin film transistor
  • each of the thin film transistors includes a source and a drain. Pole and gate.
  • One end of the OLED is connected to the power supply VDD;
  • the drain (first pole) of the driving transistor DTFT is connected to the other end of the light emitting device OLED, and the source (second pole) is connected to the drain (first pole) of the fifth switching transistor T5.
  • the drain (second pole) of the first switch transistor T1 is connected to the data line, the gate is connected to the scan line, and the source (first pole) is connected to the gate of the drive transistor DTFT;
  • the gate of the second switch T2 is connected to the control line, the drain (first pole) is connected to the power source VDD, and the source (second pole) is connected to the source (second pole) of the compensation tube T3;
  • the gate of the compensation tube T3 is connected to the drain (first pole), the drain (first pole) is connected to the drain (first pole) of the driving transistor DTFT, and the source (second pole) and the The source (second pole) of the second switch tube T2 is connected;
  • the gate of the fifth switching transistor T5 is connected to the control line, the drain (first pole) is connected to the source (second pole) of the driving transistor DTFT, and the source (second pole) is connected to the ground;
  • the first plate of the storage capacitor Cst is connected to the gate of the drive transistor DTFT, and the second plate is connected to the source (second pole) of the compensation transistor T3.
  • the operation of the pixel circuit is similar to the operation of the pixel circuit in the embodiment shown in FIG. 1, except that the scan signal Vscan controls the first switch tube T1 to be turned on or off, and in the embodiment shown in FIG.
  • the pixel circuit is different.
  • the scan signal Vscan is at a low level, thereby making the first switch tube
  • T1 is turned on.
  • the working process of the pixel circuit provided in this embodiment is similar to that of the embodiment shown in FIG. 1-4, and details are not described herein again.
  • the scan signal Vscan is at a high level, thereby turning off the first switch.
  • the working process of the pixel circuit in the hopping illuminating stage is similar to the embodiment shown in FIG. 1-4, and details are not described herein again.
  • the thin film transistors of the pixel circuit provided by the present invention are all N-type, the driving transistor DTFT and the compensation transistor T3 are P-type, the other thin film transistors are N-type, and the second switching transistor T2 and the fifth switch are used.
  • the tube T5 is of the P type
  • the other thin film transistors are of the N type
  • the case where the first switching transistor T1 is of the P type and the other thin film transistors are of the N type are described in detail.
  • the present invention is not limited thereto.
  • each of the above switching tubes, the driving tube DTFT, and the compensation tube T3 may also be P-type thin film transistors, or other forms of partial thin film transistors are P-type thin film transistors and A part of the thin film transistor is a combination of N-type thin film transistors, as long as the compensation transistor T3 and the driving transistor DTFT are the same type of thin film transistor, that is, the same type N or the same P type, and the second switching tube T2 and the fifth switching tube T5 It is just the same type of thin film transistor.
  • connection method of each P-type thin film transistor in the circuit is similar to the connection method of the original N-type thin film transistor, only according to the gate, the drain and the source of the P-type tube and the N-type tube in the semiconductor physics knowledge.
  • the connection relationship can be appropriately adjusted by the correspondence of the extreme potentials.
  • each of the thin film transistors is an N-type thin film transistor, and the first poles of each thin film transistor are both drains and the second poles are all sources, in other embodiments of the present invention.
  • connection relationship can still be described by the connection relationship between the first pole and the second pole of the thin film transistor in the embodiment shown in FIG. 1, but specifically, The one or the second pole represents the source or the drain of the thin film transistor, which may be different for different types of thin film transistors.
  • the first pole thereof corresponds to the source of the P-type thin film transistor, and the second pole Corresponding to the drain of the P-type thin film transistor; for the compensation tube T3, since the gate is always connected to the drain, when T3 is an N-type thin film transistor, the gate and the drain of the T3 (first pole) Connected, when T3 is a P-type thin film transistor, the gate of T3 is connected to the drain (second pole).
  • the compensation tube T3 is equivalent to a diode, and the drain is connected to the gate and is equivalent to one pole of the diode.
  • the source is equivalent to the other pole of this diode.
  • circuit structure provided by the embodiment of the present invention is similar to the embodiment shown in FIG. 1, except that each of the thin film transistors may be different in N type or P type, and correspondingly, in the circuit.
  • the connection is also slightly adjusted, but no matter how it is changed, it can be ensured that the circuit functions of the compensation phase and the hopping illuminating phase in the above embodiment can be normally realized.
  • the pixel circuit may further include a fourth switch tube T4. It should be noted that, in addition to the fourth switching transistor ,4, the pixel circuit in this embodiment is the same as the pixel circuit in the embodiment shown in FIG.
  • the gate of the fourth switching transistor 4 is connected to the scan line, the drain (first pole) is connected to the drain (first pole) of the second switching transistor 2, and the source (second pole) and the driving transistor DTFT
  • the drain (first pole) is connected, and the fourth switch transistor 4 is of the same type as the first switch transistor T1, that is, the same as a germanium thin film transistor or a germanium thin film transistor.
  • the driving transistor DTFT, the storage capacitor Cst, the first switching transistor T1, the second switching transistor T2, the compensation tube T3 and the fifth switching transistor T5 please refer to the detailed description of the embodiment shown in FIG. I will not repeat them here.
  • the working process of the pixel circuit in this embodiment will be described in detail below with reference to FIG. 2 and FIG. 8-10.
  • Phase 1 The compensation phase.
  • the scan signal Vscan is at a high level
  • the control signal EM is at a low level.
  • the pixel circuit shown in FIG. 8 can be equivalent to the circuit structure shown in FIG. 8 and FIG. 9, the first switching transistor T1 and the fourth switching transistor T4 are N-type thin film transistors, and the scanning signals Vscan input to the gates of the first switching transistor T1 and the fourth switching transistor T4 are at a high level, thereby The first switch tube T1 and the fourth switch tube T4 are turned on.
  • the second switching transistor T2 and the fifth switching transistor T5 are also N-type thin film transistors, and the control signal EM input to their gates is at a low level, thereby turning off the second switching transistor T2 and the fifth switching transistor T5.
  • the light emitting device OLED is short-circuited by the turned-on fourth switch tube T4. Therefore, unlike the embodiment shown in FIG. 1, in this embodiment, no current flows through the light at this stage.
  • the device OLED the light emitting device OLED does not emit light.
  • the data signal Vdata can be input to the gate of the drive transistor DTFT through the first switch T1 and held.
  • the voltage VA at point A is the data signal Vdata.
  • Point B voltage VB is the power supply voltage VDD minus the threshold voltage Vth3 of the compensation tube, ie
  • the second switching transistor T2 disconnects the storage capacitor Cst from the power supply VDD according to the input low-level control signal EM, thereby ensuring the forward conduction of the compensation tube T3.
  • the fifth switching transistor T5 disconnects the driving transistor DTFT from the ground GND according to the input low-level control signal EM, thereby preventing the data signal Vdata input to the gate of the driving transistor DTFT from passing through the fifth switching transistor T5 and the ground GND. The connection is lost.
  • the second stage the transitional lighting stage.
  • the scan signal Vscan is at a low level
  • the control signal EM is at a high level.
  • the pixel circuit shown in FIG. 8 can be equivalent to the circuit structure as shown in FIG.
  • the first switching transistor T1 is turned off according to the input scan signal Vscan, so that the gate of the driving transistor DTFT and the source of the first switching transistor T1, that is, the input end of the data signal Vdata. isolation.
  • the driving of the light-emitting device OLED by the driving transistor DTFT is not affected by the signal variation of the source of the first switching transistor T1.
  • the fourth switching transistor T4 is turned off according to the input scanning signal Vscan, so that the driving transistor DTFT is no longer short-circuited, so that the light-emitting device OLED can be driven to emit light.
  • the second switch T2 is turned on according to the control signal EM, the upper plate of the storage capacitor Cst is directly connected to the power supply VDD, and the voltage VB at the B point is instantaneously changed from Vdata to VDD. It is known from physics that the voltage between the two plates of the capacitor does not change instantaneously. Therefore, when the voltage at point B VB has just jumped to VDD, equation (11) still holds. Then, at this time, the voltage at point A is equal to the voltage at point B, VB, and the voltage VAB between point A and point B, that is,
  • the fifth switching transistor T5 is turned on according to the control signal ⁇ , and the source of the driving transistor DTFT is directly connected to the ground GND. At this time, the driving tube DTFT starts to drive the OLED to emit light.
  • the gate-source voltage of the driving transistor DTFT is
  • the current flowing through the driving transistor DTFT is
  • equation (14) can be expressed as:
  • K has the same meaning as the foregoing embodiment, and can be considered as a constant here.
  • the current flowing through the driving transistor DTFT is only related to the data signal Vdata, and is independent of the threshold voltage Vth of the driving transistor DTFT, thereby avoiding the threshold value of the driving transistor DTFT caused by the manufacturing process of the backplane and the long-time operation.
  • the difference in current flowing through the light emitting device OLED caused by the voltage offset effectively improves the uniformity of the light emitting luminance of the light emitting device.
  • the fourth switching transistor T4 short-circuits the light emitting device OLED in the compensation phase. That is, no current flows through the light-emitting device OLED during the compensation phase, and the light-emitting device OLED does not emit light, thereby avoiding the occurrence of flicker in the compensation phase of the light-emitting device OLED.
  • the present invention is described by taking an OLED as an example.
  • the illuminating device provided by the embodiment of the present invention may be another illuminating device capable of driving the pixel circuit in the embodiment of the present invention, and the present invention does not limit.
  • each thin film transistor is an N-type thin film transistor
  • the fourth switching transistor T4 is added thereto for explanation.
  • each of the thin film transistors may be replaced in whole or in part as a P-type thin film transistor, and only the following conditions are satisfied: the compensation tube T3 and the driving transistor DTFT are the same type of thin film transistor, and the fourth switching tube T4 and
  • the first switching transistor T1 is a thin film transistor of a type
  • the second switching transistor T2 and the fifth switching transistor T5 may be the same type of thin film transistor.
  • the same type of thin film transistor means an N-type thin film transistor or a P-type thin film transistor.
  • an embodiment of the present invention further provides a driving method of a pixel circuit, including:
  • the first switch tube T1 is turned on, and the second switch tube T2 and the fifth switch tube T5 are turned off, so that the data signal Vdata in the data line charges the first plate of the storage capacitor Cst through the first switch tube T1. And causing the power supply VDD to charge the second plate of the storage capacitor Cst through the light emitting device OLED and the compensation tube T3;
  • the first switch tube T1 is turned off, and the second switch tube T2 and the fifth switch tube T5 are turned on, so that the light-emitting device OLED is sequentially supplied by the power source VDD through the light-emitting device OLED, the driving tube DTFT, and the fifth switch tube.
  • the current of T5 drives the illumination.
  • the driving method of the pixel circuit divides the driving of the pixel circuit into two stages by the compensation tube T3, the storage capacitor and the plurality of switching tubes for the switching and charging and discharging control of the circuit, thereby making the driving tube DTFT
  • the driving current is independent of the threshold voltage Vth of the driving transistor DTFT, and compensates for the difference in current flowing through the light emitting device OLED due to the inconsistency or offset of the threshold voltage Vth of the driving transistor DTFT, thereby effectively improving the luminance of the light emitting device. Uniformity.
  • the turn-on voltage Voth of the light-emitting device such as the OLED can also be added between the gate and the second pole of the driving transistor DTFT in the jump light-emitting phase, it is possible to compensate for the increase in the threshold voltage of the light-emitting device OLED.
  • the difference in current flowing through the light emitting device OLED is an OLED, but the present invention is not limited thereto, and other illuminating devices that can be driven by the pixel circuit provided by the embodiment of the present invention may be used.
  • the first switch tube T1, the second switch tube ⁇ 2, and the fifth switch tube ⁇ 5 are all ⁇ -type thin film transistors, and their first extreme drain and second extreme source .
  • the driving method of the pixel circuit provided by the embodiment of the present invention can input the high level to the gate of the first switching transistor T1 through the scan line to turn on the first switching tube T1, and simultaneously input the low level through the control line.
  • the gate of the second switch transistor 2 and the gate of the fifth switch transistor 5 turn off the second switch transistor 2 and the fifth switch transistor 5; correspondingly, for step S12, the low level can also be input to the first switch through the scan line.
  • the gate of the tube T1 turns off the first switching transistor T1, and simultaneously inputs a high level through the control line to the gate of the second switching transistor ⁇ 2 and the gate of the fifth switching transistor ⁇ 5 to the second switching transistor ⁇ 2 and the fifth switching transistor ⁇ 5 is turned on.
  • the first switch transistor T1 is a ⁇ -type thin film transistor having a first extreme drain and a second extreme source; the second switch transistor ⁇ 2 and the fifth switch transistor ⁇ 5 are both The first extreme source of the second switching transistor ⁇ 2 and the fifth switching transistor ,5, and the second extreme drain.
  • the driving method of the pixel circuit provided by the embodiment of the present invention can input the high level to the gate of the first switching transistor T1 through the scan line to turn on the first switching transistor T1, and simultaneously input the high level through the control line.
  • the gate of the second switch transistor 2 and the gate of the fifth switch transistor 5 turn off the second switch transistor 2 and the fifth switch transistor 5; correspondingly, for step S12, the low level can also be input to the first switch through the scan line.
  • the gate of the tube T1 turns off the first switching transistor T1, and simultaneously inputs a low level through the control line to the gate of the second switching transistor ⁇ 2 and the gate of the fifth switching transistor ⁇ 5 to the second switching transistor ⁇ 2 and the fifth switching transistor ⁇ 5 is turned on.
  • the first switching transistor T1 is a ⁇ -type thin film transistor, the first extreme source of the first switching transistor T1, the second extreme drain; the second switching transistor ⁇ 2 and the The five switching transistors ⁇ 5 are all ⁇ -type thin film transistors, and their first extreme drain and second extreme source.
  • the driving method of the pixel circuit can input the low level to the gate of the first switching transistor T1 through the scan line to turn on the first switching transistor T1, and simultaneously input the low level through the control line.
  • the gate of the second switch transistor 2 and the gate of the fifth switch transistor 5 turn off the second switch transistor 2 and the fifth switch transistor 5; correspondingly, for step S12, the high level can be input to the first switch transistor through the scan line.
  • the gate of T1 turns off the first switching transistor T1, and simultaneously inputs a high level through the control line to the gate of the second switching transistor ⁇ 2 and the gate of the fifth switching transistor ⁇ 5 to the second switching transistor T2 and the fifth switching tube T5 are turned on.
  • the first switch tube T1, the second switch tube ⁇ 2, and the fifth switch tube ⁇ 5 are all ⁇ -type thin film transistors.
  • the driving method of the pixel circuit provided by the embodiment of the present invention can input the low level to the gate of the first switching transistor T1 through the scan line to turn on the first switching transistor T1, and simultaneously input the high level through the control line.
  • the gate of the second switch transistor 2 and the gate of the fifth switch transistor 5 turn off the second switch transistor 2 and the fifth switch transistor 5; correspondingly, for step S12, the high level can be input to the first switch transistor through the scan line.
  • the gate of T1 turns off the first switching transistor T1, and simultaneously inputs a low level through the control line to the gate of the second switching transistor 2 and the gate of the fifth switching transistor 5 to the second switching transistor 2 and the fifth switching transistor 5 Open.
  • the opening of the first switch tube T1 may further open the first switch tube T1 and the fourth switch tube ⁇ 4;
  • the first switch tube T1 and the fourth switch tube ⁇ 4 are simultaneously turned on, and the second switch tube ⁇ 2 and the fifth switch tube ⁇ 5 are simultaneously turned off, so that the data line, that is, the signal line where the data signal Vdata is located, passes through the first
  • the switch tube T1 charges the first plate of the storage capacitor Cst, so that the power source VDD charges the second plate of the storage capacitor Cst through the fourth switch tube T4 and the compensation tube T3.
  • step S12 the first switch tube T1 is turned off to close the first switch tube T1 and the fourth switch tube T4 at the same time.
  • the first switch tube T1 and the fourth switch tube T4 are simultaneously turned off, and the second switch tube T2 and the fifth switch tube T5 are turned on at the same time, so that the light emitting device OLED is sequentially supplied by the power source VDD and flows through the light emitting device OLED.
  • the gate of the fourth switching transistor T4 is connected to the scan line, the first pole is connected to the first pole of the second switching transistor T2, the second pole is connected to the first pole of the driving transistor DTFT, and the fourth switching transistor T4 and the first A switch tube T1 is of the same type.
  • the fourth switch tube T4 and the first switch tube T1 are both controlled by the scan signal Vscan, the fourth switch tube T4 is turned on or off together with the first switch tube T1.
  • the fourth switch tube T4 and the For the principle and detailed procedure of the opening or closing of a switch T1 refer to the description of the foregoing embodiment, and details are not described herein again.
  • the fourth switching transistor T4 Since the fourth switching transistor T4 is turned on during the compensation phase, the light emitting device OLED can be short-circuited by the fourth switching transistor T4, that is, no current flows through the light emitting device OLED during the compensation phase, and the light emitting device OLED does not emit light, thereby avoiding the light emitting device OLED being The compensation phase flashes.
  • the present invention also provides a display device, including any of the foregoing embodiments.
  • the pixel circuit has the beneficial technical effects brought by the pixel circuit provided by the embodiment of the present invention. The foregoing has been described in detail, and details are not described herein again.

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Abstract

一种像素电路及其驱动方法。该像素电路包括发光器件（OLED）、驱动管（DTFT）、存储电容（Cst）、第一开关管（T1）、第二开关管（T2）、补偿管（T3）和第五开关管（T5）。发光器件（OLED）的一端与电源（VDD）相连。驱动管（DTFT）的第一极与发光器件（OLED）的另一端相连，第二极与第五开关管（T5）的第一极相连，栅极与第一开关管（T1）的第一极相连。第一开关管（T1）的第二极与数据线相连，栅极与扫描线相连，第一极与驱动管（DTFT）的栅极相连。第二开关管（T2）的栅极与控制线相连，第一极与电源（VDD）相连，第二极与补偿管（T3）的第二极相连。补偿管（T3）的第一极与驱动管（DTFT）的第一极相连，第二极与第二开关管（T2）的第二极相连，栅极与补偿管（T3）的第一极或第二极相连。第五开关管（T5）的栅极与控制线相连，第一极与驱动管（DTFT）的第二极相连，第二极与地（GND）相连。存储电容（Cst）的第一极板与驱动管（DTFT）的栅极相连，第二极板与补偿管（T3）的第二极相连。

Description

一种像素电路及其驱动方法 技术领域
本发明涉及显示技术领域， 尤其涉及一种像素电路及其驱动方法、 显 示装置。
背景技术
有机发光二极管（ Organic Light Emitting Diode, OLED )为电流驱动主 动发光型器件， 具有自发光、 快速响应、 宽视角和可制作在柔性衬底上等 独特优点。 以 OLED为基础的有机发光显示预计今后几年将成为显示领域 的主流。 有机发光显示的每个显示单元， 都是由 OLED构成的， OLED按驱 动方式可分为无源矩阵驱动有机发光二极管 （Passive Matrix Driving OLED, PMOLED)和有源矩阵驱动有机发光二极管 （Active Matrix Driving OLED, AMOLED )两种。 有源矩阵驱动方式因其能够实现高品质显示， 因 此在大信息量显示中应用十分广泛。 其中， AMOLED技术中， 每个 OLED 都有薄膜晶体管 (Thin Film Transistor, TFT)电路来控制流过 OLED的电流， OLED和用于驱动 OLED的 TFT电路构成像素电路， 因此， 为保证有源有 机发光显示面板亮度的均匀性， 就要求位于背板的不同区域内的用于驱动 OLED的 TFT的特性具有一致性。
TFT的阔值电压和很多因素有关， 包括 TFT第一极的掺杂、 电介质的 厚度、 栅极材质和电介质中的过剩电荷。 目前在背板尤其是大尺寸的背板 制作过程中， 由于工艺条件和水平的限制很难做到这些因素的一致性， 使 得各 TFT的阔值电压偏移不一致； 另外， 长时间工作导致的 TFT稳定性下 降等问题， 也会使得 TFT的阔值电压偏移不一致， 而 TFT的阔值电压偏移 不一致又会造成流经各 OLED 的电流有所差异， 进而使被该电流驱动的 OLED发光均勾性差。
发明内容
本发明实施例提供一种像素电路及其驱动方法、 显示装置， 有效提高 了发光器件发光亮度的均匀性。 本发明实施例提供如下技术方案：
一种像素电路， 包括：
发光器件、 驱动管、 存储电容、 第一开关管、 第二开关管、 补偿管和 第五开关管；
所述驱动管、 第一开关管、 第二开关管、 补偿管、 第五开关管均包括 栅极、 第一极和第二极；
所述发光器件的一端与电源相连；
所述驱动管的第一极与所述发光器件的另一端相连， 第二极与所述第 五开关管的第一极相连， 栅极与所述第一开关管的第一极相连；
所述第一开关管的第二极与数据线相连， 栅极与扫描线相连， 第一极 与所述驱动管的栅极相连；
所述第二开关管的栅极与控制线相连， 第一极与电源相连， 第二极与 所述补偿管的第二极相连；
所述补偿管的第一极与所述驱动管的第一极相连， 第二极与所述第二 开关管的第二极相连， 栅极与所述补偿管的第一极或第二极相连；
所述第五开关管的栅极与控制线相连， 第一极与所述驱动管的第二极 相连， 第二极与地相连；
所述存储电容的第一极板与所述驱动管的栅极相连， 第二极板与所述 补偿管的第二极相连。
一种用于所述像素电路的驱动方法， 包括：
将所述第一开关管开启， 同时将所述第二开关管和所述第五开关管关 闭， 以使数据线中的数据信号通过所述第一开关管对所述存储电容的第一 极板充电， 使所述电源通过所述发光器件和所述补偿管对所述存储电容的 第二极板充电；
将所述第一开关管关闭， 同时将所述第二开关管和所述第五开关管开 启， 以使所述发光器件被所述电源提供的、 依次流经所述发光器件、 所述 驱动管和所述第五开关管的电流驱动发光。
一种显示装置， 包括本发明实施例提供的像素电路。
本发明实施例提供的像素电路及其驱动方法、 显示装置， 通过补偿管、 电容和多个开关管对于电路的开关和充放电控制， 使补偿管两端的电压也 能作用于驱动管， 进而使驱动管的驱动电流与驱动管的阔值电压无关， 补 偿了由于驱动管的阔值电压的不一致或偏移所造成的流过发光器件的电流 差异， 因此能够有效提高发光器件发光亮度的均匀性。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对 实施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员 来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附 图。
图 1为本发明实施例提供的一种像素电路的电路图；
图 2是驱动图 1所示像素电路时各信号线的时序图；
图 3是图 1所示像素电路在补偿阶段的等效电路示意图；
图 4是图 1所示像素电路在跳变发光阶段的等效电路示意图； 图 5为本发明实施例提供的另一种像素电路的电路图；
图 6为本发明实施例提供的另一种像素电路的电路图；
图 7为本发明实施例提供的另一种像素电路的电路图；
图 8为本发明实施例提供的另一种像素电路的电路图；
图 9是图 8所示像素电路在补偿阶段的等效电路示意图；
图 10是图 8所示像素电路在跳变发光阶段的等效电路示意图； 图 11是本发明实施例提供的像素电路的驱动方法的一种流程图。
具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进 行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没 有做出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的 范围。
如图 1所示， 本发明的实施例提供了一种像素电路， 包括：
发光器件 OLED, 驱动管 DTFT, 存储电容 Cst, 第一开关管 T1 , 第二 开关管 T2, 补偿管 Τ3和第五开关管 Τ5。 所述驱动管 DTFT、 第一开关管 Tl、 第二开关管 Τ2、 补偿管 Τ3、 第五开关管 Τ5均为 Ν型薄膜晶体管， 且 均包括源极、 漏极和栅极。
发光器件 OLED的一端与电源 VDD相连；
所述驱动管 DTFT的漏极（第一极）与所述发光器件 OLED的另一端 相连， 源极（第二极）与所述第五开关管 Τ5的漏极（第一极）相连， 栅极 与所述第一开关管 T1的漏极（第一极）相连；
所述第一开关管 T1的源极（第二极）与数据线相连， 栅极与扫描线相 连， 漏极（第一极）与所述驱动管 DTFT的栅极相连；
所述第二开关管 T2的栅极与控制线相连， 漏极（第一极）与电源 VDD 相连， 源极（第二极） 与所述补偿管 T3的源极（第二极）相连；
所述补偿管 T3的栅极与漏极 (第一极）相连， 漏极 (第一极）与所述 驱动管 DTFT的漏极（第一极）相连， 源极（第二极）与第二开关管 T2的 源极（第二极）相连；
所述第五开关管 T5的栅极与控制线相连， 漏极（第一极 )与所述驱动 管 DTFT的源极（第二极 )相连， 源极（第二极 )与地相连；
所述存储电容 Cst的第一极板与驱动管 DTFT的栅极相连，第二极板与 补偿管 T3的源极 (第二极 )相连。
需要说明的是，本实施例中，补偿管 T3相当于一个二极管，其漏极（第 一极）与栅极相连后相当于此二极管的正极， 连接到驱动管 DTFT 的漏极 (第一极） ， 其源极相当于此二极管的负极， 连接于第二开关管 T2的源极 (第二极） 。
需要指出的是， 本实施例中， 扫描线、 控制线和数据线分别用于传输 不同的信号， 其中， 扫描线中传输扫描信号 Vscan, 控制线中传输控制信号 EM, 数据线中传输数据信号 Vdata。
下面结合图 2-4对图 1所示像素电路的工作过程进行详细说明。在进行 驱动时， 图 1 所示像素电路可分为两个驱动阶段， 分别为： 补偿阶段和跳 变发光阶段。 图 2是驱动图 1 所示像素电路时各信号线的时序图。 如图 2 所示， 在图中分别用①和②来相应地表示补偿阶段和跳变发光阶段。 对图 1 所示像素电路的驱动方法具体如下：
第一阶段： 补偿阶段。 在补偿阶段中， 扫描信号 Vscan为高电平， 控制信号 EM为低电平。 第一开关管 T1 根据输入的扫描信号 Vscan为高电平而开启， 第二开关管 T2和第五开关管 T5根据控制信号 EM为低电平而关闭。 补偿管 T3在补偿 阶段处于正向导通状态。 此时， 图 1所示的像素电路可等效为如图 3所示 的电路结构。
结合图 1和图 3 ,在补偿阶段，由于第一开关管 T1开启，数据信号 Vdata 可以通过第一开关管 T1输入至驱动管 DTFT的栅极， 并向存储电容 Cst充 电以使输入至驱动管 DTFT的栅极的数据信号 Vdata得以保持。充电完毕后，
A点电压 VA即等于数据信号 Vdata,
即 VA= Vdata ( 1 )
B点电压为电源电压 VDD减去发光器件 OLED的阔值电压 Voth再减 去补偿管 T3的阔值电压 Vth3 , 即
VB=VDD-Voth-Vth3 ( 2 )
则存储电容 Cst两极板之间的电压为
VAB=VA-VB=Vdata- ( VDD- Voth- Vth3 )
= Vdata- VDD+ Voth+Vth3 ( 3 )
与此同时， 由于输入第二开关管 T2的栅极的控制信号 EM为低电平， 第二开关管 T2关闭， 因此可以使存储电容 Cst与电源 VDD相断开， 保证 了发光器件 OLED和补偿管 T3的正向导通； 由于输入第五开关管 T5的栅 极的控制信号 EM为低电平，第五开关管 T5关闭，因此可以使驱动管 DTFT 与地 GND相断开，从而避免了输入至驱动管 DTFT的栅极的数据信号 Vdata 通过第五开关管 T5与地 GND的连接而损失。
第二阶段： 跳变发光阶段。
在跳变发光阶段， 扫描信号 Vscan为低电平， 控制信号 EM为高电平。 第一开关管 T1 根据输入的扫描信号 Vscan为低电平而关闭， 第二开关管 T2和第五开关管 T5根据控制信号 EM为高电平而开启。 补偿管 T3在跳变 发光阶段处于反向截至状态。 此时， 图 1 所示的像素电路可等效为如图 4 所示的电路结构。
结合图 1和图 4, 输入至第一开关管 T1栅极的扫描信号 Vscan为低电 平， 第一开关管 T1关闭， 这样驱动管 DTFT的栅极与数据线相隔离， 驱动 管 DTFT对发光器件 OLED的驱动就不会受输入至第一开关管 T1的源极数 据信号 Vdata变化的影响。
与此同时， 由于输入至第二开关管 T2栅极的控制信号 EM为高电平， 第二开关管 T2开启，使存储电容 Cst的上极板直接与电源 VDD相连，则 B 点电压 VB瞬间变到 VDD。 由物理知识可知， 电容两极板之间的电压不会 瞬间改变 , 因此， 在跳变发光阶段， B点电压 VB刚刚跳变至 VDD时 , 式 ( 3 )仍然成立。 那么， 此时 A点电压 VA等于 B点电压 VB加上 A点和 B 点之间的电压 VAB, 即
VA=VB+VAB=VDD+ ( Vdata- VDD+ Voth+Vth3 )
= Vdata+ Voth+Vth3 ( 4 )
同时， 由于输入至第五开关管 T5的栅极的控制信号 EM为高电平， 第 五开关管 T5开启， 则驱动管 DTFT的源极直接与地 GND相连。 此时， 驱 动管 DTFT工作在饱和状态， 流过驱动管 DTFT的源极、 漏极的电流 I, 即 驱动发光器件 OLED发光的驱动电流 I随驱动管 DTFT栅极与源极间的电 压 Vgs 的变化而变化， 具体关系如式（5 )所示。 驱动管 DTFT开始驱动 OLED发光。
I=K(Vgs-Vth)2 ( 5 )
其中， Vgs为驱动管 DTFT的栅源电压， 本实施例中，
Vgs=VA- 0= Vdata+ Voth+Vth3 ( 6 )
K= eff*Cox*(W/L)/2, 其中， μείϊ表示 DTFT的载流子有效迁移率， Cox 表示驱动管 DTFT的栅绝缘层介电常数， W/L表示驱动管 DTFT的沟道宽 长比， 其中， W表示沟道宽度， L表示沟道长度。 相同结构中 W、 L、 Cox 和 μείΓ数值相对稳定， 所以 Κ可认为是一常量。
则， 将式（6 ) 带入式（5 ) 中， 本实施例中， 流经驱动管 DTFT 的电 流为
I=K(Vdata+ Voth+Vth3 -Vth)2 ( 7 )
由 （ 7 ) 式可知流经驱动管 DTFT的电流 I除与数据信号 Vdata及常量 K有关外， 还与补偿管 T3的阔值电压 Vth3、 驱动管 DTFT的阔值电压 Vth 以及发光器件 OLED 的阔值电压 Voth有关。 而根据低温多晶硅（Low Temperature Poly-silicon , LTPS )工艺的短程有序原理， 短程内的薄膜晶体 管可以认为是均匀的， 即距离相近、 结构相同的薄膜晶体管特性近似相同。 因此， 优选的， 在本实施例中， 补偿管 T3和驱动管 DTFT位置艮接近， 可 认为是在短程内 , 所以补偿管 T3的阔值电压 Vth3和驱动管 DTFT的阔值 电压 Vth近似相同， 即 Vth3-Vth=0, 这样， 根据式（7 ) , 则流经驱动管 DTFT的电流 I为
I=K(Vdata+Voth)2 ( 8 )
即流经驱动管 DTFT的电流 I就只与数据信号 Vdata和发光器件 OLED 的阔值电压 Voth相关。
这样， 本发明实施例提供的像素电路， 一方面， 驱动电流 I 与驱动管 DTFT的阔值电压 Vth无关，避免了因背板制造工艺原因及长时间工作导致 的驱动管 DTFT 的阔值电压偏移所造成的驱动电流 I, 也即流过发光器件 OLED的电流差异， 从而有效提高了发光器件发光亮度的均匀性。
另一方面， 根据式（8 ) , 本发明实施例提供的像素电路不仅能补偿由 于驱动管 DTFT的阔值电压 Vth的偏移而导致的驱动电流 I的差异， 而且， 由于驱动电流 I与发光器件 OLED的阔值电压 Voth相关， 也能够补偿由于 发光器件 OLED 的阔值电压 Voth 的偏高或偏低而导致的流过发光器件 OLED的电流差异，从而进一步提高了发光器件发光亮度的均勾性。这是因 为， 根据式（8 ) , 本发明实施例提供的像素电路中， 驱动电流 I会随着发 光器件 OLED的阔值电压 Voth的增大而增大，随着发光器件 OLED的阔值 电压 Voth的减小而减小，这样当 OLED老化而引起阔值电压 Voth升高时， 驱动电流 I也相应的有所上升以补偿由于阔值电压 Voth升高而引起的驱动 电流 I的减小。
需要说明的是， 本实施例中， 在补偿阶段， 虽然驱动管 DTFT 并未驱 动发光器件 OLED发光， 但发光器件 OLED处于存储电容 Cst的充电回路 中， 因此在数据信号 Vdata输入至驱动管 DTFT的栅极并向存储电容 Cst充 电时， OLED还是会发出一定的光。
上述实施例中， 驱动管 DTFT、 补偿管 T3、 以及各个开关管均为 Ν型 薄膜晶体管， 但本发明不限于此。 上述各 Ν型薄膜晶体管可以全部或部分 替换为 Ρ型薄膜晶体管， 只要满足下列条件。
首先要满足补偿管 Τ3与驱动管 DTFT为同一类型的薄膜晶体管， 即同 为 N型或同为 P型的条件。 这是因为， 由上述对本发明实施例的两个工作 阶段的分析可知， 补偿管 T3用于提供一个补偿电压以使驱动管 DTFT的驱 动电流 I与驱动管 DTFT的开启电压 Vth无关。这就要求其提供的补偿电压 Vth3与驱动管 DTFT的开启电压 Vth相等， 为了达到这一效果， 补偿管 T3 与驱动管 DTFT需要具有相同的结构和很近的距离，以满足 LTPS工艺的短 程有序条件。
其次， 要满足第二开关管 T2与第五开关管 T5为同一类型的薄膜晶体 管， 即同为 N型或同为 P型的条件。 因为第二开关管 T2与第五开关管 T5 需要同时开启或关闭， 该开启或关闭均由控制线上的控制信号 EM控制。
需要说明的是， 由于 P型薄膜晶体管和 N型薄膜晶体管的开启或关闭 的条件不同， 因此， 当上述实施例中的 N型薄膜晶体管被 P型薄膜晶体管 替代时， 为了保证该像素电路的功能的正常实现， 输入至相应薄膜晶体管 的栅极的信号， 如输入至第一开关管 T1的扫描信号 Vscan, 输入至第二开 关管 T2和第五开关管 T5栅极的控制信号 EM, 以及输入至驱动管 DTFT 的栅极的数据信号 Vdata都可能需要做相应的调整。下面通过具体实施例详 细说明。
如图 5所示， 在本发明的另一个实施例中， 像素电路包括：
发光器件 OLED, 驱动管 DTFT, 存储电容 Cst, 第一开关管 T1 , 第二 开关管 T2, 补偿管 T3和第五开关管 T5。 所述驱动管 DTFT和补偿管 T3 为 P型薄膜晶体管， 第一开关管 Tl、 第二开关管 Τ2和第五开关管 Τ5均为 Ν型薄膜晶体管， 且各薄膜晶体管均包括源极、 漏极和栅极。
发光器件 OLED的一端与电源 VDD相连；
所述驱动管 DTFT的源极（第一极）与所述发光器件 OLED的另一端 相连， 漏极（第二极）与所述第五开关管 T5的漏极（第一极）相连， 栅极 与所述第一开关管 T1的漏极（第一极）相连；
所述第一开关管 T1的源极（第二极）与数据线相连， 栅极与扫描线相 连， 漏极（第一极）与所述驱动管 DTFT的栅极相连；
所述第二开关管 T2的栅极与控制线相连， 漏极（第一极）与电源 VDD 相连， 源极（第二极） 与所述补偿管 T3的漏极（第二极）相连；
所述补偿管 T3的栅极与漏极（第二极 )相连， 源极（第一极 )与所述 驱动管 DTFT的源极（第一极）相连， 漏极（第二极）与第二开关管 T2的 源极（第二极）相连；
所述第五开关管 T5的栅极与控制线相连， 漏极（第一极 )与所述驱动 管 DTFT的漏极（第二极）相连， 源极（第二极）与地相连； 所述存储电容 Cst的第一极板与驱动管 DTFT的栅极相连，第二极板与 补偿管 T3的漏极（第二极 )相连。
与图 1所示的实施例相比， 本实施例中仅驱动管 DTFT和补偿管 T3与 图 1所示的实施例有所不同， 相应的， 输入至驱动管 DTFT的栅极的数据 信号 Vdata也有所不同。
在图 1所示的实施例中 ,驱动管 DTFT为 N型，流过 N型驱动管 DTFT 的源极和漏极的电流 I随着数据信号 Vdata的升高而增大， 随着数据信号 Vdata的降低而减小； 而本实施例中 , 驱动管 DTFT为 P型， 流过 P型驱动 管 DTFT的源极和漏极的电流 I随着数据信号 Vdata的升高而减小，随着数 据信号 Vdata的降低而增大。 因此，对应于相同的流过驱动管 DTFT的电流 I, 图 1所示的实施例中的数据信号 Vdata与本实施例中的数据信号 Vdata 可以不相同。
需要说明的是， 除上述区别外， 本实施例中像素电路的其它部分与图 1 所示的结构相同， 此处不再赘述。
本实施例提供的像素电路，通过将 N型驱动管 DTFT和 N型补偿管 T3 替换为相应的 P型管， 同样可以实现与图 1所示的实施例相同的技术效果， 此处不再赘述。
图 6为本发明实施例提供的像素电路的又一种电路图。 如图 6所示， 本实施例与图 1所示实施例的不同之处在于， 第二开关管 T2和第五开关管 T5不是 N型薄膜晶体管， 而是 P型薄膜晶体管。 相应的， 输入至第二开关 管 T2的栅极和第五开关管 T5的栅极的控制信号 EM也与图 1所示的实施 例有所不同。
具体的，如图 6所示，本实施例提供的像素电路包括：发光器件 OLED, 驱动管 DTFT, 存储电容 Cst, 第一开关管 T1 , 第二开关管 T2, 补偿管 T3 和第五开关管 T5。 其中， 所述驱动管 DTFT、 第一开关管 Tl、 补偿管 Τ3 均为 Ν型薄膜晶体管， 第二开关管 Τ2、 第五开关管 Τ5为 Ρ型薄膜晶体管， 各薄膜晶体管均包括源极、 漏极和栅极。
发光器件 OLED的一端与电源 VDD相连；
所述驱动管 DTFT的漏极（第一极）与所述发光器件 OLED的另一端 相连， 源极（第二极）与所述第五开关管 T5的源极（第一极）相连， 栅极 与所述第一开关管 T1的漏极（第一极）相连； 所述第一开关管 Tl的源极（第二极）与数据线相连， 栅极与扫描线相 连， 漏极（第一极）与所述驱动管 DTFT的栅极相连；
所述第二开关管 T2的栅极与控制线相连， 源极（第一极）与电源 VDD 相连， 漏极（第二极） 与所述补偿管 T3的源极（第二极）相连；
所述补偿管 T3的栅极与漏极 (第一极）相连， 漏极 (第一极）与所述 驱动管 DTFT的漏极（第一极）相连， 源极（第二极）与第二开关管 T2的 漏极（第二极）相连；
所述第五开关管 T5的栅极与控制线相连， 源极（第一极）与所述驱动 管 DTFT的源极（第二极 )相连， 漏极（第二极 )与地相连；
所述存储电容 Cst的第一极板与驱动管 DTFT的栅极相连，第二极板与 补偿管 T3的源极 (第二极 )相连。
本实施例中， 像素电路的工作过程与图 1 所示的实施例中像素电路的 工作过程类似， 只是控制信号 EM控制第二开关管 T2和第五开关管 T5的 开启或关闭时， 与图 1所示的实施例有所不同。
具体的， 与图 1 所示的实施例不同的是， 本实施例中， 在补偿阶段， 控制信号 EM为高电平从而使第二开关管 T2和第五开关管 T5关闭。 本实 施例提供的像素电路在补偿阶段的工作过程与图 1-4所示的实施例类似，此 处不再赘述。
相应的， 与图 1 所示的实施例还有所不同的是， 本实施例中， 在跳变 发光阶段， 控制信号 EM为低电平从而使第二开关管 T2和第五开关管 T5 开启。本实施例提供的像素电路在跳变发光阶段的工作过程与图 1-4所示的 实施例类似， 此处不再赘述。
如图 7 所示， 在本发明的另一个实施例中， 像素电路包括： 发光器件 OLED, 驱动管 DTFT, 存储电容 Cst, 第一开关管 Tl , 第二开关管 T2, 补 偿管 T3和第五开关管 T5。 其中， 所述驱动管 DTFT、 补偿管 T3、 第二开 关管 Τ2、第五开关管 Τ5均为 Ν型薄膜晶体管， 第一开关管 T1为 Ρ型薄膜 晶体管， 各薄膜晶体管均包括源极、 漏极和栅极。
发光器件 OLED的一端与电源 VDD相连；
所述驱动管 DTFT的漏极（第一极）与所述发光器件 OLED的另一端 相连， 源极（第二极）与所述第五开关管 T5的漏极（第一极）相连， 栅极 与所述第一开关管 T1的源极（第一极）相连； 所述第一开关管 Tl的漏极（第二极）与数据线相连， 栅极与扫描线相 连， 源极（第一极）与所述驱动管 DTFT的栅极相连；
所述第二开关管 T2的栅极与控制线相连， 漏极（第一极）与电源 VDD 相连， 源极（第二极） 与所述补偿管 T3的源极（第二极）相连；
所述补偿管 T3的栅极与漏极 (第一极）相连， 漏极 (第一极）与所述 驱动管 DTFT的漏极（第一极）相连， 源极（第二极）与第二开关管 T2的 源极（第二极）相连；
所述第五开关管 T5的栅极与控制线相连， 漏极（第一极）与所述驱动 管 DTFT的源极（第二极 )相连， 源极（第二极 )与地相连；
所述存储电容 Cst的第一极板与驱动管 DTFT的栅极相连，第二极板与 补偿管 T3的源极 (第二极 )相连。
本实施例中， 像素电路的工作过程与图 1 所示的实施例中像素电路的 工作过程类似， 只是扫描信号 Vscan控制第一开关管 T1开启或关闭时， 与 图 1所示的实施例中的像素电路有所不同。
具体的， 在补偿阶段， 扫描信号 Vscan为低电平， 从而使第一开关管
T1开启。 本实施例提供的像素电路在补偿阶段的工作过程与图 1-4所示的 实施例类似， 此处不再赘述。
具体的， 在跳变发光阶段， 扫描信号 Vscan为高电平， 从而使第一开 关管关闭。本实施例提供的像素电路在跳变发光阶段的工作过程与图 1-4所 示的实施例类似， 此处不再赘述。
上述实施例对本发明提供的像素电路的各薄膜晶体管均为 N 型的情 况， 驱动管 DTFT和补偿管 T3为 P型， 其它各薄膜晶体管为 N型的情况， 第二开关管 T2和第五开关管 T5为 P型，其它各薄膜晶体管为 N型的情况， 以及第一开关管 T1为 P型，其它各薄膜晶体管为 N型的情况分别做了详细 的说明。 但本发明不限于此， 在本发明的其它实施例中， 上述各开关管、 驱动管 DTFT以及补偿管 T3也可以都是 P型薄膜晶体管，或者其它形式的 部分薄膜晶体管为 P型薄膜晶体管和部分薄膜晶体管为 N型薄膜晶体管的 组合， 只要保证补偿管 T3与驱动管 DTFT为同一类型的薄膜晶体管， 即同 为 N型或同为 P型， 同时第二开关管 T2与第五开关管 T5为同一类型的薄 膜晶体管即可。
如果将图 1所示的电路中的某个或某些 N型薄膜晶体管替换为 P型薄 膜晶体管， 则各 P型薄膜晶体管在电路中的连接方法与原来的 N型薄膜晶 体管的连接方法相似， 只需根据半导体物理知识中 P型管和 N型管的各栅 极、 漏极和源极电位的对应关系而适当调整连接关系即可。 例如， 在图 1 所示的实施例中， 各薄膜晶体管均为 N型薄膜晶体管， 且各薄膜晶体管的 第一极均为漏极， 第二极均为源极， 在本发明的其它实施例中， 如果某薄 膜晶体管由 N型替换为 P型， 则其连接关系仍然可以用图 1所示的实施例 中的薄膜晶体管的第一极和第二极的连接关系描述， 但具体的， 第一极和 第二极所代表的是该薄膜晶体管的源极还是漏极， 对于不同类型的薄膜晶 体管可能会有所不同。
在图 1所示的实施例中，若除补偿管 T3以外的薄膜晶体管由 N型薄膜 晶体管替换为 P型薄膜晶体管， 则其第一极对应着该 P型薄膜晶体管的源 极， 第二极对应着该 P型薄膜晶体管的漏极； 对于补偿管 T3 , 由于其栅极 总是和漏极相连， 因此， 当 T3为 N型薄膜晶体管时， T3的栅极与漏极（第 一极）相连， 当 T3为 P型薄膜晶体管时， T3的栅极与漏极（第二极）相 连， 此时补偿管 T3相当于一个二极管， 其漏极与栅极相连后相当于此二极 管的一极， 源极相当于此二极管的另一极。 在电路连接时， 只需根据二极 管的正偏或反偏要求将相应的极与电路中的较高电位或较低电位相连即 可。
需要说明的是， 本发明实施例提供的电路结构与图 1 所示的实施例类 似， 不同之处在于每个薄膜晶体管是 N型还是 P型可能会有所不同， 相应 的， 其在电路中的连接也会稍作调整， 但无论怎样变化， 只要能够保证上 述实施例中补偿阶段和跳变发光阶段的电路功能能够正常实现即可。
进一步的， 如图 8 所示， 在本发明的另一个实施例中， 像素电路还可 包括第四开关管 T4。 需要说明的是， 除了第四开关管 Τ4夕卜， 本实施例中 的像素电路与图 1所示实施例中的像素电路相同。
具体的， 第四开关管 Τ4的栅极与扫描线相连， 漏极（第一极）与第二 开关管 Τ2的漏极 (第一极）相连， 源极 (第二极）与驱动管 DTFT的漏极 (第一极）相连， 第四开关管 Τ4与第一开关管 T1类型相同， 即同为 Ν型 薄膜晶体管或同为 Ρ型薄膜晶体管。 有关发光器件 OLED, 驱动管 DTFT, 存储电容 Cst, 第一开关管 T1 , 第二开关管 T2, 补偿管 T3和第五开关管 T5的连接， 请参考图 1所示的实施例的详细说明， 此处不再赘述。 下面结合图 2、 图 8-10,对本实施例中的像素电路的工作工程做详细说 明
在图 2所示的信号时序下， 图 8所示的像素电路的工作过程同样分为 两个阶段。
第一阶段： 补偿阶段。
在补偿阶段中， 扫描信号 Vscan为高电平， 控制信号 EM为低电平， 图 8所示的像素电路可等效为如图 9所示的电路结构。 结合图 8和图 9, 第 一开关管 T1和第四开关管 T4为 N型薄膜晶体管， 输入至第一开关管 T1 和第四开关管 T4 的栅极的扫描信号 Vscan为高电平， 从而使第一开关管 T1和第四开关管 T4开启。 第二开关管 T2和第五开关管 T5也为 N型薄膜 晶体管， 输入至它们栅极的控制信号 EM为低电平， 从而使第二开关管 T2 和第五开关管 T5关闭。
具体的， 第四开关管 T4的开启后， 发光器件 OLED即被开启的第四开 关管 T4所短路， 因此， 与图 1所示实施例不同， 本实施例中， 此阶段没有 电流流过发光器件 OLED,发光器件 OLED不发光。第一开关管 T1开启后， 数据信号 Vdata即可通过第一开关管 T1输入至驱动管 DTFT的栅极， 并向 持。 ^ 、 、
充电完毕后， A点电压 VA即为数据信号 Vdata,
即 VA= Vdata ( 9 )
B点电压 VB为电源电压 VDD减去补偿管的阔值电压 Vth3 , 即
VB=VDD- Vth3 ( 10 )
则存储电容 Cst的两极板之间的电压为
VAB=VA-VB=Vdata- ( VDD- Vth3 )
= Vdata- VDD+Vth3 ( 11 )
此时，第二开关管 T2根据输入的低电平控制信号 EM,使存储电容 Cst 与电源 VDD相断开，保证了补偿管 T3的正向导通。第五开关管 T5根据输 入的低电平控制信号 EM, 使驱动管 DTFT与地 GND相断开， 从而避免了 输入至驱动管 DTFT的栅极的数据信号 Vdata通过第五开关管 T5与地 GND 的连接而损失。
第二阶段： 跳变发光阶段。 在跳变发光阶段， 扫描信号 Vscan为低电平， 控制信号 EM为高电平。 此时， 图 8所示的像素电路可等效为如图 10所示的电路结构。
结合图 8和图 10,第一开关管 T1根据输入的扫描信号 Vscan为低电平 而关闭， 以使驱动管 DTFT 的栅极与第一开关管 T1 的源极， 即数据信号 Vdata的输入端隔离。 这样， 驱动管 DTFT对发光器件 OLED的驱动就不会 受第一开关管 T1的源极的信号变化的影响。 同时， 第四开关管 T4根据输 入的扫描信号 Vscan为低电平而关闭， 这样驱动管 DTFT不再被短路， 从 而能够驱动发光器件 OLED发光。
同时， 第二开关管 T2根据控制信号 EM为高电平而开启， 存储电容 Cst的上极板直接与电源 VDD相连， B点电压 VB由 Vdata瞬间跳变到 VDD。 由物理知识可知， 电容两极板之间的电压不会瞬间改变， 因此， 当 B点电 压 VB刚刚跳变至 VDD时， 式（ 11 )仍然成立。 那么， 此时 A点电压 VA 等于 B点电压 VB加上 A点和 B点之间的电压 VAB, 即
VA=VB+VAB=VDD+ ( Vdata- VDD+Vth3 )
= Vdata+Vth3 ( 12 )
第五开关管 T5才艮据控制信号 ΕΜ为高电平而开启， 则驱动管 DTFT的 源极直接与地 GND相连。 此时， 驱动管 DTFT开始驱动 OLED发光。 驱动 管 DTFT的栅源电压为
Vgs=VA- 0= Vdata+ Vth3 ( 13 )
才艮据式（ 5 )和式（ 13 ) , 本实施例中， 流经驱动管 DTFT的电流为
I=K(Vdata+ Vth3 -Vth)2 ( 14 )
与前述实施例原理类似， 当补偿管 T3和驱动管 DTFT位置艮接近时， 补偿管 T3的阔值电压 Vth3和驱动管 DTFT的阔值电压 Vth近似相同， 即 Vth3-Vth=0。 则式（14 )可表示为：
I=K · Vdata2 ( 15 )
其中， K 的含义与前述实施例相同， 此处可认为是一常量。 这样， 流 经驱动管 DTFT的电流就只与数据信号 Vdata相关，而与驱动管 DTFT的阔 值电压 Vth无关， 因此能够避免因背板制造工艺原因及长时间工作导致的 驱动管 DTFT的阔值电压偏移所造成的流过发光器件 OLED的电流差异， 从而有效提高了发光器件发光亮度的均匀性。
而且，本实施例中，第四开关管 T4在补偿阶段将发光器件 OLED短路， 即在补偿阶段没有电流流过发光器件 OLED, 发光器件 OLED不发光， 从 而避免了发光器件 OLED在补偿阶段出现闪烁。
需要说明的是， 本发明虽然以 OLED为例进行说明， 但本发明实施例 提供的发光器件还可以是其它的能够釆用本发明实施例中像素电路驱动的 发光器件， 本发明对此不做限制。
还需要说明的是， 本实施例中， 仅以图 1 所示的实施例， 即各薄膜晶 体管均为 N型薄膜晶体管的实施例为基础，在其上增加了第四开关管 T4进 行说明， 但本发明不限于此。 在本发明的其它实施例中， 各薄膜晶体管可 以全部或部分替换为 P型薄膜晶体管， 而只需满足下列条件： 补偿管 T3与 驱动管 DTFT为同一类型的薄膜晶体管， 第四开关管 T4与第一开关管 T1 为类型的薄膜晶体管， 第二开关管 T2与第五开关管 T5为同一类型的薄膜 晶体管即可。 此处， 同一类型的薄膜晶体管是指同为 N型薄膜晶体管或同 为 P型薄膜晶体管。
与前述像素电路相对应， 如图 11所示， 本发明实施例还提供了一种像 素电路的驱动方法， 包括：
S11 , 将第一开关管 T1开启， 同时将第二开关管 T2和第五开关管 T5 关闭， 以使数据线中的数据信号 Vdata通过第一开关管 T1对存储电容 Cst 的第一极板充电、 使电源 VDD通过发光器件 OLED和补偿管 T3对存储电 容 Cst的第二极板充电；
S12, 将第一开关管 T1关闭， 同时将第二开关管 T2和第五开关管 T5 开启， 以使发光器件 OLED被电源 VDD提供的依次流经发光器件 OLED、 驱动管 DTFT和第五开关管 T5的电流驱动发光。
本发明实施例提供的像素电路的驱动方法， 通过补偿管 T3、 存储电容 和多个开关管对于电路的开关和充放电控制， 将对像素电路的驱动分为两 个阶段， 从而使驱动管 DTFT的驱动电流与驱动管 DTFT的阔值电压 Vth 无关， 补偿了由于驱动管 DTFT的阔值电压 Vth的不一致或偏移所造成的 流过发光器件 OLED的电流差异， 因此能够有效提高发光器件发光亮度的 均匀性。
同时， 由于发光器件如 OLED的开启电压 Voth也可以在跳变发光阶段 被附加到驱动管 DTFT的栅极和第二极之间，从而能够补偿发光器件 OLED 的阔值电压的升高所导致的流过发光器件 OLED的电流的差异。 需要说明的是， 本实施例中， 发光器件为 OLED, 但本发明不限于此， 还可以为其它能够使用本发明实施例提供的像素电路驱动的发光器件， 本 发明对此不做限制。
可选的， 在本发明的一个实施例中， 第一开关管 Tl、 第二开关管 Τ2 和第五开关管 Τ5均为 Ν型薄膜晶体管， 它们的第一极为漏极， 第二极为源 极。对于步骤 S11 , 本发明实施例提供的像素电路的驱动方法可以通过扫描 线输入高电平至第一开关管 T1的栅极将第一开关管 T1开启， 同时通过控 制线输入低电平至第二开关管 Τ2的栅极和第五开关管 Τ5的栅极将第二开 关管 Τ2和第五开关管 Τ5关闭;相应的， 对于步骤 S12, 也可以通过扫描线 输入低电平至第一开关管 T1的栅极将第一开关管 T1关闭， 同时通过控制 线输入高电平至第二开关管 Τ2的栅极和第五开关管 Τ5的栅极将第二开关 管 Τ2和第五开关管 Τ5开启。
可选的，在本发明的另一个实施例中， 第一开关管 T1为 Ν型薄膜晶体 管， 其第一极为漏极， 第二极为源极； 第二开关管 Τ2和第五开关管 Τ5均 为 Ρ型薄膜晶体管， 第二开关管 Τ2和第五开关管 Τ5的第一极为源极， 第 二极为漏极。对于步骤 S11 , 本发明实施例提供的像素电路的驱动方法可以 通过扫描线输入高电平至第一开关管 T1的栅极将第一开关管 T1开启， 同 时通过控制线输入高电平至第二开关管 Τ2的栅极和第五开关管 Τ5的栅极 将第二开关管 Τ2和第五开关管 Τ5关闭;相应的， 对于步骤 S12, 也可以通 过扫描线输入低电平至第一开关管 T1的栅极将第一开关管 T1关闭， 同时 通过控制线输入低电平至第二开关管 Τ2的栅极和第五开关管 Τ5的栅极将 第二开关管 Τ2和第五开关管 Τ5开启。
可选的， 在本发明的另一个实施例中， 第一开关管 T1为 Ρ型薄膜晶体 管， 第一开关管 T1的第一极为源极， 第二极为漏极； 第二开关管 Τ2和第 五开关管 Τ5均为 Ν型薄膜晶体管， 它们的第一极为漏极， 第二极为源极。
对于步骤 S11 ,本发明实施例提供的像素电路的驱动方法可以通过扫描 线输入低电平至第一开关管 T1的栅极将第一开关管 T1开启， 同时通过控 制线输入低电平至第二开关管 Τ2的栅极和第五开关管 Τ5的栅极将第二开 关管 Τ2和第五开关管 Τ5关闭;相应的， 对于步骤 S12, 可以通过扫描线输 入高电平至第一开关管 T1的栅极将第一开关管 T1关闭， 同时通过控制线 输入高电平至第二开关管 Τ2的栅极和第五开关管 Τ5的栅极将第二开关管 T2和第五开关管 T5开启。
可选的， 在本发明的另一个实施例中， 第一开关管 Tl、 第二开关管 Τ2 和第五开关管 Τ5均为 Ρ型薄膜晶体管。 对于步骤 S11 , 本发明实施例提供 的像素电路的驱动方法可以通过扫描线输入低电平至第一开关管 T1的栅极 将第一开关管 T1开启， 同时通过控制线输入高电平至第二开关管 Τ2的栅 极和第五开关管 Τ5的栅极将第二开关管 Τ2和第五开关管 Τ5关闭;相应的， 对于步骤 S12, 可以通过扫描线输入高电平至第一开关管 T1的栅极将第一 开关管 T1关闭， 同时通过控制线输入低电平至第二开关管 Τ2的栅极和第 五开关管 Τ5的栅极将第二开关管 Τ2和第五开关管 Τ5开启。
进一步的， 在本发明的另一个实施例中， 在步骤 S11 中， 所述将第一 开关管 T1开启还可以为将第一开关管 T1与第四开关管 Τ4同时开启；
具体的， 将第一开关管 T1与第四开关管 Τ4同时开启， 同时将第二开 关管 Τ2和第五开关管 Τ5关闭， 可以使数据线， 即数据信号 Vdata所在的 信号线，通过第一开关管 T1对存储电容 Cst的第一极板充电，使电源 VDD 通过第四开关管 T4和补偿管 T3对存储电容 Cst的第二极板充电。
相应的， 在步骤 S12 中， 将第一开关管 T1 关闭可以为将第一开关管 T1与第四开关管 T4同时关闭。具体的，将第一开关管 T1与第四开关管 T4 同时关闭， 同时将第二开关管 T2和第五开关管 T5开启， 可以使发光器件 OLED被电源 VDD提供的、 依次流经发光器件 OLED、 驱动管 DTFT和第 五开关管 T5的电流驱动发光；
其中， 第四开关管 T4的栅极与扫描线相连， 第一极与第二开关管 T2 的第一极相连， 第二极与驱动管 DTFT的第一极相连， 第四开关管 T4与第 一开关管 T1类型相同。
由于第四开关管 T4与第一开关管 T1均由扫描信号 Vscan控制， 因此， 第四开关管 T4与第一开关管 T1一起开启或关闭， 本实施例中， 有关第四 开关管 T4与第一开关管 T1的开启或关闭的原理及详细过程， 请参考前述 实施例的说明， 此处不再赘述。
由于在补偿阶段使第四开关管 T4开启，发光器件 OLED就能够被第四 开关管 T4所短路， 即在补偿阶段没有电流流过发光器件 OLED, 发光器件 OLED不发光， 避免了发光器件 OLED在补偿阶段出现闪烁。
相应的， 本发明还提供一种显示装置， 包括前述实施例提供的任一种 像素电路， 因此具有本发明实施例提供的像素电路所带来的有益技术效果， 前文已经进行了详细说明， 此处不再赘述。
本领域普通技术人员可以理解： 实现上述方法实施例的全部或部分流 程可以通过计算机程序指令相关的硬件来完成， 前述的程序可以存储于一 计算机可读取存储介质中， 该程序在执行时， 执行包括上述方法实施例的 步骤； 而前述的存储介质包括： ROM、 RAM, 磁碟或者光盘等各种可以存 储程序代码的介质。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局 限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可 轻易想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明 的保护范围应以所述权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种像素电路， 其特征在于， 包括：
发光器件、 驱动管、 存储电容、 第一开关管、 第二开关管、 补偿管和 第五开关管；
所述驱动管、 第一开关管、 第二开关管、 补偿管、 第五开关管均包括 栅极、 第一极和第二极；
所述发光器件的一端与电源相连；
所述驱动管的第一极与所述发光器件的另一端相连， 第二极与所述第 五开关管的第一极相连， 栅极与所述第一开关管的第一极相连；
所述第一开关管的第二极与数据线相连， 栅极与扫描线相连， 第一极 与所述驱动管的栅极相连；
所述第二开关管的栅极与控制线相连， 第一极与电源相连， 第二极与 所述补偿管的第二极相连；
所述补偿管的第一极与所述驱动管的第一极相连， 第二极与所述第二 开关管的第二极相连， 栅极与所述 卜偿管的第一极或第二极相连；
所述第五开关管的栅极与控制线相连， 第一极与所述驱动管的第二极 相连， 第二极与地相连；
所述存储电容的第一极板与所述驱动管的栅极相连， 第二极板与所述 补偿管的第二极相连。
2、根据权利要求 1所述的像素电路，其特征在于，还包括第四开关管， 所述第四开关管的栅极与扫描线相连， 第一极与所述第二开关管的第一极 相连， 第二极与所述驱动管的第一极相连， 所述第四开关管与所述第一开 关管类型相同。
3、 根据权利要求 1或 2所述的像素电路， 其特征在于，
所述驱动管、 补偿管均为 N型薄膜晶体管， 所述驱动管和补偿管的第 一极为漏极， 第二极为源极； 所述补偿管的栅极与所述补偿管的第一极相 连；
或者
所述驱动管、 补偿管均为 P型薄膜晶体管， 所述驱动管和补偿管的第 一极为源极， 第二极为漏极； 所述补偿管的栅极与所述补偿管的第二极相 连。
4、 根据权利要求 1-3任一项所述的像素电路， 其特征在于，
所述第二开关管、 第五开关管均为 N型薄膜晶体管， 所述第二开关管 和第五开关管的第一极为漏极， 第二极为源极；
或者
所述第二开关管、 第五开关管均为 P型薄膜晶体管， 所述第二开关管 和第五开关管的第一极为源极， 第二极为漏极。
5、 根据权利要求 1-4任一项所述的像素电路， 其特征在于，
所述第一开关管为 N型薄膜晶体管，所述第一开关管的第一极为漏极， 第二极为源极；
或者
所述第一开关管为 P型薄膜晶体管，所述第一开关管的第一极为源极， 第二极为漏极。
6、 根据权利要求 1或 2所述的像素电路， 其特征在于， 所述发光器件 为有机发光二极管。
7、 一种用于如权利要求 1所述的像素电路的驱动方法， 其特征在于， 包括：
将所述第一开关管开启， 同时将所述第二开关管和所述第五开关管关 闭， 以使数据线中的数据信号通过所述第一开关管对所述存储电容的第一 极板充电， 使所述电源通过所述发光器件和所述补偿管对所述存储电容的 第二极板充电；
将所述第一开关管关闭， 同时将所述第二开关管和所述第五开关管开 启， 以使所述发光器件被所述电源提供的、 依次流经所述发光器件、 所述 驱动管和所述第五开关管的电流驱动发光。
8、 根据权利要求 7所述的方法， 其特征在于，
将所述第一开关管开启， 同时将所述第二开关管和所述第五开关管关 闭， 以使数据线中的数据信号通过所述第一开关管对所述存储电容的第一 极板充电， 使所述电源通过所述发光器件和所述补偿管对所述存储电容的 第二极板充电包括：
将所述第一开关管与第四开关管同时开启， 同时将所述第二开关管和 所述第五开关管关闭， 以使数据线通过所述第一开关管对所述存储电容的 第一极板充电， 使所述电源通过所述第四开关管和所述补偿管对所述存储 电容的第二极板充电；
将所述第一开关管关闭， 同时将所述第二开关管和所述第五开关管开 启， 以使所述发光器件被所述电源提供的、 依次流经所述发光器件、 所述 驱动管和所述第五开关管的电流驱动发光包括：
将所述第一开关管与第四开关管同时关闭， 同时将所述第二开关管和 所述第五开关管开启， 以使所述发光器件被所述电源提供的、 依次流经所 述发光器件、 所述驱动管和所述第五开关管的电流驱动发光；
其中， 所述第四开关管的栅极与扫描线相连， 第一极与所述第二开关 管的第一极相连， 第二极与所述驱动管的第一极相连， 所述第四开关管与 所述第一开关管类型相同。
9、 根据权利要求 7所述的方法， 其特征在于，
所述第一开关管为 N型薄膜晶体管，所述第一开关管的第一极为漏极， 第二极为源极；
所述第二开关管、 第五开关管均为 N型薄膜晶体管， 所述第二开关管 和第五开关管的第一极为漏极， 第二极为源极；
将所述第一开关管开启， 同时将所述第二开关管和所述第五开关管关 闭， 包括：
通过扫描线输入高电平至所述第一开关管的栅极将所述第一开关管开 启， 同时通过控制线输入低电平至所述第二开关管的栅极和所述第五开关 管的栅极将所述第二开关管和所述第五开关管关闭；
将所述第一开关管关闭， 同时将所述第二开关管和所述第五开关管开 启， 包括：
通过扫描线输入低电平至所述第一开关管的栅极将所述第一开关管关 闭， 同时通过控制线输入高电平至所述第二开关管的栅极和所述第五开关 管的栅极将所述第二开关管和所述第五开关管开启。
10、 根据权利要求 7所述的方法， 其特征在于，
所述第一开关管为 N型薄膜晶体管，所述第一开关管的第一极为漏极， 第二极为源极；
所述第二开关管、 第五开关管均为 P型薄膜晶体管， 所述第二开关管 和第五开关管的第一极为源极， 第二极为漏极； 将所述第一开关管开启， 同时将所述第二开关管和所述第五开关管关 闭， 包括：
通过扫描线输入高电平至所述第一开关管的栅极将所述第一开关管开 启， 同时通过控制线输入高电平至所述第二开关管的栅极和所述第五开关 管的栅极将所述第二开关管和所述第五开关管关闭；
将所述第一开关管关闭， 同时将所述第二开关管和所述第五开关管开 启， 包括：
通过扫描线输入低电平至所述第一开关管的栅极将所述第一开关管关 闭， 同时通过控制线输入低电平至所述第二开关管的栅极和所述第五开关 管的栅极将所述第二开关管和所述第五开关管开启。
11、 根据权利要求 7所述的方法， 其特征在于，
所述第一开关管为 P型薄膜晶体管，所述第一开关管的第一极为源极, 第二极为漏极；
所述第二开关管、 第五开关管均为 N型薄膜晶体管， 所述第二开关管 和第五开关管的第一极为漏极， 第二极为源极；
将所述第一开关管开启， 同时将所述第二开关管和所述第五开关管关 闭， 包括：
通过扫描线输入低电平至所述第一开关管的栅极将所述第一开关管开 启， 同时通过控制线输入低电平至所述第二开关管的栅极和所述第五开关 管的栅极将所述第二开关管和所述第五开关管关闭；
将所述第一开关管关闭， 同时将所述第二开关管和所述第五开关管开 启， 包括：
通过扫描线输入高电平至所述第一开关管的栅极将所述第一开关管关 闭， 同时通过控制线输入高电平至所述第二开关管的栅极和所述第五开关 管的栅极将所述第二开关管和所述第五开关管开启。
12、 根据权利要求 7所述的方法， 其特征在于，
所述第一开关管为 P型薄膜晶体管，所述第一开关管的第一极为源极, 第二极为漏极；
所述第二开关管、 第五开关管均为 P型薄膜晶体管， 所述第二开关管 和第五开关管的第一极为源极， 第二极为漏极；
将所述第一开关管开启， 同时将所述第二开关管和所述第五开关管关 闭， 包括：
通过扫描线输入低电平至所述第一开关管的栅极将所述第一开关管开 启， 同时通过控制线输入高电平至所述第二开关管的栅极和所述第五开关 管的栅极将所述第二开关管和所述第五开关管关闭；
将所述第一开关管关闭， 同时将所述第二开关管和所述第五开关管开 启， 包括：
通过扫描线输入高电平至所述第一开关管的栅极将所述第一开关管关 闭， 同时通过控制线输入低电平至所述第二开关管的栅极和所述第五开关 管的栅极将所述第二开关管和所述第五开关管开启。
13、 一种显示装置， 其特征在于， 包括权利要求 1至 6中任一项所述 的像素电路。
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US20140070725A1 (en) 2014-03-13
KR20130108631A (ko) 2013-10-04
JP2015510141A (ja) 2015-04-02
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