WO2013170605A1 - 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置 - Google Patents

薄膜晶体管阵列基板及其制造方法、显示面板、显示装置 Download PDF

Info

Publication number
WO2013170605A1
WO2013170605A1 PCT/CN2012/086772 CN2012086772W WO2013170605A1 WO 2013170605 A1 WO2013170605 A1 WO 2013170605A1 CN 2012086772 W CN2012086772 W CN 2012086772W WO 2013170605 A1 WO2013170605 A1 WO 2013170605A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal oxide
source
electrode
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/086772
Other languages
English (en)
French (fr)
Inventor
刘翔
李禹奉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to KR1020137008588A priority Critical patent/KR101447843B1/ko
Priority to EP12829202.6A priority patent/EP2677537A4/en
Priority to JP2015511901A priority patent/JP2015521383A/ja
Priority to US13/822,480 priority patent/US8912538B2/en
Publication of WO2013170605A1 publication Critical patent/WO2013170605A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present invention relate to a thin film transistor array substrate, a method of fabricating the same, a display panel, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT-LCD has achieved rapid development, and its size and resolution have been continuously improved.
  • Large-size, high-resolution LCD TVs have become a mainstream in the development of TFT-LCDs.
  • the mobility of existing amorphous silicon thin film transistors is difficult to meet the needs of liquid crystal displays. .
  • the mobility of amorphous silicon thin transistors is generally around 0.5cm 2 /VS, but the mobility of above 1cm 2 /VS is required when the liquid crystal display size exceeds 80 inches and the driving frequency is 120Hz.
  • the existing amorphous silicon silicon thin film transistor The mobility is obviously difficult to meet.
  • the metal oxide TFT (amorphous IGZO) has high mobility, good uniformity, transparency and simple fabrication process, and can better meet the needs of large-size liquid crystal displays and active organic electroluminescence, and has attracted much attention.
  • the technical problem to be solved by the embodiments of the present invention is to provide a thin film transistor array substrate, a manufacturing method thereof, a display panel, and a display device, which can simplify the manufacturing process of the metal oxide TFT array substrate and reduce the production cost of the product.
  • An aspect of an embodiment of the present invention provides a method of fabricating a thin film transistor array substrate, the method comprising: sequentially depositing a first metal oxide layer, a second metal oxide layer, and a source/drain metal layer, the first metal oxide The conductivity of the layer is less than the conductivity of the second metal oxide layer; patterning the first metal oxide layer, the second metal oxide layer, and the source/drain metal layer to form an active layer, respectively , buffer layer and source and drain electrodes.
  • the patterning the first metal oxide layer, the second metal oxide layer, and the source/drain metal layer comprises: coating a photoresist on the source/drain metal layer; forming a complete removal region Corresponding to the source electrode, the completely reserved region of the drain electrode, and the partial retention region of the corresponding channel region; etching away the source/drain metal layer, the first metal oxide layer and the second metal oxide layer of the completely removed region; a ashing process to remove the photoresist of the portion of the remaining region; etching away a source/drain metal layer of a portion of the remaining region; etching away a second metal oxide layer of the portion of the remaining region; removing the fully-retained region a photoresist, thereby forming a buffer layer including a source electrode buffer layer and a drain electrode buffer layer, and a source/drain metal layer formed on the source electrode buffer layer and the drain electrode buffer layer, respectively Source and drain electrodes.
  • the method further includes:
  • the manufacturing method includes: forming a pattern of a gate electrode and a gate scan line on the substrate and forming the pattern before depositing the first metal oxide layer, the second metal oxide layer, and the source/drain metal layer Forming a gate insulating layer on the substrate of the gate electrode and the gate scan line; after patterning the first metal oxide layer, the second metal oxide layer, and the source/drain metal layer, forming Forming a pattern including a passivation layer having a contact hole on a substrate having a pattern of the source electrode, the drain electrode, and the data line, and forming a pixel electrode on the passivation layer, the pixel electrode passing through the contact hole
  • the drain electrodes are connected.
  • An embodiment of the present invention further provides a thin film transistor array substrate, the array substrate comprising: an active layer formed of a first metal oxide layer; a buffer layer formed of a second metal oxide layer, and a conductive layer of the buffer layer The rate is greater than the conductivity of the active layer, the buffer layer includes a source electrode buffer layer and a drain electrode buffer layer; a source electrode and a drain electrode formed of a source/drain metal layer; wherein the source electrode buffer layer is located therein Between the source layer and the source electrode, the drain electrode buffer layer is located between the active layer and the drain electrode.
  • the buffer layer includes at least two metal oxide layers from a direction close to the active layer to a distance away from the active layer, that is, as the distance from the active layer increases, the metal Oxidation The conductivity of the layer increases in turn.
  • the thin film transistor array substrate further includes: a substrate; a gate electrode and a gate scan line formed on the substrate by a gate metal layer; and a gate on the substrate on which the gate electrode and the gate scan line are formed An insulating layer; an active layer on the gate insulating layer; a source electrode buffer layer and a drain electrode buffer layer on the active layer; respectively located at the source electrode buffer layer and the drain electrode buffer layer
  • the source electrode, the drain electrode, and the data line a passivation layer including a contact hole on a substrate on which the source electrode, the drain electrode, and the data line are formed; a pixel located on the passivation layer An electrode, wherein the pixel electrode is connected to the drain electrode through the contact hole.
  • the material of the buffer layer is amorphous IGZO.
  • the material of the active layer is amorphous IGZO, HIZO, IZO, a-InZnO, ZnO:F,
  • In 2 0 3 Sn, In 2 0 3 : Mo, Cd 2 Sn0 4 , ZnO: Al, Ti0 2 : Nb or Cd-Sn-0.
  • Embodiments of the present invention also provide a display panel including the thin film transistor array substrate as described above.
  • Embodiments of the present invention also provide a display device including the thin film transistor array substrate as described above.
  • the second metal oxide layer having high conductivity can protect the active layer while etching the source and the metal layer, and finally can form a buffer for reducing the contact resistance between the source electrode and the drain electrode and the active layer.
  • the layer, so that the active layer and the source electrode and the drain electrode formed by the source/drain metal layer are formed by one patterning process, can save the patterning process, improve the production efficiency, and reduce the production cost of the product.
  • FIG. 1 is a schematic plan view of a thin film transistor array substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view corresponding to the position of A-B in FIG. 1 after the first patterning process of the method for fabricating the thin film transistor array substrate according to the embodiment of the present invention
  • FIG. 3 is a second patterning work of a method of fabricating a thin film transistor array substrate according to an embodiment of the present invention. After exposure and development in the art, it corresponds to a schematic cross-sectional view at the position A-B in FIG. 1;
  • FIG. 4 is a cross-sectional view corresponding to the position A-B in FIG. 1 after the first etching in the second patterning process of the method for fabricating the thin film transistor array substrate according to the embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view corresponding to the position A-B in FIG. 1 after ashing in the second patterning process of the method for fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 6 is a cross-sectional view corresponding to the position of A-B in FIG. 1 after the second patterning process of the method for fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 7 is a schematic cross-sectional view corresponding to the position A-B in FIG. 1 after the first etching in the third patterning process of the thin film transistor array substrate according to the embodiment of the present invention
  • Figure 8 is a cross-sectional view showing the thin film transistor array substrate of the embodiment of the present invention corresponding to the position A - B in Figure 1.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element and A pixel electrode that controls the arrangement of liquid crystals.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • embodiments of the present invention provide a thin film transistor array substrate, a method of fabricating the same, a display panel, and a display device, which can simplify the manufacturing process of the metal oxide TFT array substrate and reduce the production cost of the product.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor array substrate capable of forming an active layer formed of a metal oxide layer and a source electrode and a drain electrode formed of a source/drain metal layer by one patterning process.
  • the step of forming the active layer and the source electrode and the drain electrode in the manufacturing method includes: sequentially depositing a first metal oxide layer, a second metal oxide layer, and a source/drain metal layer, and conductivity of the first metal oxide layer Less than the conductivity of the second metal oxide layer; Coating a photoresist on the source/drain metal layer;
  • the photoresist is exposed and developed by a gray tone or halftone mask to form a complete removal region, a correspondingly reserved region of the source electrode and the drain electrode, and a partial retention region of the corresponding channel region, and then the complete removal region is etched away.
  • a source/drain metal layer, a first metal oxide layer and a second metal oxide layer forming an active layer, performing a photoresist ashing process to remove a portion of the photoresist in the remaining region, and then etching away a portion of the remaining region Leaking the metal layer, etching away the second metal oxide layer of the partial retention region, forming a channel region of the thin film transistor, removing the photoresist in the completely remaining region, forming a buffer layer including the source electrode buffer layer and the drain electrode buffer layer a buffer layer, and source and drain electrodes formed of source and drain metal layers respectively on the source electrode buffer layer and the drain electrode buffer layer.
  • the buffer layer is located between the active layer and the source/drain metal layer, and is also formed of a metal oxide layer, the purpose of which is to reduce the contact resistance between the source electrode and the drain electrode and the active layer, while protecting the underlying active layer , improve the performance of metal oxide TFTs.
  • the buffer layer includes an active electrode buffer layer and a drain electrode buffer layer, the source electrode buffer layer is located between the active layer and the source electrode, and the drain electrode buffer layer is located between the active layer and the drain electrode.
  • the active layer is formed of a low conductivity metal oxide layer
  • the buffer layer is formed of a high conductivity metal oxide layer.
  • the high conductivity metal oxide layer has a high oxygen content, and the metal oxide layer has good conductivity, Rs ⁇ 10 6 ohm. square mm/m, close to the conductor; oxygen content in the low conductivity metal oxide layer Low, the conductivity of the metal oxide layer is not good, 10 6 ohm. square mm / m ⁇ 1 ⁇ ⁇ 10 11 ohm. square mm / m, is a semiconductor.
  • a highly conductive metal oxide layer may be doped with amorphous indium gallium oxide (IGZO).
  • the low conductivity metal oxide layer can be used for yttrium indium oxide (HIZO), IZO, a-InZnO, ZnO:F, In 2 0 3 :Sn, In 2 0 3 :Mo, Cd 2 Sn0 4 , ZnO : Al, Ti0 2 : Nb, Cd-Sn-0 or other metal oxides.
  • HIZO yttrium indium oxide
  • IZO a-InZnO
  • ZnO:F In 2 0 3 :Sn
  • In 2 0 3 :Mo Mo
  • Cd 2 Sn0 4 ZnO : Al
  • Ti0 2 : Nb Cd-Sn-0 or other metal oxides.
  • the buffer layer may be formed of at least two metal oxide layers of high conductivity, the conductivity of the at least two metal oxide layers increasing sequentially from a direction close to the active layer to a direction away from the active layer.
  • the surface of the active layer of the channel region may be repaired to repair damage and contamination of the active layer during etching.
  • the surface of the active layer of the channel region may be treated with N 2 0 or 02 plasma.
  • the plasma process parameters are: pressure 100-2000mT, RF power 500W-4000W, N 2 0 gas flow 500-3000sccm.
  • the manufacturing method of the thin film transistor array substrate of the embodiment of the present invention may include: forming a pattern of a gate electrode and a gate scan line on the substrate;
  • the photoresist is exposed and developed by a gray tone or halftone mask to form a complete removal region, a correspondingly reserved region of the corresponding source electrode, the drain electrode and the data line, and a partial retention region of the corresponding channel region, and then completely etched away.
  • the second metal oxide layer having high conductivity can protect the active layer not only when etching the source and drain metal layers, but also can form the source electrode and a buffer layer of a contact resistance between the drain electrode and the active layer, thereby forming an active layer and a source electrode and a drain electrode formed of the source/drain metal layer by one patterning process, thereby saving a patterning process, improving production efficiency, and lowering the product Production costs.
  • An embodiment of the present invention further provides a thin film transistor array substrate, the array substrate comprising: an active layer formed of a first metal oxide layer;
  • a buffer layer formed of a second metal oxide layer, wherein a conductivity of the buffer layer is greater than a conductivity of the active layer, and the buffer layer includes a source electrode buffer layer and a drain electrode buffer layer;
  • the source electrode buffer layer is located between the active layer and the source electrode
  • the drain electrode buffer layer is located between the active layer and the drain electrode.
  • the buffer layer is located between the active layer and the source/drain metal layer and is formed of a metal oxide. The purpose is to reduce the contact resistance between the source electrode and the drain electrode and the active layer, and at the same time protect the active layer and enhance metal oxidation. The performance of the TFT.
  • the material of the active layer is a metal oxide layer with low conductivity
  • the material of the buffer layer is a metal oxide layer with high conductivity.
  • the high conductivity metal oxide layer has a high oxygen content
  • the metal oxide layer has good conductivity, Rs ⁇ 10 6 ohm. square mm/m, close to the conductor; low conductivity metal oxide layer oxygen
  • the content of the metal oxide layer is low, and the conductivity of the metal oxide layer is not good, and 10 6 ohm ⁇ square mm/m ⁇ 1 ⁇ 10 11 ohm. square mm/m is a semiconductor.
  • the buffer layer may be made of amorphous IGZO
  • the active layer may be made of HIZO, IZO, a-InZnO, ZnO:F, In 2 0 3 :Sn, In 2 0 3 :Mo, Cd 2 Sn0 4 , ZnO. : Al, Ti0 2 : Nb, Cd-Sn-0 or other metal oxides.
  • the buffer layer may be formed of two or more high conductivity metal oxide layers, and the conductivity of the two or more metal oxide layers sequentially increases from a direction close to the active layer to a direction away from the active.
  • the thin film transistor array substrate of the embodiment of the present invention will be further described below in conjunction with specific embodiments.
  • the channel region and the portions of the source electrode, the drain electrode, the data line, and the like are: an active layer formed of a first metal oxide layer;
  • the buffer layer formed on the active layer by the second metal oxide layer, the conductivity of the buffer layer is greater than that of the active layer, and the buffer layer includes a source electrode buffer layer and a drain electrode buffer layer;
  • the structure of the thin film transistor array substrate can be as shown in FIG. 1 and FIG. 8 , and specifically includes: a substrate 1 ;
  • An active layer 4-1 formed of a first metal oxide layer on the gate insulating layer 3;
  • the pixel electrode 8 on the passivation layer 7 is connected to the drain electrode 6 through a contact hole.
  • a substrate 1 is provided, which may be a glass substrate or a quartz substrate on which a gate metal layer is deposited to form a gate electrode and a gate scan line.
  • a gate metal layer having a thickness of 500 to 4000 A may be deposited on the substrate 1 by sputtering or thermal evaporation, and a metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu may be selected for the gate metal layer.
  • the gate metal layer may be a single layer metal or a single layer alloy, or may be a multilayer metal or a multilayer alloy.
  • a photoresist is coated on the gate metal layer, and the photoresist is exposed and developed by the mask to be etched to form the gate electrode 2 and the gate scan line 12, and FIG. 2 shows the first patterning process. A schematic cross-sectional view of the resulting structure.
  • the second patterning process sequentially depositing a gate insulating layer 3, a first metal oxide layer, a second metal oxide layer, and a source/drain metal layer on the substrate 1 on which the gate electrode 2 and the gate scanning line 12 are formed.
  • a gate insulating layer 3 having a thickness of 2000 to 5000 A may be deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) on the substrate 1 on which the gate electrode 2 and the gate scan line 12 are formed.
  • the insulating layer 3 may be oxide, nitride, or oxynitride, corresponding to the reaction gas may be Si3 ⁇ 4, NH 3, N 2 or Si3 ⁇ 4Cl 2, NH 3, N 2 .
  • the gate insulating layer may be a single layer or a plurality of layers, and is generally an oxide gate insulating layer close to the metal oxide layer.
  • a first metal oxide layer and a second metal oxide layer each having a thickness of 50 to 2000 A are successively deposited on the gate insulating layer 3 by sputtering to form an active layer from the first metal oxide layer.
  • the second metal oxide layer forms a buffer layer.
  • the buffer layer is located between the active layer and the source/drain metal layer and is formed of a metal oxide. The purpose is to reduce the contact resistance between the source electrode and the drain electrode and the active layer, and to etch the source and drain the metal layer to form a source.
  • the electrode and the drain electrode protect the underlying active layer and enhance the performance of the metal oxide TFT.
  • the conductivity of the active layer is lower than the conductivity of the buffer layer, and the conductivity is close to the semiconductor, buffering
  • the layer may be formed of at least one metal oxide layer, when the buffer layer is formed of two or more high conductivity metal oxide layers, from a direction close to the active layer to a distance away from the active layer, that is, with The distance between the active layers is increased, and the electrical conductivity of the two or more metal oxide layers is sequentially increased.
  • the active layer may include a plurality of layers, for example, may include a plurality of metal oxide layers, such as the active layer may include three metal oxide layers, followed by a first metal oxide layer, a second metal oxide layer, and a third metal An oxide layer, wherein a conductivity of the first metal oxide layer is less than a conductivity of the second metal oxide layer, and a conductivity of the second metal oxide layer is less than a conductivity of the third metal oxide layer.
  • This embodiment is specifically described by taking a buffer layer including only one metal oxide layer as an example.
  • two metal oxide layers are successively deposited on the gate insulating layer 3.
  • the first deposited metal oxide layer has low conductivity and can be used to form the active layer 4-1 and the deposited metal oxide layer.
  • the conductivity is high and can be used to form the buffer layer 4-2. If more than three metal oxide layers are deposited on the gate insulating layer 3, the lowermost metal oxide layer is used to form the active layer, and the remaining metal oxide layer is used to form the buffer layer.
  • the conductivity of the metal oxide layer can be effectively controlled by controlling the content of oxygen when depositing the metal oxide layer.
  • the conductivity of the metal oxide layer is good, Rs ⁇ 10 6 ohm. square mm/m, close to the conductor; if the content of oxygen in the metal oxide layer is low, the metal oxide
  • the layer has poor conductivity, 10 6 ohms square mm / m ⁇ Rs ⁇ 10 ohms square mm / m, which is a semiconductor.
  • the second metal oxide layer can be made of amorphous IGZO, the first metal oxide
  • the layer may be made of amorphous IGZO, HIZO, IZO, a-InZnO, ZnO:F, In 2 0 3 :Sn, In 2 0 3 :Mo, Cd 2 Sn0 4 , ZnO:Al, Ti0 2 :Nb, Cd- Sn-0 or other metal oxide; then depositing a source/drain metal layer on the second metal oxide layer.
  • a source/drain metal layer having a thickness of 2000 to 4000 A may be deposited by sputtering or thermal evaporation.
  • the metal leakage layer may be selected from metals and alloys such as Cr, W, Ti, Ta, Mo, etc., and may be a single-layer metal film or a single-layer alloy film, or may be a multilayer metal film or a multilayer alloy film.
  • a completely removed region, a partially reserved region, and a completely reserved region are formed.
  • the fully reserved region corresponds to the source and drain metal electrodes and the data line.
  • a portion of the reserved area corresponds to the TFT channel region.
  • a second etching process is performed, first etching away the source and drain metal layers of the remaining regions, and then etching away some of the remaining regions.
  • a second metal oxide layer in order to ensure complete etching of the second metal oxide layer, a portion of the first metal oxide layer may be etched during etching, thereby forming a TFT between the source electrode and the drain electrode Channel.
  • the buffer layer 4-2 is directly in contact with the source/drain metal layer, and the design can reduce the contact resistance of the active layer 4-1 with the source electrode and the drain electrode, and increase the on-state current of the metal oxide TFT.
  • the active layer 4-1 is in direct contact with the gate insulating layer 3, and the low oxygen content metal oxide layer forming the active layer enables the TFT performance to be more stable.
  • the surface of the active layer of the TFT channel region may be treated to repair damage and contamination of the active layer during etching.
  • the surface of the active layer of the channel region may be treated with a N 2 0 or 02 plasma.
  • the process parameters of the plasma are: air pressure 100-2000mT, RF power 500W-4000W, N 2 0 gas flow 500-3000sccm, equipment of different production lines, process parameters are different, but the idea of processing the same.
  • a buffer layer 4-2 including a source electrode buffer layer and a drain electrode buffer layer, a source electrode 5, a drain electrode 6 and a data line 13, which are finally formed by a second patterning process.
  • the structure is shown in Figure 6.
  • the third patterning process depositing a passivation layer 7 on the substrate 1 on which the second patterning process is completed.
  • a passivation layer 7 having a thickness of 2000 to 5000 A may be deposited by a PECVD method, and the passivation layer 7 may be oxidized.
  • nitride or oxynitride passivation layer 7 may be a single layer structure or a multilayer structure, corresponding to the reaction gas may be Si3 ⁇ 4, Korea 3, N 2 or Si3 ⁇ 4Cl 2, Li 3, N 2.
  • a photoresist is coated on the passivation layer, and the photoresist is exposed and developed by using a mask to be etched to form a pattern including the passivation layer 7 having contact vias, as shown in FIG.
  • the fourth patterning process depositing a transparent conductive layer on the substrate 1 on which the third patterning process is completed. Specifically, a thickness of 300 ⁇ may be deposited on the substrate 1 on which the passivation layer 7 is formed by sputtering or thermal evaporation. 1500 A transparent conductive layer, transparent conductive layer can use ITO or IZO, or other transparent metal oxide. Coating a photoresist on the transparent conductive layer, exposing and developing the photoresist by using a mask, and then etching to form the pixel electrode 8, and the pixel electrode 8 passes through the contact via. It is connected to the drain electrode 6.
  • FIG. 8 is a schematic cross-sectional view showing a thin film transistor array substrate formed after the fourth patterning process
  • FIG. 1 is a plan view showing a thin film transistor array substrate formed after four patterning processes.
  • the second metal oxide layer having high conductivity can protect the active layer while etching the source and drain metal layers, and finally form a buffer layer for reducing the contact resistance between the source electrode and the drain electrode and the active layer. Therefore, the active layer, the source electrode and the drain electrode can be formed by one patterning process, which can save the patterning process, improve the production efficiency, and reduce the production cost of the product.
  • the technical solution of the embodiment of the present invention forms two or more metal oxide layers on the gate insulating layer, the bottom layer is an active layer, and the other layers serve as a buffer layer, and partially buffers are formed when the source electrode and the drain electrode are formed. The layer is formed into a channel, and the design can reduce the contact resistance between the source electrode and the drain electrode and the active layer, and at the same time, the active layer is protected by the buffer layer, and the performance of the metal oxide TFT can be improved.
  • Embodiments of the present invention also provide a display panel including the thin film transistor array substrate as described above.
  • the embodiment of the invention further provides a display device comprising the thin film transistor array substrate as described above.
  • the display device can be applied to an electronic device such as a liquid crystal display or a tablet computer.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种薄膜晶体管阵列基板及其制造方法、显示面板、显示装置。其中，薄膜晶体管阵列基板的制造方法包括：依次沉积第一金属氧化物层、第二金属氧化物层和源漏金属层，该第一金属氧化物层的导电率小于该第二金属氧化物层的导电率；图案化该第一金属氧化物层、该第二金属氧化物层和该源漏金属层，以分别形成有源层（4-1）、缓冲层（4-2）以及源电极（5）和漏电极（6）。该方法能够简化金属氧化物TFT阵列基板的制造工艺，降低产品的生产成本。

Description

薄膜晶体管阵列基板及其制造方法、 显示面板、 显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管阵列基板及其制造方法、显示面板、 显示装置。 背景技术
薄膜晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, 简 称 TFT-LCD )具有体积小、 功耗低、 无辐射等特点， 在当前的平板显示器市 场中占据了主导地位。
近年来 TFT-LCD获得了飞速的发展， 其尺寸和分辨率不断地提高， 大 尺寸、 高分辨率的液晶电视成为 TFT-LCD发展的一个主流。 随着 TFT-LCD 尺寸的不断增大、 分辨率的不断提高， 为了提高显示质量， 需要釆用更高频 率的驱动电路， 现有的非晶硅薄膜晶体管的迁移率很难满足液晶显示器的需 要。 非晶硅薄晶体管的迁移率一般在 0.5cm2/V.S左右， 但是在液晶显示器尺 寸超过 80英寸并且驱动频率为 120Hz时需要 lcm2/V.S以上的迁移率， 现有 的非晶硅硅薄膜晶体管的迁移率显然很难满足。金属氧化物 TFT(非晶 IGZO ) 迁移率高， 均一性好， 透明且制作工艺简单， 可以更好地满足大尺寸液晶显 示器和有源有机电致发光的需求， 备受人们的关注。
但是现有技术中在制作金属氧化物 TFT时，一般在金属氧化物上面加一 层保护层， 以避免在形成源漏金属电极时对金属氧化物层的破坏， 这样就增 加了构图工艺的次数， 影响了生产效率。 发明内容
本发明实施例要解决的技术问题是提供一种薄膜晶体管阵列基板及其制 造方法、 显示面板、 显示装置， 能够简化金属氧化物 TFT阵列基板的制造工 艺， 降低产品的生产成本。
为解决上述技术问题， 本发明的实施例提供技术方案如下。 本发明实施例的一方面提供一种薄膜晶体管阵列基板的制造方法， 该方 法包括： 依次沉积第一金属氧化物层、 第二金属氧化物层和源漏金属层， 所 述第一金属氧化物层的导电率小于所述第二金属氧化物层的导电率； 图案化 所述第一金属氧化物层、 所述第二金属氧化物层和所述源漏金属层， 以分别 形成有源层、 緩冲层以及源电极和漏电极。
例如， 所述图案化所述第一金属氧化物层、 所述第二金属氧化物层和所 述源漏金属层包括： 在所述源漏金属层上涂布光刻胶； 形成完全去除区、 对 应源电极、 漏电极的完全保留区和对应沟道区域的部分保留区； 刻蚀掉完全 去除区的源漏金属层、 第一金属氧化物层和第二金属氧化物层； 进行光刻胶 灰化工艺以去除掉所述部分保留区的光刻胶； 刻蚀掉部分保留区的源漏金属 层； 刻蚀掉部分保留区的第二金属氧化物层；去除所述完全保留区的光刻胶， 由此形成包括源电极緩冲层和漏电极緩冲层的緩冲层， 以及分别位于所述源 电极緩冲层和漏电极緩冲层上的由所述源漏金属层形成的源电极和漏电极。
进一步地， 所述形成源电极、 漏电极之后还包括：
对所述沟道区域的有源层的表面进行修复。
进一步地， 所述制造方法包括： 在所述沉积第一金属氧化物层、 第二金 属氧化物层和源漏金属层之前， 在基板上形成栅电极和栅极扫描线的图形以 及在形成有所述栅电极和栅极扫描线的图形的基板上形成栅绝缘层； 在图案 化所述第一金属氧化物层、 所述第二金属氧化物层和所述源漏金属层之后， 在形成有所述源电极、 漏电极和数据线的图形的基板上形成包括有接触孔的 钝化层的图形， 以及在所述钝化层上形成像素电极， 所述像素电极通过所述 接触孔与所述漏电极相连接。
本发明实施例还提供了一种薄膜晶体管阵列基板， 该阵列基板包括： 由 第一金属氧化物层形成的有源层； 由第二金属氧化物层形成的緩冲层， 緩冲 层的导电率比有源层的导电率大,緩冲层包括源电极緩冲层和漏电极緩冲层； 由源漏金属层形成的源电极、 漏电极； 其中， 源电极緩冲层位于所述有源层 和所述源电极之间， 所述漏电极緩冲层位于所述有源层和所述漏电极之间。
进一步地， 所述緩冲层包括至少两个金属氧化物层， 从靠近所述有源层 到远离所述有源层的方向上， 即， 随着与有源层相距的距离增大， 金属氧化 物层的导电率依次增大。
进一步地， 所述薄膜晶体管阵列基板还包括： 基板； 位于所述基板上由 栅金属层形成的栅电极和栅极扫描线； 位于形成有所述栅电极和栅极扫描线 的基板上的栅绝缘层； 位于所述栅绝缘层上的有源层； 位于所述有源层上的 源电极緩冲层和漏电极緩冲层； 分别位于所述源电极緩冲层和漏电极緩冲层 上的所述源电极、 所述漏电极和数据线； 位于形成有所述源电极、 漏电极和 数据线的基板上的包括有接触孔的钝化层； 位于所述钝化层上的像素电极， 所述像素电极通过所述接触孔与所述漏电极相连接。
进一步地， 所述緩冲层的材料为非晶 IGZO。
进一步地，所述有源层的材料为非晶 IGZO、HIZO、IZO、a-InZnO、ZnO:F、
In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb或 Cd-Sn-0。
本发明实施例还提供了一种显示面板， 包括如上所述的薄膜晶体管阵列 基板。
本发明实施例还提供了一种显示装置， 包括如上所述的薄膜晶体管阵列 基板。
本发明的实施例具有以下有益效果：
上述方案中， 通过导电率高的第二金属氧化物层既可在刻蚀源漏金属层 时保护有源层， 又可以最后形成减少源电极和漏电极与有源层的接触电阻的 緩冲层， 从而有源层和由源漏金属层形成的源电极、 漏电极通过一次构图工 艺形成， 能够节省构图工艺， 提升生产效率， 降低产品的生产成本。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例的薄膜晶体管阵列基板的平面示意图；
图 2为本发明实施例的薄膜晶体管阵列基板的制造方法的第一次构图工 艺后对应于图 1中 A— B位置处的截面示意图；
图 3为本发明实施例的薄膜晶体管阵列基板的制造方法的第二次构图工 艺中曝光显影后对应于图 1中 A— B位置处的截面示意图；
图 4为本发明实施例的薄膜晶体管阵列基板的制造方法的第二次构图工 艺中第一次刻蚀后对应于图 1中 A— B位置处的截面示意图；
图 5为本发明实施例的薄膜晶体管阵列基板的制造方法的第二次构图工 艺中灰化后对应于图 1中 A— B位置处的截面示意图；
图 6为本发明实施例的薄膜晶体管阵列基板的制造方法第二次构图工艺 后对应于图 1中 A— B位置处的截面示意图；
图 7为本发明实施例的薄膜晶体管阵列基板的制造方法第三次构图工艺 中第一次刻蚀后对应于图 1中 A— B位置处的截面示意图；
图 8为本发明实施例的薄膜晶体管阵列基板的对应于图 1中 A— B位置 处的截面示意图。
附图标记
1 基板
2栅电极
3 栅绝缘层
4-1 有源层
4-2緩冲层
5 源电极
6 漏电极
7 钝化层
8像素电极
10 光刻胶
12栅极扫描线
13 数据线 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 或者 "一" 等类似词语也不表示数量限制，而是表示存在至少一个。 "包括"或者"包含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵盖出 现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排除其 他元件或者物件。 "连接"或者 "相连"等类似的词语并非限定于物理的或者 机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置 改变后， 则该相对位置关系也可能相应地改变。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为开关 元件的薄膜晶体管和用于控制液晶的排列的像素电极。 例如， 每个像素的薄 膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应的数据线电连 接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下面的描述主要 针对单个或多个像素单元进行， 但是其他像素单元可以相同地形成。
现有技术中在制作金属氧化物 TFT时，一般在金属氧化物上面加一层保 护层， 以避免在形成源漏金属电极时对金属氧化物层的破坏， 这样就增加了 构图工艺的次数， 影响了生产效率。 为了解决上述问题， 本发明的实施例提 供一种薄膜晶体管阵列基板及其制造方法、 显示面板、 显示装置， 能够简化 金属氧化物 TFT阵列基板的制造工艺， 降低产品的生产成本。
本发明实施例提供了一种薄膜晶体管阵列基板的制造方法， 该制造方法 能够通过一次构图工艺形成由金属氧化物层形成的有源层和由源漏金属层形 成的源电极、 漏电极。
其中， 该制造方法中形成有源层和源电极、 漏电极的步骤包括： 依次沉积第一金属氧化物层、 第二金属氧化物层和源漏金属层， 第一金 属氧化物层的导电率小于第二金属氧化物层的导电率； 在源漏金属层上涂布光刻胶；
利用灰色调或半色调掩模板对光刻胶进行曝光和显影，形成完全去除区、 对应源电极、 漏电极的完全保留区和对应沟道区域的部分保留区， 之后刻蚀 掉完全去除区的源漏金属层、 第一金属氧化物层和第二金属氧化物层， 形成 有源层， 进行光刻胶灰化工艺去除掉部分保留区的光刻胶， 之后先刻蚀掉部 分保留区的源漏金属层， 再刻蚀掉部分保留区的第二金属氧化物层， 形成薄 膜晶体管的沟道区域， 去除完全保留区的光刻胶， 形成包括源电极緩冲层和 漏电极緩冲层的緩冲层， 以及分别位于源电极緩冲层和漏电极緩冲层上的由 源漏金属层形成的源电极和漏电极。
其中，緩冲层位于有源层和源漏金属层之间，也是由金属氧化物层形成， 其目的是为了减少源电极和漏电极与有源层的接触电阻， 同时保护下面的有 源层， 提升金属氧化物 TFT的性能。緩冲层包括有源电极緩冲层和漏电极緩 冲层， 源电极緩冲层位于有源层和源电极之间， 漏电极緩冲层位于有源层和 漏电极之间。
有源层由低导电率的金属氧化物层形成， 緩冲层为由高导电率的金属氧 化物层形成。 高导电率的金属氧化物层中氧的含量高， 该金属氧化物层的导 电性好， Rs<106欧姆 .平方毫米 /米， 接近导体； 低导电率的金属氧化物层中 氧的含量低， 该金属氧化物层的导电性不好， 106欧姆 .平方毫米 /米< 1^<1011 欧姆 .平方毫米 /米， 为半导体。 例如， 高导电率的金属氧化物层可以釆用非 晶铟镓辞氧化物（IGZO )。 低导电率的金属氧化物层可以釆用铪铟辞氧化物 ( HIZO )、 IZO、 a-InZnO, ZnO:F、 In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb、 Cd-Sn-0或其他金属氧化物。
例如， 緩冲层可以由至少两个高导电率的金属氧化物层形成， 从靠近有 源层到远离有源层的方向上， 该至少两个金属氧化物层的导电率依次增大。
例如， 在形成源电极、 漏电极之后还可以对沟道区域的有源层的表面进 行修复处理， 以修复刻蚀时对有源层的损伤和污染。 具体地， 可以利用 N20 或 02等离子体对沟道区域的有源层的表面进行处理。一种实施例中，等离子 体的工艺参数范围是： 气压 100-2000mT, 射频功率 500W-4000W, N20气体 流量 500-3000sccm。 例如， 本发明实施例的薄膜晶体管阵列基板的制造方法可以包括： 在基板上形成栅电极和栅极扫描线的图形；
在形成有栅电极和栅极扫描线的图形的基板上形成栅绝缘层；
在栅绝缘层上进行依次沉积第一金属氧化物层、 第二金属氧化物层和源 漏金属层， 第一金属氧化物层的导电率小于第二金属氧化物层的导电率； 在源漏金属层上涂布光刻胶；
利用灰色调或半色调掩模板对光刻胶进行曝光和显影，形成完全去除区、 对应源电极、 漏电极和数据线的完全保留区和对应沟道区域的部分保留区， 之后刻蚀掉完全去除区的源漏金属层、 第一金属氧化物层和第二金属氧化物 层， 形成有源层， 进行光刻胶灰化工艺以去除掉部分保留区的光刻胶， 之后 先刻蚀掉部分保留区的源漏金属层 , 再刻蚀掉部分保留区的第二金属氧化物 层， 形成薄膜晶体管的沟道区域， 去除完全保留区的光刻胶， 形成包括源电 极緩冲层和漏电极緩冲层的緩冲层， 以及分别位于源电极緩冲层和漏电极緩 冲层上的由源漏金属层形成的源电极、 漏电极和数据线；
在形成有源电极、 漏电极和数据线的图形的基板上形成包括有接触过孔 的钝化层的图形；
在钝化层上形成像素电极， 像素电极通过接触过孔与漏电极相连接。 根据本发明实施例的薄膜晶体管阵列基板的制造方法中， 导电率高的第 二金属氧化物层不仅可以在刻蚀源漏金属层时保护有源层， 而且第还可以最 后形成减少源电极和漏电极与有源层的接触电阻的緩冲层， 从而通过一次构 图工艺即可形成有源层和由源漏金属层形成的源电极、 漏电极， 能够节省构 图工艺， 提升生产效率， 降低产品的生产成本。
本发明实施例还提供了一种薄膜晶体管阵列基板， 该阵列基板包括： 由第一金属氧化物层形成的有源层；
由第二金属氧化物层形成的緩冲层， 緩冲层的导电率比有源层的导电率 大， 緩冲层包括源电极緩冲层和漏电极緩冲层；
由源漏金属层形成的源电极、 漏电极；
其中， 源电极緩冲层位于有源层和源电极之间， 漏电极緩冲层位于有源 层和漏电极之间。 其中， 緩冲层位于有源层和源漏金属层之间， 由金属氧化物形成， 其目 的是为了减少源电极和漏电极与有源层的接触电阻， 同时保护有源层， 提升 金属氧化物 TFT的性能。
其中， 有源层的材料为低导电率的金属氧化物层， 緩冲层的材料为高导 电率的金属氧化物层。 其中， 高导电率的金属氧化物层中氧的含量高， 该金 属氧化物层的导电性好， Rs<106欧姆 .平方毫米 /米， 接近导体； 低导电率的 金属氧化物层中氧的含量低， 该金属氧化物层的导电性不好， 106欧姆 ·平方 毫米 /米< 1^<1011欧姆 .平方毫米 /米， 为半导体。 例如， 緩冲层可以釆用非晶 IGZO, 有源层可以釆用 HIZO、 IZO、 a-InZnO, ZnO:F、 In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb、 Cd-Sn-0或其他金属氧化物。
例如， 緩冲层可以由两个以上高导电率的金属氧化物层形成， 从靠近有 源层到远离有源的方向上， 该两个以上金属氧化物层的导电率依次增大。
下面结合具体的实施例对本发明实施例的薄膜晶体管阵列基板进行进一 步地说明。
本实施例中， 沟道区域和源电极、 漏电极、 数据线等部分的结构为： 由第一金属氧化物层形成的有源层；
位于有源层上由第二金属氧化物层形成的緩冲层， 緩冲层的导电率比有 源层的导电率大， 緩冲层包括源电极緩冲层和漏电极緩冲层；
分别位于源电极緩冲层和漏电极緩冲层上的由源漏金属层形成的源电 极、 漏电极。
该薄膜晶体管阵列基板的结构可以如图 1和图 8所示， 具体包括： 基板 1 ;
位于基板 1上由栅金属层形成的栅电极 2和栅极扫描线 12;
位于形成有栅电极 2和栅极扫描线 12的基板 1上的栅绝缘层 3;
位于栅绝缘层 3上的由第一金属氧化物层形成的有源层 4-1 ;
位于有源层 4-1上由第二金属氧化物层形成的源电极緩冲层和漏电极緩 冲层 4-2;
分别位于源电极緩冲层和漏电极緩冲层上的由源漏金属层形成的源电极 5、 漏电极 6和数据线 13; 位于形成有源电极 5、漏电极 6和数据线 13的基板 1上的包括接触孔的 钝化层 7;
位于钝化层 7上的像素电极 8, 像素电极 8通过接触孔与漏电极 6相连 接。
下面对本实施例的薄膜晶体管阵列基板的制造工艺进行详细说明， 其工 艺流程包括：
第一次构图工艺： 提供一基板 1 , 该基板 1可以为玻璃基板或者石英基 板， 在基板 1上沉积栅金属层以形成栅电极和栅极扫描线。
具体地， 可以釆用溅射或热蒸发的方法在基板 1 上沉积厚度为 500 ~ 4000A的栅金属层， 栅金属层可以选用 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等金 属或合金， 栅金属层可以是单层金属或单层合金， 还可以是多层金属或多层 合金。 在栅金属层上涂布光刻胶， 利用掩模板对光刻胶进行曝光和显影之后 进行刻蚀， 形成栅电极 2和栅极扫描线 12 , 图 2所示为经第一次构图工艺后 所形成结构的截面示意图。
第二次构图工艺：在形成有栅电极 2和栅极扫描线 12的基板 1上依次沉 积栅绝缘层 3、 第一金属氧化物层、 第二金属氧化物层和源漏金属层。
具体地， 可以在形成有栅电极 2和栅极扫描线 12的基板 1通过 PECVD ( Plasma Enhanced Chemical Vapor Deposition, 等离子体增强化学气相沉积 法）沉积厚度为 2000 ~ 5000 A的栅绝缘层 3 , 栅绝缘层 3可以选用氧化物、 氮化物或者氧氮化合物， 对应的反应气体可以为 Si¾, NH3, N2或 Si¾Cl2, NH3, N2。 栅绝缘层可以使单层， 也可以是多层， 一般靠近金属氧化物层的 为氧化物栅绝缘层。
然后通过溅射的方法在栅绝缘层 3上连续沉积厚度均为 50 ~ 2000 A的第 一金属氧化物层和第二金属氧化物层，以便由第一金属氧化物层形成有源层， 由第二金属氧化物层形成緩冲层。 緩冲层位于有源层和源漏金属层之间， 由 金属氧化物形成， 其目的是为了减少源电极和漏电极与有源层的接触电阻， 并在刻蚀源漏金属层以形成源电极和漏电极时保护下面的有源层， 提升金属 氧化物 TFT的性能。
其中， 有源层的导电率低于緩冲层的导电率， 导电率接近半导体， 緩冲 层可以由至少一个金属氧化物层形成， 在緩冲层由两个以上高导电率的金属 氧化物层形成时， 从靠近有源层到远离有源层的方向上， 也即， 随着与有源 层相距的距离增大， 该两个以上的金属氧化物层的导电率依次增大。 有源层 可以包括多层， 例如可以包括多层金属氧化物层， 诸如有源层可以包括三层 金属氧化物层， 依次为第一金属氧化物层、 第二金属氧化物层和第三金属氧 化物层， 其中第一金属氧化物层的导电率小于第二金属氧化物层的导电率， 第二金属氧化物层的导电率小于第三金属氧化物层的导电率。
本实施例以緩冲层仅包括一个金属氧化物层为例进行具体说明。 本实施 例中， 在栅绝缘层 3上连续沉积两个金属氧化物层， 先沉积的金属氧化物层 导电率较低， 可以用于形成有源层 4-1 , 后沉积的金属氧化物层导电率较高， 可以用于形成緩冲层 4-2。 如果在栅绝缘层 3上沉积三个以上的金属氧化物 层时， 则最下层的金属氧化物层用于形成有源层， 其余的金属氧化物层用于 形成緩冲层。
沉积金属氧化物层时通过控制氧的含量可以有效地控制金属氧化物层的 导电性。金属氧化物层中氧的含量高，则该金属氧化物层的导电性好， Rs<106 欧姆 .平方毫米 /米， 接近导体； 金属氧化物层中氧的含量低， 则该金属氧化 物层导电性不好， 106欧姆 .平方毫米 /米< Rs<10"欧姆 .平方毫米 /米， 为半导 体。 具体地， 第二金属氧化物层可以釆用非晶 IGZO, 第一金属氧化物层可 以釆用非晶 IGZO、 HIZO、 IZO、 a-InZnO、 ZnO:F、 In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb、 Cd-Sn-0或其他金属氧化物； 之后在第二金属氧化物层上 沉积源漏金属层， 具体地， 可以通过溅射或热蒸发的方法沉积厚度为 2000 ~ 4000 A的源漏金属层， 源漏金属层可以选用 Cr、 W、 Ti、 Ta、 Mo等金属和 合金， 可以是单层金属薄膜或单层合金薄膜， 也可以是多层金属薄膜或多层 合金薄膜。
通过涂布光刻胶和一次灰色调或者半色调掩模板曝光显影后， 形成完全 去除区、 部分保留区和完全保留区， 如图 3所示， 完全保留区对应于源漏金 属电极和数据线， 部分保留区对应于 TFT沟道区域。 进行第一次刻蚀工艺， 刻蚀掉完全去除区的源漏金属层和第一金属氧化物层、 第二金属氧化物层 , 由此形成有源层 4-1 , 结构如图 4所示； 接着进行一次光刻胶灰化工艺以去 除掉部分保留区的光刻胶 10, 形成如图 5所示的结构； 接着再进行第二次刻 蚀工艺， 先刻蚀掉部分保留区的源漏金属层， 再刻蚀掉部分保留区的第二金 属氧化物层， 为了保证完全刻蚀掉第二金属氧化物层， 在刻蚀时可以刻蚀掉 一部分的第一金属氧化物层， 由此在源电极和漏电极之间形成 TFT的沟道。
本实施例中， 緩冲层 4-2直接与源漏金属层接触， 这样设计可以减少有 源层 4-1与源电极和漏电极的接触电阻， 提升金属氧化物 TFT的开态电流。 有源层 4-1直接与栅绝缘层 3接触， 低含氧量的金属氧化物层形成有源层能 够使得 TFT性能更稳定。
进一步地， 为提升金属氧化物 TFT的性能可以对 TFT沟道区域的有源 层的表面进行处理， 以修复刻蚀时对有源层的损伤和污染。 具体地， 可以利 用 N20或 02等离子体对沟道区域的有源层的表面进行处理。 以 5G生产线 为例， 等离子体的工艺参数范围是： 气压 100-2000mT , 射频功率 500W-4000W, N20气体流量 500-3000sccm, 不同产线的设备， 工艺参数有 所不同， 但处理的思想相同。
之后去除残余的光刻胶 10,形成包括源电极緩冲层和漏电极緩冲层的緩 冲层 4-2、 源电极 5、 漏电极 6和数据线 13, 经第二次构图工艺最后形成的 结构如图 6所示。
第三次构图工艺： 在完成第二次构图工艺的基板 1上沉积钝化层 7, 具 体地， 可以通过 PECVD方法沉积厚度为 2000 ~ 5000 A的钝化层 7, 钝化层 7可以选用氧化物、 氮化物或者氧氮化合物， 钝化层 7可以是单层结构也可 以是多层结构， 对应的反应气体可以为 Si¾, 丽 3, N2或 Si¾Cl2, 丽 3, N2。 在钝化层上涂布光刻胶，利用掩模板对光刻胶进行曝光和显影之后进行刻蚀， 形成包括有接触过孔的钝化层 7的图形， 如图 7所示为经第三次构图工艺后 所形成结构的截面示意图；
第四次构图工艺： 在完成第三次构图工艺的基板 1上沉积透明导电层， 具体地， 可以通过溅射或热蒸发的方法在形成有钝化层 7的基板 1上沉积厚 度为 300 ~ 1500 A的透明导电层， 透明导电层可以釆用 ITO或者 IZO, 或者 其他的透明金属氧化物。 在透明导电层上涂布光刻胶， 利用掩模板对光刻胶 进行曝光和显影之后进行刻蚀， 形成像素电极 8, 像素电极 8通过接触过孔 与漏电极 6相连接。
如图 8所示为经第四次构图工艺后所形成的薄膜晶体管阵列基板的截面 示意图， 如图 1所示为经过四次构图工艺后形成的薄膜晶体管阵列基板的平 面示意图。
本实施例通过导电率高的第二金属氧化物层既可在刻蚀源漏金属层时保 护有源层， 又可以最后形成减少源电极和漏电极与有源层的接触电阻的緩冲 层， 从而可通过一次构图工艺形成有源层、 源电极和漏电极， 能够节省构图 工艺， 提升生产效率， 降低产品的生产成本。 此外， 本发明实施例的技术方 案在栅绝缘层上形成两层以上的金属氧化物层， 底层是有源层， 其余层作为 緩冲层， 在形成源电极和漏电极时刻蚀掉部分緩冲层， 形成沟道， 这样设计 既可以减少源电极和漏电极与有源层的接触电阻， 同时利用緩冲层保护有源 层， 可以提升金属氧化物 TFT的性能。
本发明实施例还提供了一种显示面板， 包括如上所述的薄膜晶体管阵列 基板。
本发明实施例还提供了一种显示装置， 包括如上所述的薄膜晶体管阵列 基板， 具体地， 该显示装置可以应用在液晶显示器、平板电脑等电子器件中。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种薄膜晶体管阵列基板的制造方法， 包括：
依次沉积第一金属氧化物层、 第二金属氧化物层和源漏金属层， 所述第 一金属氧化物层的导电率小于所述第二金属氧化物层的导电率；
图案化所述第一金属氧化物层、 所述第二金属氧化物层和所述源漏金属 层， 以分别形成有源层、 緩冲层以及源电极和漏电极。
2. 根据权利要求 1所述的薄膜晶体管阵列基板的制造方法， 其中， 所述 图案化所述第一金属氧化物层、 所述第二金属氧化物层和所述源漏金属层包 括：
在所述源漏金属层上涂布光刻胶；
形成完全去除区、 对应源电极、 漏电极的完全保留区和对应沟道区域的 部分保留区；
刻蚀掉完全去除区的源漏金属层、 第一金属氧化物层和第二金属氧化物 层
进行光刻胶灰化工艺以去除掉所述部分保留区的光刻胶；
刻蚀掉部分保留区的源漏金属层；
刻蚀掉部分保留区的第二金属氧化物层； 以及
去除所述完全保留区的光刻胶。
3. 根据权利要求 1或 2所述的薄膜晶体管阵列基板的制造方法， 其中， 所述形成源电极、 漏电极之后还包括：
对所述沟道区域的有源层的表面进行修复。
4.根据权利要求 1至 3的任一项所述的薄膜晶体管阵列基板的制造方法， 其中， 所述制造方法包括：
在所述沉积第一金属氧化物层、 第二金属氧化物层和源漏金属层之前， 在基板上形成栅电极和栅极扫描线的图形以及在形成有所述栅电极和栅极扫 描线的图形的基板上形成栅绝缘层；
在图案化所述第一金属氧化物层、 所述第二金属氧化物层和所述源漏金 属层之后， 在形成有所述源电极、 漏电极和数据线的图形的基板上形成包括 有接触孔的钝化层的图形， 以及在所述钝化层上形成像素电极， 所述像素电 极通过所述接触孔与所述漏电极相连接。
5. 一种薄膜晶体管阵列基板， 包括：
由第一金属氧化物层形成的有源层；
由第二金属氧化物层形成的緩冲层， 緩冲层的导电率比有源层的导电率 大， 緩冲层包括源电极緩冲层和漏电极緩冲层；
由源漏金属层形成的源电极、 漏电极；
其中， 源电极緩冲层位于所述有源层和所述源电极之间， 所述漏电极緩 冲层位于所述有源层和所述漏电极之间。
6. 根据权利要求 5所述的薄膜晶体管阵列基板， 其中， 所述緩冲层包括 至少两个金属氧化物层， 随着与有源层相距的距离增大， 金属氧化物层的导 电率依次增大。
7. 根据权利要求 4或 5所述的薄膜晶体管阵列基板， 其中还包括： 基板；
位于所述基板上由栅金属层形成的栅电极和栅极扫描线；
位于形成有所述栅电极和栅极扫描线的基板上的栅绝缘层；
位于所述栅绝缘层上的所述有源层；
位于所述有源层上的所述源电极緩冲层和所述漏电极緩冲层； 分别位于所述源电极緩冲层和漏电极緩冲层上的所述源电极、 所述漏电 极和数据线；
位于形成有所述源电极、 漏电极和数据线的基板上的包括有接触孔的钝 化层；
位于所述钝化层上的像素电极， 所述像素电极通过所述接触孔与所述漏 电极相连接。
8. 根据权利要求 5至 7的任一项所述的薄膜晶体管阵列基板， 其中， 所 述緩冲层的材料为非晶 IGZO。
9. 根据权利要求 5至 7的任一项所述的薄膜晶体管阵列基板， 其中， 所 述有源层的材料为非晶 IGZO、 HIZO、 IZO、 a-InZnO, ZnO:F、 In203:Sn、 In203:Mo、 Cd2Sn04、 ZnO:Al、 Ti02:Nb或 Cd-Sn-0。
10. 一种显示面板， 包括如权利要求 5-9中任一项所述的薄膜晶体管阵 列基板。
11. 一种显示装置， 包括如权利要求 5-9中任一项所述的薄膜晶体管阵 列基板。
PCT/CN2012/086772 2012-05-18 2012-12-17 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置 Ceased WO2013170605A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020137008588A KR101447843B1 (ko) 2012-05-18 2012-12-17 박막 트랜지스터 어레이 기판, 그 제조 방법, 디스플레이 패널 및 디스플레이 장치
EP12829202.6A EP2677537A4 (en) 2012-05-18 2012-12-17 THIN FILM TRANSISTOR ARRAY SUBSTRATE, METHOD FOR THE PRODUCTION THEREOF, AND DISPLAY TABLE AND DISPLAY DEVICE
JP2015511901A JP2015521383A (ja) 2012-05-18 2012-12-17 薄膜トランジスタアレイ基板及びその製造方法、表示パネル、表示装置
US13/822,480 US8912538B2 (en) 2012-05-18 2012-12-17 Thin film transistor array substrate and method for manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201210157572.1 2012-05-18
CN201210157572 2012-05-18
CN201210181618.3A CN102751240B (zh) 2012-05-18 2012-06-04 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置
CN201210181618.3 2012-06-04

Publications (1)

Publication Number Publication Date
WO2013170605A1 true WO2013170605A1 (zh) 2013-11-21

Family

ID=47031306

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/086772 Ceased WO2013170605A1 (zh) 2012-05-18 2012-12-17 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置

Country Status (6)

Country Link
US (1) US8912538B2 (zh)
EP (1) EP2677537A4 (zh)
JP (1) JP2015521383A (zh)
KR (1) KR101447843B1 (zh)
CN (1) CN102751240B (zh)
WO (1) WO2013170605A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102751240B (zh) 2012-05-18 2015-03-11 京东方科技集团股份有限公司 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置
CN103022149B (zh) 2012-12-14 2015-06-10 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及制造方法和显示器件
KR20150010065A (ko) * 2013-07-18 2015-01-28 삼성디스플레이 주식회사 산화물 반도체 소자의 제조 방법 및 산화물 반도체 소자를 포함하는 표시 장치의 제조 방법
CN103441129A (zh) 2013-08-23 2013-12-11 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
US9722092B2 (en) * 2015-02-25 2017-08-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a stacked metal oxide
WO2016201610A1 (zh) * 2015-06-15 2016-12-22 北京大学深圳研究生院 金属氧化物薄膜晶体管及制备方法、显示面板和显示器
CN105070722A (zh) * 2015-07-14 2015-11-18 深圳市华星光电技术有限公司 Tft基板结构及其制作方法
CN106024608B (zh) * 2016-05-26 2019-04-02 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、衬底基板及显示装置
CN106024705B (zh) * 2016-06-01 2019-04-30 深圳市华星光电技术有限公司 Tft基板的制作方法
TWI609496B (zh) * 2016-09-07 2017-12-21 友達光電股份有限公司 薄膜電晶體及其製作方法
CN109980086A (zh) * 2017-12-28 2019-07-05 深圳Tcl工业研究院有限公司 氧化物薄膜晶体管及其制备方法
CN108598086B (zh) * 2018-04-20 2020-05-29 武汉华星光电技术有限公司 Tft阵列基板的制作方法及tft阵列基板
CN110729238A (zh) * 2019-10-23 2020-01-24 成都中电熊猫显示科技有限公司 阵列基板的制作方法及阵列基板
CN110718561A (zh) * 2019-10-23 2020-01-21 成都中电熊猫显示科技有限公司 阵列基板的制作方法及阵列基板
CN114846623A (zh) 2020-12-01 2022-08-02 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、显示装置
CN113113427A (zh) * 2021-03-23 2021-07-13 Tcl华星光电技术有限公司 阵列基板及其制备方法、显示面板
KR102890112B1 (ko) * 2021-11-08 2025-11-24 엘지디스플레이 주식회사 표시 장치
CN114284363A (zh) * 2021-12-28 2022-04-05 广州华星光电半导体显示技术有限公司 薄膜晶体管和显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542742A (zh) * 2007-04-04 2009-09-23 索尼株式会社 薄膜晶体管及其制造方法、显示装置
CN101656232A (zh) * 2008-08-19 2010-02-24 北京京东方光电科技有限公司 薄膜晶体管阵列基板制造方法
US20100155719A1 (en) * 2008-12-19 2010-06-24 Junichiro Sakata Method for manufacturing semiconductor device
CN101901838A (zh) * 2009-05-29 2010-12-01 株式会社半导体能源研究所 半导体装置及该半导体装置的制造方法
CN102751240A (zh) * 2012-05-18 2012-10-24 京东方科技集团股份有限公司 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置
CN202601621U (zh) * 2012-05-18 2012-12-12 京东方科技集团股份有限公司 薄膜晶体管阵列基板、显示面板、显示装置

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0175409B1 (ko) * 1995-11-20 1999-02-18 김광호 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법
KR100604717B1 (ko) * 1999-07-08 2006-07-28 엘지.필립스 엘시디 주식회사 액정 표시장치 제조방법 및 그 제조방법에 따른 액정표시장치
CN1445821A (zh) * 2002-03-15 2003-10-01 三洋电机株式会社 ZnO膜和ZnO半导体层的形成方法、半导体元件及其制造方法
KR100866976B1 (ko) * 2002-09-03 2008-11-05 엘지디스플레이 주식회사 액정표시장치용 어레이기판과 제조방법
KR100519377B1 (ko) * 2003-04-08 2005-10-06 엘지.필립스 엘시디 주식회사 반사투과형 액정표시장치용 어레이기판 및 그 제조방법
KR100960687B1 (ko) * 2003-06-24 2010-06-01 엘지디스플레이 주식회사 구리(또는 구리합금층)를 포함하는 이중금속층을 일괄식각하기위한 식각액
KR100938887B1 (ko) * 2003-06-30 2010-01-27 엘지디스플레이 주식회사 액정표시장치용 어레이기판과 그 제조방법
KR101034181B1 (ko) * 2003-08-21 2011-05-12 엘지디스플레이 주식회사 액정표시장치용 어레이기판 제조방법
KR100640213B1 (ko) * 2003-12-29 2006-10-31 엘지.필립스 엘시디 주식회사 폴리실리콘 액정표시소자 제조방법
KR100608403B1 (ko) * 2004-03-24 2006-08-03 엘지.필립스 엘시디 주식회사 유기전계발광 소자 및 그 제조방법
US7378286B2 (en) * 2004-08-20 2008-05-27 Sharp Laboratories Of America, Inc. Semiconductive metal oxide thin film ferroelectric memory transistor
KR100675937B1 (ko) * 2004-09-21 2007-02-02 비오이 하이디스 테크놀로지 주식회사 박막트랜지스터 액정표시장치의 어레이 기판 제조방법
AU2005302962B2 (en) * 2004-11-10 2009-05-07 Canon Kabushiki Kaisha Amorphous oxide and field effect transistor
KR101254560B1 (ko) * 2006-06-29 2013-04-19 엘지디스플레이 주식회사 유기전계 발광소자와 그 제조방법
KR101235106B1 (ko) * 2006-06-30 2013-02-20 엘지디스플레이 주식회사 액정표시장치용 어레이 기판과 그 제조방법
KR101479652B1 (ko) * 2006-11-28 2015-01-06 엘지디스플레이 주식회사 유기전계 발광소자의 홀 주입층 형성방법과 이를 포함한유기전계 발광소자의 제조방법
JP4727684B2 (ja) * 2007-03-27 2011-07-20 富士フイルム株式会社 薄膜電界効果型トランジスタおよびそれを用いた表示装置
KR100982395B1 (ko) * 2007-04-25 2010-09-14 주식회사 엘지화학 박막 트랜지스터 및 이의 제조방법
JP4986824B2 (ja) 2007-11-27 2012-07-25 Ｊｘ日鉱日石金属株式会社 微量貴金属の高周波プラズマ質量分析装置を用いた分析方法
JP5213458B2 (ja) * 2008-01-08 2013-06-19 キヤノン株式会社 アモルファス酸化物及び電界効果型トランジスタ
JP5121478B2 (ja) * 2008-01-31 2013-01-16 株式会社ジャパンディスプレイウェスト 光センサー素子、撮像装置、電子機器、およびメモリー素子
KR101496148B1 (ko) * 2008-05-15 2015-02-27 삼성전자주식회사 반도체소자 및 그 제조방법
KR100963104B1 (ko) 2008-07-08 2010-06-14 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
TWI469354B (zh) * 2008-07-31 2015-01-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
JP5537787B2 (ja) * 2008-09-01 2014-07-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR101667909B1 (ko) * 2008-10-24 2016-10-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치의 제조방법
WO2010047288A1 (en) * 2008-10-24 2010-04-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductordevice
TW201044660A (en) * 2008-12-05 2010-12-16 Du Pont Backplane structures for solution processed electronic devices
KR101246789B1 (ko) * 2009-07-23 2013-03-26 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
EP2284891B1 (en) * 2009-08-07 2019-07-24 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device and manufacturing method thereof
KR102236140B1 (ko) * 2009-09-16 2021-04-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 발광 장치 및 이의 제조 방법
WO2011036981A1 (en) * 2009-09-24 2011-03-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR20120094013A (ko) * 2009-11-13 2012-08-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 스퍼터링 타겟 및 그 제조방법, 및 트랜지스터
US8723174B2 (en) 2010-06-02 2014-05-13 Sharp Kabushiki Kaisha Thin film transistor, contact structure, substrate, display device, and methods for manufacturing the same
KR101995851B1 (ko) 2010-07-02 2019-07-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
WO2012035975A1 (en) * 2010-09-15 2012-03-22 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and manufacturing method thereof
US8569754B2 (en) * 2010-11-05 2013-10-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP2011228312A (ja) * 2011-06-30 2011-11-10 Sony Corp 機能性デバイス

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542742A (zh) * 2007-04-04 2009-09-23 索尼株式会社 薄膜晶体管及其制造方法、显示装置
CN101656232A (zh) * 2008-08-19 2010-02-24 北京京东方光电科技有限公司 薄膜晶体管阵列基板制造方法
US20100155719A1 (en) * 2008-12-19 2010-06-24 Junichiro Sakata Method for manufacturing semiconductor device
CN101901838A (zh) * 2009-05-29 2010-12-01 株式会社半导体能源研究所 半导体装置及该半导体装置的制造方法
CN102751240A (zh) * 2012-05-18 2012-10-24 京东方科技集团股份有限公司 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置
CN202601621U (zh) * 2012-05-18 2012-12-12 京东方科技集团股份有限公司 薄膜晶体管阵列基板、显示面板、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2677537A4 *

Also Published As

Publication number Publication date
US20140103333A1 (en) 2014-04-17
CN102751240A (zh) 2012-10-24
KR20140010361A (ko) 2014-01-24
US8912538B2 (en) 2014-12-16
CN102751240B (zh) 2015-03-11
EP2677537A1 (en) 2013-12-25
KR101447843B1 (ko) 2014-10-13
EP2677537A4 (en) 2014-04-23
JP2015521383A (ja) 2015-07-27

Similar Documents

Publication Publication Date Title
US8912538B2 (en) Thin film transistor array substrate and method for manufacturing the same
CN101814455B (zh) 制造阵列基板的方法
CN103700665B (zh) 金属氧化物薄膜晶体管阵列基板及其制作方法、显示装置
US9236405B2 (en) Array substrate, manufacturing method and the display device thereof
CN102955312B (zh) 一种阵列基板及其制作方法、显示装置
CN102654698B (zh) 液晶显示器阵列基板及其制造方法、液晶显示器
CN103022149B (zh) 薄膜晶体管、阵列基板及制造方法和显示器件
CN103745955B (zh) 显示装置、阵列基板及其制造方法
WO2016041304A1 (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN103915451B (zh) 一种阵列基板及其制造方法、显示装置
WO2020019908A1 (zh) 静电保护电路、阵列基板及显示装置
CN107968097B (zh) 一种显示设备、显示基板及其制作方法
CN103887245A (zh) 一种阵列基板的制造方法
CN104779302A (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN103489918A (zh) 一种薄膜晶体管和阵列基板及其制造方法
CN105655359A (zh) Tft基板的制作方法
CN103018990A (zh) 一种阵列基板和其制备方法、及液晶显示装置
CN103715266A (zh) 氧化物薄膜晶体管、阵列基板的制造方法及显示器件
CN103531640A (zh) 薄膜晶体管、阵列基板及其制造方法和显示装置
CN103928405A (zh) 一种tft阵列基板的制造方法
WO2013143294A1 (zh) 阵列基板、其制作方法以及显示装置
CN102637648A (zh) 薄膜晶体管液晶显示器、阵列基板及其制造方法
US9240424B2 (en) Thin film transistor array substrate and producing method thereof
CN111508895B (zh) 阵列基板、显示面板以及阵列基板的制作方法
CN103700663B (zh) 一种阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13822480

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2012829202

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2012829202

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20137008588

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2015511901

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE