WO2014108012A1 - 晶体管阵列及其制备方法 - Google Patents

晶体管阵列及其制备方法 Download PDF

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Publication number
WO2014108012A1
WO2014108012A1 PCT/CN2013/089184 CN2013089184W WO2014108012A1 WO 2014108012 A1 WO2014108012 A1 WO 2014108012A1 CN 2013089184 W CN2013089184 W CN 2013089184W WO 2014108012 A1 WO2014108012 A1 WO 2014108012A1
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Prior art keywords
transistor
transistor array
piezoelectric body
top electrode
piezoelectric
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Ceased
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PCT/CN2013/089184
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English (en)
French (fr)
Inventor
王中林
武文倬
温肖楠
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National Center for Nanosccience and Technology China
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National Center for Nanosccience and Technology China
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Application filed by National Center for Nanosccience and Technology China filed Critical National Center for Nanosccience and Technology China
Priority to KR1020157021714A priority Critical patent/KR101817069B1/ko
Priority to EP13870521.5A priority patent/EP2945200B1/en
Priority to US14/759,843 priority patent/US10644063B2/en
Priority to JP2015551961A priority patent/JP6268189B2/ja
Publication of WO2014108012A1 publication Critical patent/WO2014108012A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N39/00—Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/16—Measuring force or stress, in general using properties of piezoelectric devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/08—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of piezoelectric devices, i.e. electric circuits therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/06—Forming electrodes or interconnections, e.g. leads or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/30—Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors
    • H10N30/302—Sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H10N30/8548—Lead-based oxides
    • H10N30/8554—Lead-zirconium titanate [PZT] based
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/857—Macromolecular compositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
    • H10N30/877—Conductive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/88—Mounts; Supports; Enclosures; Casings
    • H10N30/883—Additional insulation means preventing electrical, physical or chemical damage, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
    • H10N30/077—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by liquid phase deposition

Definitions

  • the invention relates to a semiconductor device, and more particularly to a transistor array for use in pressure sensing imaging and a method of fabricating the same.
  • BACKGROUND OF THE INVENTION The large-scale integration of tiny functional units on transparent flexible substrates is of great significance for fields such as sensors, energy harvesting, and human-machine interaction.
  • One of the research hotspots in the field of pressure sensing based on flexible electronics is to minimize the influence of the bending deformation of the substrate material on the performance of the resulting micro-nano pressure sensor.
  • Existing pressure sensing technologies are mostly based on planar field effect transistors.
  • the present invention provides a transistor array including a substrate and a plurality of transistor cells sharing the substrate, the transistor unit comprising:
  • a bottom electrode and a bottom electrode on the substrate are connected to the line;
  • the piezoelectric body being a piezoelectric material
  • the piezoelectric body of the transistor unit has a polarization orientation.
  • the polarization orientation of the piezoelectric body of the transistor unit is substantially perpendicular to the Base plane.
  • the polarization directions of the piezoelectric bodies of each of the transistor units are substantially the same.
  • the transistor unit of the transistor array further comprises a flexible insulating filling layer, and an upper surface of the flexible insulating filling layer exposes at least a top electrode of the transistor unit.
  • the transistor unit further includes a top electrode connection line, and the top electrode connection line is used to connect the top electrode out of the transistor array.
  • the transistor array further includes an encapsulation layer on the flexible insulating filling layer, the encapsulation layer encapsulating a portion of the transistor unit exposed on an upper surface of the flexible insulating filling layer.
  • the piezoelectric body of the transistor unit is a nanowire, a nanorod or a thin film of ZnO, GaN, CdS, InN, InGaN, CdTe, CdSe or ZnSnO 3 or lead zirconate titanate, or a polyvinylidene fluoride nanofiber.
  • the piezoelectric body is a nanowire, a nanorod or a nanofiber, and the piezoelectric body has an axial direction substantially perpendicular to a bottom electrode or a substrate surface.
  • the transistor unit has a cross-sectional dimension of 25 square microns or less.
  • the distance between the transistor units is from several micrometers to several millimeters.
  • the transistor unit is a cylindrical shape, a quadrangular prism, a hexagonal prism or an irregular cylinder whose axis is substantially perpendicular to the substrate.
  • the piezoelectric body of each of the transistor units is made of the same piezoelectric material.
  • transistor units Preferably, several identical transistor units are included.
  • the substrate is a flexible or rigid substrate.
  • the top electrode and/or the bottom electrode of the transistor unit is one of a conductive oxide, a graphene or a silver nanowire coating, or a gold, silver, platinum, aluminum, nickel, copper, titanium, or a metal , one of selenium or an alloy thereof.
  • the present invention further provides a method for fabricating a transistor array, comprising: providing: a substrate;
  • a bottom electrode array including a plurality of bottom electrodes on the substrate, and a bottom electrode connecting line;
  • a piezoelectric body is prepared on the bottom electrode, a plurality of the piezoelectric bodies form a piezoelectric body array;
  • a top electrode is prepared on the piezoelectric body, and a plurality of the top electrodes form a top electrode array.
  • the method further comprises: preparing a flexible insulating filling layer between the piezoelectric bodies, the top of the piezoelectric body being exposed to the flexible insulating filling layer outer.
  • the preparing the top electrode on the piezoelectric body is:
  • the transistor array provided by the present invention comprises a substrate and a plurality of transistor units sharing the substrate, the transistor unit comprising: a bottom electrode and a bottom electrode connecting line on the substrate; a piezoelectric body on the bottom electrode
  • the piezoelectric body is a piezoelectric material; a top electrode on the piezoelectric body.
  • the transistor unit of the transistor array of the present invention is a device at both ends, and the transfer property between the top electrode and the bottom electrode of the transistor unit is regulated by external stress or strain, and Not the gate voltage of the field emission transistor.
  • the piezoelectric body using the piezoelectric material When a stress or strain is applied to the transistor array or a pressure drive causes the transistor unit to be deformed, the piezoelectric body using the piezoelectric material also undergoes a corresponding deformation, and a one end (bottom end) is formed inside the piezoelectric body as a positive end ( Top) is a negative piezoelectric potential field.
  • the generated piezoelectric potential field can effectively regulate the interface barrier between the piezoelectric body and the electrode material in the vicinity of the bottom electrode (source) or the top electrode (drain) of the transistor unit, and is applied to the field effect transistor.
  • the gate voltage at the gate acts similarly, effectively regulating or triggering the carrier transport process in the device by the stress strain applied to the transistor cell.
  • the deformation of the piezoelectric body is also different, and the transmission properties of the corresponding transistor units are different.
  • the intensity and stress of the stress or strain can be recorded by recording the change of the transmission properties of different transistor units. Spatial distribution of strain
  • the mechanical drive that causes the piezoelectric potential inside the piezoelectric body of the transistor array may be a mechanical vibration signal generated by the flow of air or water, the rotation of the machine engine, the movement of the human body, the stretching of the muscles, the breathing, the heartbeat, or the blood flow. Therefore, the transistor array of the present invention is made It has a wide range of applications for pressure sensing devices.
  • the transistor unit in the transistor array of the present invention has a simple structure and can be accessed separately, and the transistor unit can be up to 25 square micrometers or less in size, and the distance between the transistor units can be 50 micrometers or less, as a pressure sensing imaging device. Its spatial resolution is significantly higher than the resolution of existing field effect transistor arrays.
  • the piezoelectric body in the transistor unit uses piezoelectric nanowires, nanorods, thin films or nanofibers, which are sensitive to pressure, and the pressure resolution of the transistor unit can reach 1 kPa or less.
  • 1 is a top plan view of a first embodiment of a transistor array
  • FIG. 2 is a schematic cross-sectional structural view of a first embodiment of a transistor array
  • FIG. 3 and FIG. 4 are schematic structural diagrams of Embodiment 2 of a transistor array
  • FIG. 5 is a flow chart of a method of fabricating a transistor array
  • the existing pressure sensing technology is mostly based on planar field effect transistors. Due to the three-terminal structure of the field effect transistor unit, not only a relatively complicated integration process is required, but also the pressure sensor device of the transistor array based on such technology lacks the external environment. Directly with electronic devices Use an interactive mechanism. In addition, the integration density of existing flexible field sensor devices based on planar field effect transistors is also affected by the size of each cell. Generally, the cell size can be achieved on the order of hundreds of micrometers, which seriously affects the density and space of pressure sensor integration. Resolution.
  • the present invention provides a transistor array which is composed of a plurality of independently operating transistor cells sharing the same substrate, the transistor cells being of a metal, a piezoelectric body and a metal structure.
  • the invention utilizes a piezoelectric body (nano piezoelectric material) which is vertically grown or placed to form a three-dimensional large-scale piezoelectric electronic transistor array, and a piezoelectric electron obtained by using a piezoelectric potential pair generated by a piezoelectric body under stress.
  • the carrier transport of the transistor is effectively controlled, and the conduction of the transistor is controlled by the piezoelectric potential as the gate voltage, and the electronic device and the nano-electromechanical device driven and controlled by strain, stress or pressure are realized.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 1 is a schematic top view of a transistor array
  • FIG. 2 is a schematic structural view of a transistor array cross section, including a substrate 100 and a plurality of common substrates 100 (m ⁇ n, m And n is any natural number greater than or equal to 1) the transistor unit 200, wherein the transistor unit comprises: a bottom electrode 201 and a bottom electrode connection line (not shown) on the substrate 100, and a piezoelectric body 202 on the bottom electrode 201 And a top electrode 203 on the piezoelectric body 202.
  • the piezoelectric body 202 is made of a piezoelectric material, and may be selected from nanowires, nanorods or thin films of materials such as ZnO, GaN, CdS, InN, InGaN, CdTe, CdSe or ZnSnO 3 or lead zirconate titanate (PZT), or polyvinylidene fluoride. Ethylene (PVDF, poly(vinylidene fluoride)) nanofiber.
  • the piezoelectric material of each transistor unit is the same, that is, in the transistor array, the piezoelectric bodies of all transistor units are made of the same piezoelectric material.
  • the orientation of the piezoelectric body to the bottom electrode or substrate is preferably such that the axial direction of the piezoelectric body is substantially perpendicular to the bottom electrode or substrate.
  • the piezoelectric body in the transistor unit it is preferred that the piezoelectric body have a polarization orientation.
  • the single crystal or the deposition method can be obtained by a growth method to obtain a polycrystalline material, and the existing material preparation method can obtain a material having a uniform polarization orientation, such as vapor phase or liquid phase deposition.
  • the c-axis oriented ZnO nanowires serve as piezoelectric bodies. Since the c-axis is the polarization direction of ZnO, when the transistor array is subjected to stress or strain, the piezoelectric body ZnO of the transistor unit is also deformed correspondingly, and then one end of the ZnO is generated along the c-axis direction and the positive end is negative. Piezoelectric potential field.
  • the piezoelectric body preferably has a polarization orientation, and the piezoelectric material has a polarization orientation substantially perpendicular to the surface of the substrate.
  • the piezoelectric body of the transistor cell is a c-axis polarization-oriented ZnO nanowire, and the c-axis of the ZnO nanowire is perpendicular to the substrate.
  • the polarization directions of the piezoelectric bodies of each transistor unit are substantially the same, and the structure is such that the polarization directions of the piezoelectric bodies in each transistor unit are the same or similar, and each transistor unit is made of a material.
  • the response to external stress or strain is close, and the performance of each transistor unit is basically the same.
  • the substrate 100 may be a flexible or rigid substrate, and may be a flexible material such as polyimide or polyethylene terephthalate (PET), or may be a silicon wafer or a ceramic.
  • Non-flexible (hard) material may be used.
  • the bottom electrode 201 and the bottom electrode connecting line of the transistor unit 200 may be one of conductive oxide, graphene or silver nanowire coating, or gold, silver, platinum, aluminum, nickel, copper, titanium, solder, selenium. Or one of the alloys; the material of the bottom electrode connection line may be the same as the material of the bottom electrode, and the bottom electrode connection line functions to draw the bottom electrode out of the transistor array device, and the bottom electrode of the transistor unit is connected to an external circuit, such as a transistor unit. Working power and measuring equipment, etc.
  • the top electrode 203 may also be one of a conductive oxide, a graphene or a silver nanowire coating, or one of gold, silver, platinum, aluminum, nickel, copper, titanium, iron, selenium or alloys thereof.
  • the materials of the top electrode 203 and the bottom electrode 201 may be the same or different, and are not limited herein.
  • the bottom electrode and the top electrode are taken out of the transistor array by a conventional method of drawing out an electrical path, and an external circuit is connected between the top electrode and the bottom electrode of each transistor unit.
  • the shape of the transistor unit 200 in the transistor array shown in FIG. 1 is not limited to the quadrangular prism whose axis is perpendicular to the surface of the substrate as shown in the drawing, but may be a cylindrical or hexagonal prism whose axis is substantially perpendicular to the surface of the substrate, and the like, and irregular Columnar.
  • the transistor unit may have a cross-sectional dimension of 25 square micrometers or less, and the distance between the transistor units may be 50. Micron or smaller.
  • each transistor unit has the same size, shape, and material.
  • the field emission transistor includes a source, a drain and a gate, and a gate voltage applied to the gate controls a width of a channel between the source and the drain.
  • the transistor unit of the transistor array of the present invention is a device at both ends, and the control of the transmission property between the top electrode and the bottom electrode is changed from the gate voltage to the applied stress or strain, that is, by adding Stress or strain replaces the gate voltage applied by the third terminal of the existing transistor.
  • the transistor unit is deformed by applying stress or strain or pressure driving on the transistor array, the piezoelectric body using the piezoelectric material is also deformed correspondingly, and a negative voltage at one end of the piezoelectric body is generated inside the piezoelectric body. Electric potential field.
  • the mechanical drive for generating a piezoelectric potential inside the piezoelectric body may be a mechanical vibration signal generated by the flow of air or water, the rotation of the machine engine, the movement of the human body, the stretching of the muscles, the breathing, the heartbeat or the blood flow.
  • the generated piezoelectric potential field can effectively regulate the interface barrier between the piezoelectric body and the electrode material in the vicinity of the bottom electrode (source) or the top electrode (drain) of the transistor unit, and is applied to the field effect transistor.
  • the gate voltage at the gate acts similarly, effectively regulating or triggering the carrier transport process in the device by the stress strain applied to the transistor cell.
  • the deformation of the piezoelectric body is also different, and the transmission properties of the corresponding transistor units are different.
  • the intensity and spatial distribution of stress or strain can be recorded by recording the transmission properties of different transistor units. .
  • a transistor array is formed by using only two transistor units, and the transistor unit is perpendicular to the substrate.
  • the transistor is a piezoelectric electronic transistor.
  • Such a structure not only realizes direct interaction between mechanical pressure and electronic components, but also three-dimensional vertical piezoelectric.
  • the structure of the transistor array also circumvents the fabrication of surrounding gate electrodes that are difficult to achieve in conventional three-dimensional vertical nanowire transistors.
  • each transistor cell has separate top and bottom electrodes, each transistor cell can be independently addressed by a peripheral interface circuit.
  • the transistor unit may have a cross-sectional dimension of 25 square micrometers or less in the direction of the surface of the parallel substrate, and the distance between the transistor cells may be 50 micrometers or less.
  • the spatial resolution thereof The rate is significantly higher than the resolution of existing field effect transistor arrays.
  • the piezoelectric body in the transistor unit uses piezoelectric nanowires, nanorods, thin films or nanofibers, which are sensitive to pressure, and the pressure resolution of the transistor unit can reach 1 kPa or less.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • this embodiment differs from the first embodiment in that a flexible insulating filling layer 300 is filled between the transistor cells 200.
  • the filling height of the flexible insulating filling layer 300 may be slightly lower than the piezoelectric body 202 of the transistor unit, and the upper surface of the flexible insulating filling layer 300 exposes at least the top electrode 203 of the transistor unit 200, as shown in FIG.
  • the other parts of the transistor array in this embodiment are the same as those in the first embodiment, and will not be repeated here.
  • the material of the flexible insulating filling layer may be polydimethylsiloxane (PDMS), SU-8 epoxy resin or other flexible insulating material.
  • PDMS polydimethylsiloxane
  • SU-8 epoxy resin or other flexible insulating material.
  • the flexible insulating fill layer can serve to enhance the mechanical strength of the transistor array device and extend the operating life of the device.
  • the transistor array of this embodiment may further include an encapsulation layer, and the top electrode in the transistor array may be packaged.
  • the top electrode connection line ie, the electrical path, not shown in the figure
  • the encapsulation layer 400 is located in the flexible insulation pad.
  • the portion of the transistor unit described herein exposed on the upper surface of the flexible insulating filling layer includes at least a top electrode 203 and a top electrode connecting line (not shown) of the transistor unit, and a transistor unit not covered by the flexible insulating filling layer material.
  • the transistor unit as a whole is encapsulated in the flexible insulating filling layer 300 and the encapsulation layer 400.
  • the material of the encapsulation layer 400 may be a common semiconductor encapsulation material such as polydimethylsiloxane (PDMS).
  • PDMS polydimethylsiloxane
  • the encapsulation layer can enhance the mechanical strength of the transistor array device and prevent the transistor array device from being affected by factors such as humidity in the external environment.
  • the top electrode connection line may also be one of conductive oxide, graphene or silver nanowire coating, or gold, silver, platinum, aluminum, nickel, copper, titanium, iron, selenium or alloys thereof. One of them.
  • the material of the top electrode 203 and the top electrode connecting line may be the same or different, and is not limited herein.
  • the top electrode connection line and the bottom electrode connection line of each transistor unit are used to connect an external circuit of the transistor unit.
  • the conductive oxide as the top electrode, the top electrode connecting line, the bottom electrode or the bottom electrode connecting line of the transistor unit may be indium tin metal oxide ⁇ ), aluminum-doped zinc oxide (AZO), and gallium doped.
  • a conductive oxide material such as zinc oxide (GZO) and indium gallium co-doped zinc oxide (IGZO).
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 5 is a flow chart of a method for fabricating a transistor array, including:
  • Step S10 providing a substrate
  • Step S20 preparing a bottom electrode array including a plurality of bottom electrodes on the substrate, and a connecting line of each bottom electrode;
  • Step S30 preparing a piezoelectric body on the bottom electrode, and the plurality of piezoelectric bodies form a piezoelectric body array
  • Step S40 preparing a top electrode on the piezoelectric body, and the plurality of the top electrodes form a top electrode array.
  • the preparation process of the transistor array will be specifically described below with reference to the accompanying drawings, including the following steps: First, a substrate is provided.
  • the material of the substrate may be a flexible material such as polyimide (polymnde) or polyethylene terephthalate (PET), or a non-flexible material such as silicon wafer or ceramic.
  • a bottom electrode array including a plurality of bottom electrodes, and a connecting line of each of the bottom electrodes are prepared on the substrate.
  • a bottom electrode array 20 and a connection line of each bottom electrode are selectively deposited on the substrate material in a design pattern by a photolithography mask and a metal deposition technique in a semiconductor processing process on the substrate 10. Not shown in the figure).
  • the size, shape and distance between the bottom electrodes of each bottom electrode are determined according to the design requirements of the transistor array.
  • the wiring pattern of the bottom electrode connection line can be wired by an integrated circuit, and is not particularly limited herein.
  • the bottom electrode connection line is used to electrically connect the bottom electrode of the transistor unit to the outside of the transistor array and to external circuits such as other driving or measuring devices.
  • a piezoelectric body is prepared on the bottom electrode, and the plurality of piezoelectric bodies form a piezoelectric body array.
  • a seed material of a piezoelectric body is selectively deposited on the bottom electrode 20 prepared as described above by a photolithography mask and a thin film deposition technique in a semiconductor processing process.
  • the piezoelectric body is made of ZnO nanowires, and the seed crystal material is also selected from ZnO.
  • a piezoelectric material having a uniform polarization orientation is grown in a vertical direction on the bottom electrode 20 on which the seed layer is deposited by a vapor phase method or a liquid phase method to form a piezoelectric body 30, and a plurality of piezoelectric bodies 30.
  • An array of piezoelectric bodies is formed.
  • a c-axis oriented ZnO nanowire piezoelectric body is grown on the ZnO seed layer on the bottom electrode 20 by a conventional hydrothermal synthesis method.
  • the piezoelectric body has a diameter of several hundred nanometers to several micrometers and a length of several hundred nanometers to several tens of micrometers.
  • One or more nanowires or nanorods may be included in a single piezoelectric body.
  • the step of preparing the piezoelectric body 30 on the bottom electrode 20 can also be carried out by using a micromachining technique to place the previously prepared nanomaterial on the bottom electrode.
  • the step of preparing the piezoelectric body on the bottom electrode further includes the steps of: preparing a flexible insulating filling layer between the piezoelectric bodies, the top of the piezoelectric body being exposed The flexible insulation is filled outside the layer.
  • a suitable thickness of the filling material can be uniformly applied to the device prepared by using the ruthenium film technology in the semiconductor processing process, and the thickness of the filling material at least makes the bottom electrode 20 and the piezoelectric body 30 covered by the filling material.
  • the filler material is preferably a flexible insulating filler such as polydimethylsiloxane (PDMS) or SU-8 epoxy resin.
  • the top of the filling material is uniformly removed by a plasma dry etching technique, and the top of the piezoelectric body 30 obtained as described above is appropriately exposed.
  • the remaining filler material forms a flexible insulating fill layer 40.
  • a top electrode is prepared on the piezoelectric body, and a plurality of the top electrodes form a top electrode array.
  • a top electrode connection line can be simultaneously prepared for extracting the top electrode from the crystal tube array.
  • a top electrode 50 and a top electrode are selectively deposited in a design pattern on the top of the piezoelectric array and the insulating flexible filling layer prepared by using a photolithography mask and a metal deposition technique in a semiconductor processing process.
  • the output line (not shown) is such that the top electrode 50 is formed on the piezoelectric body, and the top electrode connection line is formed on the flexible insulating filling layer.
  • the top electrode forms electrical contact with the top of the piezoelectric body formed by the piezoelectric material.
  • a plurality of top electrodes 50 form a top electrode array to complete the fabrication of the transistor array.
  • the step of preparing the top electrode connection line can also be carried out separately after the top electrode preparation step.
  • the transistor array device produced in the foregoing The surface is covered with an encapsulation layer 60 such as polydimethylsiloxane (PDMS), and the transistor unit is partially exposed on the upper surface of the flexible insulating filling layer, see FIG. 10, the top electrode 50 of the transistor unit, the top electrode connecting line and the piezoelectric layer.
  • PDMS polydimethylsiloxane
  • the power is turned on between the top electrode connecting line of the transistor unit of the transistor array prepared as described above and the connecting line of the bottom electrode, and the electrical properties of each transistor unit in the transistor array device can be detected by a multi-channel electrical measuring system.
  • mechanical signals in the external environment such as the flow of air or water, the rotation of the engine engine, mechanical vibration signals generated by human movement, muscle expansion, respiration, heartbeat or blood flow
  • the multi-channel electrical measurement system records the change, and by sensing the collected electrical parameter values corresponding to the corresponding transistor units and performing processing by using processing software such as Matlab, the sensing of the external environmental mechanical signals (such as stress) can be obtained. And imaging information.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
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  • Thin Film Transistor (AREA)
  • Pressure Sensors (AREA)

Abstract

一种晶体管阵列，包括基底（100）以及共用该基底（100）的若干个晶体管单元（200），晶体管单元（200）包括：位于基底（100）上的底电极（201）和底电极连出线；底电极（201）上的压电体（202），压电体（202）为压电材料；压电体（202）上的顶电极（203）。一种晶体管阵列的制备方法，晶体管阵列的晶体管单元（200）是两端器件，晶体管单元（200）的顶电极（203）和底电极（201）之间采用具有压电性质的压电体（202），通过加在晶体管单元（200）上的应力应变对晶体管阵列器件中晶体管单元（200）的载流子输运过程进行有效的调控或触发。

Description

晶体管阵列及其制备方法 技术领域 本发明涉及一种半导体器件， 特别涉及一种应用在压力传感成像方 面的晶体管阵列及其制备方法。 背景技术 在透明柔性衬底上大规模地集成微小的功能单元对于传感器、 能量 采集和人机互动等领域有着重大的意义。 目前基于柔性电子学的压力传 感领域的研究热点之一是尽量减小衬底材料的弯曲形变对于制得的微 纳压力传感器性能的影响。 现有的压力传感技术多是基于平面型场效应 晶体管。虽然此类技术十分成熟，但鉴于场效应晶体管单元的三端结构， 通常不仅需要比较复杂的集成工艺， 而且基于此类技术的晶体管阵列的 压力传感器件缺乏外界环境与电子器件直接作用交互的机制。
另外， 现有基于平面型场效应晶体管的柔性压力传感器器件的集成 密度也受每个单元尺寸的影响， 通常能达到的单元尺寸在几百微米量 级， 这严重影响了压力传感器集成密度和空间分辨率。 发明内容 本发明的目的是提供一种电学性能直接受到外界机械作用调控的 晶体管阵列。
为实现上述目的， 本发明提供一种晶体管阵列， 包括基底以及共用 该基底的若干个晶体管单元， 所述晶体管单元包括：
位于所述基底上的底电极和底电极连出线；
所述底电极上的压电体， 所述压电体为压电材料；
所述压电体上的顶电极。
优选地， 所述晶体管单元的压电体具有极化取向。
优选地， 所述晶体管单元的压电体的所述极化取向基本垂直与所述 基底平面。
优选地， 所述晶体管阵列中， 每个所述晶体管单元的压电体的所述 极化方向基本相同。
优选地， 所述晶体管阵列的晶体管单元之间还包括柔性绝缘填充 层， 所述柔性绝缘填充层的上表面至少露出所述晶体管单元的顶电极。
优选地， 所述晶体管单元还包括顶电极连出线， 所述顶电极连出线 用于将所述顶电极连出所述晶体管阵列。
优选地， 所述晶体管阵列还包括封装层， 所述封装层位于所述柔性 绝缘填充层上， 所述封装层使所述晶体管单元裸露在所述柔性绝缘填充 层上表面的部分被封装。
优选地，所述晶体管单元的压电体为 ZnO、 GaN、 CdS、 InN、 InGaN、 CdTe、 CdSe或 ZnSn03或锆钛酸铅的纳米线、 纳米棒或薄膜， 或者聚偏 氟乙烯纳米纤维。
优选地， 所述压电体为纳米线、 纳米棒或纳米纤维， 所述压电体的 轴线方向基本垂直于底电极或基底表面。
优选地， 所述晶体管单元的横截面尺寸为 25平方微米或更小。 优选地， 所述晶体管单元之间的距离为几微米至几毫米。
优选地，所述晶体管单元为轴线基本垂直于基底的圆柱形、四棱柱、 六棱柱或不规则柱形。
优选地， 每个所述晶体管单元的压电体采用相同的压电材料。
优选地， 包括若干个相同的所述晶体管单元。
优选地， 所述基底为柔性或硬性基底。
优选地， 所述晶体管单元的顶电极和 /或底电极采用导电氧化物、石 墨烯或银纳米线涂层中的一种， 或者采用金、 银、 铂、 铝、 镍、 铜、 钛、 烙、 硒或其合金中的一种。
相应的， 本发明还提供一种晶体管阵列制备方法， 包括歩骤： 提供基底；
在所述基底上制备包括多个底电极的底电极阵列， 以及底电极连出 线； 在所述底电极上制备压电体， 多个所述压电体形成压电体阵列； 在所述压电体上制备顶电极， 多个所述顶电极形成顶电极阵列。 优选地， 在所述底电极上制备压电体歩骤之后还包括歩骤： 在所述压电体之间制备柔性绝缘填充层， 所述压电体的顶部暴露在 所述柔性绝缘填充层外。
优选地， 所述在所述压电体上制备顶电极歩骤为：
在所述压电体和所述柔性绝缘填充层上制备所述顶电极和顶电极 连出线， 其中， 所述顶电极制备在所述压电体上， 顶电极连出线与所述 顶电极电连接。
与现有技术相比， 本发明的优点在于：
本发明提供的晶体管阵列， 包括基底以及共用该基底的若干个晶体 管单元， 所述晶体管单元包括： 位于所述基底上的底电极和底电极连出 线； 所述底电极上的压电体， 所述压电体为压电材料； 所述压电体上的 顶电极。 区别与现有的采用场效应晶体管的压电感应晶体管阵列， 本发 明的晶体管阵列的晶体管单元是两端器件， 由外加应力或应变调控晶体 管单元的顶电极和底电极之间的传输性质， 而不是场发射晶体管的门电 压。 当在晶体管阵列上施加应力或应变或者压强驱动使晶体管单元产生 形变时， 采用压电材料的压电体也会发生相应的形变， 进而在压电体内 部产生一端 （底端） 为正一端 （顶端） 为负的压电电势场。 产生的压电 电势场可以对晶体管单元中底电极 （源极） 或顶电极 （漏极） 附近的压 电体和电极材料之间的界面势垒有效地调控， 起到与场效应晶体管中施 加在栅极的门电压相似的作用， 通过加在晶体管单元上的应力应变对器 件中的载流子输运过程进行有效地调控或触发。 施加在不同晶体管单元 上的应力或应变不同时， 使压电体的形变也不同， 进而使相应晶体管单 元的传输性质不同， 通过记录不同晶体管单元的传输性质变化可以记录 应力或应变的强度以及应力或应变的空间分布
使晶体管阵列的压电体内部产生压电电势的机械驱动可以是由空 气或水的流动， 机器引擎的运转转动， 人体运动、 肌肉伸缩、 呼吸、 心 跳或是血液流动等产生的机械振动信号。 因此， 本发明的晶体管阵列作 为压力感应装置具有广阔的应用范围。
本发明的晶体管阵列中晶体管单元的结构简单并且可以单独访问， 而且晶体管单元的尺寸可以达到 25 平方微米或更小， 晶体管单元之间 的距离可以为 50 微米或更小， 作为压力感应成像器件， 其空间分辨率 明显高于现有场效应晶体管阵列的分辨率。 另外， 晶体管单元中的压电 体采用压电纳米线、 纳米棒、 薄膜或纳米纤维， 对压力的响应敏感， 晶 体管单元的压力分辨率可以达到 1千帕或更小。 附图说明 通过附图所示，本发明的上述及其它目的、特征和优势将更加清晰。 在全部附图中相同的附图标记指示相同的部分。 并未刻意按实际尺寸等 比例缩放绘制附图， 重点在于示出本发明的主旨。
图 1为晶体管阵列实施例一的俯视示意图；
图 2为晶体管阵列实施例一的截面结构示意图；
图 3和图 4为晶体管阵列实施例二的结构示意图；
图 5为晶体管阵列制备方法的流程图；
图 6至图 10为晶体管阵列制备过程示意图。 具体实施方式 下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案 进行清楚、 完整地描述。 显然， 所描述的实施例仅是本发明一部分实施 例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人 员在没有做出创造性劳动前提下所获得的所有其他实施例， 都属于本发 明保护的范围。
其次， 本发明结合示意图进行详细描述， 在详述本发明实施例时， 为便于说明，所述示意图只是示例，其在此不应限制本发明保护的范围。
现有的压力传感技术多是基于平面型场效应晶体管， 由于场效应晶 体管单元的三端结构， 通常不仅需要比较复杂的集成工艺， 而且基于此 类技术的晶体管阵列的压力传感器件缺乏外界环境与电子器件直接作 用交互的机制。 另外， 现有基于平面型场效应晶体管的柔性压力传感器 器件的集成密度也受每个单元尺寸的影响， 通常能达到的单元尺寸在几 百微米量级， 这严重影响了压力传感器集成密度和空间分辨率。 为了克 服现有技术的缺点， 本发明提供一种晶体管阵列， 晶体管阵列由共用同 一基底的多个独立工作的晶体管单元组成， 所述晶体管单元的结构为金 属、 压电体和金属结构。 本发明是利用垂直生长或放置的压电体 （纳米 压电材料） 制成三维大规模压电电子学晶体管阵列， 利用压电体受应力 作用而产生的压电电势对制得的压电电子学晶体管的载流子输运进行 有效调控， 实现了利用压电势作为栅极电压调控晶体管的导通情况， 以 及实现了由应变、 应力或压强驱动和控制的电子器件、 纳微机电器件和 传感器的新方法。
为使本发明的技术方案更清楚， 下面结合附图详细介绍本发明的实 施例。
实施例一：
本实施例的晶体管阵列参见图 1和图 2， 其中， 图 1为晶体管阵列 的俯视示意图， 图 2为晶体管阵列截面的结构示意图， 包括基底 100以 及共用基底 100的若干个 （mX n个， m和 n为任意大于等于 1的自然 数） 晶体管单元 200， 其中， 晶体管单元包括： 位于基底 100上的底电 极 201和底电极连出线 （在图中未显示）、 底电极 201上的压电体 202 和压电体 202上的顶电极 203。压电体 202采用压电材料，可以选择 ZnO、 GaN、 CdS、 InN、 InGaN、 CdTe、 CdSe或 ZnSn03或锆钛酸铅 （PZT) 等材料的纳米线、纳米棒或薄膜，或者聚偏氟乙烯 (PVDF, poly(vinylidene fluoride^)纳米纤维。 优选为， 每个晶体管单元的压电体材料相同， 即晶 体管阵列中， 所有晶体管单元的压电体采用相同的压电材料。 压电体优 选为具有压电性的纳米线、 纳米棒或纳米纤维， 压电体与底电极或基底 的取向优选为压电体的轴线方向基本垂直于底电极或基底。
对于晶体管单元中的压电体， 优选为压电体具有极化取向。 可以通 过生长方法获得单晶或者沉积方法获得多晶材料， 现有的材料制备方法 可以实现获得具有一致极化取向的材料， 例如气相法或液相法沉积获得 的 c轴取向的 ZnO纳米线作为压电体。 由于 c轴为 ZnO的极化方向， 当晶体管阵列受到应力或应变时，晶体管单元的压电体 ZnO也会发生相 应的变形，进而在 ZnO内部沿着 c轴方向产生一端为正一端为负的压电 电势场。
在本发明的晶体管阵列， 晶体管单元中压电体优选为具有极化取 向， 并且所述压电体材料的极化取向基本垂直于基底表面。 例如晶体管 阵列中， 晶体管单元的压电体为 c轴极化取向的 ZnO纳米线， 并且 ZnO 纳米线的 c轴垂直于基底。 更优选的， 晶体管阵列中， 每个晶体管单元 的压电体的极化方向基本相同， 这种结构使每个晶体管单元中的压电体 的极化方向相同或相近， 每个晶体管单元如果材料相同， 对外界应力或 应变的响应能力接近， 则每个晶体管单元的性能也基本相同。
本实施例中， 基底 100可以为柔性或硬性基底， 可以采用聚酰亚胺 (polyimide) 或聚对苯二甲酸乙二醇酯 （PET) 等柔性材料， 也可以采 用硅片或陶瓷之类的非柔性 （硬性） 材料。
晶体管单元 200 的底电极 201 和底电极连出线可以采用导电氧化 物、 石墨烯或银纳米线涂层中的一种， 或者采用金、 银、 铂、 铝、 镍、 铜、 钛、 烙、 硒或其合金中的一种； 底电极连出线的材料可以与底电极 材料相同， 底电极连出线的作用是将底电极引出晶体管阵列器件外， 为 晶体管单元的底电极连接外电路， 例如晶体管单元的工作电源和测量设 备等。 顶电极 203也可以采用导电氧化物、 石墨烯或银纳米线涂层中的 一种， 或者采用金、 银、 铂、 铝、 镍、 铜、 钛、 烙、 硒或其合金中的一 种。 顶电极 203和底电极 201的材料可以相同， 也可以不同， 在这里不 做限定。 在实际使用中， 采用常用的引出电气通路的方法将底电极和顶 电极引出晶体管阵列， 在每个晶体管单元的顶电极和底电极之间连接外 电路。
图 1所示的晶体管阵列中晶体管单元 200的形状不限于图中所示的 轴线垂直于基底表面的四棱柱， 还可以为轴线基本垂直于基底表面的圆 柱形或六棱柱等， 以及不规则的柱状。 晶体管阵列中， 晶体管单元的横 截面尺寸可以为 25平方微米或更小， 晶体管单元之间的距离可以为 50 微米或更小。
晶体管阵列中， 优选为每个晶体管单元的尺寸、 形状和材料相同。 场发射晶体管包括源极、 漏极和栅极， 由施加在栅极的门电压控制 源极和漏极之间的沟道的宽度， 对于三维垂直纳米线压电晶体管阵列的 结构中， 需要制备环绕栅极， 这样的结构在制备技术上难度较大。
区别于现有的压电晶体管阵列， 本发明的晶体管阵列的晶体管单元 是两端器件， 对顶电极和底电极之间的传输性质的控制由门电压转为外 加应力或应变， 也就是由外加应力或应变代替现有晶体管的第三端施加 的门电压。 当在晶体管阵列上施加应力或应变或者压强驱动而使晶体管 单元产生形变时， 采用压电材料的压电体也会发生相应的形变， 进而在 压电体内部产生一端为正一端为负的压电电势场。 使压电体内部产生压 电电势的机械驱动可以是由空气或水的流动， 机器引擎的运转转动， 人 体运动、 肌肉伸缩、 呼吸、 心跳或是血液流动等产生的机械振动信号。 产生的压电电势场可以对晶体管单元中底电极（源极）或顶电极（漏极) 附近的压电体和电极材料之间的界面势垒有效地调控， 起到与场效应晶 体管中施加在栅极的门电压相似的作用， 通过加在晶体管单元上的应力 应变对器件中的载流子输运过程进行有效地调控或触发。 施加在不同晶 体管单元上的应力或应变不同时， 使压电体的形变也不同， 进而使相应 晶体管单元的传输性质不同， 通过记录不同晶体管单元的传输性质可以 记录应力或应变的强度和空间分布。
本实施例中采用只有两端的晶体管单元形成晶体管阵列， 而且晶体 管单元垂直与基底， 是一种压电电子学晶体管， 这样的结构不仅实现了 机械压力与电子器件的直接交互， 而且三维垂直压电晶体管阵列的结构 也规避了传统三维垂直纳米线晶体管中难以实现的环绕栅电极的制备。
由于每个晶体管单元具有独立的顶电极和底电极， 可以通过外围接 口电路对每个晶体管单元进行独立寻址访问。 本实施例中的晶体管阵列 中， 晶体管单元在平行基底表面方向的截面尺寸可以达到 25 平方微米 或更小， 晶体管单元之间的距离可以为 50 微米或更小， 作为压力感应 器件， 其空间分辨率明显高于现有场效应晶体管阵列的分辨率。 另外， 晶体管单元中的压电体采用压电纳米线、 纳米棒、 薄膜或纳米纤维， 对 压力的响应敏感， 晶体管单元的压力分辨率可以达到 1千帕或更小。
实施例二：
参见图 3， 本实施例与实施例一的区别在于， 在晶体管单元 200之 间填充柔性绝缘填充层 300。 柔性绝缘填充层 300的填充高度可以略低 于晶体管单元的压电体 202， 柔性绝缘填充层 300的上表面至少露出晶 体管单元 200的顶电极 203， 参见图 3中所示。 本实施例中晶体管阵列 的其他部分与实施例一中相同， 在这里不再重复。
柔性绝缘填充层的材料可以采用聚二甲硅氧垸 （PDMS)、 SU-8 环 氧树脂或其他柔性绝缘材料。 柔性绝缘填充层可以起到增强晶体管阵列 器件机械强度和延长器件工作寿命的作用。
另外， 为了保护晶体管阵列的机械结构， 本实施例的晶体管阵列还 可以包括封装层， 可以将晶体管阵列中的顶电极进行封装。 参见图 4， 将晶体管单元的顶电极电连接的顶电极连出线 （即电气通路， 在图中未 示出） 引出后在晶体管阵列的顶部用封装层 400进行封装， 封装层 400 位于柔性绝缘填充层 300上， 晶体管阵列中晶体管单元裸露在柔性绝缘 填充层 300上表面的部分被封装在封装层 400内。 这里所述的晶体管单 元裸露在柔性绝缘填充层上表面的部分至少包括晶体管单元的顶电极 203和顶电极连出线（图中未示出）， 以及未被柔性绝缘填充层材料包裹 住的晶体管单元的压电体顶部。 这样， 晶体管阵列中， 晶体管单元整体 被封装在柔性绝缘填充层 300和封装层 400内。 封装层 400的材料可以 为聚二甲硅氧垸 （PDMS ) 等常用半导体封装材料， 封装层可以增强晶 体管阵列器件的机械强度， 以及避免晶体管阵列器件受到外界环境中湿 度等因素的影响。
本实施例中， 顶电极连出线也可以采用导电氧化物、 石墨烯或银纳 米线涂层中的一种， 或者金、 银、 铂、 铝、 镍、 铜、 钛、 烙、 硒或其合 金中的一种。顶电极 203和顶电极连出线的材料可以相同，也可以不同， 在这里不做限定。 每个晶体管单元的顶电极连出线和底电极连出线用于 连接该晶体管单元的外电路。 本发明的晶体管阵列中，作为晶体管单元的顶电极、顶电极连出线、 底电极或底电极连出线的导电氧化物可以为铟锡金属氧化物 ατο)， 掺 铝氧化锌 （AZO), 掺镓氧化锌 （GZO) 和铟镓共掺氧化锌 （IGZO) 等 导电氧化物材料。
实施例三：
本实施例中提供一种晶体管阵列的制备方法， 图 5为晶体管阵列制 备方法的流程图， 包括：
歩骤 S10, 提供基底；
歩骤 S20, 在所述基底上制备包括多个底电极的底电极阵列， 以及 每个底电极的连出线；
歩骤 S30, 在所述底电极上制备压电体， 多个所述压电体形成压电 体阵列；
歩骤 S40, 在所述压电体上制备顶电极， 多个所述顶电极形成顶电 极阵列。
下面结合附图具体介绍晶体管阵列的制备过程， 包括以下歩骤： 首先， 提供基底。 基底的材料可以为聚酰亚胺 （polymnde) 或聚对 苯二甲酸乙二醇酯 （PET) 等柔性材料， 也可以为硅片和陶瓷等非柔性 材料。
在基底上制备包括多个底电极的底电极阵列， 以及每个底电极的连 出线。参见图 6， 在基底 10上通过半导体加工工艺中的光刻掩膜和金属 淀积技术， 在基底材料上按设计图案选择性地淀积底电极阵列 20， 以及 每个底电极的连出线 （图中未显示）。 底电极阵列中， 每个底电极的尺 寸、 形状以及底电极之间的距离根据晶体管阵列的设计要求决定。 底电 极连出线的布线方式可以采用集成电路的布线方式， 在这里不做特别限 定。 底电极连出线的作用是将晶体管单元的底电极电连接至晶体管阵列 外， 与其他驱动或测量设备等外电路连接。
在底电极上制备压电体， 多个所述压电体形成压电体阵列。 参见图 7， 首先， 通过半导体加工工艺中的光刻掩膜和薄膜淀积技术， 在前述 制得的底电极 20 上按设计图案选择性地淀积压电体的籽晶材料。 例如 压电体采用 ZnO纳米线， 则籽晶材料也选择 ZnO。然后， 利用气相法或 液相法在前述淀积了籽晶层的底电极 20 上沿竖直方向生长出具有一致 极化取向的压电材料， 形成压电体 30， 多个压电体 30形成压电体阵列。 例如采用常规水热合成方法在底电极 20上的 ZnO籽晶层上生长 c轴取 向的 ZnO纳米线压电体。压电体的直径为几百纳米至几微米， 长度为几 百纳米至几十微米。 单独一个压电体中可以包括一根或多根纳米线或纳 米棒。
在底电极 20上制备压电体 30的歩骤也可以采用微加工技术， 将预 先制备好的纳米材料放置在底电极上。
为了增强晶体管阵列的机械强度和延迟器件工作寿命， 可以在底电 极上制备压电体歩骤之后还包括步骤： 在压电体之间制备柔性绝缘填充 层， 所述压电体的顶部暴露在柔性绝缘填充层外。 具体参见图 8， 可以 利用半导体加工工艺中的甩膜技术在前述制得的器件上均匀甩一层厚 度合适的填充材料， 填充材料的厚度至少使底电极 20和压电体 30被填 充材料掩盖，填充材料优选柔性绝缘填充材料，如聚二甲硅氧垸（PDMS) 或 SU-8环氧树脂等。 将填充材料进行如加热或曝光等处理使其机械强 度达到要求范围后， 利用等离子体干法刻蚀技术将填充材料顶部均匀除 去合适厚度后， 将前述制得的压电体 30 的顶部露出适当高度， 剩余的 填充材料形成柔性绝缘填充层 40。
在压电体上制备顶电极， 多个所述顶电极形成顶电极阵列。 该歩骤 中在制备顶电极时可以同时制备顶电极连出线， 用于将顶电极引出晶体 管阵列。参见图 9， 利用半导体加工工艺中的光刻掩膜和金属淀积技术， 在前述制得的压电体阵列顶部和绝缘柔性填充层上按设计图案选择性 地淀积顶电极 50以及顶电极连出线 （图中未显示）， 使得顶电极 50制 备在压电体上， 顶电极连出线制备在所述柔性绝缘填充层上。 顶电极与 压电材料形成的压电体顶部形成电学接触。 多个顶电极 50 形成顶电极 阵列， 完成晶体管阵列的制备。
制备顶电极连出线的歩骤也可以在顶电极制备歩骤之后单独进行。 为了增强晶体管阵列的机械强度， 在前述制得的晶体管阵列器件的 表面覆盖一层聚二甲硅氧垸 （PDMS) 等封装层 60， 将晶体管单元露出 柔性绝缘填充层上表面的部分封装， 参见图 10， 晶体管单元的顶电极 50、 顶电极连出线和压电体 30露出柔性绝缘填充层 40的部分封装在封 装层 60内。
为前述制得的晶体管阵列的晶体管单元的顶电极连出线和底电极 的连出线之间接通电源， 可以通过多通道电学测量系统对晶体管阵列器 件内的每一个晶体管单元的电学性质进行检测。 当外界环境中的机械信 号 （如空气或水的流动， 机器引擎的运转转动， 人体运动、 肌肉伸缩、 呼吸、 心跳或是血液流动等产生的机械振动信号） 作用于晶体管阵列器 件时， 由于机械应变引起的压电电势的存在， 受机械应力作用的每个晶 体管单元中的压电体的电学性质发生变化。 多通道电学测量系统记录该 变化， 通过将采集得到的电学参数值和相应的晶体管单元对应， 并利用 诸如 Matlab 等处理软件进行绘图处理， 即可得到对外界环境机械信号 (如应力） 的传感和成像信息。
以上所述， 仅是本发明的较佳实施例而已， 并非对本发明作任何形 式上的限制。 任何熟悉本领域的技术人员， 在不脱离本发明技术方案范 围情况下， 都可利用上述揭示的方法和技术内容对本发明技术方案做出 许多可能的变动和修饰， 或修改为等同变化的等效实施例。 因此， 凡是 未脱离本发明技术方案的内容， 依据本发明的技术实质对以上实施例所 做的任何简单修改、 等同变化及修饰， 均仍属于本发明技术方案保护的 范围内。

Claims

权利要求
1、 一种晶体管阵列， 其特征在于， 包括基底以及共用该基底的若 干个晶体管单元， 所述晶体管单元包括：
位于所述基底上的底电极和底电极连出线；
所述底电极上的压电体， 所述压电体为压电材料；
所述压电体上的顶电极。
2、 根据权利要求 1 所述的晶体管阵列， 其特征在于， 所述晶体管 单元的压电体具有极化取向。
3、 根据权利要求 2所述的晶体管阵列， 其特征在于， 所述晶体管 单元的压电体的所述极化取向基本垂直与所述基底平面。
4、 根据权利要求 2或 3所述的晶体管阵列， 其特征在于， 所述晶 体管阵列中， 每个所述晶体管单元的压电体的所述极化方向基本相同。
5、根据权利要求 1-4任一项所述的晶体管阵列， 其特征在于， 所述 晶体管阵列的晶体管单元之间还包括柔性绝缘填充层， 所述柔性绝缘填 充层的上表面至少露出所述晶体管单元的顶电极。
6、 根据权利要求 5所述的晶体管阵列， 其特征在于， 所述晶体管 单元还包括顶电极连出线， 所述顶电极连出线用于将所述顶电极连出所 述晶体管阵列。
7、 根据权利要求 6所述的晶体管阵列， 其特征在于， 所述晶体管 阵列还包括封装层， 所述封装层位于所述柔性绝缘填充层上， 所述封装 层使所述晶体管单元裸露在所述柔性绝缘填充层上表面的部分被封装。
8、根据权利要求 1-7任一项所述的晶体管阵列， 其特征在于， 所述 晶体管单元的压电体为 ZnO、 GaN、 CdS、 InN、 InGaN、 CdTe、 CdSe 或 ZnSn03或锆钛酸铅的纳米线、 纳米棒或薄膜， 或者聚偏氟乙烯纳米 纤维。
9、 根据权利要求 8所述的晶体管阵列， 其特征在于， 所述压电体 为纳米线、 纳米棒或纳米纤维， 所述压电体的轴线方向基本垂直于底电 极或基底表面。
10、 根据权利要求 1-9任一项所述的晶体管阵列， 其特征在于， 所 述晶体管单元的横截面尺寸为 25平方微米或更小。
11、 根据权利要求 1-10任一项所述的晶体管阵列， 其特征在于， 所 述晶体管单元之间的距离为几微米至几毫米。
12、 根据权利要求 1-11任一项所述的晶体管阵列， 其特征在于， 所 述晶体管单元为轴线基本垂直于基底的圆柱形、 四棱柱、 六棱柱或不规 则柱形。
13、根据权利要求 1-12任一项所述的晶体管阵列， 其特征在于， 每 个所述晶体管单元的压电体采用相同的压电材料。
14、根据权利要求 1-13任一项所述的晶体管阵列， 其特征在于， 包 括若干个相同的所述晶体管单元。
15、根据权利要求 1-14任一项所述的晶体管阵列， 其特征在于， 所 述基底为柔性或硬性基底。
16、根据权利要求 1-15任一项所述的晶体管阵列， 其特征在于， 所 述晶体管单元的顶电极和 /或底电极采用导电氧化物、石墨烯或银纳米线 涂层中的一种， 或者采用金、 银、 铂、 铝、 镍、 铜、 钛、 烙、 硒或其合 金中的一种。
17、 一种晶体管阵列制备方法， 其特征在于， 包括：
提供基底；
在所述基底上制备包括多个底电极的底电极阵列， 以及底电极连出 线；
在所述底电极上制备压电体， 多个所述压电体形成压电体阵列； 在所述压电体上制备顶电极， 多个所述顶电极形成顶电极阵列。
18、 根据权利要求 17所述的晶体管阵列的制备方法， 其特征在于， 在所述底电极上制备压电体歩骤之后还包括歩骤：
在所述压电体之间制备柔性绝缘填充层， 所述压电体的顶部暴露在 所述柔性绝缘填充层外。
19、 根据权利要求 18所述的晶体管阵列的制备方法， 其特征在于， 所述在所述压电体上制备顶电极步骤为：
在所述压电体和所述柔性绝缘填充层上制备所述顶电极和顶电极 连出线， 其中， 所述顶电极制备在所述压电体上， 顶电极连出线与所述 顶电极电连接。
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US20150357374A1 (en) 2015-12-10
JP2016503967A (ja) 2016-02-08
US10644063B2 (en) 2020-05-05
EP2945200B1 (en) 2019-02-27
EP2945200A1 (en) 2015-11-18
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CN103779272B (zh) 2017-06-20

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