WO2014121668A1 - 氮化物高压器件及其制造方法 - Google Patents

氮化物高压器件及其制造方法 Download PDF

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WO2014121668A1
WO2014121668A1 PCT/CN2014/070148 CN2014070148W WO2014121668A1 WO 2014121668 A1 WO2014121668 A1 WO 2014121668A1 CN 2014070148 W CN2014070148 W CN 2014070148W WO 2014121668 A1 WO2014121668 A1 WO 2014121668A1
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nitride
layer
silicon substrate
voltage device
voltage
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French (fr)
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程凯
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Enkris Semiconductor Inc
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Enkris Semiconductor Inc
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Priority to KR1020157024360A priority Critical patent/KR101770489B1/ko
Priority to EP14749251.6A priority patent/EP2955755B1/en
Priority to SG11201506228TA priority patent/SG11201506228TA/en
Priority to JP2015556382A priority patent/JP6182794B2/ja
Publication of WO2014121668A1 publication Critical patent/WO2014121668A1/zh
Priority to US14/820,552 priority patent/US9455315B2/en
Anticipated expiration legal-status Critical
Priority to US15/247,044 priority patent/US9831333B2/en
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3216—Nitrides
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H10P50/646—Chemical etching of Group III-V materials

Definitions

  • the present invention relates to the field of microelectronics, and more particularly to a nitride high voltage device and a method of fabricating the same.
  • Wide bandgap compound semiconductor materials show great potential in high frequency, high temperature, high power, etc. due to their large forbidden band width, high electron saturation drift speed, high breakdown field strength, and good thermal conductivity. Nitride high-voltage devices are attracting the attention of many researchers around the world for their superior performance and great development potential.
  • the technology for growing nitride high-voltage devices by growing nitride epitaxial layers on the silicon substrate is becoming more mature because of its lower cost and greatly promotes the marketization of nitride high-voltage devices.
  • the silicon material itself has electrical conductivity and the breakdown electric field is relatively small, under the condition of high voltage, the silicon substrate is equivalent to a low resistance region, which cannot effectively prevent leakage of the device; when the applied voltage is high enough to reach the critical breakdown electric field of silicon
  • the bottom of the silicon village first breaks down, which in turn causes longitudinal breakdown of the epitaxial layer, so that the breakdown of the silicon nitride high voltage device is basically through the longitudinal breakdown of the silicon substrate, especially when the silicon village bottom is grounded. Reduce it by half compared to when it is not grounded.
  • the breakdown voltage of the silicon nitride high-voltage device is mainly related to the thickness of the epitaxial layer
  • the thickness of the silicon nitride epitaxial layer is generally small, for example, about 2 ⁇ m to 7 ⁇ m, so the nitrogen on the silicon substrate
  • the highest breakdown voltage of a high voltage device is typically no more than 2000V, which is much less than the highest breakdown voltage of a nitride high voltage device on a sapphire or silicon carbide substrate.
  • the thickness of the nitride epitaxial layer In order to increase the breakdown voltage of the silicon nitride high voltage device, it can be realized by increasing the thickness of the nitride epitaxial layer and increasing the withstand voltage of the silicon substrate.
  • Current growth techniques can solve the large lattice mismatch and thermal mismatch between silicon materials and nitrides, but the thickness of the nitride epitaxial layer grown is greatly limited, generally about 2 ⁇ m to 4 ⁇ . ⁇ , grow thicker epitaxial layer will The need for more raw materials and longer growth time will greatly increase the cost and reduce the productivity.
  • As the thickness increases a large number of defects including dislocations exist in the epitaxial layer. As the operating voltage increases, the leakage current also increases. increase.
  • stripping off the silicon substrate can eliminate the impact of the silicon substrate on the breakdown voltage and greatly increase the breakdown voltage of the device, but the thickness of the silicon substrate used to grow the nitride is several hundred microns or even more than one. Millimeters, the bottom stripping process on the back is relatively cumbersome, so it is necessary to consider other ways to improve the pressure resistance of the silicon village.
  • the applied high voltage is generally applied to the drain of the device, and the gate-drain region is the main tolerant region of the high voltage. Especially in the case of the ground connection of the silicon village, the voltage mainly falls between the drain and the bottom electrode of the silicon village. Silicon Village is also the easiest to break through in this area. Therefore, in view of the above technical problems, it is necessary to provide a nitride high voltage device and a method of manufacturing the same.
  • the nitride epitaxial layer having a higher breakdown electric field is isolated from the easily-breakable silicon substrate, or further added.
  • Other high-critical electric field materials can avoid the premature breakdown of the silicon substrate in this area, which can greatly increase the breakdown voltage of the device.
  • oxidation of the silicon material in the isolation region to form a silicon dioxide layer can further increase the breakdown voltage of the device.
  • the isolation region can be realized by wet etching and/or dry etching.
  • a selective etching process and/or a dry etching process can be used to improve the lateral side of the silicon village. Corrosion/etching speed to improve isolation.
  • the device is less prone to longitudinal breakdown, mainly through lateral breakdown of the nitride epitaxial layer, so the thickness of the nitride epitaxial layer does not need to grow too thick, and the thin epitaxial layer can also achieve high impact.
  • the voltage is applied, and the opening etching process of the front nitride epitaxial layer is also easy to control when the thickness of the epitaxial layer is thin, which greatly improves the production efficiency and process controllability.
  • the area between the gate and the drain is the main source of high voltage
  • the load zone, the breakdown mainly occurs on the bottom of the silicon village in this area.
  • Another object of the present invention is to provide a method for fabricating the above device.
  • the opening position can be performed on the outside of the drain electrode of the device, and can be performed on the inner side of the drain electrode.
  • the outer side of the source electrode of the device can also be performed on the inner side of the source electrode.
  • the nitride epitaxial layer is etched first until the bottom layer of the silicon village, and then the selective etching process and/or the dry etching process are continued, according to the process and the device.
  • the design requires the formation of a structurally controllable spatial isolation area, such as a square groove, a trapezoidal groove, an arcuate groove or a U-shaped groove.
  • a nitride high voltage device comprising:
  • nitride buffer layer on the nitride nucleation layer
  • nitride channel layer on the nitride buffer layer
  • a source and a drain in contact with the nitride channel layer and a gate between the source and the drain;
  • one or more partial spatial isolation regions are disposed between the nitride nucleation layer below the region between the gate and the drain and the silicon substrate.
  • the partial spatial isolation region is filled with a high voltage resistant filler.
  • the high voltage resistant filler comprises a combination of one or more of A1203, SiO2, SiNx, AlN, diamond.
  • the partial spatial isolation region is a square groove, a trapezoidal groove, an arc groove or a U-shaped groove.
  • the inner wall of the partial space isolation region is formed with a high pressure resistant silicon dioxide layer by oxidation treatment.
  • an insulating high voltage withstand layer crossing the entire silicon substrate is disposed under the partial space isolation region, and the insulating high voltage withstand layer is one or more of oxides and nitrides. Combination of species.
  • a nitride barrier layer is provided on the nitride channel layer, and a two-dimensional electron gas is formed at an interface between the nitride channel layer and the nitride barrier layer.
  • a dielectric layer is further provided on the nitride barrier layer.
  • the dielectric layer is a combination of one or more of SiN, SiO 2 , SiON, A1203, HfO 2, HfAlOx.
  • a nitride layer is provided on the nitride barrier layer.
  • an A1N intercalation layer is provided between the nitride barrier layer and the nitride channel layer.
  • an AlGaN back barrier layer is provided between the nitride buffer layer and the nitride channel layer.
  • a method for manufacturing a nitride high voltage device comprising:
  • One or more local spatial isolation regions are formed between the nitride nucleation layer below the region between the gate and the drain and the silicon substrate.
  • the method for preparing the partial spatial isolation region is a dry method Etching and/or wet etching.
  • the method further includes:
  • a local spatial isolation region is formed by etching and/or etching from the middle to the sides.
  • a partial spatial isolation region is formed by partially removing a portion of the silicon substrate below the nitride epitaxial layer between the gate and the drain, and the region is penetrated by the nitride epitaxial layer having a higher electric field and the silicon bottom liquid which is easily broken down. Isolation, avoiding the breakdown that may be caused by the silicon substrate, thereby realizing a device that can withstand high breakdown voltage;
  • 1-A and 1-B are processes for forming a local spatial isolation region between a nitride epitaxial layer and a silicon substrate under the region between the gate and the drain of the nitride HEMT device of the first embodiment;
  • FIGS. 2A and 2B are schematic diagrams showing the structure of a HEMT device for forming a local spatial isolation region by etching an opening on a nitride epitaxial layer on the inner side of the drain electrode according to the second embodiment of the present invention
  • 3 is a plurality of nitride epitaxial layers on the inner side of the drain electrode according to the third embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing the structure of a HEMT device forming a local spatial isolation region by opening etching;
  • FIG. 4 is a fourth embodiment of the present invention, introducing a high voltage resistant silicon dioxide layer in a local space isolation region between a nitride epitaxial layer and a silicon substrate; Schematic diagram of HEMT device structure;
  • FIG. 5 is a schematic structural view of a HEMT device in which an insulating high voltage withstand layer is introduced under a partial space isolation region between a nitride epitaxial layer and a silicon substrate according to a fifth embodiment of the present invention
  • FIG. 6 is a schematic structural view of a HEMT device incorporating a high voltage filler in a local space isolation region between a nitride epitaxial layer and a silicon substrate according to a sixth embodiment of the present invention
  • FIG. 7 is a schematic structural view of a HEMT device in which a partial spatial isolation region between a nitride epitaxial layer and a silicon substrate is a ladder structure according to a seventh embodiment of the present invention
  • FIG. 8 is a schematic structural view of a HEMT device in which an edge of a local space isolation region between a nitride epitaxial layer and a silicon substrate is an arc structure according to an eighth embodiment of the present invention
  • FIG. 9 is a schematic structural view of a nitride MOSFET device to which the present invention is applied in a ninth embodiment of the present invention, wherein a local spatial isolation region is formed between a nitride nucleation layer below a region between a gate and a drain and a silicon substrate; ;
  • FIG. 10 is a schematic structural view of a nitride MESFET device to which the present invention is applied in a tenth embodiment of the present invention, wherein a local spatial isolation region is formed between a nitride nucleation layer under the region between the gate and the drain and a silicon substrate. ;
  • FIG. 11 is a schematic structural view of a nitride HEMT device for growing a GaN layer on a barrier layer according to an eleventh embodiment of the present invention
  • FIG. 12 is a schematic structural view of a nitride HEMT device in which an A1N interposer is introduced between a barrier layer and a channel layer according to a twelfth embodiment of the present invention
  • FIG. 13 is a schematic structural view of a nitride HEMT device in which an AlGaN back barrier layer is interposed between a buffer layer and a channel layer according to a thirteenth embodiment of the present invention
  • FIG. 14 is a schematic view showing a structure of a nitride HEMT device in which a plurality of holes are etched in a drain region to form a plurality of partial spatial isolation regions, and an insulating high voltage withstand layer is inserted immediately below the fourteenth embodiment of the present invention;
  • 15-A and 15-B are process flows for forming a partial spatial isolation region between a nitride epitaxial layer and a silicon substrate under the region between the source and the drain of the nitride HEMT device according to the fifteenth embodiment of the present invention.
  • schematic diagram; 16-A and 16-B are schematic diagrams showing the structure of a HEMT device for forming a local spatial isolation region by etching an opening on a nitride epitaxial layer on the drain end and the gate inside of the sixteenth embodiment of the present invention.
  • a nitride high voltage device of the present invention includes:
  • nitride buffer layer on the nitride nucleation layer
  • nitride channel layer on the nitride buffer layer
  • a source and a drain in contact with the nitride channel layer and a gate between the source and the drain;
  • one or more partial spatial isolation regions are provided between the nitride nucleation layer below the region between the gate and the drain and the silicon substrate.
  • a method for manufacturing a nitride high voltage device includes:
  • the invention separates the silicon substrate from the nitride epitaxial layer capable of withstanding high voltage by removing a part of the silicon substrate under the nitride epitaxial layer between the gate and the drain, thereby avoiding longitudinal breakdown which may be caused by the silicon substrate, thereby A device that can withstand high breakdown voltages is realized.
  • FIGS. 1A and 1B are schematic diagrams showing a process flow for forming a local spatial isolation region between a nitride epitaxial layer and a silicon substrate under the region between the gate and the drain of the nitride HEMT device according to the first embodiment of the present invention. .
  • the first layer is the silicon village bottom 1;
  • a nitride nucleation layer 2 and a nitride buffer layer 3 are epitaxially grown on the silicon substrate 1, and the nitride buffer layer 3 includes GaN or AlN or other nitrides to match the substrate material and the high quality epitaxial gallium nitride layer.
  • a nitride channel layer 4 is grown on the nitride buffer layer 3, and the nitride channel layer 4 may include an undoped GaN layer;
  • a nitride barrier layer 5 is grown on the nitride channel layer 4, the nitride barrier layer 5 comprises AlGaN or other nitride, and the nitride channel layer 4 and the nitride barrier layer 5 together form a semiconductor heterojunction structure. Forming a high concentration two-dimensional electron gas at the interface, and generating a conductive channel at the heterojunction interface of the GaN channel layer;
  • one or more partial spatial isolation regions 11 are provided between the nitride nucleation layer below the region between the gate 8 and the drain 7 and the silicon substrate.
  • the nitrogen outside the drain 7 is etched. Opening a hole in the epitaxial layer up to the silicon substrate 1 to form an etch hole 10, as shown in FIG. 1-A; then continuing to dry-gate and/or selective wet etching between the gate 8 and the drain 7
  • the silicon substrate 1 under the regional nitride epitaxial layer is locally selectively etched or etched to form a local spatial isolation region 11 between the nitride epitaxial layer and the silicon substrate in the region, as shown in FIG. 1-B.
  • the length and height of the local empty separation region 11 in the present invention can be adjusted in accordance with the required withstand voltage.
  • the local spatial isolation region 11 formed between the nitride epitaxial layer under the region between the gate 8 and the drain 7 and the silicon substrate realizes a nitride epitaxial layer region with a higher breakdown electric field between the gate and the drain.
  • the partial space separation between the easily-transparent conductive silicon substrate blocks the conductive path and breakdown path through the silicon substrate, so that the breakdown of the device is no longer through the longitudinal breakdown of the silicon substrate, but only It is a lateral breakdown on the nitride epitaxial layer. Since the breakdown electric field of the nitride epitaxial layer is high and the gate-to-drain spacing is generally large, the breakdown voltage of the device is greatly increased, and even if the ground is grounded, the breakdown voltage of the device is not affected.
  • FIGS. 2A and 2B are schematic views showing the structure of a HEMT device in which an open-hole etch is formed on a nitride epitaxial layer on the inner side of the drain electrode to form a local spatial isolation region in the second embodiment of the present invention.
  • a nitride epitaxial layer is formed on the nitride epitaxial layer on the inner side of the drain electrode 7 to form an etch hole 10, and then etched/etched from the middle to the both sides to form a nitride epitaxial layer and a silicon substrate at the gate 8 and drain 7 regions.
  • the method can increase the etching range and shorten the process time, wherein the etching hole 10 on the inner side of the drain 7 does not need to be 4 inches, and the influence on the two-dimensional electron gas is not large, such as Figure 2-B shows.
  • FIG 3 is a schematic structural view of a HEMT device in which a plurality of openings are etched to form a local spatial isolation region on a nitride epitaxial layer on the inner side of the drain electrode according to the third embodiment of the present invention.
  • the embodiment is provided with a plurality of etching holes 10, and the plurality of etching holes 10 may be arranged in a straight line or may be arranged in other forms. This method can further increase the corrosion range and shorten the length. Process time while reducing the impact on device performance.
  • FIG. 4 is a schematic structural view of a HEMT device incorporating a high voltage resistant silicon dioxide layer in a local space isolation region between a nitride epitaxial layer and a silicon substrate according to a fourth embodiment of the present invention.
  • a thicker and high-voltage-resistant silicon dioxide layer 12 can be formed in the silicon substrate of the local spatial isolation region between the nitride epitaxial layer and the silicon substrate 1 by an oxidation treatment, compared to pure spatial isolation.
  • the isolation effect can be further improved, the breakdown voltage of the device can be increased, and the thickness of the oxide layer can be adjusted according to the required withstand voltage and a specific process.
  • the oxidation treatment method is thermal oxidation, plasma oxidation or other oxidation treatment.
  • FIG. 5 is a schematic structural view of a HEMT device in which an insulating high voltage withstand layer is introduced under a partial space isolation region between a nitride epitaxial layer and a silicon substrate according to a fifth embodiment of the present invention.
  • An insulating high voltage withstand layer 17 is disposed under the partial space isolation region 11 across the entire silicon substrate 1, and the insulating high voltage withstand layer 17 is adjacent to the local space isolation region 11 and traverses the entire silicon substrate 1 .
  • the longitudinal breakdown voltage of the device can be further increased.
  • the breakdown voltage of the insulating high voltage withstand layer is relatively high, and may be a combination of one or more of oxides and nitrides.
  • FIG. 6 is a schematic structural view of a HEMT device incorporating a high voltage filler in a local space isolation region between a nitride epitaxial layer and a silicon substrate according to a sixth embodiment of the present invention.
  • a high voltage resistant filler 13 such as one or more of A1203, SiO2, SiNx, A1N, diamond, may be introduced into the local spatial isolation region.
  • a material having a high critical electric field such as a combination of a material having a high critical electric field and a high thermal conductivity, such as A1N and diamond, to improve the insulation isolation effect and increase the breakdown voltage of the device.
  • FIG. 7 is a schematic structural view of a HEMT device in which a partial spatial isolation region between a nitride epitaxial layer and a silicon substrate is a trapezoidal structure according to a seventh embodiment of the present invention.
  • the partial spatial isolation region 11 between the nitride epitaxial layer and the silicon substrate is set as a trapezoidal structure, and the silicon substrate can be enhanced on the basis of the isolation. Support for the epitaxial layer.
  • FIG. 8 is a schematic structural view of a HEMT device in which an edge of a local space isolation region between a nitride epitaxial layer and a silicon substrate is curved in an eighth embodiment of the present invention.
  • the local space isolation area is set to an edge with an arc structure, and the process is relatively easy to implement.
  • Figure 9 is a schematic view showing the structure of a nitride MOSFET device to which the present invention is applied in a ninth embodiment, in which a local space isolation region is formed between a nitride nucleation layer under the region between the gate and the drain and a silicon substrate.
  • the nitride channel layer region under the source 6 and the drain 7 is an n-type heavily doped region, generally doped with silicon, and the lower region of the gate 8 is p-type lightly doped, generally doped.
  • the dielectric layer under the gate metal is generally SiO 2 , SiN, A1N, A1203 or other insulating dielectric layer.
  • Figure 10 is a schematic view showing the structure of a nitride MESFET device to which the present invention is applied in a tenth embodiment, wherein a local spatial isolation region is formed between a nitride nucleation layer below the region between the gate and the drain and the silicon substrate.
  • the nitride channel layer 4 is generally n-type lightly doped
  • the nitride channel layer 4 region under the source 6 and the drain 7 is n-type heavily doped
  • the gate 8 is Schottky knot.
  • Fig. 11 is a view showing the structure of a nitride HEMT device in which a GaN layer is grown on a barrier layer in an eleventh embodiment of the present invention.
  • a nitride layer 14 is provided on the nitride barrier layer 5, and the barrier layer is made of an AlGaN material. Due to the defects on the surface of the AlGaN barrier layer material and the high surface state density, more than 4 electrons are trapped, which will affect the two-dimensional electron gas in the channel and reduce device characteristics and reliability.
  • the nitride layer 14 is GaN.
  • Fig. 12 is a view showing the structure of a nitride HEMT device in which an A1N insertion layer is introduced between a barrier layer and a channel layer in a twelfth embodiment of the present invention.
  • an A1N insertion layer 15 is provided between the nitride barrier layer 5 and the nitride channel layer 4, and the barrier layer is made of an AlGaN material. Because the forbidden band width of A1N is very high, the electrons can be more effectively confined in the heterojunction well, and the concentration of the two-dimensional electron gas is increased. The A1N insertion layer also isolates the conductive channel from the AlGaN barrier layer, reducing The scattering effect of the barrier layer on electrons increases the mobility of the electrons and improves the overall characteristics of the device.
  • Figure 13 is a view showing the structure of a nitride HEMT device in which an AlGaN back barrier layer is interposed between a buffer layer and a channel layer in a thirteenth embodiment of the present invention.
  • the channel electrons in the channel enter the nitride buffer layer 3, especially in short-channel devices, which makes the gate-to-channel electrons relatively weak, and short channels appear. Effect; plus more defects and impurities in the buffer layer, will affect the two-dimensional electron gas in the channel, such as the occurrence of current collapse.
  • the channel electrons can be isolated from the buffer layer, and the two-dimensional electron gas can be effectively confined to the channel. In the layer, the short channel effect and current collapse effect are improved.
  • FIG. 14 shows a nitride HEMT device in which a plurality of holes are etched in a drain region to form a plurality of partial spatial isolation regions, and an insulating high voltage withstand layer is inserted immediately below the fourteenth embodiment of the present invention.
  • a plurality of etch holes 10 are etched in the drain 7 region, a plurality of partial spatial isolation regions 11 are formed between the nitride epitaxial layer and the silicon substrate, and an insulating high voltage withstand layer is inserted immediately below 17 (such as silicon dioxide layer, etc.), this spatial isolation region combined with the structure of the high voltage withstand layer can not only improve the lateral withstand voltage of the silicon substrate, but also increase the longitudinal withstand voltage of the silicon substrate, thereby improving the total device. Breakdown voltage. Compared with forming a large local spatial isolation region in the drain region, this structure can greatly improve the etching/etching process efficiency of the spatial isolation region, and the silicon substrate between each isolation region can provide support to avoid isolation. Excessive area causes the device to collapse; it is also possible to oxidize the silicon substrate in these multiple spatial isolation regions, or to fill the high voltage resistant material to further increase the breakdown voltage of the device.
  • 15-A and 15-B are process flows for forming a partial spatial isolation region between a nitride epitaxial layer and a silicon substrate under the region between the source and the drain of the nitride HEMT device according to the fifteenth embodiment of the present invention.
  • one or more partial spatial isolation regions 11 are disposed between the nitride nucleation layer below the region between the source 6 and the drain 7 and the silicon substrate, firstly etched outside the source 6 Opening a hole in the nitride epitaxial layer up to the silicon substrate 1 to form an etched hole 10, as shown in FIG. 15-A; and then continuing to dry and/or selectively wet etch the source 6 and the drain 7
  • the silicon substrate 1 under the inter-region nitride epitaxial layer is locally selectively etched or etched to form a local spatial isolation region 11 between the nitride epitaxial layer and the silicon substrate in the region, as shown in Fig. 15-B.
  • the length and height of the partial space isolation region 11 in the present invention can be adjusted in accordance with the required withstand voltage.
  • 16-A and 16-B are schematic views showing the structure of a HEMT device in which a hole is etched to form a local spatial isolation region on a nitride epitaxial layer on the inner side of the source electrode according to the sixteenth embodiment of the present invention.
  • a nitride epitaxial layer on the inner side of the source 6 is etched to form an etched hole 10, and then etched/etched from the middle to the both sides to form a source 6 and a drain 7 region nitride epitaxial layer and a silicon substrate.
  • a local space isolation region 11 between them as shown in Figure 16-A.
  • the method can increase the etching range and shorten the process time, wherein the etching holes 10 on the inner side of the source 6 and the gate 8 do not need to be 4 ,, which affects the two-dimensional electron gas.
  • the source 6 and the gate 8 may further be provided with a plurality of etching holes.
  • the plurality of etching holes may be arranged in a straight line, or may be arranged in other forms, which may further increase the corrosion range and shorten the process. Time while reducing the impact on device performance.
  • the structure or device manufacturing process of the nitride channel layer or the barrier layer on the silicon substrate can also be changed, and the silicon-based nitride high-voltage device enhancement device can also be realized, such as using a fluoride ion bombardment gate.
  • the material region under the metal can form an enhanced device or the like.
  • the nitride high voltage device of the present invention and the method of manufacturing the same have the following beneficial effects:
  • a partial spatial isolation region is formed by partially removing a portion of the silicon substrate below the nitride epitaxial layer between the gate and the drain, and the region is penetrated by the nitride epitaxial layer having a higher electric field and the silicon bottom liquid which is easily broken down. Isolation, avoiding the breakdown that may be caused by the silicon substrate, thereby realizing a device that can withstand high breakdown voltage;

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Abstract

一种氮化物高压器件及其制造方法，氮化物高压器件包括：硅衬底（1）；位于硅衬底上的氮化物成核层（2）；位于氮化物成核层上的氮化物缓冲层（3）；位于氮化物缓冲层上的氮化物沟道层（4）；与氮化物沟道层相接触的源极（6）和漏极（7）以及位于源极和漏极之间的栅极（8）；其中，栅极和漏极之间区域下方的氮化物成核层与硅衬底之间设有一个或多个局部空间隔离区域（11）。通过去除栅极和漏极之间氮化物外延层下方的部分硅衬底，将硅衬底与能够承受高电压的氮化物外延层隔离，避免硅衬底可能引起的纵向击穿，从而实现可以耐高击穿电压的器件。

Description

氮化物高压器件及其制造方法 本申请要求于 2013 年 2 月 7 日提交中国专利局、 申请号为 201310049853.X, 发明名称为"氮化物高压器件及其制造方法"的中国专利 申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及微电子技术领域， 特别是涉及一种氮化物高压器件及其制 造方法。
背景技术
宽禁带化合物半导体材料由于具有禁带宽度大、电子饱和漂移速度高、 击穿场强高、 导热性能好等特点， 在高频、 高温、 大功率等领域显示出极 大的潜力， 尤其是氮化物高压器件更以其优越的性能和巨大的发展潜力而 备受全世界众多研究者的关注。
目前在硅村底上生长氮化物外延层制作氮化物高压器件的技术正曰趋 成熟， 因为其成本较低， 极大的促进了氮化物高压器件的市场化。
由于硅材料本身具有导电性且击穿电场比较小，在外加高电压条件下， 硅村底相当于低阻区， 不能有效阻止器件漏电； 当外加电压足够高， 达到 硅的临界击穿电场时硅村底首先击穿， 继而引起外延层纵向击穿， 使得硅 村底氮化物高压器件的击穿基本上都是通过硅村底的纵向击穿， 尤其是当 硅村底接地时击穿电压相比未接地时要减少一半。 虽然硅村底氮化物高压 器件的击穿电压主要跟外延层的厚度有关， 但硅村底氮化物外延层厚度一 般比较小， 比如说 2 μ ιη至 7 μ ιη左右，所以硅村底上氮化物高压器件的 最高击穿电压一般不超过 2000V, 远远小于蓝宝石或碳化硅村底上的氮化 物高压器件的最高击穿电压。
为了提高硅村底氮化物高压器件的击穿电压可以通过增加氮化物外延 层的厚度和提高硅村底的耐压性来实现。 目前的生长技术可以解决硅材料 和氮化物之间巨大的晶格失配和热失配， 但其生长的氮化物外延层厚度受 到极大的限制，一般来说大约在 2 μ ιη至 4 μ ιη左右，生长更厚的外延层会 需要更多的原材料、 更长的生长时间， 会大大提高成本、 降低产能， 并且 随着厚度的增加， 外延层内存在包括位错在内的大量缺陷， 随着工作电压 的提高漏电流也会增加。
人们也发现剥离掉硅村底可以消除硅村底对击穿电压的影响， 极大的 提高器件的击穿电压， 但是用于生长氮化物的硅村底的厚度都是几百微米 甚至超过 1个毫米， 背部的村底剥离工艺相对比较繁瑣， 因此需要考虑通 过其他方式来提高硅村底的耐压性。
外加高电压一般是加载在器件的漏极上， 栅漏区域是高电压的主要耐 受区域， 尤其是在硅村底接地情况下， 电压主要落在漏极和硅村底电极之 间区域， 硅村底也是在此区域最容易击穿。 因此， 针对上述技术问题， 有 必要提供一种氮化物高压器件及其制造方法。
发明内容
有鉴于此， 如果能够去除栅漏区域氮化物外延层下方的部分硅村底， 将该区域击穿电场较高的氮化物外延层与容易击穿的硅村底用空气进行隔 离，或者进一步添加其他高临界电场材料，避免此区域硅村底的过早击穿， 就可以大幅提高器件的击穿电压。 另外， 对隔离区域内的硅材料进行氧化 形成二氧化硅层也可以进一步提高器件击穿电压。 隔离区域可以通过湿法 腐蚀和 \或干法刻蚀的方式来实现， 为了实现结构可控的空间隔离区域， 可 以使用选择性腐蚀工艺和 /或干法刻蚀工艺，提高硅村底侧向的腐蚀 /刻蚀速 度， 提高隔离效果。 形成此空间隔离区域后， 器件不容易发生纵向击穿， 主要是通过氮化物外延层的横向击穿， 因此氮化物外延层的厚度不需要生 长太厚， 较薄的外延层也可以实现高击穿电压， 并且在外延层厚度^艮薄的 情况下正面氮化物外延层开孔刻蚀工艺也容易控制， 大大提高了生产效率 及工艺可控性。
本发明的目的在于提供一种通过局部去除栅极和漏极之间氮化物外延 层下方的部分硅村底， 将该区域击穿电场较高的氮化物外延层与容易击穿 的硅村底用空气等物质进行隔离， 避免通过硅村底可能引起的击穿， 从而 实现可以耐高击穿电压的器件。 栅极和漏极之间的区域是高电压的主要承 载区， 击穿主要发生在这个区域的硅村底上。 通过选择性腐蚀和 /或刻蚀工 艺选择性去除栅极和漏极之间氮化物外延层下方的部分硅村底， 实现栅极 和漏极之间可承受高电压的氮化物外延层区与容易击穿的导电硅村底之间 的局部空间隔离， 阻断通过硅村底的导电通路和击穿路径， 使得器件的击 穿不再是通过硅村底的击穿， 而只能是在氮化物外延层上的横向击穿。 因 为氮化物外延层的击穿电场较高且栅漏间距一般比较大， 所以器件的击穿 电压大幅提高， 即使村底接地也不影响器件的击穿电压， 还可以在此隔离 区域内填充击穿电场更高的材料来提高器件的击穿电压， 对隔离区域内的 硅材料进行氧化形成二氧化硅层也可以进一步提高器件击穿电压。
本发明的另一目的在于还提出了上述器件的制造方法， 通过在氮化物 外延层上方开孔， 开孔位置可以在器件漏端电极的外侧进行， 可以在漏端 电极的内侧进行， 可以在器件源端电极的外侧进行， 也可以在源端电极的 内侧进行， 先刻蚀掉氮化物外延层直至硅村底层， 再继续用选择性腐蚀工 艺和 /或干法刻蚀工艺，根据工艺及器件设计要求形成结构可控的空间隔离 区域， 如方形槽、 梯形槽、 弧形槽或 U形槽等。 为了进一步提高器件的击 穿电压，还可以在此隔离区域内填充击穿电场更高的材料和 /或对隔离区域 内的硅材料进行氧化形成二氧化硅层。
为了实现上述目的， 本发明实施例提供的技术方案如下：
一种氮化物高压器件， 所述氮化物高压器件包括：
硅村底；
位于所述硅村底上的氮化物成核层；
位于所述氮化物成核层上的氮化物緩沖层；
位于所述氮化物緩沖层上的氮化物沟道层；
与所述氮化物沟道层相接触的源极和漏极以及位于所述源极和漏极之 间的栅极；
其中， 所述栅极和漏极之间区域下方的氮化物成核层与硅村底之间设 有一个或多个局部空间隔离区域。
作为本发明的进一步改进， 所述局部空间隔离区域内填充有耐高电压 填充物。 作为本发明的进一步改进， 所述耐高电压填充物包括 A1203、 Si02、 SiNx、 A1N、 金刚石中的一种或多种的组合。
作为本发明的进一步改进，所述局部空间隔离区域为方形槽、梯形槽、 弧形槽或 U形槽。
作为本发明的进一步改进， 所述局部空间隔离区域的内壁上通过氧化 处理形成有耐高压的二氧化硅层。
作为本发明的进一步改进， 所述局部空间隔离区域下方设有横穿整个 硅村底的绝缘高电压耐受层， 所述绝缘高电压耐受层为氧化物、 氮化物中 的一种或多种的组合。
作为本发明的进一步改进， 所述氮化物沟道层上设有氮化物势垒层， 在氮化物沟道层和氮化物势垒层的界面处形成有二维电子气。
作为本发明的进一步改进， 所述氮化物势垒层上还设有介质层。
作为本发明的进一步改进， 所述介质层为 SiN、 Si02、 SiON、 A1203、 Hf02、 HfAlOx中的一种或多种的组合。
作为本发明的进一步改进， 所述氮化物势垒层上设有氮化物冒层。 作为本发明的进一步改进， 所述氮化物势垒层和氮化物沟道层之间设 有 A1N插入层。
作为本发明的进一步改进， 所述氮化物緩沖层和氮化物沟道层之间设 有 AlGaN背势垒层。
相应地， 一种氮化物高压器件的制造方法， 所述方法包括：
提供一硅村底；
在所述硅村底上形成氮化物成核层；
在所述氮化物成核层上形成氮化物緩沖层；
在所述氮化物緩沖层上形成氮化物沟道层；
在所述氮化物沟道层上形成源极和漏极以及位于源极和漏极之间的栅 极；
在所述栅极和漏极之间区域下方的氮化物成核层与硅村底之间形成一 个或多个局部空间隔离区域。
作为本发明的进一步改进， 所述局部空间隔离区域的制备方法为干法 刻蚀和 /或湿法腐蚀。
作为本发明的进一步改进， 所述方法还包括：
在漏极和栅极之间和 /或漏极外侧和 /或源极和栅极之间和 /或源极外侧 的氮化物外延层上开孔刻蚀， 形成刻蚀孔， 通过刻蚀孔从中间向两侧腐蚀 和 /或刻蚀形成局部空间隔离区域。
本发明的有益效果是：
通过局部去除栅极和漏极之间氮化物外延层下方的部分硅村底形成局 部空间隔离区域， 将该区域击穿电场较高的氮化物外延层与容易击穿的硅 村底用空气进行隔离， 避免通过硅村底可能引起的击穿， 从而实现可以耐 高击穿电压的器件；
在局部空间隔离区域内填充击穿电场更高的材料来提高器件的击穿电 压， 对局部空间隔离区域内的硅材料进行氧化形成二氧化硅层可以进一步 提高器件击穿电压；
在氮化物外延层上方开孔， 先刻蚀掉氮化物外延层直至硅村底层， 再 继续用选择性腐蚀工艺和 /或干法刻蚀工艺， 整个工艺容易控制， 大大提高 了生产效率及工艺可控性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对 实施例或现有技术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图仅仅是本发明中记载的一些实施例， 对于本领域普通技 术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其 他的附图。
图 1-A和 1-B为第一实施方式在氮化物 HEMT器件的栅极和漏极之间 区域下方的氮化物外延层与硅村底之间形成局部空间隔离区域的工艺过 程；
图 2-A和 2-B为本发明第二实施方式在漏端电极内侧的氮化物外延层 上一个开孔刻蚀形成局部空间隔离区域的 HEMT器件结构示意图；
图 3为本发明第三实施方式在在漏端电极内侧的氮化物外延层上多个
+ 开孔刻蚀形成局部空间隔离区域的 HEMT器件结构示意图； 图 4为本发明第四实施方式在氮化物外延层与硅村底之间的局部空间 隔离区域内引入耐高电压二氧化硅层的 HEMT器件结构示意图；
图 5为本发明第五实施方式在氮化物外延层与硅村底之间的局部空间 隔离区域下方引入绝缘高电压耐受层的 HEMT器件结构示意图；
图 6为本发明第六实施方式在氮化物外延层与硅村底之间的局部空间 隔离区域内引入耐高电压填充物的 HEMT器件结构示意图；
图 7为本发明第七实施方式中氮化物外延层与硅村底之间的局部空间 隔离区域为梯形结构的 HEMT器件结构示意图；
图 8为本发明第八实施方式中氮化物外延层与硅村底之间的局部空间 隔离区域边缘为弧形结构的 HEMT器件结构示意图；
图 9为本发明第九实施方式中应用本发明的氮化物 MOSFET器件结构 示意图， 其中在栅极和漏极之间区域下方的氮化物成核层与硅村底之间形 成了局部空间隔离区域；
图 10为本发明第十实施方式中应用本发明的氮化物 MESFET器件结 构示意图， 其中在栅极和漏极之间区域下方的氮化物成核层与硅村底之间 形成了局部空间隔离区域；
图 11 为本发明第十一实施方式在势垒层上生长 GaN 冒层的氮化物 HEMT器件结构示意图；
图 12为本发明第十二实施方式在势垒层和沟道层之间引入 A1N插入 层的氮化物 HEMT器件结构示意图；
图 13为本发明第十三实施方式在緩沖层和沟道层之间插入 AlGaN背 势垒层的氮化物 HEMT器件结构示意图；
图 14 为本发明第十四实施方式在漏极区域刻蚀多个孔形成多个局部 空间隔离区域， 紧挨其下方插入绝缘高电压耐受层的氮化物 HEMT器件结 构示意图；
图 15-A和 15-B为本发明第十五实施方式在氮化物 HEMT器件的源极 和漏极之间区域下方的氮化物外延层与硅村底之间形成局部空间隔离区域 的工艺流程示意图； 图 16-A和 16-B为本发明第十六实施方式在漏端和栅极内侧的氮化物 外延层上一个开孔刻蚀形成局部空间隔离区域的 HEMT器件结构示意图。
具体实施方式
本发明的一种氮化物高压器件， 包括：
石圭村底；
位于硅村底上的氮化物成核层；
位于氮化物成核层上的氮化物緩沖层；
位于氮化物緩沖层上的氮化物沟道层；
与氮化物沟道层相接触的源极和漏极以及位于源极和漏极之间的栅 极；
其中， 栅极和漏极之间区域下方的氮化物成核层与硅村底之间设有一 个或多个局部空间隔离区域。
相应地， 一种氮化物高压器件的制造方法， 包括：
提供一硅村底；
在硅村底上形成氮化物成核层；
在氮化物成核层上形成氮化物緩沖层；
在氮化物緩沖层上形成氮化物沟道层；
在氮化物沟道层上形成源极和漏极以及位于源极和漏极之间的栅极； 在栅极和漏极之间区域下方的氮化物成核层与硅村底之间形成一个或 多个局部空间隔离区域。
本发明通过去除栅极和漏极之间氮化物外延层下方的部分硅村底， 将 硅村底与能够承受高电压的氮化物外延层隔离， 避免硅村底可能引起的纵 向击穿， 从而实现可以耐高击穿电压的器件。
以下将结合附图所示的具体实施方式对本发明进行详细描述。 但这些 实施方式并不限制本发明， 本领域的普通技术人员根据这些实施方式所做 出的结构、 方法、 或功能上的变换均包含在本发明的保护范围内。
此外， 在不同的实施例中可能使用重复的标号或标示。 这些重复仅为 了筒单清楚地叙述本发明， 不代表所讨论的不同实施例及 /或结构之间具有 任何关联性。
图 1-A和 1-B为本发明第一实施方式在氮化物 HEMT器件的栅极和漏 极之间区域下方的氮化物外延层与硅村底之间形成局部空间隔离区域的工 艺流程示意图。
其中第一层为硅村底 1;
在硅村底 1上外延生长氮化物成核层 2和氮化物緩沖层 3, 氮化物緩 沖层 3包括 GaN或 A1N或其他氮化物， 起到匹配村底材料和高质量外延 氮化镓层的作用；
在氮化物緩沖层 3上生长氮化物沟道层 4, 氮化物沟道层 4可包含非 掺杂 GaN层；
在氮化物沟道层 4上生长氮化物势垒层 5 ,氮化物势垒层 5包含 AlGaN 或其他氮化物， 氮化物沟道层 4和氮化物势垒层 5—起组成半导体异质结 结构， 在界面处形成高浓度二维电子气， 并在 GaN沟道层的异质结界面处 产生导电沟道；
在氮化物势垒层 5上沉积介质层 9对材料表面进行钝化保护， 介质层 为 SiN、 Si02、 SiON、 A1203、 Hf02、 HfAlOx中的一种或多种的组合； 在源极 6和漏极 7之间的区域， 介质层 9被刻蚀出凹槽， 然后沉积金 属形成栅极 8。
本发明中栅极 8和漏极 7之间区域下方的氮化物成核层与硅村底之间 设有一个或多个局部空间隔离区域 11 , 首先用刻蚀方法在漏极 7外侧的氮 化物外延层上开孔直至硅村底 1 , 形成刻蚀孔 10, 如图 1-A; 然后继续用 干法刻蚀和 /或选择性湿法腐蚀方法对栅极 8和漏极 7之间区域氮化物外延 层下方的硅村底 1进行局部选择性刻蚀或腐蚀， 形成该区域氮化物外延层 与硅村底之间的局部空间隔离区域 11 , 如图 1-B。 本发明中的局部空间隔 离区域 11的长度和高度可根据所需耐受电压进行调节。
栅极 8和漏极 7之间区域下方的氮化物外延层与硅村底之间形成的局 部空间隔离区域 11 实现了栅极和漏极之间击穿电场较高的氮化物外延层 区与容易击穿的导电硅村底之间的局部空间隔离， 阻断通过硅村底的导电 通路和击穿路径， 使得器件的击穿不再是通过硅村底的纵向击穿， 而只能 是在氮化物外延层上的横向击穿。 因为氮化物外延层的击穿电场较高且栅 漏间距一般比较大， 所以器件的击穿电压大幅提高， 即使村底接地也不影 响器件的击穿电压。
图 2-A和 2-B为本发明第二实施方式在漏端电极内侧的氮化物外延层 上一个开孔刻蚀形成局部空间隔离区域的 HEMT器件结构示意图。
在漏极 7内侧的氮化物外延层上开孔刻蚀， 形成一个刻蚀孔 10, 再从 中间向两侧腐蚀 /刻蚀形成栅极 8和漏极 7区域氮化物外延层与硅村底之间 的局部空间隔离区域 11 , 如图 2-A。 与第一实施方式相比， 此工艺方法可 以增大腐蚀范围，缩短工艺时间，其中在漏极 7内侧的刻蚀孔 10不需要 4艮 大， 对二维电子气的影响并不大， 如图 2-B所示。
图 3为本发明第三实施方式在在漏端电极内侧的氮化物外延层上多个 开孔刻蚀形成局部空间隔离区域的 HEMT器件结构示意图。
在漏极 7内侧的氮化物外延层上开孔刻蚀， 形成多个刻蚀孔 10, 再从 中间向两侧腐蚀 /刻蚀形成栅极 8和漏极 7区域氮化物外延层与硅村底之间 的局部空间隔离区域 11 , 如图 3所示。 与第二实施方式相比， 此实施方式 设有多个刻蚀孔 10, 多个刻蚀孔 10可沿直线排列， 也可以以其他形式进 行排列， 此工艺方法可以进一步增大腐蚀范围， 缩短工艺时间， 同时减小 对器件性能的影响。
图 4为本发明第四实施方式在氮化物外延层与硅村底之间的局部空间 隔离区域内引入耐高电压二氧化硅层的 HEMT器件结构示意图。
通过氧化处理方式可以在氮化物外延层与硅村底 1之间的局部空间隔 离区域内 11 的硅村底中形成较厚且耐高电压的二氧化硅层 12, 相比单纯 的空间隔离， 可更进一步提高隔离效果， 增加器件击穿电压， 氧化层厚度 可以根据所需耐受电压及具体工艺进行调节。 本实施方式中氧化处理方式 为热氧化、 等离子体氧化或其他氧化处理方式。
图 5为本发明第五实施方式在氮化物外延层与硅村底之间的局部空间 隔离区域下方引入绝缘高电压耐受层的 HEMT器件结构示意图。
局部空间隔离区域 11下方设有横穿整个硅村底 1的绝缘高电压耐受层 17,此绝缘高电压耐受层 17紧挨局部空间隔离区域 11 ,横穿整个硅村底 1 , 可以进一步提高器件的纵向击穿电压。绝缘高电压耐受层击穿电场比较高， 可以是氧化物、 氮化物中的一种或多种的组合。
图 6为本发明第六实施方式在氮化物外延层与硅村底之间的局部空间 隔离区域内引入耐高电压填充物的 HEMT器件结构示意图。
为了更进一步提高隔离效果，防止局部空间隔离区域内发生空气击穿， 可以在该局部空间隔离区域内引入耐高电压填充物 13, 如 A1203、 Si02、 SiNx、 A1N、 金刚石中的一种或多种的组合等具有高临界电场的材料， 尤 其是既有高的临界电场又有高的导热率的材料， 如 A1N和金刚石等来提高 绝缘隔离效果， 提高器件击穿电压。
图 7为本发明第七实施方式中氮化物外延层与硅村底之间的局部空间 隔离区域为梯形结构的 HEMT器件结构示意图。
因为栅极 8和源极 6之间的距离较之栅极 8和漏极 7之间的距离小很 多，如果氮化物外延层与硅村底之间的局部空间隔离区域 11的横向长度过 长， 则剩余硅村底对氮化物外延层的支撑力将大大减小， 外延层有可能会 坍塌， 本实施方式中将局部空间隔离区域设为梯形结构可以在满足隔离的 基础上增强硅村底对外延层的支撑。
图 8为本发明第八实施方式中氮化物外延层与硅村底之间的局部空间 隔离区域边缘为弧形结构的 HEMT器件结构示意图。
局部空间隔离区域设为边缘为弧形结构， 工艺较易实现。
图 9为第九实施方式中应用本发明的氮化物 MOSFET器件结构示意 图， 其中在栅极和漏极之间区域下方的氮化物成核层与硅村底之间形成了 局部空间隔离区域。
本实施方式氮化物 MOSFET器件中，源极 6和漏极 7下方的氮化物沟 道层区域为 n型重掺杂区域， 一般掺硅， 栅极 8下方区域为 p型轻掺杂， 一般掺镁， 栅金属下的介质层一般为 Si02、 SiN、 A1N、 A1203或其他绝缘 介质层。
图 10为第十实施方式中应用本发明的氮化物 MESFET器件结构示意 图， 其中在栅极和漏极之间区域下方的氮化物成核层与硅村底之间形成了 局部空间隔离区域。 本实施方式氮化物 MESFET器件中，氮化物沟道层 4一般为 n型轻掺 杂， 源极 6和漏极 7下方的氮化物沟道层 4区域为 n型重掺杂， 栅极 8为 肖特基结。
图 11 出了本发明第十一实施方式在势垒层上生长 GaN冒层的氮化物 HEMT器件结构示意图。
本实施例中在氮化物势垒层 5 上设有氮化物冒层 14, 势垒层选用 AlGaN材料。 由于 AlGaN势垒层材料表面的缺陷和表面态密度较大，会俘 获 4艮多电子，会对沟道中的二维电子气产生影响， 降低器件特性及可靠性。 通过在氮化物势垒层 5表面生长一层氮化物冒层 14作为保护层可以有效减 小势垒层材料表面的缺陷和表面态对器件特性的影响。 优选地， 在本实施 方式中氮化物冒层 14为 GaN。
图 12出了本发明第十二实施方式在势垒层和沟道层之间引入 A1N插 入层的氮化物 HEMT器件结构示意图。
本实施方式中在氮化物势垒层 5和氮化物沟道层 4之间设有 A1N插入 层 15, 势垒层选用 AlGaN材料。 因为 A1N的禁带宽度非常高， 可以更有 效地将电子限制在异质结势井中， 提高了二维电子气的浓度； A1N插入层 还将导电沟道与 AlGaN势垒层隔离开， 减小了势垒层对电子的散射效应， 从而提高电子的迁移率， 使得器件整体特性得以提高。
图 13 示出了本发明第十三实施方式在緩沖层和沟道层之间插入 AlGaN背势垒层的氮化物 HEMT器件结构示意图。
在一定外加电压下， 沟道中的电子会进入氮化物緩沖层 3, 尤其是在 短沟道器件中这种现象更为严重， 使得栅极对沟道电子的控制相对变弱， 出现短沟道效应； 加上緩沖层中的缺陷和杂质比较多， 会对沟道中的二维 电子气产生影响， 如产生电流崩塌。 本实施方式通过在氮化物緩沖层 3和 氮化物沟道层 4之间设有 AlGaN背势垒层 16, 可以将沟道电子与緩沖层 隔离开， 将二维电子气有效地限制在沟道层中， 改善短沟道效应及电流崩 塌效应。
图 14 示出了本发明第十四实施方式在漏极区域刻蚀多个孔形成多个 局部空间隔离区域， 紧挨其下方插入绝缘高电压耐受层的氮化物 HEMT器 件结构示意图。
本实施方式中， 在漏极 7区域刻蚀多个刻蚀孔 10, 在氮化物外延层与 硅村底之间形成多个局部空间隔离区域 11 , 紧挨其下方插入绝缘高电压耐 受层 17 (如二氧化硅层等）， 这种空间隔离区域结合高电压耐受层的结构 既可以提高硅村底的横向耐压， 也可以提高硅村底的纵向耐压， 从而提高 器件总的击穿电压。 相比在漏极区域形成一个大的局部空间隔离区域， 这 种结构可以大大提高空间隔离区域的腐蚀 /刻蚀工艺效率， 而且每个隔离区 域之间的硅村底可以提供支撑作用， 避免隔离区域过大引起器件的坍塌； 也可以对这些多个空间隔离区域内的硅村底进行氧化， 或填充耐高电压材 料进一步提高器件击穿电压。
图 15-A和 15-B为本发明第十五实施方式在氮化物 HEMT器件的源极 和漏极之间区域下方的氮化物外延层与硅村底之间形成局部空间隔离区域 的工艺流程示意图。
本实施例中源极 6和漏极 7之间区域下方的氮化物成核层与硅村底之 间设有一个或多个局部空间隔离区域 11 , 首先用刻蚀方法在源极 6外侧的 氮化物外延层上开孔直至硅村底 1 , 形成刻蚀孔 10, 如图 15-A; 然后继续 用干法刻蚀和 /或选择性湿法腐蚀方法对源极 6和漏极 7之间区域氮化物外 延层下方的硅村底 1进行局部选择性刻蚀或腐蚀， 形成该区域氮化物外延 层与硅村底之间的局部空间隔离区域 11 ,如图 15-B。本发明中的局部空间 隔离区域 11的长度和高度可根据所需耐受电压进行调节。
图 16-A和 16-B为本发明第十六实施方式在源端电极内侧的氮化物外 延层上一个开孔刻蚀形成局部空间隔离区域的 HEMT器件结构示意图。
在源极 6内侧的氮化物外延层上开孔刻蚀， 形成一个刻蚀孔 10, 再从 中间向两侧腐蚀 /刻蚀形成源极 6和漏极 7区域氮化物外延层与硅村底之间 的局部空间隔离区域 11 , 如图 16-A。 与第十四实施方式相比， 此工艺方法 可以增大腐蚀范围， 缩短工艺时间， 其中在源极 6与栅极 8内侧的刻蚀孔 10不需要 4艮大， 对二维电子气的影响并不大， 如图 16-B所示。 在本实施 方式中源极 6与栅极 8内侧还可以设有多个刻蚀孔， 多个刻蚀孔可沿直线 排列， 也可以以其他形式进行排列， 可以进一步增大腐蚀范围， 缩短工艺 时间， 同时减小对器件性能的影响。
在其他实施方式中， 还可以通过改变硅村底上氮化物沟道层或势垒层 的结构或器件制造工艺， 也可以实现硅村底氮化物高压器件增强型器件， 如用氟离子轰击栅金属下方材料区域可以形成增强型器件等。
由上述技术方案可以看出， 本发明氮化物高压器件及其制造方法具有 以下有益效果：
通过局部去除栅极和漏极之间氮化物外延层下方的部分硅村底形成局 部空间隔离区域， 将该区域击穿电场较高的氮化物外延层与容易击穿的硅 村底用空气进行隔离， 避免通过硅村底可能引起的击穿， 从而实现可以耐 高击穿电压的器件；
在局部空间隔离区域内填充击穿电场更高的材料来提高器件的击穿电 压， 对局部空间隔离区域内的硅材料进行氧化形成二氧化硅层可以进一步 提高器件击穿电压；
在氮化物外延层上方开孔， 先刻蚀掉氮化物外延层直至硅村底层， 再 继续用选择性腐蚀工艺和 /或干法刻蚀工艺， 整个工艺容易控制， 大大提高 了生产效率及工艺可控性。
对于本领域技术人员而言， 显然本发明不限于上述示范性实施例的细 节， 而且在不背离本发明的精神或基本特征的情况下， 能够以其他的具体 形式实现本发明。 因此， 无论从哪一点来看， 均应将实施例看作是示范性 的， 而且是非限制性的， 本发明的范围由所附权利要求而不是上述说明限 定， 因此旨在将落在权利要求的等同要件的含义和范围内的所有变化嚢括 在本发明内。 不应将权利要求中的任何附图标记视为限制所涉及的权利要 求。
此外， 应当理解， 虽然本说明书按照实施方式加以描述， 但并非每个 实施方式仅包含一个独立的技术方案， 说明书的这种叙述方式仅仅是为清 楚起见， 本领域技术人员应当将说明书作为一个整体， 各实施例中的技术 方案也可以经适当组合， 形成本领域技术人员可以理解的其他实施方式。

Claims

权 利 要 求
1、 一种氮化物高压器件， 其特征在于， 所述氮化物高压器件包括： 石圭村底；
位于所述硅村底上的氮化物成核层；
位于所述氮化物成核层上的氮化物緩沖层；
位于所述氮化物緩沖层上的氮化物沟道层；
与所述氮化物沟道层相接触的源极和漏极以及位于所述源极和漏极之 间的极极；
其中， 所述栅极和漏极之间区域下方的氮化物成核层与硅村底之间设 有一个或多个局部空间隔离区域。
2、根据权利要求 1所述的氮化物高压器件， 其特征在于， 所述局部空 间隔离区域内填充有耐高电压填充物。
3、根据权利要求 2所述的氮化物高压器件， 其特征在于， 所述耐高电 压填充物包括 A1203、 Si02、 SiNx、 A1N、 金刚石中的一种或多种的组合。
4、根据权利要求 1所述的氮化物高压器件， 其特征在于， 所述局部空 间隔离区域为方形槽、 梯形槽、 弧形槽或 U形槽。
5、根据权利要求 1所述的氮化物高压器件， 其特征在于， 所述局部空 间隔离区域的内壁上通过氧化处理形成有耐高压的二氧化硅层。
6、根据权利要求 1所述的氮化物高压器件， 其特征在于， 所述局部空 间隔离区域下方设有横穿整个硅村底的绝缘高电压耐受层， 所述绝缘高电 压耐受层为氧化物、 氮化物中的一种或多种的组合。
7、根据权利要求 1所述的氮化物高压器件， 其特征在于， 所述氮化物 沟道层上设有氮化物势垒层， 在氮化物沟道层和氮化物势垒层的界面处形 成有二维电子气。
8、根据权利要求 7所述的氮化物高压器件， 其特征在于， 所述氮化物 势垒层上还设有介质层。
9、根据权利要求 8所述的氮化物高压器件， 其特征在于， 所述介质层 为 SiN、 Si02、 SiON、 A1203、 Hf02、 HfAlOx中的一种或多种的组合。
10、 根据权利要求 7所述的氮化物高压器件， 其特征在于， 所述氮化 物势垒层上设有氮化物冒层。
11、 根据权利要求 7所述的氮化物高压器件， 其特征在于， 所述氮化 物势垒层和氮化物沟道层之间设有 A1N插入层。
12、 根据权利要求 1所述的氮化物高压器件， 其特征在于， 所述氮化 物緩沖层和氮化物沟道层之间设有 AlGaN背势垒层。
13、 一种如权利要求 1所述的氮化物高压器件的制造方法， 其特征在 于， 所述方法包括：
提供一硅村底；
在所述硅村底上形成氮化物成核层；
在所述氮化物成核层上形成氮化物緩沖层；
在所述氮化物緩沖层上形成氮化物沟道层；
在所述氮化物沟道层上形成源极和漏极以及位于源极和漏极之间的栅 极；
在所述栅极和漏极之间区域下方的氮化物成核层与硅村底之间形成一 个或多个局部空间隔离区域。
14、根据权利要求 13所述的氮化物高压器件的制造方法，其特征在于， 所述局部空间隔离区域的制备方法为干法刻蚀和 /或湿法腐蚀。
15、根据权利要求 14所述的氮化物高压器件的制造方法，其特征在于， 所述方法还包括：
在漏极和栅极之间和 /或漏极外侧和 /或源极和栅极之间和 /或源极外侧 的氮化物外延层上开孔刻蚀， 形成刻蚀孔， 通过刻蚀孔从中间向两侧腐蚀 和 /或刻蚀形成局部空间隔离区域。
PCT/CN2014/070148 2013-02-07 2014-01-06 氮化物高压器件及其制造方法 Ceased WO2014121668A1 (zh)

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