WO2014149831A1

WO2014149831A1 - Apparatuses and methods for variable latency memory operations

Info

Publication number: WO2014149831A1
Application number: PCT/US2014/021118
Authority: WO
Inventors: Graziano Mirichigni; Daniele Balluchi; Luca Porzio
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2013-03-15
Filing date: 2014-03-06
Publication date: 2014-09-25
Anticipated expiration: 2015-09-15
Also published as: US20140281182A1; EP2972914A1; US20180349302A1; KR101693137B1; CN104981789B; JP6123017B2; US10740263B2; EP2972914B1; US20170329534A1; US10067890B2; JP2016514329A; KR20150113180A; CN104981789A; SG11201505417SA; US9734097B2; EP2972914A4

Abstract

Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

Description

APPARATUSES AND METHODS FOR VARIABLE LATENCY MEMORY

OPERATIONS

CROSS-REFERENCE

{0011 This application claims priority to U.S. Non-Provisional Application No.

13/838,296 filed March 15, 2013, which application is incorporated herein by reference, in its entirety, for any purpose.

TECHNICAL FIELD

(002) Embodiments of the present invention relate generally to memories, and more specifically, in one or more described embodiments, to variable latency memory operations.

BACKGROUND

J0031 Memories may be provided in a variety of apparatuses, such as computers or other devices, including but not limited to portable memory devices, solid state drives, personal digital, assistants, music players, cameras, phones, wireless devices, displays, chi sets, set top boxes, gaming systems, vehicles, and appliances. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory, among others,

(004) Apparatuses, such as resistance variable memory devices, may be used as nonvolatile memory for a wide range of electronic devices. Resistance variable memory devices may include, for example, phase change memory (PCM) or resistive memory

(RR), among others.

(O05| A conventional read operation using PCM is also similar to read operations for RAM, Accordingly, PCM may be used to implement random access memory. Write operations with PCM, however, may be relatively slower than write operations for conventional RAM. For example, PCMs may require additional time to manage and complete write operations, such as preparing data to be written to memory, suspending a write operation in case of a read access request, and momtoring progress of a write operation. Read operations may be slower than for conventional AM and read operations cannot be performed at a memory location undergoing write operation,

006] As a result of the limitations of using PCM as RAM replacement, operation of

PCMs in memory systems may be restricted. For example, write and read operations may not be performed at any time on any memory location. Status registers used for monitoring the progress of write operations may be regularly queried to determine whether a particular write operation has completed before another write operation is performed. Additionally, in some applications write operations are necessarily suspended for read operations and resumed upon completion of the read operation,

SUMMARY βθ^'71 Examples of apparatuses are provided. An example apparatus may include a memory configured to receive an activate command indicative of a type of a. command during a first addressing phase and to receive the command during a second addressing phase. In some examples, the memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

00 1 An example apparatus may include a memory configured to provide data not valid information during variable latency period. In some examples, the data not valid information may be indicative of a remaining length of the variable latency period and the variable latency period following receipt of an activate command by the memory. In some examples, the memory further may be configured to provide data valid information after the variable latency period, in some examples, the activate command may comprise an activate read command or a activate write command.

[009] An example apparatus may include a controller configured to provide to memory an activate command indicative of a command during a first addressing phase. In some examples, the controller ma further be configured to provide the command a first time during a second addressing phase. In some examples, the controller may further be configured to provide the command a second time responsive, at least in part. to receipt of information indicating that the memory is not available to perforin the command.

[010] Example methods are discloses herein. An example method may include receiving, with a memory, an activate command indicative of a type of a command during a first addressing phase; receiving the command during a second addressing phase; if the command is received during a variable latency period, providing information indicating that the memory is not available to perform the command: and if the commaiid is received after the variable latency period, providing information indicating that the memory is available to perform the command,

(^'01 J. J An example method may include providing, with a controller, an activate command indicati ve of a command; after providing the acti vate command, providing the command; and receiving at least one of data not valid information or data valid information responsive, at least in part, to providing the command.

BRIEF DESCRIPTION OF THE DRAWINGS

(01 ^'J Figure 1 A is a block diagram of an apparatus according to a embodiment of the present invention.

(013| Figure I B is a schematic block diagram of a memory according to an embodiment of die present invention.

|014| Figure 2.4 is a timing diagram illustrating various signals of a read operation according to an embodiment of the present invention.

(015] Figure 2B is a timing diagram illustrating various signals of a write operation according to an embodiment of the present invention.

(0161 Figure 3 A is a timing diagram illustrating various signals of a read operation according to an embodiment of the present invention.

[0171 Figure 3B is a timing diagram illustrating various signals of a write operation according to an embodiment of the present invention.

[018] Figure 4.4 is a timing diagram illustrating variou signals of a read operation accordi ng to an embod iment of the presen t i nven tion ,

(019| Figure 4B is a timing diagram illustrating various signals of a write operation according to an embodiment of the present invention. |^'020| Figure 5 is a schematic state diagram illustrating various states of operation of an apparatus according to art embodiment of the present invention.

[021 J Figure 6 is a table illustrating example latencies according to an embodiment of the present invention.

(022| figure 7 is a table illustrating example bit assignments for wait states during memory operations according to an embodiment of the present invention.

j023j Figure 8 is a table illustrating example bit assignments for acknowledgement e vents of memory commands according to an embodiment of the present invention.

DETAILED DESCRIPTION

[024J Apparatuses and methods for variable latency memory operations are disclosed herein. Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one having skill in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention,

[025] Figure ! A is a block diagram of an apparatus 100 according to an embodiment of the present invention. The apparatus may comprise circuitry, one or more semiconductor dice, a packaged semiconductor, a device including such circuitry, die, or package, and/or system including such device. The apparatus 100 includes a controller 1 10 (e.g., memory controller) and a memory 120. The controller 1 10 and the memory 120 may be coupled by a command and address (CA) bus BO and a data bus 135. The memory 120 may be configured to receive commands and/or addresses from the controller 110 over the CA bus 130, and the memory may be configured to receive data and/or provide data over the data bus 135.

[0261 The memory 120 may be configured to perform memory operations (e.g., read operations or write operations) in response to the received commands and/or addresses that are provided by the controller 1 10, For example, the memory 120 may provide read data to the controller 1 10 over the data bus 135 in response to a read command. and may store write data received over the data bus 135 in response to a write command. Additionally, the memory 120 may farther provide information to the controller 1 10 over the data bus 135 in response to particular commands. The information may indicate, for instance, whether the memory 120 is available to perform a memory operation and/or an amount of time before the memory 120 may become available to perform a memory operation.

[027] In at least one embodiment, the apparatus 100 may be configured to operate in accordance with three-phase addressing. Generally, three-phase addressing may include three phases during which the memory 120 receives commands and addresses provided by the memory controller 1 10, responsi ve to which memory operations (e.g., read operations or write operations) are performed. For example, three-phase addressing may include a first phase in which the memory 120 may receive a preactive command from the controller 1 10 over the CA bus 120. The controller 1 10 may further provide a first portion of a row address to the memory 120. In response, the memory 120 may store the first portion of a row address received with the preacti ve command on the CA bus 120. In a second phase, the memory 120 may receive an active command from the controller 1 10. The controller 1 10 may further provide a second portion of a row address to the memory 120. In response, the memory 120 may store the second portion of the row address provided with the active command on the CA bus 120. The first portion and second portion of the row address may comprise a full row address, and the memory 120 may access data associated with the row address and store the data in a buffer. During a third phase, the memory 120 ma receive a command that is provided by the controller 1 10. For example, the memory 120 may receive a read command or a write command that is provided by the controller 1 1.0. In response to a read command, the buffered data may be provided to the controller 1 10 over the data bus 135. In response to a write command, write data may be received on the data bus 135. and the memory 120 may store the write data at the row address.

[028] In at least one embodiment, the second phase of a three-phase addressing operatio may include a variable latency period tLAT, During the tLAT period, the memor 120 may manage memory operations, for instance, by preparing circuits t perform the command received in the third phase, completing a current memory operation, and/or suspending a current memory operation. Accordingly, because the

3 memory 120 may manage any number of these ami/or other memory operations during the tLAT period, the variable Latency period tLAT ma vary. For example, the tLAT period may vary between relatively short arid relatively long durations.

[029] In some embodiments, the memory 120 may be configured such that the tLAT period is guaranteed to elapse within one or more particular amounts of time. For example, in at !east one embodiment, when the command of the third phase comprises a read command, the memory 120 may be configured to complete the second phase at least within a time tMAXLATR. That is, the tLAT period will elapse within tM AX LAI R. When the command provided in the third phase comprises a write command, the memory 120 may be configured to complete the second phase at least within a time tMAXLATW. That is, the tLAT period will elapse within tMAXLATW, Values for both tMAXLATR and tMAXLATW may be stored as parameters in a register (not shown in Figure ί ). The values for tMAXLATR and tMAXLATW, in some instances, may he predetermined and/or equal or unequal. The values for tMAXLATR and tMAXLATW may be adjusted in real-time, for instance, based on priority of commands. By way of example, tMAXLATW may be increased when read commands are prioritized over write commands.

(030) Accordingly, because a maximum duration of the tLAT period may depend on the type of command provided in a subsequent phase, in some embodiments, activate commands may indicate the type of command provided in the third phase. For example, in at least one embodiment, an activate command may comprise an activate read command or an activate write command. In this manner, the variable latency period tLAT ma be based, at least in part, on whether an activate command comprises an activate read command or an activate write command. In some instances, activate read commands and activate write commands may be distinguished based on a bit value, for example, as represented by a signal. By way of example, one or more bits of a buffer address BA may be used to distinguish activate read and activate write commands. In another example, particular combination of bits recei ved on the CA bus 130 may indicate that an activate command comprises an activate read command or comprises an activate write command.

(031) in some instances, the controller 1 10 may be configured to provide a read or write command a particular amount of time after providing an activate command, and as previously described, the tLAT period ma vary based, at least in part, on the number and type of operations the memory 120 may perform during the second phase of a three-phase addressing procedure. As a result, a read or write command may be provided by the controller 110 before the tLAT period elapses, that is, prior to a time at which the memory 120 is available to perform the respective command. As will be explained in further detail below, when a command is provided prior to the tLAT period elapsing, the memory 120 may provide information indicating that the memory 120 is not available to perform a command. n some embodiments, data not valid (DNV) information is provided on the data bus 135 to indicate that the ^'memory 120 is not available to perform a command. If a command is provided after the tLAT period elapses, the memory 120 may provide information indicating mat the memory 120 is available to perform a command, in some embodiments, data valid (DV) information indicating that the memory 120 is available to perform a command and/or read data is provided on the dat bus 135. In at least one embodiment, the data bus 135 may include one or more data mask signal Sines that may be used for providing respective DN V and DV information.

[032 j Figure IB is a schematic block diagram of a memor 150 according to an embodiment of the present invention. The memory 150 ma be used to implement, at least in part, the memory 120 of Figure 1 A, The memory 150 may include an address buffer 160 and a data buffer 170. The memory 150 includes elements that have been previously described with respect to the apparatus 1.00 of Figure l.A. Those elements have been identified in Figure 1 B using the same reference numbers used in Figure I A and operation of the common elements is as previously described. Consequently, a detailed description of the operation of these elements will not be repeated in the interest of brevity.

[033] The address buffer 160 may include a multiplexer 154 that may be configured to receive a first portion (e.g.. higher portion) of an N-bit address (e.g., row address) from the CA bus 130 and further configured to provide the firs portion of the row address to one of a plurality of row address buffers 166. The address butter 160 may include any number of row address buffers 166, such as four row address buffers 1 6 as illustrated in Fiaure 1 B. j034| The multiplexer 154 may be configured to provide the first portion of the row address to a row address buffer 166 based, at least in par on a buffer address BA. B ^¬ way of example, the buffer address BA may be used to determine which row address buffer 166 receives the first portion of the row address. In embodiments having 4 row address buffers 1 6, for instance, 2 bits of the buffer address BA may be used to determine the row address buffer 1 6 that receives the first portion of the ro address, |035| Each of the row address buffers 166 may be coupled to a multiplexer 168. The multiplexer 168 may be configured to receive the first portion of the row address and provide it to a row address register 1 0 based, at feast in part, on the buffer address B A. The row address register 1.90 may receive the first portion of the row address from the multiplexer 168 and further may receive a second portion (e.g., lower portion) of the row address from the CA bus 130. Accordingly, the row address register 1 0 may store an entire address. As previously described, the address .may comprise N bits, and any number of bits may be allocated between the first and second portions of the row address. A row decoder 192 may be configured to receive the row address for accessing memory of array 194 associated with the address for read and/or write operations.

|03 | In an example read operation, read data may be provided from the array 1 4 to the multiplexer 172 via the I/O circuitry 196. The I/O circuitry 196 may include, for instance, a plurality of sense amplifiers configured to sense and/or amplify respective data such that the data may be provided to or received from the array 194. Based, at least in part, on the buffer address BA, the multiplexer 172 may provide the read data to one of a pluralit of row-^' data buffers 174 of the data buffer 170. The data buffer 170 may include any number of row data buffers 174 and in at least one embodiment, the address buffer 160 and data buffer 170 ma include a same niimber of row address buffers 1 6 and row data buffers 1 4.. respectively. In some embodiments, the number of row data buffers 174 and row address buffers 166 may be different. The read data may be provided from the row data buffer 174 to a multiplexer 176 based, at least on part, on the buffer address BA, and thereafter provided to a state machine 178. The state machine 178 may provide the read data to the data bus 135 based, at least in part, on a control signal CTL. 037] in. an example write operation, write data (e.g., associated with a write command received on the CA bus) may be provided from the data bus 135 to the state machine 178. Based, at least in part, on the control signal CTL, the state machine 178 may provide the write data to the multiplexer 176, which may in turn provide the write data to one of the plurality of row data buffers 174 based, at least in part, on the buffer address BA, The selected row data buffer 174 may provide the write data to the multiplexer 1 2. which may in turn provide the write data to the I/O circuitry 1 6 for storing in the array 194. The write data may be stored in memory eel is of the array 1 4 associated with the row address provided by the row decoder 1 2.

(038] As previously described, the memory .150 may be configured to operate in accordance with three-phase addressing. Accordingly, during the first phase, a preactive command may cause first portio of a row address to be provided to the multiplexer 154 over the CA bus 130. The first portion of the row address may be stored in a row address buffer 166.

(039] In the second phase, an acti vate command may be provided and cause the first portion of the row address to be provided from the row address buffer 166 to the row address register 190. Moreover, a second portion of the row address .may be provided to the row address register 190 over the CA bus 130. The row address may be used to access data of the array 194 such that data may be pro v ided from the array 194 to a row data buffer 174, The particular row address buffer 166 and row data buffer 174 receive the first portion of the row address and the data from the array 194, respectively , may be based, at least in part, on buffer address BA.

040 j During the third phase, a read operation or a write operation may be performed in response to a read command or a write command, respectively. As previously described, commands provided in this manner may be provided after a tLAT period. In a read operation, the data stored in the row data buffer 174 may be provided to the data bus 135 as read data using the output state machine 3 78. In a write operation, write data may be received on the data bu 135 by the state machine 178 and provided to the row data buffer 174. The write data may then be stored in the array 194 at the row address.

041] Figure 2 A is a timing diagram 200 illustrating various signals of a read operation according to an embodiment of the present invention. The timing diagram 200 may include signals provided on the CA bus 1 0 and the data bus 1 5 of Figure 1 A.

[042] At time TO. the controller 1 10 ma provide a preaetive command 202 on the C A bus 130. and at time TL may further provide an activate read command 204, As previously described, the activate read command 204 may indicate an upcoming read operation. The activate read command 204 ma be de-asserted at time T2, arid after a delay tRC , at time T3, the controller 1 10 may provide a read command 206. The delay tRCD may, for instance, comprise a RA.S to CAS delay that defines the minimum time between a time when an activate command is provided and a time when a subsequent read command or write command is provided. The time tRCD may be predetermined and/or specified in accordance with one or more standards, such as the JEDEC LPDDR2 standard.

[0431 At time T4, in response to the read command 206 and after a time RL has eiapsed, the memory 120 may provide data not valid (DNV) information on the data bits 135. The time RL may comprise an amount of time for the memory 120 to provide a response (e.g., DNV or DV information) to the read command 206 and may comprise, for instance, a number of clock cycles (e.g. , 3 clock cycles of a system clock signal. In at least one embodiment, the DNV information 210 may be provided on data mask signal lines of the data bus 135 and further may be provided with a burst length having; for instance, a length of 8 bits. As previously described, the DN V information 210 may indicate that the memory 120 is not available to perform a read command. For example, the DNV information 210 may indicate that the tLAT period has not yet elapsed. The DNV information 210 may further include information indicating an. amount of time until the apparatus 100 will be available to perform a read command, or the amount of time before the tLAT period elapses.

[044] After time T5 at which the tLAT period elapses., the controller 1 10 may provide a read command 208 to the CA bus 130 at time T6. In response, at time T7, the memory 120 may provide DV information 212 on the data bus 135 indicating that the memory is available for the operation. As previously described, because the command is provided after the tLAT period has elapsed, the command ma be performed. In at least one embodiment, the DV information 212 may be provided on the data mask signal Hives of the data bus and the data associated with the read command 208 ma be provided on the data bus at time T7 as well.

10 1 While the timing diagram 200 has been described with respect to read commands 206. 208, other read commands may be provided as well. For example, multiple read commands may be provided to cause the memory 120 to provide DNV information before the tLAT period has elapsed. Because each of these commands are provided before the apparatus 100 is available to perform a command, DNV information may be provided on the dam bus 135 in response to each of these read commands, as previously described,

(^'046J Figure 2B is a timing diagram 250 illustrating various signals of a write operation according to an embodiment of the present invention. The timing diagram 250 may include signals provided on the CA bus 130 and the data bus 135 of Figure iA.

{047} At time TO, a preactive command 252 may be provided on the CA bus 130. At time XL the controller 1 10 may provide an activate write command 254, and at time T2 may no longer provide the write command 254, As previously described, the activate write command 254 may indicate an upcoming write operation. After a time tRCD, at time T3, a read command 256 may be provided.

{048} At time T4, after RL has elapsed, the memory 120 may provide DNV information 270 on the data bus 135 in response to the read command 256. The read command 256, for example, may be used to cause the memory 120 to provide DNV or DV information. The DN V information 270 may be provided on data mask signal lines of the data bus 135 and may be provided with a burst length, for instance, of 8 bits. As previously described, the DNV information 270 may indicate that the memory 120 is not yet available to perform a write command. The DN V information 270 may fiirther include information indicating an amount of time until the memory 120 will be available to perform a command.

|^'049J After time T5 at which the tLAT period elapses, the controller 1.10 ma provide a read command 258 on the CA bus 130 at time T6. In response, at time 17, the memory 120 may provide DV information 272 o the data b«s, e.g., data mask; signal lines, indicating that the memory is available for the operation. Because the command is provided at a time after the tLAT period has elapsed, a write command may be performed, in response to the DV information 272 being provided on the data bus 135, the controller may provide a write command 260 on the CA bus 130 at a time T8. Write data 274 associated with the write command 260 is provided to the memory 120 on the data bus 135 at time T9,

{0501 While the timing diagram 200 of Figure 2A and the timing diagram 250 of Figure 2B have been described with respect to read commands 206, 208, and 256, 258, respectively, other read commands may be provided as well. For example, in some embodiments, an external device may be configured to periodically provide read commands to cause the memory 120 to provide DNV/DV information until DV information is provided, e.g., multiple read commands may be provided before the tLAT period has elapsed, in other embodiments, the external device may be configured to provide one or more read commands based, at least in pari, on information included in the DNV information. By way of example, D^'NV information may indicate that the tLAT period may elapse in 50 microseconds, and the controller 1 10 may wait 50 or more microseconds before providing another read command.

051) Moreover, in both the timing diagram 200 of Figure 2A and the timing diagram 250 of Figure 2B, a respective read command is pro vided a time tRCD after an activate command is provided. In this manner, it may be determined whether the memory 120 is available to perform a read command or a write command. As previously described, read commands may be provided periodically and/or based, at least in part, on information included with DNV information. Accordingly, in at least one embodiment, for read operations, read commands may be provided until DV information and associated read data is provided to the data bos 135, For write operations, read commands may be provided until DV information is provided, and in response, a write command may be provided causing the memory 120 to store write data provided from the data bus 135,

052| Figure 3A is a timing diagram 300 illustrating various signals of a read operation according to an embodiment of the present invention. The timing diagram 300 may include signals provided on the CA bus 130 and the data bus 135 of Figure l A.

0531 At time TO, the controller 1 10 may provide a proactive command 302 on the CA bus 130, and at time Tl , may further provide an activate read command 304. The activate read command 304 may be deasserted at time T2, and after a time tRCD, at time T3, the controller Π0 may provide a read check command 306. The read check command 306 may comprise a "dummy" command that may cause the memory 120 to indicate whether it is available to perform a command (e.g., provide DNV information or DV information), that is, whether the tLAT period has elapsed. In at least one embodiment, providing the read check command 306 may comprise providing a read command and asserting one or more particular bits of the buffer address BA (e.g., bit 2 of the buffer address BA). In other embodiments, particular signal combinations on the CA bus 130 may be used to provide a read check command.

] In response to the read check command 306. the memory 1 0 may provide

DNV information 320 on the data bus 135 at time T4. The DNV information 320 ma indicate that the tLAT period has not yet elapsed, and may farther may include information indicating an amount of time until the tLA T period will elapse.

j After time T5 at which the tLAT period elapses, the controller 1 10 may provide a read check command 308 on the CA bus 130 at time T6. in response, at time T7, the memory 120 may provide DV information 322 on the data bus 135 indicating that the memory 120 is available for a read operation. Accordingly, the controller 1 10 may provide a read command 310 at a time T8, and at time T9, the memory 120 may provide read data 324 associated with the read command 310 to the data bus 135,] Figure 3B is a timing diagram 350 illustrating various signals of a write operation according to an embodiment of the present, invention. The timing diagram 350 may include signals provided on the CA bus 130 and the data bus 135 of Figure 1 A.

] At time T0_} the controller 1 1.0 may provide a preactive command 352 on the CA bus 130, and at time TI„ and further may provide an activate write command 354. The activate write command 354 may be deasserted at time ΤΓ2, and after a time tRCD.. at time T3, the controller i 10 may provide a read check command 356. As previously described, the read check command 356 may comprise a "dummy" command that may cause the memory 120 to indicate whether it is available to perform a command (e.g., provide DNV information or DV information). Because the activate command 354 is an activate write command, the read check command 356 may cause the memory 120 to indicate whether it is available to perform write command. The read check cominand may be provided by asserting a read command and one or more particular bits of the buffer address BA (e.g., bit 2 of the buffer address BA), or by asserting particular signal combinations on the CA bus 130,

[0581 In response to the read check command 356. the memory 120 may provide DNV information 370 on the data bus 135 at time T4, indicating to the controller 110 that the tLAT period has not elapsed since an activate command was provided. The DHV information 370 may further may mclude information indicating an amount of time until the tLAT period will elapse.

[05 1 After time 15 at which the tLAT period elapses, the controller Ϊ 10 may provide a read check command 35S on the CA bus 130 at time T6. hi response, at time T7, the memory 120 may provide DV information 372 on the data bus 135 indicating that the memory is available for a write operation. The controller 110 ma provide a write command 360 at time T8, and at time T9, the controller 1 10 may further provide write data 374 to the data bus 135 for storing in the memory 120.

(060) Timing diagram 300 of Figure 3A and timing diagram 350 of Figure 3B have been described with reference to a read check command. In at least one embodiment, the read check command may differ from a read command in that the apparatus 100 may provide indication of its status without providing any data to the data bus 135.

{061.) Figure 4A is a timing diagram 400 illustrating various signals of a read operation according to an embodiment of the present invention. The timing diagram 400 may include signals provided on the CA bus 130 and the data bus 135 of Figure 1A.

(062 J At time TO, the controller 1 10 may provide a proactive command 402 on the CA bus 130, and at time Tl , may further provide an activate read command 404. In response to the activate read command 404, the memory 120 may provide DNV information 420 to the data bus 135, and in at least one embodiment., the DNV information 420 may be provided on the data bus 1 5 until time T4 at which the tLAT period elapses. Moreover, the memory 120 may provide DV information 422 on the data bits 135 at time T4. n response to the DV information 422 being provided, the controller 1 10 may provide a read command 406 at time T5, thereby causing the memory 120 to provide read data 424 on the data bus 135 at time T6, {063] Figure 4B is a timing diagram 450 illustrating various signals of a write operation according to an embodiment of the present invention. The timing diagram 450 may include signals provided on the CA bus 130 and the data bus 135 of Figure 1A.

(06 1 At time TO, the controller 1 10 may provide a preactive command 452 on the CA bus 130, and at time Tl , may further provide an activate write command 454. In response to the activate write command 454, the memory 120 may provide DNV information 470 on the data bus 1.35, and in at least one embodiment, the DNV information 470 may be provided until time T3 at which the tLAT period elapses. Moreover, the memory 120 may provide DV information 472 at time T3. In response to the DV information 472 being provided, the controller 1 10 ma provide a write command 456 at time T4. The controller 1 10 may further provide write dat 474 to the data bus 135 at lime T5 for storing in the memory 120.

(065 j Figure 5 is a schematic state diagram 500 illustrating various states of operation of an apparatus according to an embodiment of the present invention. The state diagram 500 may include an idle state 502, an active state 504. a read state 506, and a write state 508, and a preactive state 510 and may be used, for instance, in operation of an apparatus, such as the apparatus 100 of Figure 1A. The state diagram 500 may be used to implement, modify, or replace, wholly or in part, any state diagram in accordance with one or more standards, such as the JEDEC LPDDE2 standard. In at least one embodiment, the state diagram 500 may comprise a simplified version of a state diagram and accordingly may omit one or more known states to avoid unnecessarily obscuring the invention..

{^'066] In an example operation, after initialization, the apparatus 100 may enter the idle state 502. In the idle state 502, the apparatus 100 may not be operating in an of the phases of three-phase addressing described herein. In response to a preactive command, the apparatus 100 may enter the preactive state 510 and operate in a first phase of three-phase addressing. Once the first phase has completed, the apparatus 100 may reenter the idle state 502.

[067] In response to an activate command (e.g., activate read or activate write), the apparatus 100 may enter the active state 504, When in the active state 504, the apparatus 100 may operate in a second phase of three-phase addressing. As previously described, the controller 1 10 ma provide an activate read command or an activate write command, and the memory 120 may manage any operations during a tLAT period. As previously described, in at least one embodiment, the memory 120 may be configured to complete the second phase of three-phase addressing within tMAXLATR in response to an activate read command and within tMAXLATW in response to an aciivate write command.

[068] In accordance with at least one embodiment of the invention, once in an active state 504, the controller 1 .10 may provide a command to the memory 120, for example, as previously described with reference to Figures 2A and 2B. As previousiv described, in some instances, the controller 1 10 may provide a read command, for instance, before the tLA T period elapses. Accordingly, the apparatus 100 may enter the read state 506. provide DNV information, and return to the active stale 504. If read command is received at a time at which the apparatus 100 is available to perform a read command, for instance the tLAT period has elapsed, the apparatus 100 may enter the read state 506, provide DV information, and return to the active state 504. If the activate command was an activate read command, the memory 100 may further provide read data with the DV information. If the activate command was an activate write command, the apparatus 100 may return to the active state 504. Subsequently, the apparatus 100 may enter the write state 508, and the controller 110 may provide a write command and associated write data to the memory 120. The memory 120 may store write dat associated with the write command and the apparatus 1 0 may return to the active state 504.

(069{ In other embodiments, once in an active state, the controller 110 may provide a read check command to the memory 120, for example, as previously described with reference to Figures 3 and 3B, In response, the memory 120 may provide DNV information if the read check command is received before the tLAT period elapses. If the read check command is received after the tLAT period has elapsed, the memory .120 may provide DV information if the read check command and the apparatus 100 may return to the active state 504 once the DV information is provided. A read or write command may subsequently be performed by entering the read state 506 or the write state 508, respectively. Once the command has been performed, the apparatus 100 may return to the active state 504. J In. yet other embodiments, once in the active state 504, the memory 1.20 may provide DNV information to the controller 1 10 until the memory 120 is available to perform a command, for instance, after the tLAT period has elapsed, for example, as previously described with reference to Figures 4A and 4B. Once the memory 120 is available to perform a command, the memory 120 may provide DV information. A read or write command may subsequently be performed by entering the read state 506 or the write state 508, respectively. Once the command has bee performed, the apparatus 100 may return to the active state 504.

1 In each case, after performing a read command or a write command, the apparatus 100 may return to the active state 504. During a subsequent three-phase addressing process, another preactive command may he provided. The apparatus 100 may enter the preactive state 510 and transition to the idle state 502 before receiving an acti ve command, as previously described,

] Figure 6 is a table 600 illustrating example latencies according to an embodiment of the present invention. As previously described, tMAXLATR and tMAXLATW may comprise maximum times for the tLAT period for read and write operations, respectively. The table 600 illustrates example latencies for both tMAXLATR and tMAXLATW that may he used in accordance with described examples. Values for tMAXLAT and tMAXLATW may be stored in one or more registers, suc as a transparent operations register (TOR). Registers storing tMAXLATR and tMAXLATW may, in some embodiments, may be read-only, or may be writeahle such that a user may specify values for tMAXLATR and/or tMAXLA TW.] Figure 7 is a table 700 illustrating example bit assignments for wait, states during memory operations according to an embodiment of the present invention. As previously described, DNV mformarion, such as the DNV information 210 of Figure 2, ma include information indicating the remaining duration before the tLAT period elapses. As illustrated in Figure 7„ in at least one embodiment, DNV information may indicate whether relatively short, normal, or long periods of time remain. In this manner, a controller, such as the controller 1 .10 of Figure LA, may determine whether t hold the CA bus 130 and/or the data bus 135 in a wait state, or to abort (e.g., terminate) a pending command such that another command, for instance, having higher priority, may be performed. In at least one embodiment, information included, in the DNV information may be provided in parallel and/or in serial using one or more data mask si anal lines of the data bus 135.

[074) Figure 8 is a table 800 illustrating example bit assignments for acknowledgement events of memory commands according to an embodiment of the present invention. As previously described, DV information may be used to indicate that the apparatus 100 is available to perform a read command or a write command, respectively. In some embodiments, and as illustrated in Figure 8, the DV information may further include information, for instance, indicating whether an error has occurred and or whether a particular action (e.g., check status register) is suggested as a result, in at least one embodiment, each of the bit state assignments may be provided in parallel and/or in serial using one or more data mask signal lines of the data bus 135,

[075) From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims

What is claimed is:

1. An apparatus, comprising:

a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to recei ve the command during a second addressing phase, the memory further configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

2. The apparatus of claim 1 , wherein the variable latency period is measured relative to the activate command.

3. The apparatus of claim 1. wherein the command comprises a read command, a read check command, or a combination thereof

4. The apparatus of claim J , wherein a maximum duration of the variable latency period is based, at least in pari, on a type of the activate command.

5. The apparatus of claim 1 , wherein the information indicating that the memory is not available to perfonii a command comprises data not valid information.

6. The apparatus of claim 5, wherein the data not valid information is indicative of a remaining duration of the variable latenc period.

7. The apparatus of claim 1 , wherein the activate command comprises an acti ate read command or an. activate write command.

8. The apparatus of claim 1 , further compri sing:

a controller coupled to the memory and configured to provide the activate command.

9. An. apparatus, comprising:

a memory configured to provide data not valid infotmatioa during a variable latency period, the data not valid information indicative of a remaining length of the variable latency period and the variable latency period following receipt of an activate command by the memory, the memory further configured to provide data valid information after the variable latency period,

wherein the activate command comprises an activate read command or an activate write command,

10. The apparatus of claim 9. wherei the memory is further configured to manage memory operations during the variable latency period.

1.1. lire apparatus of claim 9, wherein the activate read command and the activate write command are based, at least in part, on one or more bits of a buffer address.

12. lire apparatus of claim 9_S wherein the memory is further configured to provide the data valid information responsive, at least in part, to the variable latency period elapsing.

13. The apparatus of claim 9, wherein the variable latency period has a first maximum duration when the activate command comprises an activate read command and a second maximum duration when the activate command comprises an. activate write command.

14. The apparatus of claim 9, wherein the data not valid information is indicative of a remaining dura tion of the variable latency period.

15. The apparatus of claim 9, wherei the data valid information in indicative of an error, a suggested action, or a combination: thereof.

16. An apparatus, comprising: a controller configured to provide to memory an activate command indicative of a command during a first addressing phase, the controller further configured to provide the command a first time daring a second addressing phase,

wherein the controller is further configured to provide the command a second time responsive, at least in part, to receipt of infomiation mdicatmg that the memory is not a vai lable to perform the command.

17. The apparatus of claim 16, wherein the activate command comprises at least one of an activate read command or an activate write command.

18. The apparatus of claim 16, wherein the controller is further configured to recei ve read data responsive, at least in part, to receipt of data valid information and the activate command comprising an activate read command and to provide a write command responsive, at least in part, to receipt of data valid information and the activate command comprising an activate write command.

19. Hie apparatus of claim 16, wherein the controller is further configured to provide the command after a delay.

20. The apparatus of claim 19, wherein the delay comprises a RAS to CAS delay in accordance with the LPDD 2 standard.

21. The apparatus of claim 16, wherein the controller is further configured to provide a pieacti ve command during a. third addressing phase.

22. The apparatus of claim 16, wherein the controller is configured to receive the information indicating that the memory is not available to perform the command on one or more data mask signal lines of a data bus.

23. The apparatus of claim 16, wherein the controller is configured to provide the command after a RAS to CAS delay has elapsed.

24. The apparatus of claim 16, wherein the iuformaiion is indicative of a remaining duration of the variable latency period.

25. A method, comprising:

receiving, with a memory, an activate command indicative of a type of a command during a first addressing phase;

receiving the command during a second addressing phase;

if the command is received during a variable latency period, providing information indicating that the memory is not available to perform the command; and if the command is received after the variable latency period, providing

information indicating that the memory is available to perform tire command,

2(1 lire method of claim 25, farther comprising:

managing one or more memory operations during the variable latency period,

27. The method of claim 25, wherein said receiving, with a memory, an activate command comprises:

determining whether the activate command comprises an activate read command or a activate write command.

28. The method of claim 27. wherein the variable latency period has a first maximum duration responsive, at least in part, to the activate command comprising an activate read command and the variable latency period has a second maximum duration responsive, at least in part, to the activate command comprising an activate write command.

29. The method of claim 27, wherein determining whether the activate command comprises an activate read command or an activate write command comprises determining a state of a bit of a buffer address .

30. The method of claim 27, wherein providing tnfo.rma.tioK indicating that the memory is not available to perform the command comprises providing data not valid information indicating a remaining duration of the variable latency period.

31 . The method of claim 27, wherein providing information indicating that the memory is available to perform, the command comprises providing data valid information indicating an error.

32. The method of claim 27, further comprising:

receiving, with the memory, a preactive command.

33. A method, comprising:

providing, with a controller, an activate command indicative of a command; after providing the activate command, providing the command; and

receiving at. least one of data not valid information or data valid information responsive, at least in part, to providing the command.

34. The method of claim 33, wherein providing, with a controller, an activate command indicative of a command comprises:

providing at least one of an activate read command or an activate write command.

35. The method of claim 33, wherein receiving at least one of data not valid information or data valid information comprises:

receiving read data and the data valid signal on a same bus,

36. The method of claim 33, wherein providing the command comprises : providing the command after a delay.

37. The method of claim 33, wherein receiving at least one of data not valid information or data valid information comprises:

if the command was provided during a variable latency period, receiving data not valid information; and if the command was provided after a variable latency period, receiving data valid tormation.

38. The method of claim 37, wherein the variable latency period has a maximum duration based, at least in pan, on the activate command.

39. The method of claim 33, further comprising^'.

before providing the activate command, providing a preactive command.

40. The method of claim 33, wherein receiving at least one of data not valid information or data valid information responsive, at least in part, to providing the command comprises:

receiving the at least one of data not valid information or data valid information on one or more data mask signal lines.