WO2015043397A1 - 频偏检测方法和装置 - Google Patents

频偏检测方法和装置 Download PDF

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Publication number
WO2015043397A1
WO2015043397A1 PCT/CN2014/086674 CN2014086674W WO2015043397A1 WO 2015043397 A1 WO2015043397 A1 WO 2015043397A1 CN 2014086674 W CN2014086674 W CN 2014086674W WO 2015043397 A1 WO2015043397 A1 WO 2015043397A1
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Prior art keywords
clock signal
frequency offset
counter
crystal oscillator
local crystal
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PCT/CN2014/086674
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English (en)
French (fr)
Inventor
刘旺
刘永亮
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP14847912.4A priority Critical patent/EP3043493B1/en
Publication of WO2015043397A1 publication Critical patent/WO2015043397A1/zh
Priority to US15/084,031 priority patent/US9755820B2/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal

Definitions

  • Embodiments of the present invention relate to communication technologies, and in particular, to a frequency offset detection method and apparatus.
  • Synchronous Digital Hierarchy (SDH) network adopts hierarchical master-slave synchronization mode, that is, a single reference clock (Primary Reference Clock, referred to as PRC) is used to synchronize the whole network synchronization through the synchronous link of the synchronous distribution network, and the SDH network uses one.
  • PRC Primary Reference Clock
  • the network element device in the SDH network uses the clock signal transmitted by the upper-level network element device that it tracks as the reference clock signal, and continues to transmit the reference clock signal to its next-level network element device.
  • the reference clock signal is affected by complicated factors, a frequency offset occurs during the transmission process. Therefore, the network element devices at all levels need to perform frequency offset detection on the reference clock signal.
  • the clock signal outputted by the local crystal oscillator of the network element device is used to count the reference clock signal to detect whether the reference clock signal has a frequency offset.
  • the 19.44MHz signal obtained by dividing the 38.88MHz signal of the local crystal oscillator output is used as a clock counter, and the rising edge of the clock signal with a uniform frequency division of 8KHz is periodically counted, and judged according to the actual count value of the counter and the preset value. Whether the reference clock signal has a frequency offset.
  • the test results obtained in this way are not accurate.
  • the embodiment of the invention provides a frequency offset detection method and device, which solves the problem that the detection result of the frequency offset of the reference clock signal is inaccurate due to the parameter drift caused by the frequency offset and aging of the local crystal oscillator in the prior art. .
  • an embodiment of the present invention provides a frequency offset detection method, including:
  • the tracked reference clock signal is frequency offset detected by the calibrated clock signal of the local crystal oscillator output.
  • the calibrating the frequency offset of the clock signal output by the local crystal oscillator of the network element device includes:
  • the frequency offset of the clock signal output by the local crystal oscillator is externally calibrated according to EXT_CAL.
  • the calculating the external calibration value EXT_CAL according to the first count value X of the first counter and the first reference value X 0 includes:
  • stop the second counter counting clear the second counter, and send a stop signal to the first counter, so that the first counter stops counting and reads the X;
  • ⁇ f represents the reference clock signal input to the local crystal through the external clock interface The frequency of the number.
  • M 3i represents the local crystal oscillator after the externally calibrated by the ith third counter pair
  • M 0 indicates that the i-th third counter counterclocks the rising edge of the externally calibrated clock signal of the local crystal oscillator when the i-th reference clock signal has no frequency offset
  • M 0 X 0 ⁇ (1 + EXT_CAL)
  • the m-way reference clock signal is a clock signal extracted by the local crystal oscillator from the received service signal
  • m is an integer greater than 2
  • i is greater than An integer equal to 1 and less than or equal to m;
  • the frequency offset of the externally calibrated clock signal of the local crystal oscillator is internally calibrated according to INNER_CAL1.
  • m fourth counters respectively respectively refer to m-channel reference clocks Counting a rising edge of the signal, the m-way reference clock signal being a clock signal extracted by the local crystal oscillator from the received service signal;
  • M 4i of the i th fourth counter Determining whether the fourth count value M 4i of the i th fourth counter is greater than or equal to A, and M 4i is a count value for counting the rising edge of the i th path reference clock signal by the i th fourth counter;
  • ⁇ i represents the frequency offset of the i-th reference clock signal with respect to the externally calibrated clock signal of the local crystal oscillator
  • ⁇ f′ represents the frequency offset of the clock signal output by the externally calibrated local crystal oscillator.
  • ⁇ x and ⁇ y respectively represent according to the formula The maximum and minimum values of the calculated m values.
  • the clock signal output by the calibrated local crystal oscillator performs frequency offset detection on the tracked reference clock signal, including:
  • the ppm is one in a million.
  • the frequency offset of the clock signal outputted by the local crystal oscillator of the network element device is calibrated, including:
  • N 5k represents a clock signal output by the kth fifth counter to the local crystal oscillator a rising value of the rising edge, N 0 indicating that the kth reference clock signal has no frequency offset, and the clock signal output by the local crystal oscillator has no frequency offset
  • the kth fifth counter outputs the local crystal oscillator
  • the count value of the count of the rising edge of the clock signal, A ' is a second pre-designed values, A' according to the desired accuracy of the frequency offset of the local crystal oscillator clock signal output by calibrating determined, f '0 indicates the local crystal oscillator clock signal when the output of the frequency offset without
  • the frequency, f k represents the frequency at which the kth reference clock signal has no frequency offset.
  • the n-channel reference clock signal is a clock signal extracted by the local crystal oscillator from the received service signal, n is an integer greater
  • the frequency offset of the clock signal output by the local crystal oscillator is internally calibrated according to INNER_CAL.
  • the calculating the internal part according to the n fifth count values N 5k and the third reference value N 0 of the n fifth counters Calibration value INNER_CAL including:
  • the n sixth The counter counts the rising edges of the n reference clock signals, respectively;
  • N 6k of the kth sixth counter Determining whether the sixth count value N 6k of the kth sixth counter is greater than or equal to A', and N 6k represents a count value of the kth sixth counter counting the rising edge of the kth reference clock signal;
  • ⁇ k represents the frequency offset of the k-th reference clock signal with respect to the clock signal output by the local crystal oscillator
  • ⁇ f′ represents the frequency offset of the clock signal output by the local crystal oscillator
  • ⁇ m and ⁇ n respectively represent According to the formula The maximum and minimum values of the calculated n values.
  • the clock signal output by the calibrated local crystal oscillator is used for performing frequency offset detection on the tracked reference clock signal, including:
  • the ppm is one in a million.
  • an embodiment of the present invention provides a frequency offset detecting apparatus, including:
  • a frequency offset calibration module configured to calibrate a frequency offset of a clock signal output by a local crystal oscillator of the network element device
  • the frequency offset detecting module is configured to perform frequency offset detection on the tracked reference clock signal by using the calibrated clock signal output by the local crystal oscillator.
  • the frequency offset calibration module includes:
  • An external calibration value calculation unit configured to calculate an external calibration value EXT_CAL according to the first count value X of the first counter and the first reference value X 0 , wherein X represents the reference clock input to the local crystal through an external clock interface a count value that the first counter counts a rising edge of a clock signal output by the local crystal oscillator when the signal has no frequency offset, and X 0 indicates that the clock signal output by the local crystal oscillator has no frequency offset, and the external clock interface passes through And inputting, by the first counter, a count value of counting a rising edge of a clock signal output by the local crystal oscillator when the reference clock signal of the local crystal oscillator is not frequency-biased, A is a first pre-designed value, A is determined according to the required accuracy of calibrating the frequency offset of the clock signal output by the local crystal oscillator, and f 0 represents the frequency at which the clock signal output by the local crystal oscillator has no frequency offset, f Representing a frequency at which the reference clock signal input to the local
  • An external calibration unit for externally calibrating the frequency offset of the clock signal output by the local crystal according to EXT_CAL.
  • the external calibration value calculation unit is specifically configured to clear the second counter and the first counter, and simultaneously start the first counter and the second counter to start counting, and the second counter is opposite to the
  • the clock interface inputs a rising edge of the reference clock signal of the local crystal oscillator to count; determines whether the second counter value of the second counter is greater than or equal to A; if yes, stops the second counter counting, and the The second counter is cleared, and sends a stop signal to the first counter, so that the first counter stops counting and reads the X; and calculates EXT_CAL according to the X and the X 0 , Where ⁇ f represents the frequency offset of the reference clock signal input to the local crystal through the external clock interface.
  • the method further includes:
  • a first internal calibration value calculation unit configured to perform m third count values M 3i and second according to m third counters after externally calibrating the frequency offset of the clock signal output by the local crystal oscillator according to EXT_CAL
  • the reference value M 0 is used to calculate an internal calibration value INNER_CAL1, where M 3i represents a count value of the i-th third counter counting the rising edge of the externally calibrated clock signal of the local crystal oscillator, and M 0 represents the i-th
  • the m-way reference clock signal is a clock signal extracted by the local crystal oscillator from the received service signal, m is an integer greater than 2, and i is an integer greater than or equal to 1 and less than or equal to m;
  • the first internal calibration unit is configured to internally calibrate the frequency offset of the externally calibrated clock signal of the local crystal oscillator according to INNER_CAL1.
  • the first internal calibration value calculation unit is specifically configured to clear the m fourth counters and the m third counters, and simultaneously start the m third counters and the m fourth counters to start counting.
  • the m fourth counters respectively count the rising edges of the m-channel reference clock signals, the m-channel reference clock signals are clock signals extracted by the local crystal oscillator from the received service signals; determining the i-th fourth counter Whether the fourth count value M 4i is greater than or equal to A, M 4i represents a count value of the i-th fourth counter counting the rising edge of the i-th reference clock signal; if yes, stopping the ith fourth counter Counting, clearing the ith fourth counter, and sending a stop signal to the ith third counter, so that the ith third counter stops counting and reads the M 3i ; according to the M 3i and the M 0 calculation according to Calculate the internal calibration value INNER_CAL1, Where ⁇ i represents the frequency offset of the i-th reference clock signal with respect to the externally calibrated clock signal
  • the frequency offset calibration module includes:
  • a second internal calibration value calculation unit configured to calculate an internal calibration value INNER_CAL according to the n fifth count values N 5k and the third reference value N 0 of the n fifth counters, wherein N 5k represents the kth fifth counter a count value for counting a rising edge of a clock signal output by the local crystal oscillator, where N 0 indicates that the kth reference clock signal has no frequency offset, and the clock signal output by the local crystal oscillator has no frequency offset, the kth a count value that the fifth counter counts the rising edge of the clock signal output by the local crystal oscillator, A 'is a second pre-designed values, A' according to the desired accuracy of the frequency offset of the local crystal oscillator clock signal output by calibrating determined, f '0 indicates the local crystal oscillator clock signal when the output of the frequency offset without The frequency, f k , represents the frequency at which the kth reference clock signal has no frequency offset.
  • the n-way reference clock signal is a clock signal extracted by the local crystal oscill
  • a second internal calibration unit for internally calibrating the frequency offset of the clock signal output by the local crystal according to INNER_CAL.
  • the second internal calibration value calculation unit is specifically configured to use a count value of the n sixth counters and the n The fifth counter count value is cleared, and the n fifth counters and the n sixth counters are started to start counting, and the n sixth counters respectively count the rising edges of the n reference clock signals Determining whether the sixth count value N 6k of the kth sixth counter is greater than or equal to A', and N 6k represents a count value of the kth sixth counter counting the rising edge of the kth reference clock signal; if yes, Stopping the kth sixth counter, clearing the kth sixth counter, and sending a stop signal to the kth fifth counter, so that the kth fifth counter stops counting and reading Taking the N 5k ; calculating according to the N 5k and the N 0 according to Calculate the internal calibration value INNER_CAL, Where ⁇ k represents the frequency offset of the k-th reference clock signal with respect to the clock signal output
  • the required precision is selected from the p-channel reference clock signal whose frequency offset meets the required accuracy, and the channel clock signal with the smallest absolute value of the frequency offset is selected as the system clock signal of the network element device, where p is greater than or equal to 1 and less than or equal to An integer of n; where ppm is one in a million.
  • the frequency offset detecting method and device of the embodiment of the present invention calibrates the frequency offset of the clock signal output by the local crystal oscillator of the network element device, and performs frequency offset detection on the tracked reference clock signal by the clock signal output by the calibrated local crystal oscillator.
  • the prior art has a frequency offset due to the local crystal oscillator itself. As well as the parameter drift caused by aging, the detection result of the frequency offset of the reference clock signal is inaccurate, and the detection accuracy is improved without replacing the hardware.
  • FIG. 1 is a flowchart of a frequency offset detecting method according to Embodiment 1 of the present invention.
  • FIG. 2 is a flowchart of a frequency offset detecting method according to Embodiment 2 of the present invention.
  • FIG. 3 is a flowchart of a frequency offset detecting method according to Embodiment 3 of the present invention.
  • FIG. 4 is a flowchart of a frequency offset detecting method according to Embodiment 4 of the present invention.
  • FIG. 5 is a schematic structural diagram of a frequency offset detecting apparatus 500 according to Embodiment 5 of the present invention.
  • FIG. 6 is a schematic structural diagram of a frequency offset detecting apparatus 600 according to Embodiment 6 of the present invention.
  • FIG. 7 is a schematic structural diagram of a frequency offset detecting apparatus 700 according to Embodiment 7 of the present invention.
  • FIG. 1 is a flowchart of a frequency offset detecting method according to Embodiment 1 of the present invention.
  • the method of this embodiment is applicable to a case where frequency offset detection is performed on a reference clock signal in an SDH synchronization network.
  • the method is performed by a frequency offset detection device configured in a network element device in an SDH network, the device being typically implemented in hardware and/or software.
  • the method of this embodiment includes the following:
  • the prior art detects whether the reference clock signal has a frequency offset by using a clock signal output by the local crystal oscillator of the network element device to count the reference clock signal.
  • the precondition for detecting whether the reference clock signal has a frequency offset in this way is that the clock signal of the local crystal oscillator output is accurate.
  • the constant crystal oscillator is usually used as the local crystal oscillator of the network element device.
  • the constant temperature crystal oscillator is inevitably present, the frequency offset and the parameter drift caused by aging are present. Bias, resulting in reduced detection accuracy or even false detection. And after the constant temperature crystal oscillator appears frequency offset, it can't be calibrated.
  • the frequency offset problem can only be solved by replacing the hardware.
  • the 110 in this embodiment calibrates the frequency offset of the clock signal output by the local crystal oscillator of the network element device, so that the accuracy of the frequency offset detection of the reference clock signal by the clock signal output by the constant temperature crystal oscillator can be improved to ensure the tracking reference.
  • the clock signal satisfies the requirements of the International Telecommunications Union Telecommunication Standardization Sector (ITU-T) G.813.
  • the frequency deviation detection of the tracked reference clock signal by the clock signal outputted by the calibrated local crystal oscillator in 120 can compensate for the deviation of the frequency deviation detection of the reference clock signal due to the frequency offset of the clock signal output by the local crystal oscillator, and obtain accurate Test results.
  • the frequency offset detecting method provided in this embodiment performs frequency offset detection on the tracked reference clock signal by the clock signal outputted by the calibrated local crystal oscillator, thereby improving the accuracy of detecting the frequency offset of the reference clock signal by the clock signal output by the local crystal oscillator. It ensures that the accuracy of the tracked reference clock signal meets the requirements of ITU-T G.813.
  • FIG. 2 is a flowchart of a frequency offset detecting method according to Embodiment 2 of the present invention.
  • the frequency offset of the clock signal outputted by the local crystal oscillator is externally calibrated, and the reference clock signal is detected by the externally calibrated clock signal output by the local crystal oscillator.
  • the method in this embodiment may include:
  • X represents the count value of the first counter counting the rising edge of the local crystal oscillator output signal when the reference clock signal input to the local crystal oscillator through the external clock interface has no frequency offset
  • X 0 indicates that the clock signal of the local crystal oscillator output has no frequency offset.
  • the first counter counts the rising edge of the clock signal output by the local crystal oscillator
  • A is the first pre-designed value
  • A is determined according to the required accuracy of calibrating the frequency offset of the clock signal output from the local crystal oscillator
  • f 0 is the frequency at which the clock signal of the local crystal oscillator output is not frequency-biased
  • f is the external clock. The frequency at which the interface input local crystal oscillator's reference clock signal has no frequency offset.
  • a high-stability constant-temperature crystal oscillator is generally used as the local crystal oscillator. Assume that the frequency offset of the reference clock signal input to the local crystal through the external clock interface is 0, and the reference clock signal input to the local crystal through the external clock interface is counted for A period, and the time taken to count A cycles is A/f, the unit In seconds, the first counter counts the rising edge of the clock signal output by the local crystal oscillator in the same time as the value of X.
  • the first counter value X of the first counter in the same counting period is larger, that is, the first count.
  • the value X is greater than X 0 ; when the clock signal output by the local crystal oscillator is negatively biased, the count value X of the first counter is less than X 0 .
  • the difference between the count value X of the first counter and X 0 reflects the frequency offset of the clock signal output by the local crystal oscillator. Further, the frequency offset of the clock signal output by the local crystal oscillator can be calculated according to the difference between X and X 0 .
  • calculating the external calibration value EXT_CAL according to the first count value X of the first counter and the first reference value X 0 can be obtained in the following manner:
  • the process of determining whether the second counter value of the second counter is greater than or equal to A is If it is determined that the second count value of the second counter is less than A, the second counter is controlled to continue counting the rising edge of the reference clock signal input to the local crystal through the external clock interface.
  • EXT_CAL is also the frequency offset of the clock signal output by the local crystal oscillator. According to the external calibration value EXT_CAL, the frequency offset detection can be performed on the reference clock signal input to the local crystal through the external clock interface.
  • EXT_CAL is calculated in 210 to 220, when the tracking reference signal is subjected to frequency offset detection, the detection result can be corrected to obtain an accurate detection result.
  • the frequency offset detection method provided in this embodiment performs external calibration on the frequency offset of the clock signal output by the local crystal oscillator according to EXT_CAL by calculating EXT_CAL, and frequency-shifts the tracked reference clock signal by the clock signal outputted by the calibrated local crystal oscillator.
  • the detection improves the accuracy of the frequency offset detection of the reference clock signal by the clock signal output by the local crystal oscillator, and ensures that the accuracy of the tracked reference clock signal satisfies the requirements of ITU-T G.813.
  • FIG. 3 is a flowchart of a frequency offset detecting method according to Embodiment 3 of the present invention.
  • the frequency offset of the clock signal outputted by the local crystal oscillator is externally calibrated, and after external calibration, the internal calibration is performed, and the reference clock signal is frequency-biased by the external calibration and the internal calibration of the local crystal oscillator output clock signal. Detection.
  • the method in this embodiment may include:
  • M 3i represents a count value of the i-th third counter counting the rising edge of the clock signal outputted by the externally calibrated local crystal oscillator
  • M 0 represents the i-th third when the i-th reference clock signal has no frequency offset.
  • the clock signal, m is an integer greater than 2
  • i is an integer greater than or equal to 1 and less than or equal to m.
  • the calculation of the internal calibration value INNER_CAL1 can be obtained in the following manner:
  • the reference clock signal is a clock signal extracted by the local crystal oscillator from the received service signal; determining whether the fourth count value M 4i of the i-th fourth counter is greater than or equal to A, and M 4i represents the i-th fourth counter to the i-th reference Counting value of the rising edge of the clock signal; if yes, stopping the ith fourth counter counting, clearing the ith fourth counter, and sending a stop signal to the ith third counter, so that the ith
  • the third counter stops counting and reads M 3i ; is calculated according to M 3i and M 0 according to Calculate the internal calibration value INNER_CAL1, Where ⁇ i represents the frequency offset of the i-th reference clock signal with respect to the externally calibrated local crystal oscillator output clock signal, and ⁇ f' represents
  • the frequency offset detection of the tracked reference clock signal by the calibrated clock signal of the local crystal oscillator can be obtained by:
  • Calculating the frequency offset ⁇ f i of the i-th reference clock signal Determine whether the formula -4.6ppm ⁇ ⁇ f i ⁇ 4.6ppm is established; if the formula -4.6ppm ⁇ ⁇ f i ⁇ 4.6ppm is established, it is determined that the frequency offset of the i-th reference clock signal satisfies the required accuracy;
  • the j-channel reference clock signal of the required precision selects one channel reference clock signal with the smallest absolute value of the frequency offset as the system clock signal of the network element device, and j is an integer greater than or equal to 1 and less than or equal to m; wherein, ppm is millions of points one.
  • the frequency offset detection method provided in this embodiment performs external calibration on the frequency offset of the clock signal output by the local crystal oscillator according to EXT_CAL by calculating EXT_CAL, and further calculates INNER_CAL1 after external calibration, and externally calibrated according to INNER_CAL1.
  • the frequency offset of the clock signal output by the crystal oscillator is internally calibrated, and the frequency offset detection of the tracked reference clock signal is performed by the external calibration and the internal calibration of the local crystal oscillator output clock signal, thereby improving the clock signal to the reference clock using the local crystal oscillator output.
  • the accuracy of the frequency offset detection of the signal ensures that the accuracy of the tracked reference clock signal meets the requirements of ITU-T G.813.
  • the frequency offset of the clock signal output by the local crystal oscillator is internally calibrated, and the reference clock signal is detected by the internal calibration of the clock signal output by the local crystal oscillator.
  • the method in this embodiment may include:
  • N 5k represents a count value of the k-th fifth counter counting the rising edge of the clock signal output by the local crystal oscillator
  • N 0 represents that the k-th reference clock signal has no frequency offset
  • the clock signal output by the local crystal oscillator has no frequency.
  • the count value of counting the rising edge of the clock signal output by the local crystal oscillator by the kth fifth counter when biasing, A ' is a second pre-designed values, A' according to the desired accuracy of the frequency offset of the local oscillator output clock signal for calibrating the determination
  • f '0 represents the frequency of the local oscillator clock signal when the output without a frequency offset
  • f k Indicates the frequency at which the kth reference clock signal has no frequency offset.
  • the n-way reference clock signal is a clock signal extracted by the local crystal oscillator from the received service signal, n is an integer greater than 2, and k is an integer greater than or equal to 1 and less than or equal to n.
  • the calculation of the internal calibration value INNER_CAL can be obtained in the following manner:
  • n sixth counters Clearing the count value of the n sixth counters and the count counters of the n fifth counts, simultaneously starting n fifth counters and n sixth counters to start counting, and n sixth counters respectively respectively n-way reference clock signals a rising edge count; determining whether the sixth count value N 6k of the kth sixth counter is greater than or equal to A', and N 6k represents a count value of the kth sixth counter counting the rising edge of the kth reference clock signal; If yes, stop the kth sixth counter counting, clear the kth sixth counter, and send a stop signal to the kth fifth counter, so that the kth fifth counter stops counting and reads N 5k ; Calculated according to N 5k and N 0 according to Calculate the internal calibration value INNER_CAL, Where ⁇ k represents the frequency offset of the k-th reference clock signal with respect to the clock signal output by the local crystal oscillator, ⁇ f' represents the frequency offset of the clock signal output by the local crystal oscillator, and ⁇
  • the frequency offset detection of the tracked reference clock signal by the calibrated clock signal of the local crystal oscillator can be obtained by:
  • the frequency offset detection method provided in this embodiment performs internal calibration by calculating INNER_CAL and frequency offset of the clock signal output by the local crystal oscillator according to INNER_CAL, and frequency-tracking the referenced reference clock signal by the internally calibrated clock signal of the local crystal oscillator output.
  • the bias detection improves the accuracy of the frequency offset detection of the reference clock signal by the clock signal output by the local crystal oscillator, and ensures that the accuracy of the tracked reference clock signal satisfies the requirements of ITU-T G.813.
  • FIG. 5 is a schematic structural diagram of a frequency offset detecting apparatus 500 according to Embodiment 5 of the present invention.
  • the apparatus of this embodiment is applicable to a case where frequency offset detection is performed on a reference clock signal in an SDH synchronization network.
  • the device is typically implemented in hardware and/or software.
  • the frequency offset detecting apparatus includes the following modules: a frequency offset calibration module 510 and a frequency offset detecting module 520.
  • the frequency offset calibration module 510 is configured to calibrate the frequency offset of the clock signal output by the local crystal oscillator of the network element device; the frequency offset detection module 520 is configured to perform frequency offset on the tracked reference clock signal by using the clock signal of the calibrated local crystal oscillator output. Detection.
  • the frequency offset detecting apparatus performs frequency offset detection on the tracked reference clock signal by the clock signal outputted by the calibrated local crystal oscillator, thereby improving the accuracy of detecting the frequency offset of the reference clock signal by the clock signal output by the local crystal oscillator. It ensures that the accuracy of the tracked reference clock signal meets the requirements of ITU-T G.813.
  • FIG. 6 is a schematic structural diagram of a frequency offset detecting apparatus 600 according to Embodiment 6 of the present invention.
  • the frequency offset calibration module 510 specifically includes the following units: an external calibration value calculation unit 511 and an external calibration unit 512 .
  • the external calibration value calculation unit 511 is configured to calculate an external calibration value EXT_CAL according to the first count value X of the first counter and the first reference value X 0 , where X represents a reference clock signal input to the local crystal oscillator through the external clock interface without frequency offset
  • X 0 indicates that the clock signal of the local crystal oscillator output has no frequency offset
  • the reference clock signal input to the local crystal oscillator through the external clock interface has no frequency offset.
  • the count value of the count of the rising edge of the clock signal, A is the first pre-designed value, A is determined according to the required accuracy of the calibration of the frequency offset of the local crystal oscillator output signal, f 0 represents the frequency of the local crystal oscillator output clock signal without frequency offset, and f represents the external clock
  • the interface inputs the frequency of the reference clock signal of the local crystal without frequency offset; the external calibration unit 512 is used for externally calibrating the frequency offset of the clock signal output by the local crystal according to EXT_CAL.
  • the external calibration value calculation unit 511 is specifically configured to clear the second counter and the first counter, simultaneously start the first counter and the second counter to start counting, and the second counter inputs the reference clock signal of the local crystal through the external clock interface.
  • the rising edge of the counting is performed; determining whether the second counter value of the second counter is greater than or equal to A; if yes, stopping the second counter counting, clearing the second counter, and sending a stop signal to the first counter to cause the first counter Stop counting and read X; calculate EXT_CAL based on X and X 0 , Where ⁇ f represents the frequency offset of the reference clock signal input to the local crystal through the external clock interface.
  • the frequency offset calibration module 510 may further include the following units: a first internal calibration value calculation unit and a first internal calibration unit.
  • a first internal calibration value calculation unit configured to perform m third count values M 3i and second reference values M 0 of the m third counters after externally calibrating the frequency offset of the clock signal output by the local crystal oscillator according to EXT_CAL Calculate the internal calibration value INNER_CAL1, where M 3i represents the count value of the i-th third counter counting the rising edge of the externally calibrated local crystal oscillator output signal, and M 0 represents the i-th reference clock signal without frequency
  • the clock signal extracted from the received service signal m is an integer greater than 2, and i is an integer greater than or equal to 1 and less than or equal to m.
  • the first internal calibration unit is used for internally calibrating the frequency offset of the externally calibrated local crystal oscillator output signal according to INNER_CAL1.
  • the first internal calibration value calculation unit is specifically configured to clear m fourth counters and m third counters, simultaneously start m third counters and m fourth counters to start counting, and m fourth counters
  • the rising edge of the m-channel reference clock signal is respectively counted, and the m-channel reference clock signal is a clock signal extracted by the local crystal oscillator from the received service signal; determining whether the fourth count value M 4i of the i-th fourth counter is greater than or equal to A, M 4i represents the count value of the i-th fourth counter counting the rising edge of the i-th reference clock signal; if yes, stopping the i-th fourth counter count, clearing the ith fourth counter, and
  • the i third counters send a stop signal to stop the i th third counter and read M 3i ; calculate according to M 3i and M 0 according to Calculate the internal calibration value INNER_CAL1, Where ⁇ i represents the frequency offset of the i-th reference clock signal with respect to the externally calibrated local crystal oscillator
  • the frequency offset detection module 520 is specifically configured to calculate a frequency offset ⁇ f i of the i-th reference clock signal, Determine whether the formula -4.6ppm ⁇ ⁇ f i ⁇ 4.6ppm is established; if the formula -4.6ppm ⁇ ⁇ f i ⁇ 4.6ppm is established, it is determined that the frequency offset of the i-th reference clock signal satisfies the required accuracy;
  • the j-channel reference clock signal of the required precision selects one channel reference clock signal with the smallest absolute value of the frequency offset as the system clock signal of the network element device, and j is an integer greater than or equal to 1 and less than or equal to m; wherein, ppm is millions of points one.
  • the frequency offset detecting apparatus performs frequency offset detection on the tracked reference clock signal by the clock signal outputted by the calibrated local crystal oscillator, thereby improving the accuracy of detecting the frequency offset of the reference clock signal by the clock signal output by the local crystal oscillator. It ensures that the tracked reference clock signal meets the requirements of ITU-TG.813.
  • FIG. 7 is a schematic structural diagram of a frequency offset detecting apparatus 700 according to Embodiment 7 of the present invention.
  • the frequency offset calibration module 510 specifically includes the following units: a second internal calibration value calculation unit 710 and a second internal calibration unit 720.
  • the second internal calibration value calculation unit 710 is configured to calculate an internal calibration value INNER_CAL according to the n fifth count values N 5k and the third reference value N 0 of the n fifth counters, where N 5k represents the kth fifth counter
  • the count value of counting the rising edge of the clock signal of the local crystal oscillator output, N 0 indicates that the kth fifth counter counters the local crystal oscillator when the k-th reference clock signal has no frequency offset and the clock signal of the local crystal oscillator output has no frequency offset
  • the count value of the counted edge of the output clock signal, A ' is a second pre-designed values, A' according to the desired accuracy of the frequency offset of the local oscillator output clock signal for calibrating the determination, f '0 represents the frequency of the local oscillator clock signal when the output without a frequency offset, f k Indicates the frequency at which the kth reference clock signal has no frequency offset.
  • the n-way reference clock signal is a clock signal extracted by the local crystal oscillator from the received service signal, n is an integer greater than 2, k is an integer greater than or equal to 1 and less than or equal to n; and the second internal calibration unit 720 is configured to locally according to INNER_CAL The frequency offset of the clock signal from the crystal output is internally calibrated.
  • the second internal calibration value calculation unit 710 is specifically configured to clear the count value of the n sixth counters and the count counters of the n fifth counts, and start n fifth counters and n sixth counters to start.
  • Counting, n sixth counters respectively count the rising edges of the n-way reference clock signals; determining whether the sixth counter value N 6k of the k-th sixth counter is greater than or equal to A', and N 6k represents the k-th sixth counter pair Counting value of the rising edge of the k-channel reference clock signal; if yes, stopping the kth sixth counter counting, clearing the kth sixth counter, and transmitting a stop signal to the kth fifth counter, so that The kth fifth counter stops counting and reads N 5k ; calculates according to N 5k and N 0 according to Calculate the internal calibration value INNER_CAL, Where ⁇ k represents the frequency offset of the k-th reference clock signal with respect to the clock signal output by the local crystal oscillator, ⁇ f' represents the frequency offset
  • the one reference clock signal signal having the smallest value is used as the system clock signal of the network element device, and p is an integer greater than or equal to 1 and less than or equal to n; wherein, ppm is one in a million.
  • the frequency offset detecting apparatus performs frequency offset detection on the tracked reference clock signal by the clock signal outputted by the local crystal oscillator after internal calibration, thereby improving the frequency offset detection of the reference clock signal by the clock signal output by the local crystal oscillator. Accuracy ensures that the tracked reference clock signal meets ITU-T G.813 requirements.
  • the aforementioned program can be stored in a computer readable storage medium.
  • the program when executed, includes the above-described various method embodiments; and the foregoing storage medium includes various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

本发明实施例提供一种频偏检测方法和装置。本发明频偏检测方法，包括：对网元设备的本地晶振输出的时钟信号的频偏进行校准，通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。本发明实施例解决了现有技术中由于本地晶振自身存在频偏以及老化带来的参数漂移，导致对参考时钟信号的频偏的检测结果不准确的问题，实现了在不更换硬件的前提下提高检测精度。

Description

频偏检测方法和装置
本申请要求申请日为2013年9月30日，申请号为201310465515.4，名称为“频偏检测方法和装置”的中国专利申请的优先权。
技术领域
本发明实施例涉及通信技术，尤其涉及一种频偏检测方法和装置。
背景技术
同步数字序列(Synchronnous Digital Hierarchy，简称SDH)网络采用分级的主从同步方式，即用单一基准时钟(Primary Reference Clock，简称PRC)经同步分配网的同步链路控制全网同步，SDH网络使用一系列分级时钟，每一级时钟都与其上一级时钟或同一级时钟同步。SDH网络中的本级网元设备将其跟踪的上一级网元设备传输的时钟信号作为参考时钟信号，并继续向其下一级网元设备传输该参考时钟信号。但由于参考时钟信号受复杂因素的影响在传输过程中发生了频偏，因此，各级网元设备需要对参考时钟信号进行频偏检测。
现有技术中采用网元设备的本地晶振输出的时钟信号对参考时钟信号计数的方式来检测参考时钟信号是否发生了频偏。即将本地晶振输出的38.88MHz信号二分频后得到的19.44MHz信号作为时钟计数器，对统一分频为8KHz的时钟信号的上升沿进行周期计数，根据计数器的实际的计数值与预设值来判断参考时钟信号是否发生了频偏。然而采用这种方式获得的检测结果是不准确的。
发明内容
本发明实施例提供一种频偏检测方法和装置，以解决现有技术中由于本地晶振自身存在频偏以及老化带来的参数漂移，导致对参考时钟信号的频偏的检测结果不准确的问题。
第一方面，本发明实施例提供一种频偏检测方法，包括：
对网元设备的本地晶振输出的时钟信号的频偏进行校准；
通过校准后的所述本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
在第一方面的第一种可能的实现方式中，所述对网元设备的本地晶振输出的时钟信号的频偏进行校准，包括：
根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL，其中，X表示通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时所述第一计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，X0表示所述本地晶振输出的时钟信号无频偏、且所述通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时所述第一计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，
Figure PCTCN2014086674-appb-000001
A为第一预设计数值，A根据所需的对所述本地晶振输出的时钟信号的频偏进行校准的精度确定，f0表示所述本地晶振输出的时钟信号无频偏时的频率，f表示所述通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时的频率；
根据EXT_CAL对所述本地晶振输出的时钟信号的频偏进行外部校准。
根据第一方面的第一种可能的实现方式，在第二种可能的实现方式中，
所述根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL，包括：
将第二计数器和所述第一计数器清零，同时启动所述第一计数器和所述第二计数器开始计数，所述第二计数器对所述通过外时钟接口输入所述本地晶振的所述参考时钟信号的上升沿进行计数；
确定所述第二计数器的第二计数值是否大于等于A；
若是，则停止所述第二计数器计数，将所述第二计数器清零，并向所述第一计数器发送停止信号，以使所述第一计数器停止计数并读取所述X；
根据所述X和所述X0计算EXT_CAL，
Figure PCTCN2014086674-appb-000002
其中，△f表示所述通过外时钟接口输入所述本地晶振的所述参考时钟信 号的频偏。
根据第一方面的第一种或第二种可能的实现方式，在第三种可能的实现方式中，在所述根据EXT_CAL对所述本地晶振输出的时钟信号的频偏进行外部校准之后，还包括：
根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1，其中，M3i表示第i个第三计数器对经过外部校准后的所述本地晶振输出的时钟信号的上升沿进行计数的计数值，M0表示第i路参考时钟信号无频偏时第i个第三计数器对经过外部校准后的所述本地晶振输出的时钟信号的上升沿进行计数的计数值，M0＝X0×(1+EXT_CAL)，所述m路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号，m为大于2的整数，i为大于等于1且小于等于m的整数；
根据INNER_CAL1对经过外部校准后的所述本地晶振输出的时钟信号的频偏进行内部校准。
根据第一方面的第三种可能的实现方式，在第四种可能的实现方式中，所述根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1，包括：
将m个第四计数器和所述m个第三计数器清零，同时启动所述m个第三计数器和所述m个第四计数器开始计数，所述m个第四计数器分别对m路参考时钟信号的上升沿计数，所述m路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号；
确定第i个第四计数器的第四计数值M4i是否大于等于A，M4i表示所述第i个第四计数器对第i路参考时钟信号的上升沿进行计数的计数值；
若是，则停止所述第i个第四计数器计数，将所述第i个第四计数器清零，并向第i个第三计数器发送停止信号，以使所述第i个第三计数器停止计数并读取所述M3i；
根据所述M3i和所述M0计算
Figure PCTCN2014086674-appb-000003
根据
Figure PCTCN2014086674-appb-000004
计算内部校准值INNER_CAL1，
Figure PCTCN2014086674-appb-000005
其中，△i表示第i路参考时钟信号相对于经过外部校准后的所述本地晶振输出的时钟信号的频偏，△f'表示经过外部校准后的所述本地晶振输出的时钟信号的频偏，△x和△y分别表示根据公式
Figure PCTCN2014086674-appb-000006
计算出的m个数值中的最大值和最小值。
根据第一方面的第四种可能的实现方式，在第五种可能的实现方式中，所述通过校准后的所述本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，包括：
计算所述第i路参考时钟信号的频偏△fi，△fi＝△i+EXT_CAL+INNER_CAL1；
确定公式-4.6ppm≤△fi≤4.6ppm是否成立；
若公式-4.6ppm≤△fi≤4.6ppm成立，则确定第i路参考时钟信号的频偏满足所需的精度；
从频偏满足所需的精度的j路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号作为所述网元设备的系统时钟信号，j为大于等于1小于等于m的整数；
其中，ppm为百万分之一。
根据第一方面，在第六种可能的实现方式中，所述对网元设备的本地晶振输出的时钟信号的频偏进行校准，包括：
根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL，其中，N5k表示第k个第五计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，N0表示第k路参考时钟信号无频偏时、且所述本地晶振输出的时钟信号无频偏时所述第k个第五计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，
Figure PCTCN2014086674-appb-000007
A'为第二预设计数值，A'根据所需的对所述本地晶振输出的时钟信号的频偏进行校准的精度确定，f′0表示所述本地晶振输出的时钟信号无频偏时的频率，fk表示所述 第k路参考时钟信号无频偏时的频率。所述n路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号，n为大于2的整数，k为大于等于1且小于等于n的整数；
根据INNER_CAL对所述本地晶振输出的时钟信号的频偏进行内部校准。
根据第一方面的第六种可能的实现方式，在第七种可能的实现方式中，所述根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL，包括：
将n个第六计数器的计数值和所述n个第五计数的计数值器清零，同时启动所述n个第五计数器和所述n个第六计数器开始计数，所述n个第六计数器分别对所述n路参考时钟信号的上升沿计数；
确定第k个第六计数器的第六计数值N6k是否大于等于A'，N6k表示所述第k个第六计数器对第k路参考时钟信号的上升沿进行计数的计数值；
若是，则停止所述第k个第六计数器计数，将所述第k个第六计数器清零，并向第k个第五计数器发送停止信号，以使所述第k个第五计数器停止计数并读取所述N5k；
根据所述N5k和所述N0计算
Figure PCTCN2014086674-appb-000008
根据
Figure PCTCN2014086674-appb-000009
计算内部校准值INNER_CAL，
Figure PCTCN2014086674-appb-000010
其中，△k表示所述第k路参考时钟信号相对于所述本地晶振输出的时钟信号的频偏，△f'表示所述本地晶振输出的时钟信号的频偏，△m和△n分别表示根据公式
Figure PCTCN2014086674-appb-000011
计算出的n个数值中的最大值和最小值。
根据第一方面的第七种可能的实现方式，在第八种可能的实现方式中，所述通过校准后的所述本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，包括：
计算所述第k路参考时钟信号的频偏△fk，△fk＝△k+INNER_CAL；
确定公式-4.6ppm≤△fk≤4.6ppm是否成立；
若公式-4.6ppm≤△fk≤4.6ppm成立，则确定第k路参考时钟信号的频偏满足所需的精度；
从频偏满足所需的精度的p路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号信号作为所述网元设备的系统时钟信号，p为大于等于1小于等于n的整数；
其中，ppm为百万分之一。
第二方面，本发明实施例提供一种频偏检测装置，包括：
频偏校准模块，用于对网元设备的本地晶振输出的时钟信号的频偏进行校准；
频偏检测模块，用于通过校准后的所述本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
在第二方面的第一种可能的实现方式中，所述频偏校准模块包括：
外部校准值计算单元，用于根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL，其中，X表示通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时所述第一计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，X0表示所述本地晶振输出的时钟信号无频偏、且所述通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时所述第一计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，
Figure PCTCN2014086674-appb-000012
A为第一预设计数值，A根据所需的对所述本地晶振输出的时钟信号的频偏进行校准的精度确定，f0表示所述本地晶振输出的时钟信号无频偏时的频率，f表示所述通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时的频率；
外部校准单元，用于根据EXT_CAL对所述本地晶振输出的时钟信号的频偏进行外部校准。
根据第二方面的第一种可能的实现方式，在第二种可能的实现方式中，
所述外部校准值计算单元，具体用于将第二计数器和所述第一计数器清 零，同时启动所述第一计数器和所述第二计数器开始计数，所述第二计数器对所述通过外时钟接口输入所述本地晶振的所述参考时钟信号的上升沿进行计数；确定所述第二计数器的第二计数值是否大于等于A；若是，则停止所述第二计数器计数，将所述第二计数器清零，并向所述第一计数器发送停止信号，以使所述第一计数器停止计数并读取所述X；根据所述X和所述X0计算EXT_CAL，
Figure PCTCN2014086674-appb-000013
其中，△f表示所述通过外时钟接口输入所述本地晶振的所述参考时钟信号的频偏。
根据第二方面的第一种或第二种可能的实现方式，在第三种可能的实现方式中，还包括：
第一内部校准值计算单元，用于在所述根据EXT_CAL对所述本地晶振输出的时钟信号的频偏进行外部校准之后，根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1，其中，M3i表示第i个第三计数器对经过外部校准后的所述本地晶振输出的时钟信号的上升沿进行计数的计数值，M0表示第i路参考时钟信号无频偏时第i个第三计数器对经过外部校准后的所述本地晶振输出的时钟信号的上升沿进行计数的计数值，M0＝X0×(1+EXT_CAL)，所述m路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号，m为大于2的整数，i为大于等于1且小于等于m的整数；
第一内部校准单元，用于根据INNER_CAL1对经过外部校准后的所述本地晶振输出的时钟信号的频偏进行内部校准。
根据第二方面的第三种可能的实现方式，在第四种可能的实现方式中，
所述第一内部校准值计算单元，具体用于将m个第四计数器和所述m个第三计数器清零，同时启动所述m个第三计数器和所述m个第四计数器开始计数，所述m个第四计数器分别对m路参考时钟信号的上升沿计数，所述m路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号；确定第i个第四计数器的第四计数值M4i是否大于等于A，M4i表示所述第i个第四计数器对第i路参考时钟信号的上升沿进行计数的计数值；若是，则停止所 述第i个第四计数器计数，将所述第i个第四计数器清零，并向第i个第三计数器发送停止信号，以使所述第i个第三计数器停止计数并读取所述M3i；根据所述M3i和所述M0计算
Figure PCTCN2014086674-appb-000014
根据
Figure PCTCN2014086674-appb-000015
计算内部校准值INNER_CAL1，
Figure PCTCN2014086674-appb-000016
其中，△i表示第i路参考时钟信号相对于经过外部校准后的所述本地晶振输出的时钟信号的频偏，△f'表示经过外部校准后的所述本地晶振输出的时钟信号的频偏，△x和△y分别表示根据公式
Figure PCTCN2014086674-appb-000017
计算出的m个数值中的最大值和最小值。
根据第二方面的第四种可能的实现方式，在第五种可能的实现方式中，所述频偏检测模块，具体用于计算所述第i路参考时钟信号的频偏△fi，△fi＝△i+EXT_CAL+INNER_CAL1；确定公式-4.6ppm≤△fi≤4.6ppm是否成立；若公式-4.6ppm≤△fi≤4.6ppm成立，则确定第i路参考时钟信号的频偏满足所需的精度；从频偏满足所需的精度的j路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号作为所述网元设备的系统时钟信号，j为大于等于1小于等于m的整数；其中，ppm为百万分之一。
根据第二方面，在第六种可能的实现方式中，所述频偏校准模块，包括：
第二内部校准值计算单元，用于根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL，其中，N5k表示第k个第五计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，N0表示第k路参考时钟信号无频偏时、且所述本地晶振输出的时钟信号无频偏时所述第k个第五计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，
Figure PCTCN2014086674-appb-000018
A'为第二预设计数值，A'根据所需的对所述本地晶振输出的时钟信号的频偏进行校准的精度确定，f′0表示所述本地晶振输出的时钟信号无频偏时的频率，fk表示所述第k路参考时钟信号无频偏时的频率。所述n路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号，n 为大于2的整数，k为大于等于1且小于等于n的整数；
第二内部校准单元，用于根据INNER_CAL对所述本地晶振输出的时钟信号的频偏进行内部校准。
根据第二方面的第六种可能的实现方式，在第七种可能的实现方式中，所述第二内部校准值计算单元，具体用于将n个第六计数器的计数值和所述n个第五计数的计数值器清零，同时启动所述n个第五计数器和所述n个第六计数器开始计数，所述n个第六计数器分别对所述n路参考时钟信号的上升沿计数；确定第k个第六计数器的第六计数值N6k是否大于等于A'，N6k表示所述第k个第六计数器对第k路参考时钟信号的上升沿进行计数的计数值；若是，则停止所述第k个第六计数器计数，将所述第k个第六计数器清零，并向第k个第五计数器发送停止信号，以使所述第k个第五计数器停止计数并读取所述N5k；根据所述N5k和所述N0计算
Figure PCTCN2014086674-appb-000019
根据
Figure PCTCN2014086674-appb-000020
计算内部校准值INNER_CAL，
Figure PCTCN2014086674-appb-000021
其中，△k表示所述第k路参考时钟信号相对于所述本地晶振输出的时钟信号的频偏，△f'表示所述本地晶振输出的时钟信号的频偏，△m和△n分别表示根据公式
Figure PCTCN2014086674-appb-000022
计算出的n个数值中的最大值和最小值。
根据第二方面的第七种可能的实现方式，在第八种可能的实现方式中，所述频偏检测模块，具体用于计算所述第k路参考时钟信号的频偏△fk，△fk＝△k+INNER_CAL；确定公式-4.6ppm≤△fk≤4.6ppm是否成立；若公式-4.6ppm≤△fk≤4.6ppm成立，则确定第k路参考时钟信号的频偏满足所需的精度；从频偏满足所需的精度的p路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号信号作为所述网元设备的系统时钟信号，p为大于等于1小于等于n的整数；其中，ppm为百万分之一。
本发明实施例频偏检测方法和装置，通过对网元设备的本地晶振输出的时钟信号的频偏进行校准，通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，解决了现有技术中由于本地晶振自身存在频偏 以及老化带来的参数漂移，导致对参考时钟信号的频偏的检测结果不准确的问题，并且实现了在不更换硬件的前提下提高了检测精度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例一所提供的频偏检测方法的流程图；
图2为本发明实施例二所提供的频偏检测方法的流程图；
图3为本发明实施例三所提供的频偏检测方法的流程图；
图4为本发明实施例四所提供的频偏检测方法的流程图；
图5为本发明实施例五所提供的频偏检测装置500的结构示意图；
图6为本发明实施例六所提供的频偏检测装置600的结构示意图；
图7为本发明实施例七所提供的频偏检测装置700的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1为本发明实施例一所提供的频偏检测方法的流程图。本实施例的方法适用于SDH同步网络中对参考时钟信号进行频偏检测的情况。该方法由配置在SDH网络中的网元设备中的频偏检测装置执行，该装置通常以硬件和/或软件的方式来实现。本实施例的方法包括如下：
110、对网元设备的本地晶振输出的时钟信号的频偏进行校准。
由于现有技术中采用网元设备的本地晶振输出的时钟信号对参考时钟信号计数的方式来检测参考时钟信号是否发生了频偏。然而采用这种方式检测参考时钟信号是否发生频偏的前提条件是本地晶振输出的时钟信号是精确、 无频偏的，为了保证本地晶振输出的时钟信号精确，通常采用恒温晶振作为网元设备的本地晶振，但由于恒温晶振出厂时自身也不可避免的存在频偏以及老化引起的参数漂移而存在频偏，导致检测精度下降甚至误检。并且在恒温晶振出现频偏后无法校准，只能通过更换硬件解决频偏问题。本实施例中的110通过对网元设备的本地晶振输出的时钟信号的频偏进行校准，从而可以提高采用恒温晶振输出的时钟信号对参考时钟信号的频偏检测的精度，以保证跟踪的参考时钟信号满足国际电信联盟远程通信标准化组织(International Telecommunications Union Telecommunication Standardization Sector，简称ITU-T)G.813要求。
120、通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
120中通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，可以弥补本地晶振输出的时钟信号因频偏导致对参考时钟信号的频偏检测的偏差，获取到精确的检测结果。
本实施例提供的频偏检测方法，通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，提高了采用本地晶振输出的时钟信号对参考时钟信号的频偏检测的精度，保证了跟踪的参考时钟信号的精度满足ITU-T G.813要求。
本实施例以上述实施例一为基础，进一步进行了优化。图2为本发明实施例二所提供的频偏检测方法的流程图。本实施例通过对本地晶振输出的时钟信号的频偏进行外部校准，通过外部校准后的本地晶振输出的时钟信号对参考时钟信号进行频偏检测。参照图2，本实施例的方法可以包括：
210、根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL。
其中，X表示通过外时钟接口输入本地晶振的参考时钟信号无频偏时第一计数器对本地晶振输出的时钟信号的上升沿进行计数的计数值，X0表示本地晶振输出的时钟信号无频偏、且通过外时钟接口输入本地晶振的参考时钟信号无频偏时第一计数器对本地晶振输出的时钟信号的上升沿进行计数的计数值，
Figure PCTCN2014086674-appb-000023
A为第一预设计数值，A根据所需的对本地晶振输出的时 钟信号的频偏进行校准的精度确定，f0表示本地晶振输出的时钟信号无频偏时的频率，f表示通过外时钟接口输入本地晶振的参考时钟信号无频偏时的频率。
需要说明的是，在实际应用中，通常采用高稳定度的恒温晶振作为本地晶振。假设通过外时钟接口输入本地晶振的参考时钟信号的频偏为0，且对通过外时钟接口输入本地晶振的参考时钟信号计数A个周期，则计数A个周期所用的时间为A/f，单位为秒，第一计数器在同样的时间内对本地晶振输出的时钟信号的上升沿进行计数的计数值为X。从公式
Figure PCTCN2014086674-appb-000024
中可知，当本地晶振输出的时钟信号的频率大于f0，也即本地晶振输出的时钟信号正频偏时，则相同计数周期内第一计数器的第一计数值X越大，即第一计数值X大于X0；当本地晶振输出的时钟信号负频偏时，第一计数器的计数值X小于X0。第一计数器的计数值X与X0的差值反应了本地晶振输出的时钟信号的频偏大小，进一步的，可以根据X与X0的差值计算出本地晶振输出的时钟信号的频偏。
举例来说，根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL可以采用下述方式得到：
将第二计数器和第一计数器清零，同时启动第一计数器和第二计数器开始计数，第二计数器对通过外时钟接口输入本地晶振的参考时钟信号的上升沿进行计数；确定第二计数器的第二计数值是否大于等于A；若是，则停止第二计数器计数，将第二计数器清零，并向第一计数器发送停止信号，以使第一计数器停止计数并读取X；根据X和X0计算EXT_CAL，
Figure PCTCN2014086674-appb-000025
其中，△f表示通过外时钟接口输入本地晶振的参考时钟信号的频偏。
需要说明的是，在确定第二计数器的第二计数值是否大于等于A的过程 中，如果确定第二计数器的第二计数值小于A，则控制第二计数器继续对通过外时钟接口输入本地晶振的参考时钟信号的上升沿进行计数。210中详细介绍了计算EXT_CAL的方法，如果在实际应用中，用户未采用外部校准方法，则可以确定EXT_CAL＝0。
220、根据EXT_CAL对本地晶振输出的时钟信号的频偏进行外部校准。
EXT_CAL也即为本地晶振输出的时钟信号的频偏，根据外部校准值EXT_CAL可以对通过外时钟接口输入本地晶振的参考时钟信号进行频偏检测。
230、通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
由于在210至220中计算出了EXT_CAL，在对跟踪的参考时钟信号进行频偏检测时，可以对检测结果进行修正，获取到准确的检测结果。
本实施例提供的频偏检测方法，通过计算EXT_CAL，并根据EXT_CAL对本地晶振输出的时钟信号的频偏进行外部校准，通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，提高了采用本地晶振输出的时钟信号对参考时钟信号的频偏检测的精度，保证了跟踪的参考时钟信号的精度满足ITU-T G.813要求。
图3为本发明实施例三所提供的频偏检测方法的流程图。本实施例通过对本地晶振输出的时钟信号的频偏进行外部校准，并在外部校准后又进行了内部校准，通过外部校准和内部校准后的本地晶振输出的时钟信号对参考时钟信号进行频偏检测。参照图3，本实施例的方法可以包括：
310、根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL。
320、根据EXT_CAL对本地晶振输出的时钟信号的频偏进行外部校准。
330、根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1。
其中，M3i表示第i个第三计数器对经过外部校准后的本地晶振输出的时钟信号的上升沿进行计数的计数值，M0表示第i路参考时钟信号无频偏时第i个第三计数器对经过外部校准后的本地晶振输出的时钟信号的上升沿进行计数的计数值，M0＝X0×(1+EXT_CAL)，m路参考时钟信号为本地晶振从接收 的业务信号中提取的时钟信号，m为大于2的整数，i为大于等于1且小于等于m的整数。
举例来说，根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1可以采用下述方式得到：
将m个第四计数器和m个第三计数器清零，同时启动m个第三计数器和m个第四计数器开始计数，m个第四计数器分别对m路参考时钟信号的上升沿计数，m路参考时钟信号为本地晶振从接收的业务信号中提取的时钟信号；确定第i个第四计数器的第四计数值M4i是否大于等于A，M4i表示第i个第四计数器对第i路参考时钟信号的上升沿进行计数的计数值；若是，则停止第i个第四计数器计数，将第i个第四计数器清零，并向第i个第三计数器发送停止信号，以使第i个第三计数器停止计数并读取M3i；根据M3i和M0计算
Figure PCTCN2014086674-appb-000026
根据
Figure PCTCN2014086674-appb-000027
计算内部校准值INNER_CAL1，
Figure PCTCN2014086674-appb-000028
其中，△i表示第i路参考时钟信号相对于经过外部校准后的本地晶振输出的时钟信号的频偏，△f'表示经过外部校准后的本地晶振输出的时钟信号的频偏，△x和△y分别表示根据公式
Figure PCTCN2014086674-appb-000029
计算出的m个数值中的最大值和最小值。需要说明的是，计算内部校准值INNER_CAL1的过程中，由于m的取值受限，当某路参考时钟信号的频偏较大时，会影响到经过外部校准后的本地晶振输出的时钟信号的频偏结果，因此在设计过程中，去掉根据公式
Figure PCTCN2014086674-appb-000030
计算出的m个数值中的最大值△x和最小值△y，将剩余的m-2个频偏计算结果求和后取平均值来得到经过外部校准后的本地晶振输出的时钟信号的频偏，将此频偏作为经过外部校准后的本地晶振输出的时钟信号的内部校准值，在此需要说明的是，本实施例中的内部校准值计算方法可以扩展至其他统计学算法，以达到更精确的校准效果。
上述在确定第i个第四计数器的第四计数值M4i是否大于等于A的过程中，如果确定第i个第四计数器的第四计数值M4i小于A，则控制第i个第四计数器继续对第i路参考时钟信号的上升沿进行计数。
340、根据INNER_CAL1对经过外部校准后的本地晶振输出的时钟信号的频偏进行内部校准。
350、通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
举例来说，通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测可以采用下述方式得到：
计算第i路参考时钟信号的频偏△fi，
Figure PCTCN2014086674-appb-000031
确定公式-4.6ppm≤△fi≤4.6ppm是否成立；若公式-4.6ppm≤△fi≤4.6ppm成立，则确定第i路参考时钟信号的频偏满足所需的精度；从频偏满足所需的精度的j路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号作为网元设备的系统时钟信号，j为大于等于1小于等于m的整数；其中，ppm为百万分之一。
本实施例提供的频偏检测方法，通过计算EXT_CAL，并根据EXT_CAL对本地晶振输出的时钟信号的频偏进行外部校准，并且在外部校准后还进一步计算INNER_CAL1，根据INNER_CAL1对经过外部校准后的本地晶振输出的时钟信号的频偏再进行内部校准，通过外部校准和内部校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，提高了采用本地晶振输出的时钟信号对参考时钟信号的频偏检测的精度，保证了跟踪的参考时钟信号的精度满足ITU-T G.813要求。
图4为本发明实施例四所提供的频偏检测方法的流程图。本实施例通过对本地晶振输出的时钟信号的频偏进行内部校准，通过内部校准后的本地晶振输出的时钟信号对参考时钟信号进行频偏检测。参照图4，本实施例的方法可以包括：
410、根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL。
其中，N5k表示第k个第五计数器对本地晶振输出的时钟信号的上升沿进行计数的计数值，N0表示第k路参考时钟信号无频偏时、且本地晶振输出的时钟信号无频偏时第k个第五计数器对本地晶振输出的时钟信号的上升沿进行计数的计数值，
Figure PCTCN2014086674-appb-000032
A'为第二预设计数值，A'根据所需的对本地晶振输出的时钟信号的频偏进行校准的精度确定，f′0表示本地晶振输出的时钟信号无频偏时的频率，fk表示第k路参考时钟信号无频偏时的频率。n路参考时钟信号为本地晶振从接收的业务信号中提取的时钟信号，n为大于2的整数，k为大于等于1且小于等于n的整数。
举例来说，根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL可以采用下述方式得到：
将n个第六计数器的计数值和n个第五计数的计数值器清零，同时启动n个第五计数器和n个第六计数器开始计数，n个第六计数器分别对n路参考时钟信号的上升沿计数；确定第k个第六计数器的第六计数值N6k是否大于等于A'，N6k表示第k个第六计数器对第k路参考时钟信号的上升沿进行计数的计数值；若是，则停止第k个第六计数器计数，将第k个第六计数器清零，并向第k个第五计数器发送停止信号，以使第k个第五计数器停止计数并读取N5k；根据N5k和N0计算
Figure PCTCN2014086674-appb-000033
根据
Figure PCTCN2014086674-appb-000034
计算内部校准值INNER_CAL，
Figure PCTCN2014086674-appb-000035
其中，△k表示第k路参考时钟信号相对于本地晶振输出的时钟信号的频偏，△f'表示本地晶振输出的时钟信号的频偏，△m和△n分别表示根据公式
Figure PCTCN2014086674-appb-000036
计算出的n个数值中的最大值和最小值。
需要说明的是，在确定第k个第六计数器的第六计数值N6k是否大于等于 A'的过程中，如果确定第k个第六计数器的第六计数值N6k小于A'，则控制第k个第六计数器继续对第k路参考时钟信号的上升沿进行计数。
420、根据INNER_CAL对本地晶振输出的时钟信号的频偏进行内部校准。
430、通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
举例来说，通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测可以采用下述方式得到：
计算第k路参考时钟信号的频偏△fk，△fk＝△k+INNER_CAL；确定公式-4.6ppm≤△fk≤4.6ppm是否成立；若公式-4.6ppm≤△fk≤4.6ppm成立，则确定第k路参考时钟信号的频偏满足所需的精度；从频偏满足所需的精度的p路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号信号作为网元设备的系统时钟信号，p为大于等于1小于等于n的整数；其中，ppm为百万分之一。
本实施例提供的频偏检测方法，通过计算INNER_CAL，并根据INNER_CAL对本地晶振输出的时钟信号的频偏进行内部校准，通过内部校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，提高了采用本地晶振输出的时钟信号对参考时钟信号的频偏检测的精度，保证了跟踪的参考时钟信号的精度满足ITU-T G.813要求。
图5为本发明实施例五所提供的频偏检测装置500的结构示意图。本实施例的装置适用于SDH同步网络中对参考时钟信号进行频偏检测的情况。该装置通常以硬件和/或软件的方式来实现。参照图5，该频偏检测装置包括如下模块：频偏校准模块510和频偏检测模块520。
频偏校准模块510用于对网元设备的本地晶振输出的时钟信号的频偏进行校准；频偏检测模块520用于通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
本实施例提供的频偏检测装置，通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，提高了采用本地晶振输出的时钟信号对参考时钟信号的频偏检测的精度，保证了跟踪的参考时钟信号的精度满足ITU-T G.813要求。
图6为本发明实施例六所提供的频偏检测装置600的结构示意图。参照 图6，在上述实施例五的基础上，频偏校准模块510具体包括如下单元：外部校准值计算单元511和外部校准单元512。
外部校准值计算单元511用于根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL，其中，X表示通过外时钟接口输入本地晶振的参考时钟信号无频偏时第一计数器对本地晶振输出的时钟信号的上升沿进行计数的计数值，X0表示本地晶振输出的时钟信号无频偏、且通过外时钟接口输入本地晶振的参考时钟信号无频偏时第一计数器对本地晶振输出的
时钟信号的上升沿进行计数的计数值，
Figure PCTCN2014086674-appb-000037
A为第一预设计数值，A根据所需的对本地晶振输出的时钟信号的频偏进行校准的精度确定，f0表示本地晶振输出的时钟信号无频偏时的频率，f表示通过外时钟接口输入本地晶振的参考时钟信号无频偏时的频率；外部校准单元512用于根据EXT_CAL对本地晶振输出的时钟信号的频偏进行外部校准。
进一步的，外部校准值计算单元511具体用于将第二计数器和第一计数器清零，同时启动第一计数器和第二计数器开始计数，第二计数器对通过外时钟接口输入本地晶振的参考时钟信号的上升沿进行计数；确定第二计数器的第二计数值是否大于等于A；若是，则停止第二计数器计数，将第二计数器清零，并向第一计数器发送停止信号，以使第一计数器停止计数并读取X；根据X和X0计算EXT_CAL，
Figure PCTCN2014086674-appb-000038
其中，△f表示通过外时钟接口输入本地晶振的参考时钟信号的频偏。
进一步的，频偏校准模块510还可以包括如下单元：第一内部校准值计算单元和第一内部校准单元。
第一内部校准值计算单元，用于在根据EXT_CAL对本地晶振输出的时钟信号的频偏进行外部校准之后，根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1，其中，M3i表示第i个第三计数器对经过外部校准后的本地晶振输出的时钟信号的上升沿进行计数的计数值，M0表示第i路参考时钟信号无频偏时第i个第三计数器对经过外部校准后的本地晶振输出的时钟信号的上升沿进行计数的计数值， M0＝X0×(1+EXT_CAL)，m路参考时钟信号为本地晶振从接收的业务信号中提取的时钟信号，m为大于2的整数，i为大于等于1且小于等于m的整数。
第一内部校准单元，用于根据INNER_CAL1对经过外部校准后的本地晶振输出的时钟信号的频偏进行内部校准。
进一步的，第一内部校准值计算单元，具体用于将m个第四计数器和m个第三计数器清零，同时启动m个第三计数器和m个第四计数器开始计数，m个第四计数器分别对m路参考时钟信号的上升沿计数，m路参考时钟信号为本地晶振从接收的业务信号中提取的时钟信号；确定第i个第四计数器的第四计数值M4i是否大于等于A，M4i表示第i个第四计数器对第i路参考时钟信号的上升沿进行计数的计数值；若是，则停止第i个第四计数器计数，将第i个第四计数器清零，并向第i个第三计数器发送停止信号，以使第i个第三计数器停止计数并读取M3i；根据M3i和M0计算
Figure PCTCN2014086674-appb-000039
根据
Figure PCTCN2014086674-appb-000040
计算内部校准值INNER_CAL1，
Figure PCTCN2014086674-appb-000041
其中，△i表示第i路参考时钟信号相对于经过外部校准后的本地晶振输出的时钟信号的频偏，△f'表示经过外部校准后的本地晶振输出的时钟信号的频偏，△x和△y分别表示根据公式
Figure PCTCN2014086674-appb-000042
计算出的m个数值中的最大值和最小值。
进一步的，频偏检测模块520具体用于计算第i路参考时钟信号的频偏△fi，
Figure PCTCN2014086674-appb-000043
确定公式-4.6ppm≤△fi≤4.6ppm是否成立；若公式-4.6ppm≤△fi≤4.6ppm成立，则确定第i路参考时钟信号的频偏满足所需的精度；从频偏满足所需的精度的j路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号作为网元设备的系统时钟信号，j为大于等于1小于等于m的整数；其中，ppm为百万分之一。
本实施例提供的频偏检测装置，通过校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，提高了采用本地晶振输出的时钟信号对参考时钟信号的频偏检测的精度，保证了跟踪的参考时钟信号满足ITU-TG.813要求。
图7为本发明实施例七所提供的频偏检测装置700的结构示意图。参照图7，在上述实施例五的基础上，频偏校准模块510具体包括如下单元：第二内部校准值计算单元710和第二内部校准单元720。
第二内部校准值计算单元710用于根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL，其中，N5k表示第k个第五计数器对本地晶振输出的时钟信号的上升沿进行计数的计数值，N0表示第k路参考时钟信号无频偏时、且本地晶振输出的时钟信号无频偏时第k个第五计数器对本地晶振输出的时钟信号的上升沿进行计数的计数值，
Figure PCTCN2014086674-appb-000044
A'为第二预设计数值，A'根据所需的对本地晶振输出的时钟信号的频偏进行校准的精度确定，f′0表示本地晶振输出的时钟信号无频偏时的频率，fk表示第k路参考时钟信号无频偏时的频率。n路参考时钟信号为本地晶振从接收的业务信号中提取的时钟信号，n为大于2的整数，k为大于等于1且小于等于n的整数；第二内部校准单元720用于根据INNER_CAL对本地晶振输出的时钟信号的频偏进行内部校准。
进一步的，第二内部校准值计算单元710具体用于将n个第六计数器的计数值和n个第五计数的计数值器清零，同时启动n个第五计数器和n个第六计数器开始计数，n个第六计数器分别对n路参考时钟信号的上升沿计数；确定第k个第六计数器的第六计数值N6k是否大于等于A'，N6k表示第k个第六计数器对第k路参考时钟信号的上升沿进行计数的计数值；若是，则停止第k个第六计数器计数，将第k个第六计数器清零，并向第k个第五计数器发送停止信号，以使第k个第五计数器停止计数并读取N5k；根据N5k和N0计 算
Figure PCTCN2014086674-appb-000045
根据
Figure PCTCN2014086674-appb-000046
计算内部校准值INNER_CAL，
Figure PCTCN2014086674-appb-000047
其中，△k表示第k路参考时钟信号相对于本地晶振输出的时钟信号的频偏，△f'表示本地晶振输出的时钟信号的频偏，△m和△n分别表示根据公式
Figure PCTCN2014086674-appb-000048
计算出的n个数值中的最大值和最小值。
进一步的，频偏检测模块520具体用于计算第k路参考时钟信号的频偏△fk，△fk＝△k+INNER_CAL；确定公式-4.6ppm≤△fk≤4.6ppm是否成立；若公式-4.6ppm≤△fk≤4.6ppm成立，则确定第k路参考时钟信号的频偏满足所需的精度；从频偏满足所需的精度的p路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号信号作为网元设备的系统时钟信号，p为大于等于1小于等于n的整数；其中，ppm为百万分之一。
本实施例提供的频偏检测装置，通过内部校准后的本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，提高了采用本地晶振输出的时钟信号对参考时钟信号的频偏检测的精度，保证了跟踪的参考时钟信号满足ITU-T G.813要求。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (18)

  1. 一种频偏检测方法，其特征在于，包括：
    对网元设备的本地晶振输出的时钟信号的频偏进行校准；
    通过校准后的所述本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
  2. 根据权利要求1所述的方法，其特征在于，所述对网元设备的本地晶振输出的时钟信号的频偏进行校准，包括：
    根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL，其中，X表示通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时所述第一计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，X0表示所述本地晶振输出的时钟信号无频偏、且所述通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时所述第一计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，
    Figure PCTCN2014086674-appb-100001
    A为第一预设计数值，A根据所需的对所述本地晶振输出的时钟信号的频偏进行校准的精度确定，f0表示所述本地晶振输出的时钟信号无频偏时的频率，f表示所述通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时的频率；
    根据EXT_CAL对所述本地晶振输出的时钟信号的频偏进行外部校准。
  3. 根据权利要求2所述的方法，其特征在于，所述根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL，包括：
    将第二计数器和所述第一计数器清零，同时启动所述第一计数器和所述第二计数器开始计数，所述第二计数器对所述通过外时钟接口输入所述本地晶振的所述参考时钟信号的上升沿进行计数；
    确定所述第二计数器的第二计数值是否大于等于A；
    若是，则停止所述第二计数器计数，将所述第二计数器清零，并向所述第一计数器发送停止信号，以使所述第一计数器停止计数并读取所述X；
    根据所述X和所述X0计算EXT_CAL，
    Figure PCTCN2014086674-appb-100002
    其中，△f表示所述通过外时钟接口输入所述本地晶振的所述参考时钟信号的频偏。
  4. 根据权利要求2或3所述的方法，其特征在于，在所述根据EXT_CAL对所述本地晶振输出的时钟信号的频偏进行外部校准之后，还包括：
    根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1，其中，M3i表示第i个第三计数器对经过外部校准后的所述本地晶振输出的时钟信号的上升沿进行计数的计数值，M0表示第i路参考时钟信号无频偏时第i个第三计数器对经过外部校准后的所述本地晶振输出的时钟信号的上升沿进行计数的计数值，M0＝X0×(1+EXT_CAL)，所述m路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号，m为大于2的整数，i为大于等于1且小于等于m的整数；
    根据INNER_CAL1对经过外部校准后的所述本地晶振输出的时钟信号的频偏进行内部校准。
  5. 根据权利要求4所述的方法，其特征在于，所述根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1，包括：
    将m个第四计数器和所述m个第三计数器清零，同时启动所述m个第三计数器和所述m个第四计数器开始计数，所述m个第四计数器分别对m路参考时钟信号的上升沿计数，所述m路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号；
    确定第i个第四计数器的第四计数值M4i是否大于等于A，M4i表示所述第i个第四计数器对第i路参考时钟信号的上升沿进行计数的计数值；
    若是，则停止所述第i个第四计数器计数，将所述第i个第四计数器清零，并向第i个第三计数器发送停止信号，以使所述第i个第三计数器停止计数并读取所述M3i；
    根据所述M3i和所述M0计算
    Figure PCTCN2014086674-appb-100003
    根据
    Figure PCTCN2014086674-appb-100004
    计算内部校准值INNER_CAL1，
    Figure PCTCN2014086674-appb-100005
    其中，△i表示第i路参考时钟信号相对于经过外部校准后的所述本地晶振输出的时钟信号的频偏，△f'表示经过外部校准后的所述本地晶振输出的时钟信号的频偏，△x和△y分别表示根据公式
    Figure PCTCN2014086674-appb-100006
    计算出的m个数值中的最大值和最小值。
  6. 根据权利要求5所述的方法，其特征在于，所述通过校准后的所述本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，包括：
    计算所述第i路参考时钟信号的频偏△fi，△fi＝△i+EXT_CAL+INNER_CAL1；
    确定公式-4.6ppm≤△fi≤4.6ppm是否成立；
    若公式-4.6ppm≤△fi≤4.6ppm成立，则确定第i路参考时钟信号的频偏满足所需的精度；
    从频偏满足所需的精度的j路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号作为所述网元设备的系统时钟信号，j为大于等于1小于等于m的整数；
    其中，ppm为百万分之一。
  7. 根据权利要求1所述的方法，其特征在于，所述对网元设备的本地晶振输出的时钟信号的频偏进行校准，包括：
    根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL，其中，N5k表示第k个第五计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，N0表示第k路参考时钟信号无频偏时、且所述本地晶振输出的时钟信号无频偏时所述第k个第五计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，
    Figure PCTCN2014086674-appb-100007
    A'为第二预设计数值，A'根据所需的对所述本地晶振输出的时钟信号的频偏进行校准的精度确定，f′0表示所述本地晶振输出的时钟信号无频偏时的频率，fk表示所述 第k路参考时钟信号无频偏时的频率。所述n路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号，n为大于2的整数，k为大于等于1且小于等于n的整数；
    根据INNER_CAL对所述本地晶振输出的时钟信号的频偏进行内部校准。
  8. 根据权利要求7所述的方法，其特征在于，所述根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL，包括：
    将n个第六计数器的计数值和所述n个第五计数的计数值器清零，同时启动所述n个第五计数器和所述n个第六计数器开始计数，所述n个第六计数器分别对所述n路参考时钟信号的上升沿计数；
    确定第k个第六计数器的第六计数值N6k是否大于等于A'，N6k表示所述第k个第六计数器对第k路参考时钟信号的上升沿进行计数的计数值；
    若是，则停止所述第k个第六计数器计数，将所述第k个第六计数器清零，并向第k个第五计数器发送停止信号，以使所述第k个第五计数器停止计数并读取所述N5k；
    根据所述N5k和所述N0计算
    Figure PCTCN2014086674-appb-100008
    根据
    Figure PCTCN2014086674-appb-100009
    计算内部校准值INNER_CAL，
    Figure PCTCN2014086674-appb-100010
    其中，△k表示所述第k路参考时钟信号相对于所述本地晶振输出的时钟信号的频偏，△f'表示所述本地晶振输出的时钟信号的频偏，△m和△n分别表示根据公式
    Figure PCTCN2014086674-appb-100011
    计算出的n个数值中的最大值和最小值。
  9. 根据权利要求8所述的方法，其特征在于，所述通过校准后的所述本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测，包括：
    计算所述第k路参考时钟信号的频偏△fk，△fk＝△k+INNER_CAL；
    确定公式-4.6ppm≤△fk≤4.6ppm是否成立；
    若公式-4.6ppm≤△fk≤4.6ppm成立，则确定第k路参考时钟信号的频偏满 足所需的精度；
    从频偏满足所需的精度的p路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号信号作为所述网元设备的系统时钟信号，p为大于等于1小于等于n的整数；
    其中，ppm为百万分之一。
  10. 一种频偏检测装置，其特征在于，包括：
    频偏校准模块，用于对网元设备的本地晶振输出的时钟信号的频偏进行校准；
    频偏检测模块，用于通过校准后的所述本地晶振输出的时钟信号对跟踪的参考时钟信号进行频偏检测。
  11. 根据权利要求10所述的装置，其特征在于，所述频偏校准模块包括：
    外部校准值计算单元，用于根据第一计数器的第一计数值X和第一参考值X0，计算外部校准值EXT_CAL，其中，X表示通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时所述第一计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，X0表示所述本地晶振输出的时钟信号无频偏、且所述通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时所述第一计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，
    Figure PCTCN2014086674-appb-100012
    A为第一预设计数值，A根据所需的对所述本地晶振输出的时钟信号的频偏进行校准的精度确定，f0表示所述本地晶振输出的时钟信号无频偏时的频率，f表示所述通过外时钟接口输入所述本地晶振的所述参考时钟信号无频偏时的频率；
    外部校准单元，用于根据EXT_CAL对所述本地晶振输出的时钟信号的频偏进行外部校准。
  12. 根据权利要求11所述的装置，其特征在于，所述外部校准值计算单元，具体用于将第二计数器和所述第一计数器清零，同时启动所述第一计数器和所述第二计数器开始计数，所述第二计数器对所述通过外时钟接口输入所述本地晶振的所述参考时钟信号的上升沿进行计数；确定所述第二计数器 的第二计数值是否大于等于A；若是，则停止所述第二计数器计数，将所述第二计数器清零，并向所述第一计数器发送停止信号，以使所述第一计数器停止计数并读取所述X；根据所述X和所述X0计算EXT_CAL，
    Figure PCTCN2014086674-appb-100013
    其中，△f表示所述通过外时钟接口输入所述本地晶振的所述参考时钟信号的频偏。
  13. 根据权利要求11或12所述的装置，其特征在于，还包括：
    第一内部校准值计算单元，用于在所述根据EXT_CAL对所述本地晶振输出的时钟信号的频偏进行外部校准之后，根据m个第三计数器的m个第三计数值M3i和第二参考值M0，计算内部校准值INNER_CAL1，其中，M3i表示第i个第三计数器对经过外部校准后的所述本地晶振输出的时钟信号的上升沿进行计数的计数值，M0表示第i路参考时钟信号无频偏时第i个第三计数器对经过外部校准后的所述本地晶振输出的时钟信号的上升沿进行计数的计数值，M0＝X0×(1+EXT_CAL)，所述m路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号，m为大于2的整数，i为大于等于1且小于等于m的整数；
    第一内部校准单元，用于根据INNER_CAL1对经过外部校准后的所述本地晶振输出的时钟信号的频偏进行内部校准。
  14. 根据权利要求13所述的装置，其特征在于，所述第一内部校准值计算单元，具体用于将m个第四计数器和所述m个第三计数器清零，同时启动所述m个第三计数器和所述m个第四计数器开始计数，所述m个第四计数器分别对m路参考时钟信号的上升沿计数，所述m路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号；确定第i个第四计数器的第四计数值M4i是否大于等于A，M4i表示所述第i个第四计数器对第i路参考时钟信号的上升沿进行计数的计数值；若是，则停止所述第i个第四计数器计数，将所述第i个第四计数器清零，并向第i个第三计数器发送停止信号，以使所述第i个第三计数器停止计数并读取所述M3i；根据所述M3i和所述M0计算
    Figure PCTCN2014086674-appb-100014
    根据
    Figure PCTCN2014086674-appb-100015
    计算内部校准值INNER_CAL1，
    Figure PCTCN2014086674-appb-100016
    其中，△i表示第i路参考时钟信号相对于经过外部校准后的所述本地晶振输出的时钟信号的频偏，△f'表示经过外部校准后的所述本地晶振输出的时钟信号的频偏，△x和△y分别表示根据公式
    Figure PCTCN2014086674-appb-100017
    计算出的m个数值中的最大值和最小值。
  15. 根据权利要求14所述的装置，其特征在于，所述频偏检测模块，具体用于计算所述第i路参考时钟信号的频偏△fi，△fi＝△i+EXT_CAL+INNER_CAL1；确定公式-4.6ppm≤△fi≤4.6ppm是否成立；若公式-4.6ppm≤△fi≤4.6ppm成立，则确定第i路参考时钟信号的频偏满足所需的精度；从频偏满足所需的精度的j路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号作为所述网元设备的系统时钟信号，j为大于等于1小于等于m的整数；其中，ppm为百万分之一。
  16. 根据权利要求10所述的装置，其特征在于，所述频偏校准模块，包括：
    第二内部校准值计算单元，用于根据n个第五计数器的n个第五计数值N5k和第三参考值N0，计算内部校准值INNER_CAL，其中，N5k表示第k个第五计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，N0表示第k路参考时钟信号无频偏时、且所述本地晶振输出的时钟信号无频偏时所述第k个第五计数器对所述本地晶振输出的时钟信号的上升沿进行计数的计数值，
    Figure PCTCN2014086674-appb-100018
    A'为第二预设计数值，A'根据所需的对所述本地晶振输出的时钟信号的频偏进行校准的精度确定，f′0表示所述本地晶振输出的时钟信号无频偏时的频率，fk表示所述第k路参考时钟信号无频偏时的频率。所 述n路参考时钟信号为所述本地晶振从接收的业务信号中提取的时钟信号，n为大于2的整数，k为大于等于1且小于等于n的整数；
    第二内部校准单元，用于根据INNER_CAL对所述本地晶振输出的时钟信号的频偏进行内部校准。
  17. 根据权利要求16所述的装置，其特征在于，所述第二内部校准值计算单元，具体用于将n个第六计数器的计数值和所述n个第五计数的计数值器清零，同时启动所述n个第五计数器和所述n个第六计数器开始计数，所述n个第六计数器分别对所述n路参考时钟信号的上升沿计数；确定第k个第六计数器的第六计数值N6k是否大于等于A'，N6k表示所述第k个第六计数器对第k路参考时钟信号的上升沿进行计数的计数值；若是，则停止所述第k个第六计数器计数，将所述第k个第六计数器清零，并向第k个第五计数器发送停止信号，以使所述第k个第五计数器停止计数并读取所述N5k；根据所述N5k和所述N0计算
    Figure PCTCN2014086674-appb-100019
    根据
    Figure PCTCN2014086674-appb-100020
    计算内部校准值INNER_CAL，
    Figure PCTCN2014086674-appb-100021
    其中，△k表示所述第k路参考时钟信号相对于所述本地晶振输出的时钟信号的频偏，△f'表示所述本地晶振输出的时钟信号的频偏，△m和△n分别表示根据公式
    Figure PCTCN2014086674-appb-100022
    计算出的n个数值中的最大值和最小值。
  18. 根据权利要求17所述的装置，其特征在于，所述频偏检测模块，具体用于计算所述第k路参考时钟信号的频偏△fk，△fk＝△k+INNER_CAL；确定公式-4.6ppm≤△fk≤4.6ppm是否成立；若公式-4.6ppm≤△fk≤4.6ppm成立，则确定第k路参考时钟信号的频偏满足所需的精度；从频偏满足所需的精度的p路参考时钟信号中选取频偏的绝对值最小的一路参考时钟信号信号作为所述网元设备的系统时钟信号，p为大于等于1小于等于n的整数；其中，ppm为百万分之一。
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US20160211969A1 (en) 2016-07-21
EP3043493A4 (en) 2016-07-13
EP3043493B1 (en) 2017-12-27

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