WO2015096010A1 - 一种无线收发信机 - Google Patents
一种无线收发信机 Download PDFInfo
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- WO2015096010A1 WO2015096010A1 PCT/CN2013/090243 CN2013090243W WO2015096010A1 WO 2015096010 A1 WO2015096010 A1 WO 2015096010A1 CN 2013090243 W CN2013090243 W CN 2013090243W WO 2015096010 A1 WO2015096010 A1 WO 2015096010A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B1/0475—Circuits with means for limiting noise, interference or distortion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/36—Modulator circuits; Transmitter circuits
- H04L27/366—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator
- H04L27/367—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion
- H04L27/368—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion adaptive predistortion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0408—Circuits with power amplifiers
- H04B2001/0425—Circuits with power amplifiers with linearisation using predistortion
Definitions
- the present invention relates to the field of communications technologies, and in particular, to a wireless transceiver. Background technique
- Pre-distortion technology is a digital pre-distortion (DPD) that is cascaded with a conversion function (amplitude and phase) before the nonlinear power amplifier (PA).
- DPD digital pre-distortion
- PA nonlinear power amplifier
- the 4 bar input signal changes in the opposite direction of the power amplifier characteristics, so that the input and output of the ⁇ are linear in a whole. Since the nonlinear characteristics of the power amplifier change in the actual environment due to temperature, humidity, power supply voltage, device aging, and channel switching, in order to ensure a stable linear output of the system, the predistorter can be automatically adjusted according to the change of the power amplifier characteristics. .
- an observer circuit including the coupler connected in sequence in FIG. , analog-to-digital converter ADC, algorithm module.
- ADC analog-to-digital converter
- the embodiment of the invention provides a wireless transceiver for solving the problem of increasing hardware cost caused by the observer circuit in order to perform pre-distortion processing in the prior art.
- a first aspect of the embodiments of the present invention provides a wireless transceiver, including: a digital predistorter DPD (11), a digital to analog converter DAC (12), an upconverter (13), and a power amplifier PA ( 14), first control switch (30), transceiver antenna (40), coupler (50), low noise The sound amplifier LNA (21), the second control switch (60), the down converter (22), and the analog to digital converter ADC (23), wherein:
- the digital predistorter DPD (11), the digital-to-analog converter DAC (12), the up-converter (13), the power amplifier PA (14), and the coupler (50) are sequentially connected;
- the first control switch (30) selectively connects a signal output end of the power amplifier PA (14) or a signal input end of the low noise amplifier LNA (21) to the transceiver antenna (40);
- the second control switch (60) selectively inputs a signal output of the coupler (50) or a signal output of the low noise amplifier LNA (21) and a signal of the down converter (22) Connected to each other;
- the signal output of the down converter (22) is coupled to the signal input of the analog to digital converter ADC (23).
- the digital predistorter DPD (11) includes an algorithm module (70) for converting an original signal according to an input and an analog to digital converter ADC (23) The signal outputted by the first signal output obtains the coefficients of the predistortion model.
- the wireless transceiver includes an algorithm module (70), a first input end of the algorithm module (70) and the analog-to-digital converter ADC (23)
- the first signal output is connected, the signal input by the second input of the algorithm module (70) is the original signal, and the output of the algorithm module (70) and the input of the digital predistorter DPD (11) Connected to the end, the algorithm module is configured to obtain coefficients of the predistortion model according to the input original signal and the signal output by the analog to digital converter ADC (23).
- the wireless transceiver of the embodiment of the present invention includes a second control switch, and the second control switch can selectively connect the signal output end of the coupler or the signal output end of the low noise amplifier LNA.
- the signal input end of the down converter is connected, so when the signal output end of the coupler is connected to the down converter, the coupler, the down converter, and the analog to digital converter ADC are composed.
- the second control switch connects a signal output end of the low noise amplifier LNA with a signal input end of the down converter, the transceiver antenna, the low noise amplifier LNA, the down conversion
- the analog-to-digital converter ADC constitutes a receiver.
- the embodiment of the present invention can reuse the existing down converter of the wireless transceiver and the digital-to-analog converter ADC through the second control switch.
- the function of the observing machine realizes the effective compatibility between the observing machine and the receiver, and it can greatly save the hardware cost of the observing circuit of the system compared with the case of the newly added circuit.
- FIG. 1 is a schematic structural diagram of a wireless transceiver in the prior art.
- FIG. 2 is a schematic structural diagram of an embodiment of a wireless transceiver of the present invention.
- FIG. 3 is a schematic structural diagram of another embodiment of a wireless transceiver of the present invention.
- FIG. 4 is a schematic structural diagram of still another embodiment of a wireless transceiver of the present invention.
- FIG. 5 is a schematic structural diagram of a transmitter of the wireless transceiver of the present invention when it operates.
- FIG. 6 is a schematic structural diagram of a receiver of a wireless transceiver of the present invention when it operates. detailed description
- FIG. 2 is a schematic structural diagram of an embodiment of a wireless transceiver of the present invention. As shown in Figure 2, it can include:
- An analog-to-digital converter ADC23 wherein: the digital predistorter DPD11, the digital-to-analog converter DAC12, the up-converter 13, the power amplifier PA14, and the coupler 50 are sequentially connected;
- the sequential connection means that the output of the previous device is connected to the input of the next device, and so on.
- the first control switch 30 selectively outputs a signal output of the power amplifier PA14 or the signal of the low noise amplifier LNA21.
- An input end is in communication with the transceiver antenna 40; the second control switch 60 selectively outputs a signal output end of the coupler 50 or a signal output end of the low noise amplifier LNA21 and the downconverter 22 The input end is connected; the signal output end of the down converter 22 is connected to the signal input end of the analog-to-digital converter ADC23; the signal output end of the analog-to-digital converter ADC23 and the signal input of the digital predistorter DPD11 Connected to the end.
- the first control switch 30 can selectively connect the signal output end of the power amplifier PA14 or the signal input end of the low noise amplifier LNA21 to the transceiver antenna 40 in a time division multiplexing manner; the second control The switch 60 selectively connects the signal output of the coupler 50 or the signal output of the low noise amplifier LNA21 to the signal input of the downconverter 22 in a time division multiplex manner.
- the second control switch 60 When the first control switch 30 is closed to connect the signal output end of the power amplifier PA14 with the transceiver antenna 40, the second control switch 60 is closed to make the signal output end of the coupler 50 and the lower The inverter 22 is connected; when the first control switch 30 is closed to connect the signal input end of the low noise amplifier LNA21 with the transceiver antenna 40, the second control switch 60 is closed to make the low noise amplifier LNA21 The signal output is in communication with the signal input of the downconverter 22.
- the wireless transceiver in the embodiment of the present invention may be a TDD wireless transceiver, and the first control switch 30 and the second control switch 60 may be distinguished and controlled in time by the antenna switch, such that the first control switch 30
- the principle of system time division multiplexing for example, in TD-LET, the ratio of transmission and reception is 1:1, then the time of lms can be divided into 500us transmission, 500us reception
- the ground is selectively used in time division multiplexing.
- the signal output terminal of the power amplifier PA14 or the signal input terminal of the low noise amplifier LNA21 is connected to the transceiver antenna 40.
- the signal output end of the power amplifier PA14 will be connected to the transceiver antenna 40 through the first control switch 30; after the 500us is the signal reception period, the first control switch 30 will be used.
- the signal input terminal of the low noise amplifier LNA21 is in communication with the transceiver antenna 40.
- the digital predistorter DPD11 of the embodiment of the present invention may preset the coefficients of the predistortion model, and when receiving the signal outputted through the analog to digital converter ADC23, may implement the input according to the coefficients of the preset predistortion model.
- the sampling frequency of the digital-to-analog converter DAC12 of the embodiment of the present invention is K times the bandwidth of the baseband signal, where K is the distortion model order of the power amplifier PA14 (for example, 3 Order or 5th order); Under this condition, it is guaranteed that there is no aliasing distortion after the signal passes through the nonlinear device PA14.
- the frequency of the analog to digital converter ADC23 of the embodiment of the present invention can be kept consistent with the frequency of the analog to digital converter DAC12. At this time, the received signal and the feedback signal sent to the DPD can be recovered without distortion in the receiver circuit.
- the second control switch 60 can selectively connect the signal output end of the coupler 50 or the signal output end of the low noise amplifier LNA21 to the signal input end of the down converter 22, when When the signal output end of the coupler 50 is in communication with the down converter 22, the coupler 50, the down converter 22, and the analog to digital converter ADC23 constitute an observer, when the second control switch 60, when the signal output end of the low noise amplifier LNA21 is connected to the signal input end of the down converter 22, the transmitting and receiving antenna 40, the low noise amplifier LNA21, the down converter 22, the modulus The converter ADC23 constitutes a receiver.
- FIG. 3 is a schematic structural diagram of another embodiment of a wireless transceiver of the present invention.
- the difference from the previous embodiment is that in the embodiment, after the analog-to-digital converter ADC23, an algorithm module 70 is added, which can be integrated in the digital predistorter DPD11 or a single module.
- the algorithm module 70 may be a DSP (Digital Signal Processing) chip, or an FPGA (Field-Programmable Gate Array), etc., which is not limited herein.
- the wireless transceiver includes: a digital predistorter DPD11, a digital to analog converter DAC12, an upconverter 13, a power amplifier PA14, and a first control switch 30. a transceiver antenna 40, a coupler 50, a low noise amplifier LNA21, a second control switch 60, a down converter 22, an analog to digital converter ADC23, and an algorithm module 70, wherein: the digital predistorter DPD11, the digital mode The converter DAC 12, the up-converter 13, the power amplifier PA14, and the coupler 50 are sequentially connected.
- the first control switch 30 selectively The signal output terminal of the power amplifier PA14 or the signal input end of the low noise amplifier LNA21 is in communication with the transceiver antenna 40; the second control switch 60 selectively outputs the signal output terminal of the coupler 50 or a signal output end of the low noise amplifier LNA21 is connected to a signal input end of the down converter 22; a signal output end of the down converter 22 is connected to a signal input end of the analog to digital converter ADC23;
- the first input end of the module 70 is connected to the first signal output end of the analog-to-digital converter ADC23, the signal input by the second input end of the algorithm module 70 is the original signal, and the output end of the algorithm module 70 is The input terminal of the digital predistorter DPD11 is connected, and the algorithm module 70 is configured to obtain coefficients of the predistortion model according to the input original signal and the signal outputted by the first signal output end of the analog to digital converter ADC23.
- the coefficients of the pre-distortion model are obtained based on the input original signal and the signal output from the first signal output of the analog-to-digital converter ADC23.
- the predistortion processing model of the digital predistorter 11 in the embodiment of the present invention is related to the model of the power amplifier PA14 and can be represented by a polynomial series with a memory effect, such as a simplified model of the Volterra series.
- the predistortion processing model of the digital predistorter 11 is not limited in the embodiment of the present invention.
- the parameters of the predistortion model output by the algorithm module 70 can be obtained by calculating and calculating the difference between the two signals, for example, by comparing the original input signal with the signal processed by the power amplifier PA14 and the downconverter 32, the analog to digital converter ADC23, and the like.
- the first control switch 30 connects the signal output end of the power amplifier PA14 with the transceiver antenna 40
- the second control switch 60 connects the signal output end of the coupler 50 with the down converter
- the digital predistorter DPD11, the digital-to-analog converter DAC12, the up-converter 13, the power amplifier PA14, and the transceiver antenna 40 form a transmitter;
- the coupler 50, The down converter 22, the analog to digital converter ADC23, and the algorithm module 70 constitute an observation machine.
- the first control switch 30 connects the signal input end of the low noise amplifier LNA21 with the transceiver antenna 40
- the second control switch 60 connects the signal output end of the low noise amplifier LNA21 with the lower
- the transceiver antenna 40, the low noise amplifier LNA21, the down converter 22, and the analog-to-digital converter ADC23 form a receiving signal.
- the second signal output port of the analog-to-digital converter ADC23 is configured to output a received signal from the transceiver antenna 40.
- the second control switch re-uses the existing down converter of the wireless transceiver and the digital-to-analog converter ADC to realize the function of the observing machine, and realizes the effective compatibility between the observing machine and the receiver, which is relatively new. In the case of increasing the circuit, the hardware cost of the system to realize the observing circuit can be greatly saved.
- 4 is a schematic structural diagram of still another embodiment of a wireless transceiver of the present invention. As shown in FIG. 4, on the basis of the embodiment of FIG. 3, an interpolation compensation module 90 and a predistortion mapping module 80 are connected between the algorithm module 70 and the analog to digital converter module ADC23, wherein
- the predistortion mapping module 80 is configured to perform predistortion processing on a signal outputted by the first signal output end of the analog to digital converter ADC to compensate for distortion caused by the power amplifier PA.
- the interpolation compensation module 90 is configured to perform interpolation compensation on the signal processed by the predistortion mapping module 80.
- the interpolation compensation module 90 can interpolate and compensate the signal output by the ADC 23 by interpolation.
- the interpolation compensation module 90 may perform interpolation compensation on the signal output from the ADC 23 by using bilinear interpolation, high-order spline interpolation, and the like.
- the embodiments of the present invention are not limited herein.
- the second signal input end of the algorithm module 70 in FIG. 4 is connected to the signal output end of the digital predistorter DPD, that is, one of the input signals of the algorithm module in the embodiment of FIG. 4 is
- the digital predistorter DPD processes the subsequent signals, while one of the input signals of the algorithm module in the embodiment of Figure 3 is the original signal, which is not processed by the digital predistorter DPD.
- the sampling frequency of the analog-to-digital converter ADC23 can be reduced, for example, at least twice the bandwidth of the baseband signal.
- the signal processed by the ADC is a distorted signal. Due to the spread of the frequency transmission, if only the 3rd and 5th order intermodulation distortions are considered, the spectrum bandwidth is extended to about 5 times of the original signal bandwidth, usually ⁇ The distortion feedback signal is sampled at a very high sampling rate, which is highly demanding on the device.
- the signal output from the ADC 23 can be pre-distorted and interpolated.
- the sampling frequency of the ADC 23 can be reduced, and the minimum can be reduced. It is twice the bandwidth of the baseband signal.
- the embodiment of the present invention can also reduce the system requirements for the ADC23 sampling frequency and reduce the ADC hardware cost.
- the signal flow of the embodiment of the present invention will be described below with reference to FIG. 5 and FIG. 6 through the structural embodiment of FIG. Specifically, as shown in FIG. 5, in the embodiment of the present invention, when the transmitter of the wireless transceiver operates, the switch contact of the first control switch 30 is closed to the signal output end of the power amplifier PA14.
- the power amplifier PA14 is in communication with the transceiver antenna 40; the switch contact of the second control switch 60 is closed to the signal output of the coupler 50 to cause the coupler 50 to communicate with the downconverter.
- the digital predistorter DPD11, the digital-to-analog converter DAC12, the up-converter 13, the power amplifier PA14, and the transceiver antenna 40 may constitute a transmitter, and the coupler 50,
- the down converter 22, the analog-to-digital converter ADC23, and the algorithm module 70 can constitute an observer (wherein the down converter 22 and the analog-to-digital converter ADC23 are receiver components inherent to the TDD wireless transceiver) ). It can be seen from Fig. 5 that the signal flow of the whole system is as follows (see the direction of the dotted arrow in Fig. 5):
- the digital baseband signal (including two signals of Inphase Components and Quadrature Components) is input to the digital predistorter DPD11, corrected by DPD11, converted to an analog signal by DAC12, and then upconverted.
- the carrier 13 is modulated into a high frequency signal, then becomes a high power signal through the power amplifier PA14, and then transmitted through the transmitting and receiving antenna 40. Since the signal becomes a high-power signal after being amplified by the PA, the power needs to be reduced when the observer works.
- This part of the function attenuates the signal through the coupler, and the attenuated low-power signal passes through the second control switch 30 via the down converter 22 After being down-converted, it is converted into a digital baseband signal by the ADC23, and is fed back to the algorithm module 70 through the first signal output port of the analog-to-digital converter ADC.
- the partial feedback signal and the input signal are obtained in the algorithm module 70 for predistortion model parameter acquisition, that is, calculation.
- the specific degree of distortion forms an adjustment model for the input signal, and controls the DPD11 module to perform specific adjustment of the input signal.
- the switch contact of the first control switch 30 is closed to the signal input end of the low noise amplifier LNA21.
- a signal input end of the low noise amplifier LNA21 is in communication with the transceiver antenna 40, and a switch contact of the second control switch 60 is closed to a signal output end of the low noise amplifier LNA21 to make the low noise amplifier LNA21
- the signal output end is connected to the signal input end of the down converter 22, and the transceiver antenna 40, the low noise amplifier LNA21, the down converter 22, and the analog to digital converter ADC23 form a receiver.
- the received signal is converted into a high-power signal by the low-noise amplifier LNA21, and then demodulated by the down-converter 22 to become a low-frequency baseband analog signal, and then converted into a baseband digital signal by the analog-to-digital converter ADC23, and then the analog-to-digital converter
- the second signal output port of the ADC 23 outputs a received signal from the transceiver antenna.
- the embodiment of the present invention utilizes the characteristics of time division multiplexing of the TDD system, and when the system transmitter works, the down converter and the ADC module in the receiver of the multiplexing system realize the whole.
- the function of the system observing machine, and when the system receiver works, the downconverter and ADC module in the receiver are re-used as the functional modules of the receiver. Therefore, the embodiment of the present invention implements the observing machine by multiplexing the functional modules of the receiver, which is relatively expensive compared to the prior art, and can greatly save the hardware cost of the observing circuit of the system.
- the radio transceiver of the embodiment of the present invention may be a base station, such as a macro base station or a micro base station, and its structure and working principle are as described in the foregoing FIG. 2 to FIG. 6, and details are not described herein again.
- the wireless transceiver in the embodiment of the present invention may also be an access point AP in a WiFi system, or may be a mobile terminal, such as a mobile phone or an in-vehicle terminal.
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Abstract
本发明实施例公开了一种无线收发信机其中,所述无线收发信机包括:第二控制开关,所述第二控制开关可选择性地将耦合器的信号输出端或低噪声放大器LNA的信号输出端与所述下变频器的信号输入端相连将,因此,当所述耦合器的信号输出端与所述下变频器连通时,所述耦合器、所述下变频器、所述模数转换器ADC组成观测机,当所述第二控制开关将所述低噪声放大器LNA的信号输出端与所述下变频器的信号输入端连通时,所述收发天线、所述低噪声放大器LNA、所述下变频器、所述模数转换器ADC组成收信机。因此,本发明实施例可大大节省系统实现观测机电路的硬件成本。
Description
一种无线 信机
技术领域
本发明涉及通信技术领域, 尤其涉及一种无线收发信机。 背景技术
预失真( Pre-distortion) 技术是通过在非线性功率放大器 ( Power Amplifier, PA )前级联一个与转换函数(幅度和相位)特性相反的数字预失 真器(Digital Pre-distortion, DPD ) , 预先 4巴输入信号往功放特性相反的方向 变化, 从而使 ΡΑ的输入输出在整体上呈现线性关系。 由于功放的非线性特性 在实际环境中会因为温度、 湿度、 供电电压、 器件老化和信道切换等原因发生 改变, 为了保证系统的稳定线性输出,要求预失真器能够根据功放特性的改变 而自动调节。
如图 1所示, 现有技术中, 为了动态的通过算法调整非线性放大器 ΡΑ引起 的失真度, 增加一部分电路调整电路, 称为观测机电路(包括图 1中依次相连 的耦合器、 下变频器、 模数转换器 ADC、 算法模块) 。 在图 1中, 耦合器得到 PA的失真信号后, 利用下变频器变为基带信号, 经过模数转换器 (Analog Digital Converter, ADC )进行模数转换, 然后通过算法模块进行一定的算法 进行调整, 以保证后续输入到 DPD的信号经 线性输出。
参考图 1可知, 现有技术的上述方案为了实现预失真技术, 需要在时分复 用( Time Division Duplexing, TDD )原有的收发信系统中增加一部分电路 (观 测机) , 这样无疑增加了系统的硬件成本。 发明内容
本发明实施例提供了一种无线收发信机,用以解决现有技术中为了做预失 真处理而增加观测机电路导致的硬件成本增加的问题。
本发明实施例第一方面提供一种无线收发信机, 其特征在于, 包括: 数字预失真器 DPD ( 11 )、 数模转换器 DAC ( 12 )、 上变频器( 13 )、 功率 放大器 PA ( 14 )、 第一控制开关 (30 )、 收发天线(40 )、 耦合器(50 )、 低噪
声放大器 LNA ( 21 )、 第二控制开关( 60 )、 下变频器( 22 )、 模数转换器 ADC (23), 其中:
所述数字预失真器 DPD (11), 所述数模转换器 DAC ( 12 )、 所述上变频 器( 13 )、 所述功率放大器 PA ( 14 )、 所述耦合器( 50 )依次相连;
所述第一控制开关(30)选择性地将所述功率放大器 PA (14) 的信号输 出端或所述低噪声放大器 LNA (21) 的信号输入端与所述收发天线(40)连 通;
所述第二控制开关(60)选择性地将所述耦合器(50)的信号输出端或所 述低噪声放大器 LNA (21) 的信号输出端与所述下变频器(22) 的信号输入 端相连;
所述下变频器(22) 的信号输出端与所述模数转换器 ADC (23) 的信号 输入端相连。
在第一方面的第一种可能的实现方式中, 所述数字预失真器 DPD (11) 包括算法模块(70), 所述算法模块用于根据输入的原始信号以及模数转化器 ADC ( 23 )第一信号输出端输出的信号, 获得预失真模型的系数。
在第一方面的另一种可能的实现方式中,所述无线收发信机包括算法模块 (70), 所述算法模块(70)的第一输入端与所述模数转换器 ADC (23)的第 一信号输出端相连,所述算法模块( 70 )的第二输入端输入的信号为原始信号, 所述算法模块(70) 的输出端与所述数字预失真器 DPD (11) 的输入端相连, 所述算法模块用于根据输入的原始信号以及模数转化器 ADC (23)输出的信 号, 获得预失真模型的系数。
由上可见, 本发明实施例的无线收发信机包括第二控制开关, 所述第二控 制开关可选择性地将所述耦合器的信号输出端或所述低噪声放大器 LNA的信 号输出端与所述下变频器的信号输入端相连, 因此, 当所述耦合器的信号输出 端与所述下变频器连通时,所述耦合器、所述下变频器、所述模数转换器 ADC 组成观测机, 当所述第二控制开关将所述低噪声放大器 LNA的信号输出端与 所述下变频器的信号输入端连通时, 所述收发天线、 所述低噪声放大器 LNA、 所述下变频器、 所述模数转换器 ADC组成收信机。 因此, 本发明实施例可通 过第二控制开关, 重用无线收发信机已有的下变频器和数模转换器 ADC来实
现观测机的功能, 实现了观测机与收信机的有效兼容,其相对于新增电路的情 况, 可大大节省系统实现观测机电路的硬件成本。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施 例中所需要使用的附图作简单地介绍,显而易见地, 下面描述中的附图仅仅是 本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的 前提下, 还可以根据这些附图获得其他的附图。
图 1为现有技术中的无线收发信机的结构示意图。
图 2为本发明的无线收发信机的一实施例的结构示意图。
图 3为本发明的无线收发信机的另一实施例的结构示意图。
图 4为本发明的无线收发信机的又一实施例的结构示意图。
图 5为本发明的无线收发信机的发信机工作时的结构示意图。
图 6为本发明的无线收发信机的收信机工作时的结构示意图。 具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清 楚、 完整地描述, 显然, 所描述的实施例仅仅是本发明一部分实施例, 而不是 全部的实施例。基于本发明中的实施例, 本领域普通技术人员在没有作出创造 性劳动前提下所获得的所有其他实施例, 都属于本发明保护的范围。
图 2为本发明的无线收发信机的一实施例的结构示意图。如图 2所示, 其 可包括:
数字预失真器 DPD11、 数模转换器 DAC12、 上变频器 13、 功率放大器 PA14、 第一控制开关 30、 收发天线 40、 耦合器 50、 低噪声放大器 LNA21、 第二控制开关 60、 下变频器 22、 模数转换器 ADC23 , 其中: 所述数字预失真 器 DPD11、所述数模转换器 DAC12、所述上变频器 13、所述功率放大器 PA14、 所述耦合器 50依次相连; 本发明实施例所指的依次相连, 是指上一个器件的 输出端与下一个器件的输入端相连, 依此类推。 所述第一控制开关 30选择性 地将所述功率放大器 PA14的信号输出端或所述低噪声放大器 LNA21的信号
输入端与所述收发天线 40连通;所述第二控制开关 60选择性地将所述耦合器 50的信号输出端或所述低噪声放大器 LNA21的信号输出端与所述下变频器 22 的信号输入端相连;所述下变频器 22的信号输出端与所述模数转换器 ADC23 的信号输入端相连; 所述模数转换器 ADC23的信号输出端与所述数字预失真 器 DPD11的信号输入端相连。
第一控制开关 30 可以釆用时分复用的方式选择性地将所述功率放大器 PA14 的信号输出端或所述低噪声放大器 LNA21 的信号输入端与所述收发天 线 40连通;所述第二控制开关 60釆用时分复用的方式选择性地将所述耦合器 50的信号输出端或所述低噪声放大器 LNA21的信号输出端与所述下变频器 22 的信号输入端相连。
当所述第一控制开关 30闭合使所述功率放大器 PA14的信号输出端与所 述收发天线 40连通时, 所述第二控制开关 60闭合使所述耦合器 50的信号输 出端与所述下变频器 22连通;当所述第一控制开关 30闭合使所述低噪声放大 器 LNA21的信号输入端与所述收发天线 40连通时, 所述第二控制开关 60闭 合使所述低噪声放大器 LNA21的信号输出端与所述下变频器 22的信号输入端 连通。
具体实现中, 本发明实施例的无线收发信机可为 TDD无线收发信机, 第 一控制开关 30和第二控制开关 60可以通过天线开关在时间上进行区分和控 制, 这样第一控制开关 30则可根据系统时分复用的原则 (比如, 在 TD-LET 中, 收发比例为 1 : 1 , 那么 lms的时间可划分为 500us发, 500us收)釆用时 分复用的方式选择性地将地将所述功率放大器 PA14的信号输出端或所述低噪 声放大器 LNA21的信号输入端与所述收发天线 40连通。如前 500us为信号发 射周期, 则将通过第一控制开关 30将所述功率放大器 PA14的信号输出端与 所述收发天线 40连通; 后 500us为信号接收周期, 则通过第一控制开关 30将 所述低噪声放大器 LNA21的信号输入端与所述收发天线 40连通。
具体地, 本发明实施例的数字预失真器 DPD11可以预置预失真模型的系 数, 当接收到经由模数转换器 ADC23输出的信号时, 可以根据预置的预失真 模型的系数, 实现对输入信号的预失真处理, 用以补偿功率放大器 PA14的非 线性失真。
具体实现中, 在该实施例中, 本发明实施例的数模转换器 DAC12的釆样 频率为基带信号带宽的 K倍, 其中, K为所述功率放大器 PA14的失真模型阶 数(比如, 3阶或者 5阶); 在这个条件下, 可保证信号经非线性器件 PA14后 没有混叠失真。 本发明实施例的模数转换器 ADC23 的频率可与模数转换器 DAC12 的频率保持一致。 此时, 在收信机电路中可无失真恢复接收信号和发 送给 DPD的反馈信号。
本发明实施例中,第二控制开关 60可选择性地将所述耦合器 50的信号输 出端或所述低噪声放大器 LNA21的信号输出端与所述下变频器 22的信号输入 端相连, 当所述耦合器 50的信号输出端与所述下变频器 22连通时, 所述耦合 器 50、 所述下变频器 22、 所述模数转换器 ADC23组成观测机, 当所述第二控 制开关 60将所述低噪声放大器 LNA21的信号输出端与所述下变频器 22的信 号输入端连通时, 所述收发天线 40、 所述低噪声放大器 LNA21、 所述下变频 器 22、 所述模数转换器 ADC23组成收信机。 因此, 本发明实施例可通过第二 控制开关, 重用无线收发信机已有的下变频器和数模转换器 ADC来实现观测 机的功能, 实现了观测机与收信机的有效兼容, 其比现有技术中新增观测机电 路的情况, 可大大节省系统实现观测机电路的硬件成本。 图 3为本发明的无线收发信机的另一实施例的结构示意图。与上一实施例 的区别是, 本实施例在模数转换器 ADC23后, 增加一个算法模块 70, 该算法 模块 70可以集成在数字预失真器 DPD11里, 也可以是一个单独模块。 算法模 块 70作为单独模块时,可以为 DSP ( Digital Signal Processing,数字信号处理) 芯片, 或 FPGA ( Field - Programmable Gate Array, 现场可编程门阵列 )等, 本发明实施例在此不作限定。
如图 3所示, 以算法模块 70为一个单独模块为例, 该无线收发信机包括: 数字预失真器 DPD11、 数模转换器 DAC12、 上变频器 13、 功率放大器 PA14、 第一控制开关 30、 收发天线 40、 耦合器 50、 低噪声放大器 LNA21、 第二控制开关 60、下变频器 22、模数转换器 ADC23 , 以及算法模块 70,其中: 所述数字预失真器 DPD11、 所述数模转换器 DAC12、 所述上变频器 13、 所述 功率放大器 PA14、 所述耦合器 50依次相连。 所述第一控制开关 30选择性地
将所述功率放大器 PA14的信号输出端或所述低噪声放大器 LNA21的信号输 入端与所述收发天线 40连通; 所述第二控制开关 60选择性地将所述耦合器 50的信号输出端或所述低噪声放大器 LNA21的信号输出端与所述下变频器 22 的信号输入端相连; 所述下变频器 22的信号输出端与所述模数转换器 ADC23 的信号输入端相连; 所述算法模块 70的第一输入端与所述模数转换器 ADC23 的第一信号输出端相连, 所述算法模块 70的第二输入端输入的信号为原始信 号, 所述算法模块 70的输出端与所述数字预失真器 DPD11的输入端相连, 所 述算法模块 70用于根据输入的原始信号以及模数转化器 ADC23的第一信号输 出端输出的信号, 获得预失真模型的系数。
可选地, 当算法模块 70集成在数字预失真器 DPD11里时, 用于根据输入 的原始信号以及模数转化器 ADC23的第一信号输出端输出的信号, 获得预失 真模型的系数。
本发明实施例中数字预失真器 11 的预失真处理模型与功率放大器 PA14 的模型相关, 可以用带记忆效应的多项式级数表示, 如 Volterra级数的简化模 型。 本发明实施例对数字预失真器 11的预失真处理模型不作限制。 算法模块 70 输出的预失真模型的参数, 可以根据两路信号作差并求解得到, 如通过比 较原始输入信号和经过功率放大器 PA14以及下变频 32, 模数转换器 ADC23 等处理后的信号得到。 当所述第一控制开关 30将所述功率放大器 PA14的信号输出端与所述收 发天线 40连通、 以及所述第二控制开关 60将所述耦合器 50的信号输出端与 所述下变频器 22连通时,所述数字预失真器 DPD11、所述数模转换器 DAC12、 所述上变频器 13、 所述功率放大器 PA14与所述收发天线 40组成发信机; 所 述耦合器 50、 所述下变频器 22、 所述模数转换器 ADC23 , 所述算法模块 70 组成观测机。
当所述第一控制开关 30将所述低噪声放大器 LNA21的信号输入端与所述 收发天线 40连通, 以及所述第二控制开关 60将所述低噪声放大器 LNA21的 信号输出端与所述下变频器 22的信号输入端连通时, 所述收发天线 40、 所述 低噪声放大器 LNA21、 所述下变频器 22、 所述模数转换器 ADC23组成收信
机, 其中, 所述模数转换器 ADC23的第二信号输出端口用于输出来自收发天 线 40的接收信号。
本发明实施例通过第二控制开关,重用无线收发信机已有的下变频器和数 模转换器 ADC来实现观测机的功能, 实现了观测机与收信机的有效兼容, 其 相对于新增电路的情况, 可大大节省系统实现观测机电路的硬件成本。 图 4为本发明的无线收发信机的又一实施例的结构示意图。 如图 4所示, 本实施例在图 3 的实施例的基础上, 在算法模块 70和模数转换模器 ADC23 之间连接有插值补偿模块 90和预失真映射模块 80, 其中,
所述预失真映射模块 80用于将所述模数转换器 ADC第一信号输出端输出 的信号进行预失真处理, 补偿所述功率放大器 PA带来的失真。
所述插值补偿模块 90用于将所述预失真映射模块 80处理后的信号进行插 值补偿。具体实现中,插值补偿模块 90可通过插值的方式对 ADC23输出的信 号进行插值补偿。 具体的, 插值补偿模块 90可以釆用双线性插值, 高阶样条 插值等算法对 ADC23输出的信号进行插值补偿。本发明实施例在此不作限制。
图 4与图 3不同的是, 图 4中算法模块 70的第二信号输入端与所述数字预失 真器 DPD的信号输出端相连, 即图 4实施例中的算法模块的输入信号之一是数 字预失真器 DPD处理之后的信号, 而图 3实施例中的算法模块的输入信号之一 是原始信号, 未经数字预失真器 DPD处理。
由此,本发明实施例由于插值补偿模块 90可对信号进行釆样点补充,因此, 所述模数转换器 ADC23的釆样频率可得到降低, 比如,最低为基带信号带宽的 2倍。 在现有技术中, 在 ADC处理的信号是失真信号, 由于其频傳的扩展, 如 果只考虑 3阶和 5阶交调失真, 其频谱带宽大约会扩展到原信号带宽的 5倍, 通 常是釆用很高的釆样率对失真反馈信号进行釆样,对器件的要求很高。 而本发 明实施例通过在 ADC23之后连接预失真映射模块 80和插值补偿模块 90之后,可 对 ADC23输出的信号进行预失真处理和插值补偿, 此时, ADC23的釆样频率 可得到降低, 最低可为基带信号带宽的 2倍。
由此, 本发明实施例在复用 ADC23时, 还可降低系统对 ADC23釆样频 率的要求, 以及降低 ADC硬件成本。
以下通过图 3的结构实施例,利用图 5和图 6对本发明实施例的信号流向 进行说明。 具体的, 如图 5所示, 在本发明实施例中, 当无线收发信机的发信 机工作时, 第一控制开关 30的开关触点向所述功率放大器 PA14的信号输出 端闭合使所述功率放大器 PA14与所述收发天线 40连通; 所述第二控制开关 60的开关触点向所述耦合器 50的信号输出端闭合以使所述耦合器 50与所述 下变频器连通。 此时, 所述数字预失真器 DPD11、 所述数模转换器 DAC12、 所述上变频器 13、所述功率放大器 PA14与所述收发天线 40则可组成发信机, 所述耦合器 50、 所述下变频器 22、 所述模数转换器 ADC23 , 所述算法模块 70 则可组成观测机(其中, 下变频器 22、 模数转换器 ADC23为 TDD无线收发 信机固有的收信机部件)。 由图 5可知, 此时整个系统的信号流走向如下 (参 见图 5中虚线箭头的走向):
发射数字基带信号(包括同相分量 I ( Inphase Components )和正交分量 Q ( Quadrature Components )两路信号)输入到数字预失真器 DPD11 ,经过 DPD11 校正,然后经 DAC12转换为模拟信号,然后经上变频器 13载波调制变为高频信 号, 然后经过功率放大器 PA14变为大功率信号, 然后通过收发天线 40发射出 去。 由于信号经过 PA放大后变为大功率信号, 在观测机工作时需要把功率降 下来, 这部分功能通过耦合器进行信号衰减, 衰减后的小功率信号通过第二控 制开关 30经下变频器 22降频后,经 ADC23转化为数字基带信号,通过模数转换 器 ADC的第一信号输出端口反馈给算法模块 70,这部分反馈信号与输入信号在 算法模块 70进行预失真模型参数获取, 即计算失真的具体程度, 形成对输入信 号的调整模型, 控制 DPD11模块进行具体的对输入信号的调整。
进一步, 如图 6所示, 在本发明实施例中, 当无线收发信机的收信机工作 时,所述第一控制开关 30的开关触点向低噪声放大器 LNA21的信号输入端闭 合使所述低噪声放大器 LNA21的信号输入端与所述收发天线 40连通,所述第 二控制开关 60的开关触点向所述低噪声放大器 LNA21的信号输出端闭合,以 使所述低噪声放大器 LNA21的信号输出端与所述下变频器 22的信号输入端连 通, 此时, 所述收发天线 40、 所述低噪声放大器 LNA21、 所述下变频器 22、 所述模数转换器 ADC23组成收信机。 由图 6可知, 此时整个系统的信号流走 向如下 (参见图 6中虚线箭头的走向):
接收信号经低噪声放大器 LNA21变为大功率信号,然后经下变频器 22解调 后变为低频基带模拟信号,再经模数转换器 ADC23转换为基带数字信号后, 由 所述模数转换器 ADC23的第二信号输出端口输出来自收发天线的接收信号。进 行接收。
通过比较图 5和图 6可知, 本发明实施例利用了 TDD系统收发时分复用 的特点, 在系统发信机工作时, 复用系统的收信机中的下变频器和 ADC模块 来实现整个系统观测机的功能, 而在系统收信机工作时, 收信机中的下变频器 和 ADC模块又重新被作为收信机的功能模块。 由此, 本发明实施例通过复用 收信机的功能模块来实现观测机, 其相对于现有技术需新增观测机电路的方 案, 可大大节省系统实现观测机电路的硬件成本。
本发明实施例的无线收发信机, 可以是基站, 如宏基站或微基站, 其结构 及工作原理如上面图 2至图 6的相关介绍, 在此不再赘述。 另外, 本发明实施 例的无线收发信机也可以是 WiFi系统里的接入点 AP,也可以是移动终端,如 手机或车载终端。 以上实 施例的说明只是用于帮助理解本发明的方法及其核心思想; 同时,对于本领域 的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改 变之处, 综上所述, 本说明书内容不应理解为对本发明的限制。
Claims
权 利 要 求
1、 一种无线收发信机, 其特征在于, 包括:
数字预失真器 DPD ( 11 )、 数模转换器 DAC ( 12 )、 上变频器( 13 )、 功率 放大器 PA (14)、 第一控制开关 (30)、 收发天线(40)、 耦合器(50)、 低噪 声放大器 LNA ( 21 )、 第二控制开关( 60 )、 下变频器( 22 )、 模数转换器 ADC (23), 其中:
所述数字预失真器 DPD (11), 所述数模转换器 DAC ( 12 )、 所述上变频 器( 13 )、 所述功率放大器 PA ( 14 )、 所述耦合器( 50 )依次相连;
所述第一控制开关(30)选择性地将所述功率放大器 PA (14) 的信号输 出端或所述低噪声放大器 LNA (21) 的信号输入端与所述收发天线(40)连 通;
所述第二控制开关(60)选择性地将所述耦合器(50)的信号输出端或所 述低噪声放大器 LNA (21) 的信号输出端与所述下变频器(22) 的信号输入 端相连;
所述下变频器(22) 的信号输出端与所述模数转换器 ADC (23) 的信号 输入端相连。
2、 如权利要求 1所述的无线收发信机, 其特征在于, 所述数字预失真器 DPD (11) 包括算法模块(70), 所述算法模块(70)用于根据输入的原始信 号以及模数转化器 ADC (23)第一信号输出端输出的信号, 获得预失真模型 的系数。
3、 如权利要求 1所述的无线收发信机, 其特征在于, 所述无线收发信机 包括算法模块( 70 ),所述算法模块( 70 )的第一输入端与所述模数转换器 ADC
(23)的第一信号输出端相连, 所述算法模块(70)的第二输入端输入的信号 为原始信号, 所述算法模块(70) 的输出端与所述数字预失真器 DPD (11) 的输入端相连, 所述算法模块用于根据输入的原始信号以及模数转化器 ADC
( 23 )输出的信号, 获得预失真模型的系数。
4、 如权利要求 2或 3所述的无线收发信机, 其特征在于,
当所述第一控制开关(30)将所述功率放大器 PA ( 14) 的信号输出端与 所述收发天线(40)连通、 以及所述第二控制开关(60)将所述耦合器(50) 的信号输出端与所述下变频器(22)连通时, 所述数字预失真器 DPD ( 11)、 所述数模转换器 DAC ( 12 )、 所述上变频器( 13 )、 所述功率放大器 PA ( 14 ) 与所述收发天线(40)组成发信机, 所述耦合器(50)、 所述下变频器(22)、 所述模数转换器 ADC ( 23 ), 所述算法模块( 70 )组成观测机;
当所述第一控制开关(30)将所述低噪声放大器 LNA (21 ) 的信号输入 端与所述收发天线(40)连通, 以及所述第二控制开关(60)将所述低噪声放 大器 LNA (21 ) 的信号输出端与所述下变频器(22) 的信号输入端连通时, 所述收发天线(40)、 所述低噪声放大器 LNA (21)、 所述下变频器(22)、 所 述模数转换器 ADC (23)组成收信机, 其中, 所述模数转换器 ADC ( 23 ) 的 第二信号输出端口用于输出来自天线的接收信号。
5、 如权利要求 1所述的无线收发信机, 其特征在于, 所述无线收发信机 包括算法模块(70), 预失真映射模块(80), 插值补偿模块(90), 其中, 所述算法模块(70)的第一输入端与所述插值补偿模块(90)的信号输出 端相连, 所述算法模块(70) 的第二输入端与所述预失真器 DPD ( 11 ) 的信 号输出端相连, 所述算法模块(70) 的输出端与所述数字预失真器 DPD ( 11 ) 的输入端相连, 所述算法模块(70)用于根据所述预失真器 DPD ( 11 )处理 后的信号以及所述插值补偿模块(90)输出的信号, 获得预失真模型的系数。
6、 如权利要求 5所述的无线收发信机, 其特征在于,
所述预失真映射模块(80)用于将所述模数转换器 ADC (23) 第一信号 输出端输出的信号进行预失真处理, 补偿所述功率放大器 PA ( 14) 带来的失 真;
所述插值补偿模块( 90 )用于将所述预失真映射模块( 80 )处理后的信号 进行插值补偿。
7、 如权利要求 1-6 中任一项所述的无线收发信机, 其特征在于, 所述第 一控制开关 (30)釆用时分复用的方式选择性地将所述功率放大器 PA (14) 的信号输出端或所述低噪声放大器 LNA( 21)的信号输入端与所述天线(40) 连通;
所述第二控制开关( 60 )釆用时分复用的方式选择性地将所述耦合器( 50 ) 的信号输出端或所述低噪声放大器 LNA (21) 的信号输出端与所述下变频器 (22) 的信号输入端相连。
8、 如权利要求 1-7 中任一项所述的无线收发信机, 其特征在于, 当所述 第一控制开关(30) 闭合使所述功率放大器 PA (14) 的信号输出端与所述收 发天线(40)连通时, 所述第二控制开关(60) 闭合使所述耦合器(50)的信 号输出端与所述下变频器(22)连通;
当所述第一控制开关(30) 闭合使所述低噪声放大器 LNA (21) 的信号 输入端与所述收发天线(40)连通时, 所述第二控制开关(60)闭合使所述低 噪声放大器 LNA (21) 的信号输出端与所述下变频器(22) 的信号输入端连 通。
9、 如权利要求 1至 8任一项所述的无线收发信机, 其特征在于, 所述无 线收发信机为移动终端。
10、 如权利要求 1至 8任一项所述的无线收发信机, 其特征在于, 所述无 线收发信机为基站或 WiFi系统的接入点 AP。
Priority Applications (4)
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|---|---|---|---|
| CN201380078357.5A CN105409178B (zh) | 2013-12-23 | 2013-12-23 | 一种无线收发信机 |
| EP13900178.8A EP3018874B1 (en) | 2013-12-23 | 2013-12-23 | Wireless transceiver |
| PCT/CN2013/090243 WO2015096010A1 (zh) | 2013-12-23 | 2013-12-23 | 一种无线收发信机 |
| US15/014,851 US9762268B2 (en) | 2013-12-23 | 2016-02-03 | Wireless transceiver |
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| PCT/CN2013/090243 WO2015096010A1 (zh) | 2013-12-23 | 2013-12-23 | 一种无线收发信机 |
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| US15/014,851 Continuation US9762268B2 (en) | 2013-12-23 | 2016-02-03 | Wireless transceiver |
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| Country | Link |
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| US (1) | US9762268B2 (zh) |
| EP (1) | EP3018874B1 (zh) |
| CN (1) | CN105409178B (zh) |
| WO (1) | WO2015096010A1 (zh) |
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| US12107611B2 (en) | 2020-12-11 | 2024-10-01 | Intel Corporation | Receiver with reduced noise figure using split LNA and digital combining |
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| CN107395246A (zh) * | 2017-07-19 | 2017-11-24 | 泉州泽仕通科技有限公司 | 全波段多功能数字通信电台及其运行方法 |
| US10615754B2 (en) * | 2017-08-10 | 2020-04-07 | Commscope Technologies Llc | Methods and apparatuses for digital pre-distortion |
| US11038474B2 (en) * | 2017-11-01 | 2021-06-15 | Analog Devices Global Unlimited Company | Phased array amplifier linearization |
| US10985951B2 (en) | 2019-03-15 | 2021-04-20 | The Research Foundation for the State University | Integrating Volterra series model and deep neural networks to equalize nonlinear power amplifiers |
| US10972139B1 (en) * | 2020-04-15 | 2021-04-06 | Micron Technology, Inc. | Wireless devices and systems including examples of compensating power amplifier noise with neural networks or recurrent neural networks |
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| CN115085743A (zh) * | 2021-03-11 | 2022-09-20 | 中国电信股份有限公司 | 双通道数字射频拉远系统 |
| US11901925B2 (en) * | 2021-07-21 | 2024-02-13 | Marvell Asia Pte Ltd | Method and apparatus for cancelling front-end distortion |
| EP4354742A1 (en) * | 2022-10-12 | 2024-04-17 | Nokia Technologies Oy | Flexible reception |
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Also Published As
| Publication number | Publication date |
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| EP3018874A1 (en) | 2016-05-11 |
| CN105409178A (zh) | 2016-03-16 |
| EP3018874A4 (en) | 2016-08-17 |
| US20160156375A1 (en) | 2016-06-02 |
| CN105409178B (zh) | 2019-03-05 |
| US9762268B2 (en) | 2017-09-12 |
| EP3018874B1 (en) | 2018-05-23 |
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