WO2015096385A1 - 一种栅极驱动电路、显示装置及驱动方法 - Google Patents

一种栅极驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2015096385A1
WO2015096385A1 PCT/CN2014/078638 CN2014078638W WO2015096385A1 WO 2015096385 A1 WO2015096385 A1 WO 2015096385A1 CN 2014078638 W CN2014078638 W CN 2014078638W WO 2015096385 A1 WO2015096385 A1 WO 2015096385A1
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WIPO (PCT)
Prior art keywords
shift register
gate
unit
line
control
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2014/078638
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English (en)
French (fr)
Inventor
李红敏
李小和
张晓洁
邵贤杰
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to KR1020157014065A priority Critical patent/KR101692656B1/ko
Priority to US14/424,917 priority patent/US9520098B2/en
Priority to EP14838766.5A priority patent/EP2911146A4/en
Priority to JP2016561055A priority patent/JP2017503218A/ja
Publication of WO2015096385A1 publication Critical patent/WO2015096385A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a display device. Set the driving method.
  • FIG. 1 is a circuit diagram of a liquid crystal display panel array substrate in the prior art.
  • the array substrate includes a plurality of data lines 1, a plurality of gate lines 2, Gate1 to Gate8, and a plurality of pixel units defined by a plurality of data lines and a plurality of gate lines, the plurality of pixels
  • the cells form an array of pixel cells; each pixel cell passes through a thin film transistor (Thin Film Transistor (TFT) is connected to a gate line and a data line, and the gate line is connected.
  • TFT Thin Film Transistor
  • the data line is connected to the source of the thin film transistor, each of which The odd columns in the pixel unit are connected to the same gate line, and the even columns are connected to the other gate line.
  • the adjacent two columns of pixel units are connected to the same data line.
  • Multiple data lines 1 are driven by data
  • the circuit is driven to receive the data signal output by the data driving circuit; the plurality of gate lines 2 are connected to a gate driving circuit including a plurality of shift register units SR1 to SR8, Sequentially turned on and off during a frame scan, the pulse signals generated after turning on are respectively Output to the plurality of gate lines 2.
  • the first shift The register unit SR1 After the start of the frame scan, the first scan period, the first shift The register unit SR1 turns on and outputs a pulse signal to the first gate line Gate1, so that the first line The thin film transistor of the pixel unit of the odd column is turned on, and the corresponding data line receives the data signal pair The pixel unit of the odd row of the first row is charged, and the corresponding data is stored; in the second scan period, The first shift register unit SR1 is turned off, and the second shift register unit SR2 is turned on and output Pulse signal to the second gate line Gate2, at this time, the film of the first row of even-numbered column pixel units The transistor is turned on and the corresponding data line charges the first row of even-numbered column pixel cells.
  • the first row of even-numbered column pixel units is undercharged.
  • the third shift register SR3 outputs a pulse signal to the third gate line Gate3, and the second row is odd
  • the column pixel unit starts charging, at this time, since the data signal on the data line is always negative, In the second row of odd-numbered columns, the pixel unit charging time and charging rate are sufficient. But the second row is even Column pixel units also appear to be undercharged.
  • the present invention is in the original shift Based on the bit register, the gate drive circuit structure is improved, and different frames are realized. Inter-charge rate compensation to improve the vertical streak (V-line) of existing products Elephant.
  • a gate drive circuit comprising a plurality of cascades Shift register unit and control unit, two adjacent shift register units are one shift a register set connected to the two gate lines by the control unit; the control unit controls Shift register units in the shift register set are respectively provided to the two gate lines Drive signal.
  • control unit includes a first control line, a second control line, and the A thin film transistor connected to the shift register unit.
  • each shift register unit in the shift register group passes two thin Membrane transistors are respectively connected to the first control line and the second control line, the two thin film crystals
  • the gates of the body tubes are respectively connected to the first control line and the second control line, and the drains are respectively connected To the two gate lines, the sources are respectively connected to the output terminals of the shift register unit.
  • control unit controls the shift register unit in the shift register group to Different ones of the two gate lines provide a drive signal.
  • the first control line and the second control line alternately output a high potential driving signal.
  • the two gate lines are respectively associated with odd columns and even numbers in the pixel cell array
  • the column pixel units are connected.
  • the gate line and the pixel unit pass through the pixel unit thin film transistor phase Connecting the gate of the pixel unit thin film transistor to the gate line, and connecting the drain to a pixel electrode of the pixel unit, the source being connected to the data line.
  • a display device comprising the above Gate drive circuit.
  • the display device comprises N rows ⁇ M columns of pixel units, 2N gate lines And M/2 data lines, wherein the 2N gate lines are intersected with the M/2 data lines
  • the pixel unit, the odd gate line is connected to the odd column pixel unit, and the even gate line is connected to the even a series of pixel units, adjacent odd pixel units and even pixel units connected to the same data line,
  • the two gate lines are adjacent odd gate lines and even gate lines.
  • a drive for a display device as described above Method which includes:
  • the control unit controls the open shift register unit to an odd gate of the two gate lines a polar or even gate line provides a drive signal;
  • Control control unit controls said open shift register unit to be in said two gate lines
  • the even gate line or the odd gate line provides a drive signal.
  • the current frame scan includes:
  • the first shift register unit turned on by the meta control controls the two gate lines connected thereto
  • the odd gate line in the middle provides a drive signal to the odd-numbered column of pixel units through the data line to the nth row Charging
  • the second shift register unit turned on by the element controls an even gate of the two gate lines
  • the polar line provides a driving signal for charging the n-th row of even-numbered column pixel units through the data line;
  • the next frame scan includes:
  • the first shift register unit turned on by the meta control controls the two gate lines connected thereto
  • the even gate line in the middle provides the driving signal, and the pixel unit is in the nth row even column through the data line Charging
  • the second shift register unit turned on by the element controls an odd gate of the two gate lines
  • the polar line provides a driving signal for charging the n-th row of odd-numbered column pixel units through the data line;
  • the adjacent two rows of pixel units have opposite charging polarities and are connected to the same data line.
  • Two adjacent columns of pixel units have opposite charging polarities and are connected to adjacent two columns of pixels of different data lines.
  • the unit charging polarity is the same, and n is a natural number less than or equal to N.
  • the present invention improves the gate driving circuit by providing a control unit in the gate driving circuit Structure, such that the control unit controls adjacent two shift register units to be adjacent to two adjacent
  • the gate line provides a drive signal, and the two shift register units are provided in adjacent two frame scans
  • the gate lines of the drive signals are different.
  • the above solution proposed by the present invention adopts a point reversal in the display device In the drive mode, the charging order of the odd-numbered columns of pixel units in the adjacent two frames is not Same, so that the odd-numbered or even-numbered column pixel units are fully charged in the current frame, and the next frame is charged. Insufficient, thereby improving the phenomenon of vertical streaking (V-line).
  • FIG. 1 is a circuit diagram of a liquid crystal display panel array substrate in the prior art
  • FIG. 2 is a partial schematic structural view of a gate driving circuit in an alternative embodiment of the present invention.
  • FIG. 3 is a diagram showing a connection between a gate driving circuit and a pixel cell array in an alternative embodiment of the present invention. Connected to the schematic.
  • the invention provides a gate driving circuit comprising a plurality of cascaded shift register Element and control unit, two adjacent shift register units are a shift register group,
  • the control unit is connected to two gate lines; the control unit controls the shift register Shift register cells in the group provide drive signals to the two gate lines, respectively.
  • FIG. 2 is a partial schematic view showing the structure of a gate driving circuit proposed by the present invention.
  • the gate drive circuit includes a control unit 10 and a plurality of cascaded shift registers Unit 11, wherein two adjacent shift register units are a shift register group, The first shift formed by the two shift register units SR1 to SR2 is schematically shown in the embodiment.
  • Register groups those skilled in the art should know that the number is based on the pixel array of the display device The column size is determined.
  • Each shift register group corresponds to two adjacent gate lines Gate1 to Gate2,
  • the control unit 10 controls two shift register units in the shift register group SR1 to SR2 respectively supply driving signals to the two adjacent gate lines Gate1 to Gate2.
  • the control unit 10 includes a first control line 101, a second control line 102, and a plurality of A thin film transistor 103 connected to the shift register unit. Every two adjacent shifts
  • the memory unit 11 is a shift register group, and each shift register group is shifted.
  • the register unit passes through two thin film transistors respectively with the first control line 101 and the second control Line 102 is connected.
  • first shift register unit in the shift register group SR1 is respectively connected to the first thin film transistor T1 and the second thin film transistor T2
  • the first control line 101 and the second control line 102 are connected to each other, the first thin film transistor T1
  • the gate is connected to the first control line 101
  • the gate of the second thin film transistor T2 is connected to the second control
  • the line 102 is connected, and the drains of the first thin film transistor T1 and the second thin film transistor T2 Connected to two adjacent gate lines Gate1 to Gate2, respectively, the first thin film transistor T1 And a source of the second thin film transistor T2 is connected to an output of the first shift register SR1
  • the second shift register unit SR2 in the first shift register group is connected
  • the adjacent third thin film transistor T3 and the fourth thin film transistor T4 are respectively associated with the first control
  • the line 101 is connected to the second control 102, and the gate of the third thin film transistor T3 is connected.
  • each adjacent two shift register units is a shift register group, each shift register The group corresponds to four thin film transistors, and each shift register in each shift register group
  • the cells are connected to the first control line 101 and the second control line 102 through two thin film transistors, respectively.
  • the control unit 10 controls a shift register unit in the shift register group to Different ones of the two adjacent gate lines provide a drive signal.
  • the first control line 101 and the second control line 102 alternately output a high potential driving signal.
  • the first control line 101 outputs a high potential driving signal
  • the second control line 102 outputs a low potential drive signal
  • the first control line The 101 outputs a low potential drive signal
  • the second control line 102 outputs a high potential drive signal.
  • FIG. 3 shows a gate drive in an alternative embodiment of the invention Schematic diagram of the connection between the moving circuit and the pixel unit array.
  • Figure 3 shows four shift register sets, A total of eight cascaded shift register units SR1 to SR8, the portion shown in the dashed box and FIG. 2 Part of the structure of the gate drive circuit is identical.
  • Figure 3 with the first shift register Two adjacent gates connected by the first shift register SR1 and the second shift register SR2 in the group
  • the first gate line Gate1 and the first row in the pixel unit array are odd
  • the plurality of pixel units are connected by the first pixel unit thin film transistor;
  • the second gate line Gate2 and the first row of even-numbered column pixel units pass through the second pixel unit thin film transistor phase Connected, the gate of the pixel unit thin film transistor is connected to a corresponding gate line, and the drain is connected to The pixel electrode of the corresponding pixel unit is connected to the data line.
  • every two columns A pixel unit is connected to the same data line, that is, the number of columns of the pixel unit is a data line.
  • the thin film transistor is connected to the first data line, the second odd column pixel unit and the second even column
  • the pixel unit is connected to the second data line through the pixel unit thin film transistor.
  • Other gate lines and Shift register cells in a shift register group and pixel cells in a pixel cell array Connection mode, pixel unit through the pixel unit thin film transistor and other data lines The connection methods are similar and will not be described here.
  • the first control line 101 outputs a high potential
  • the second control line 102 outputs Low potential due to the gate of the first thin film transistor T1 and the fourth thin film transistor T4 and the first The control lines 101 are connected, and the second thin film transistor T2 and the third thin film transistor T3 and the second The control lines 102 are connected, so the first thin film transistor T1 and the fourth thin film transistor T4 are struck open.
  • the cascaded shift register units are turned on and off one by one.
  • the first shift register SR1 turns on and outputs a pulse signal, and the output thereof
  • the pulse signal is output to the first gate line Gate1 through the first thin film transistor T1, so that a first pixel unit film between a gate line Gate1 and a first row of odd-numbered column pixel units
  • the transistor is turned on, and the corresponding data line charges the first row of odd-numbered column pixel units; currently
  • the second shift period of the frame the first shift register SR1 is turned off, and the second shift register SR2 turns on and outputs a pulse signal, and the output pulse signal passes through the fourth thin film transistor T4.
  • the third scan cycle the second shift register The SR2 is turned off, and the third shift register unit SR3 turns on and outputs a pulse signal, and the output is The pulse signal is output to the third gate line Gate3 such that the third gate line Gate3 and the second line
  • the pixel unit thin film transistor between the odd-numbered column pixel units is turned on, and the corresponding data line pair Two rows of odd column pixel units for charging; fourth scan period, third shift register SR3 Closed, and the fourth shift register SR4 turns on and outputs a pulse signal, and the pulse signal of the output thereof
  • the number is output to the fourth gate line Gate4 such that the fourth gate line Gate4 and the second row even column
  • the pixel unit thin film transistor between the pixel units is turned on, and the corresponding data line pair is connected to the second line
  • the series of pixel units are charged.
  • the fifth shift register unit SR5, the sixth shift register unit SR6, ... are sequentially turned on And outputting a pulse signal, and charging the corresponding pixel unit with the corresponding data line until The previous frame scan is complete.
  • the first column and the second column of pixel units are taken as an example. Ming, its scanning order is odd, even, odd, even, odd, even..., with the same "Z" shape scanning. Other adjacent columns have the same scanning order.
  • the next frame scan the driving signals output by the first control line 101 and the second control line 102
  • the potential is opposite to the previous frame
  • the first control line 101 outputs a low potential driving signal
  • the second control The line 102 outputs a high potential driving signal due to the first thin film transistor T1 and the fourth thin film
  • the gate of the transistor T4 is connected to the first control line 101
  • the three thin film transistor T3 is connected to the second control line 102, and thus the second thin film transistor T2 and The third thin film transistor T3 is turned on.
  • Start of frame scan cascaded shift register unit Turn on and off.
  • the first shift register SR1 turns on and outputs a pulse a signal whose output pulse signal is output to the second gate line through the second thin film transistor T2 Gate2, the second between the second gate line Gate2 and the first row of even-numbered column pixel units
  • the pixel unit thin film transistor is turned on, and the corresponding data line is input to the first row of even-numbered column pixel units.
  • the pulse signal is output to the fourth gate line Gate4 such that the fourth gate line Gate4 and the second The pixel unit thin film transistor between the even-numbered column pixel units is turned on, and the corresponding data line pair
  • the second row of even-numbered column pixel cells is charged; the fourth scan period, the third shift register SR3 is turned off, and the fourth shift register SR4 is turned on and outputs a pulse signal, and the pulse of its output
  • the punch signal is output to the third gate line Gate3 such that the third gate line Gate3 and the second row are odd
  • the pixel unit thin film transistor between the pixel units of the series is turned on, and the corresponding data line pair is second The odd-numbered column pixel cells are charged.
  • the fifth shift register unit SR5, the sixth shift register unit SR6, ... are sequentially turned on And outputting a pulse signal, and charging the corresponding pixel unit with the corresponding data line until The previous frame scan is complete.
  • the first column and the second column of pixel units are taken as an example. Ming, its scanning order is even, odd, even, odd, even, odd..., the same anti-"Z" shape scanning. Other adjacent columns have the same scanning order.
  • the above-mentioned gate driving circuit proposed by the present invention can be modified by the control unit.
  • the charging sequence of the adjacent two columns of pixel units is changed to achieve the purpose of uniform charging.
  • the polarity inversion of the pixel is 1 + 2 dot inversion as an example.
  • the data line outputs data signals of different polarities, and is made with a common voltage.
  • the data signal whose voltage is higher than the common voltage is a positive polarity data signal, and the voltage is low.
  • the data signal of the common voltage is a negative polarity data signal.
  • First scan period data line output Negative/positive polarity data signal, the polarity of the pixel unit receiving its data signal after charging Negative/positive, and the data signal outputted by the data line of the second scan period is reversed, receiving it
  • the polarity of the pixel unit of the data signal is reversed after charging, which is positive/negative; the third scanning week
  • the data signal outputted by the data line is unchanged, and the pixel unit receiving the data signal is charged.
  • the polarity after the change is also unchanged, which is positive/negative, and the data signal output of the data line of the fourth scan period is The polarity is reversed, and the polarity of the pixel unit receiving its data signal is also reversed. Negative/positive. And so on, except for the first scan cycle, the data line every two scan cycles The polarity of the output data signal is inverted once, and the data signal output by the data line of the second scan period The polarity is different from the first scan period.
  • two adjacent data lines are in the same scanning week. The polarity of the data signal outputted during the period is different, for example, the first data line outputs a positive polarity data signal, Then, the adjacent second data line outputs a negative polarity data signal.
  • the first row of even columns The polarity of the pixel unit is opposite to the polarity of the pixel unit of the first row of odd columns, due to the first row
  • the even-numbered column pixel unit When the even-numbered column pixel unit is charged, its polarity is transferred, and this inversion process is inevitable. Will cause some electrons to be lost, so that the first row of even-numbered columns of pixel units is not fully charged;
  • the polarity of the pixel cells of the two rows of odd columns is the same as the polarity of the pixel cells of the first row of even columns, Charging is more sufficient, and the polarity of the pixel unit of the second row even column and the pixel of the second row of odd columns
  • the polarity of the unit is reversed and its charging is less adequate. And so on, after the frame scan is completed, All odd-numbered column pixel units are fully charged, while even-numbered column pixel units are not charged. Minute.
  • the bit drive signal changes, that is, the first control line 101 outputs a low potential drive signal, and the first The second control line 102 outputs a high potential driving signal.
  • the even columns are charged first. Electric, then charge the odd column, the data line output data signal polarity and the previous frame sweep In the case where the output in the trace is the same, the first row of the first row of the even-numbered column of pixel units is performed.
  • the above is merely an exemplary illustration, and the gate driving circuit of the present invention can also be controlled.
  • the first control line and the second control line alternately output high and low potential driving signals, so that each column is odd
  • the scanning order of the even pixel units is different as long as the purpose of charging equalization can be achieved.
  • each of the first odd columns The pixel units are numbered from top to bottom, 1, 3, 5, 7, ..., each pixel unit in the first even column Numbered from top to bottom, 2, 4, 6, 8, ..., in the first scanning method described above, before The scanning order of one frame is 1, 2, 3, 4, 5, 6, 7, 8, ..., that is, a positive "Z" type scan, and then The scanning order of one frame is 2, 1, 4, 3, 6, 5, 8, 7, ..., that is, an anti-"Z" type scanning.
  • the above scanning method can also be transformed into the second scanning mode: the scanning order of the previous frame is 1,2,4,3,5,6,8,7, whil, that is, the "bow" font scan, the next frame scan order is: 2,1,3,4,6,5,7,8,..., that is, the anti-"bow” type scan.
  • the invention can also adopt other Scanning order, or a combination of different scanning methods, such as the first and second frames using the first Scanning method, and the third and fourth frames adopt the second scanning method or the like as long as the present invention is employed
  • the proposed technical solution for achieving the purpose of charging equalization of the above-mentioned gate circuit is covered by the present invention. Within the scope of protection.
  • the present invention also proposes a display device comprising the gate drive circuit as described above.
  • the display device further includes N rows ⁇ M columns of pixel units, 2N gate lines and M/2 numbers According to the line, the 2N gate lines intersect with the M/2 data lines to define the pixel list Yuan, odd gate lines are connected to odd column pixel units, even gate lines are connected to even columns of pixel units Yuan, adjacent odd pixel unit and even pixel unit are connected to the same data line, the two gates The lines are adjacent odd gate lines and even gate lines.
  • the display device proposed by the invention comprises a gate drive Circuit, pixel unit array of N ⁇ M pixel units, 2N gate lines, and M/2 Strip data lines,
  • odd gate lines (Gate1, Gate3, Gate5, Gate7) connect odd-numbered column pixel units
  • even gate lines (Gate2, Gate4, Gate6, Gate8) are connected to even-numbered column pixel units, and each data line is connected to two adjacent columns.
  • a unit such as a first data line connecting the first odd column pixel unit and the first even column pixel unit
  • the second data line is connected to the second odd column pixel unit and the second even column pixel unit.
  • the shift register unit in each shift register group in the gate driving circuit is controlled
  • the unit is connected to adjacent odd gate lines and even gate lines, such as a first shift register unit SR1 and second shift register unit SR2 are connected to the first gate line through the control unit Gate1 and second gate line Gate2.
  • the invention also provides a driving method of the above display device, which comprises:
  • Control control unit controls open shift register unit to odd among said two gate lines a number of gate lines or even gate lines provide driving signals;
  • Control control unit controls said open shift register unit to be in said two gate lines
  • the even gate line or the odd gate line provides a drive signal.
  • the current frame scan includes:
  • the first shift register unit turned on by the meta control controls the two gate lines connected thereto
  • the odd gate line in the middle provides a drive signal to the odd-numbered column of pixel units through the data line to the nth row Charging
  • the second shift register unit turned on by the element controls an even gate of the two gate lines
  • the polar line provides a driving signal for charging the n-th row of even-numbered column pixel units through the data line;
  • the next frame scan includes:
  • the first shift register unit turned on by the meta control controls the two gate lines connected thereto
  • the even gate line in the middle provides the driving signal, and the pixel unit is in the nth row even column through the data line Charging
  • the second shift register unit turned on by the element controls an odd gate of the two gate lines
  • the polar line provides a driving signal for charging the n-th row of odd-numbered column pixel units through the data line;
  • the adjacent two rows of pixel units have opposite charging polarities and are connected to the same data line.
  • Two adjacent columns of pixel units have opposite charging polarities and are connected to adjacent two columns of pixels of different data lines.
  • the unit charging polarity is the same, and n is a natural number less than or equal to N.
  • the above-described gate driving circuit, display device and drive disclosed by the present invention are utilized.
  • the charging rate of the odd-numbered column pixel unit is smaller than that of the even-numbered column pixel in the previous frame scanning
  • the unit is sufficient, and in the next frame scan, the even column pixel unit is more than the odd column pixel unit charge Fully charged, considering the visual effect, the two can make up to a certain extent, so that they can be changed Good V-line and other phenomena that produce light and dark stripes.

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Abstract

公开了一种栅极驱动电路、显示装置及驱动方法。该栅极驱动电路包括级联的多个移位寄存器单元（SR1，SR2）和控制单元（10），两个相邻的移位寄存器单元（SR1，SR2）为一移位寄存器组，通过控制单元（10）连接至两条栅极线（Gate1，Gate2）；控制单元（10）控制移位寄存器组中的移位寄存器单元（SR1，SR2）分别向两条栅极线（Gate1，Gate2）提供驱动信号。该栅极驱动电路在原有移位寄存器的基础上对电路结构进行了改进，实现了不同帧之间的充电率补偿，有效改善了现有产品的V-line等明显的亮暗条纹现象。

Description

一种栅极驱动电路、显示装置及驱动方法 技术领域
本发明涉及显示技术领域，尤其涉及一种栅极驱动电路、显示装 置及驱动方法。
背景技术
目前，薄膜晶体管液晶显示器(TFT-LCD)已成为主流显示器。阵列 基板上栅极驱动技术(Gate-driver On Array，GOA)在液晶显示器的 应用让液晶显示器有了一个质的飞跃。GOA技术直接将栅极驱动电路 (Gate driver ICs)制作在液晶显示面板中的阵列基板(Array)上，来代 替由外接芯片制作的驱动芯片，可以减少制作工序，降低成本。但是 现有的应用GOA技术的液晶显示面板的双栅(dual gate)设计中，栅极 驱动只能实现正“Z”型的扫描，这样会导致液晶显示面板中某一列 像素单元充电较为充分，而另一列像素单元充电不充分，容易出现竖 向条纹不良(V-line)等现象。在此以双栅结构的液晶显示面板采用 1+2点像素极性反转方式为例进行说明，详见图1。
图1所示为现有技术中液晶显示面板阵列基板的电路图。如图1 所示，阵列基板包括多条数据线1、多条栅极线2，Gate1～Gate8，及 其由多条数据线和多条栅极线限定出的多个像素单元，所述多个像素 单元形成像素单元阵列；每个像素单元通过一个薄膜晶体管(Thin  Film Transistor，TFT)与一条栅极线和一条数据线连接，栅极线连接 至薄膜晶体管的栅极，数据线连接至薄膜晶体管的源极，其中每一行 像素单元中奇数列连接至同一条栅极线，偶数列连接至另一条栅极线， 而相邻两列像素单元连接至同一条数据线。多条数据线1由数据驱动 电路驱动，接收数据驱动电路输出的数据信号；多条栅极线2连接至 栅极驱动电路，栅极驱动电路包括多个移位寄存器单元SR1～SR8，其 在一帧扫描期间顺序地开启和关闭，其开启后所产生的脉冲信号分别 输出至所述多条栅极线2。帧扫描开始后，第一扫描周期，第一移位 寄存器单元SR1开启并输出脉冲信号至第一栅极线Gate1，使第一行 奇数列的像素单元的薄膜晶体管开启，对应的数据线接收数据信号对 第一行奇数列的像素单元充电，并存储相应数据；在第二扫描周期， 第一移位寄存器单元SR1关闭，第二移位寄存器单元SR2开启并输出 脉冲信号至第二栅极线Gate2，此时，第一行偶数列像素单元的薄膜 晶体管开启，对应的数据线对第一行偶数列像素单元充电。然后第三 移位寄存器单元、第四移位寄存器单元等依次开启输出脉冲信号，配 合对应的数据线为对应的像素单元充电。由于每一扫描周期输出至数 据线上的数据极性相反，且每个扫描周期内相邻两条数据线上的数据 极性也相反。因此，在第一扫描周期，如果第一行奇数列像素单元接 收到的数据信号极性为正，而在第二扫描周期第一行偶数列像素单元 接收到的数据信号就会由正性变为负性，考虑数据线负载，第一行偶 数列像素单元的充电时间和充电率将会受到影响。相对第一行奇数列 像素单元来说，第一行偶数列像素单元充电不足。在第三扫描周期， 第三移位寄存器SR3输出脉冲信号至第三栅极线Gate3，第二行奇数 列像素单元开始充电，此时由于数据线上数据信号一直为负极性，所 以第二行奇数列像素单元充电时间和充电率较为充足。但第二行偶数 列像素单元也会出现充电不足。综合以上，在1+2点反转时，基于以 上结构和反转方式的液晶显示面板会出现奇数列像素单元充电总是 较偶数列像素单元充电充分的情况，当二者充电率差异较大时，就会 影响显示效果，即产生竖向条纹(V-line)不良现象。
因此，在产品设计时，有必要对阵列基板结构和驱动方式进行变 更，避免奇数列像素单元和偶数列像素单元的充电率差异，改善V-line 不良现象。
发明内容
为解决上述现有技术中存在的一个或多个问题，本发明在原有移 位寄存器的基础上对栅极驱动电路结构进行了改进，实现了不同帧之 间的充电率补偿，改善现有产品的竖向条纹(V-line)等相关不良现 象。
根据本发明一方面，其提供了一种栅极驱动电路，包括级联的多 个移位寄存器单元和控制单元，两个相邻的移位寄存器单元为一移位 寄存器组，通过所述控制单元连接至两条栅极线；所述控制单元控制 所述移位寄存器组中的移位寄存器单元分别向所述两条栅极线提供 驱动信号。
可选地，所述控制单元包括第一控制线、第二控制线以及与所述 移位寄存器单元相连的薄膜晶体管。
可选地，所述移位寄存器组中的每个移位寄存器单元通过两个薄 膜晶体管分别与所述第一控制线和第二控制线连接，所述两个薄膜晶 体管的栅极分别连接至所述第一控制线和第二控制线，漏极分别连接 至所述两条栅极线，源极分别连接所述移位寄存器单元的输出端。
可选地，控制单元控制移位寄存器组中的移位寄存器单元向所述 两条栅极线中的不同栅极线提供驱动信号。
可选地，所述第一控制线和第二控制线交替输出高电位驱动信号。
可选地，所述两条栅极线分别与像素单元阵列中的奇数列和偶数 列像素单元相连。
可选地，所述栅极线与像素单元之间通过像素单元薄膜晶体管相 连；所述像素单元薄膜晶体管的栅极连接至所述栅极线，漏极连接至 像素单元的像素电极，源极连接至数据线。
根据本发明另一方面，其提供了一种显示装置，包括如上所述的 栅极驱动电路。
可选地，所述显示装置包括N行×M列像素单元，2N条栅极线 和M/2条数据线，所述2N条栅极线与所述M/2条数据线交叉限定出 所述像素单元，奇数栅极线连接奇数列像素单元，偶数栅极线连接偶 数列像素单元，相邻奇数像素单元与偶数像素单元连接同一数据线， 所述两条栅极线为相邻的奇数栅极线和偶数栅极线。
根据本发明了另一方面，其提供了一种如上所述的显示装置的驱 动方法，其包括：
当前帧扫描，依次开启和关断级联的移位寄存器单元，通过所述 控制单元控制开启的移位寄存器单元向所述两条栅极线中的奇数栅 极线或偶数栅极线提供驱动信号；
下一帧扫描，依次开启和关断级联的移位寄存器单元，通过所述 控制控制单元控制所述开启的移位寄存器单元向所述两条栅极线中 偶数栅极线或奇数栅极线提供驱动信号。
可选地，所述当前帧扫描包括：
开启第n个移位寄存器组中的第一移位寄存器单元，通过控制单 元控制所开启的第一移位寄存器单元向与其相连的所述两条栅极线 中的奇数栅极线提供驱动信号，通过数据线向第n行奇数列像素单元 充电；
开启第n个移位寄存器组中的第二移位寄存器单元，通过控制单 元控制所开启的第二移位寄存器单元向所述两条栅极线中的偶数栅 极线提供驱动信号，通过数据线向第n行偶数列像素单元充电；
所述下一帧扫描包括：
开启第n个移位寄存器组中的第一移位寄存器单元，通过控制单 元控制所开启的第一移位寄存器单元向与其相连的所述两条栅极线 中的偶数栅极线提供驱动信号，通过数据线向第n行偶数列像素单元 充电；
开启第n个移位寄存器组中的第二移位寄存器单元，通过控制单 元控制所开启的第二移位寄存器单元向所述两条栅极线中的奇数栅 极线提供驱动信号，通过数据线向第n行奇数列像素单元充电；
其中，相邻两行像素单元的充电极性相反，连接至同一数据线的 相邻两列像素单元充电极性相反，连接至不同数据线的相邻两列像素 单元充电极性相同，n为小于等于N的自然数。
本发明通过在栅极驱动电路中设置控制单元，改进栅极驱动电路 的结构，使得控制单元控制相邻两个移位寄存器单元分别向相邻两条 栅极线提供驱动信号，相邻两帧扫描中所述两个移位寄存器单元提供 驱动信号的栅极线不同。本发明提出的上述方案在显示装置采用点反 转驱动方式时，使得相邻两帧扫描中奇偶数列像素单元的充电顺序不 同，使得奇数列或偶数列像素单元在当前帧充电充分，而下一帧充电 不充分，进而改善了竖向条纹不良(V-line)等现象。
附图说明
图1为现有技术中液晶显示面板阵列基板的电路图；
图2是本发明可选实施例中栅极驱动电路的局部结构示意图；
图3是本发明可选实施例中栅极驱动电路与像素单元阵列的连 接示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具 体实施例，并参照附图，对本发明作进一步的详细说明。
本发明提出了一种栅极驱动电路，包括级联的多个移位寄存器单 元和控制单元，两个相邻的移位寄存器单元为一移位寄存器组，通过 所述控制单元连接至两条栅极线；所述控制单元控制所述移位寄存器 组中的移位寄存器单元分别向所述两条栅极线提供驱动信号。
图2示出了本发明提出的栅极驱动电路的局部结构示意图。如图 2所示，该栅极驱动电路包括控制单元10和多个级联的移位寄存器 单元11，其中两个相邻的移位寄存器单元为一移位寄存器组，本实 施例中示意性的示出了2个移位寄存器单元SR1～SR2构成的第一移位 寄存器组，本领域技术人员应当知道，其数量根据显示装置的像素阵 列大小决定。每一移位寄存器组对应两条相邻栅极线Gate1～Gate2， 所述控制单元10控制所述移位寄存器组中的两个移位寄存器单元 SR1～SR2分别向所述两条相邻栅极线Gate1～Gate2提供驱动信号。
其中，控制单元10包括第一控制线101、第二控制线102和多 个与所述移位寄存器单元相连的薄膜晶体管103。每两个相邻移位寄 存器单元11为一移位寄存器组，且每个移位寄存器组中的每个移位 寄存器单元通过两个薄膜晶体管分别与第一控制线101和第二控制 线102连接。其中，所述一移位寄存器组中的第一移位寄存器单元 SR1通过相邻的第一薄膜晶体管T1和第二薄膜晶体管T2分别与所述 第一控制线101和第二控制线102连接，所述第一薄膜晶体管T1的 栅极与第一控制线101连接，而第二薄膜晶体管T2的栅极与第二控 制线102连接，所述第一薄膜晶体管T1和第二薄膜晶体管T2的漏极 分别连接至相邻的两条栅极线Gate1～Gate2，所述第一薄膜晶体管T1 和第二薄膜晶体管T2的源极连接至所述第一移位寄存器SR1的输出 端；同样地，所述第一移位寄存器组中的第二移位寄存器单元SR2通 过相邻的第三薄膜晶体管T3和第四薄膜晶体管T4分别与所述第一控 制线101和第二控制102连接，所述第三薄膜晶体管T3的栅极连接 至第二控制线102，第四薄膜晶体管T4的栅极连接至第一控制线101， 所述第三薄膜晶体管T3和第四薄膜晶体管T4的漏极分别连接至两条 相邻的栅极线Gate1～Gate2，所述第三薄膜晶体管T3和第四薄膜晶体 管T4的源极连接至所述第二移位寄存器单元SR2的输出端。依次类 推，每相邻两个移位寄存器单元为一移位寄存器组，每个移位寄存器 组对应四个薄膜晶体管，且每个移位寄存器组中的每个移位寄存器单 元分别通过两个薄膜晶体管连接至第一控制线101和第二控制线102。
所述控制单元10控制移位寄存器组中的移位寄存器单元向所述 两条相邻栅极线中的不同栅极线提供驱动信号。根据本发明的上述实 施例，第一控制线101和第二控制线102交替输出高电位驱动信号。 可选地，在当前帧扫描中，第一控制线101输出高电位驱动信号，第 二控制线102输出低电位驱动信号，而在下一帧扫描中，第一控制线 101输出低电位驱动信号，第二控制线102输出高电位驱动信号。
所述两条相邻的栅极线Gate1～Gate2分别与像素单元阵列中的奇 数列和偶数列像素单元连接。图3示出了本发明可选实施例中栅极驱 动电路与像素单元阵列的连接示意图。图3示出了四个移位寄存器组， 共8个级联的移位寄存器单元SR1～SR8，虚框内示出的部分与图2示 出的栅极驱动电路的部分结构一致。如图3所示，与第一移位寄存器 组中的第一移位寄存器SR1和第二移位寄存器SR2连接的相邻两条栅 极线Gate1～Gate2分别与像素单元阵列中的奇数列像素单元和偶数列 像素单元连接。其中，第一栅极线Gate1与像素单元阵列中第一行奇 数列像素单元之间通过第一像素单元薄膜晶体管相连；第二栅极线 Gate2与第一行偶数列像素单元之间通过第二像素单元薄膜晶体管相 连，所述像素单元薄膜晶体管的栅极连接至相应栅极线，漏极连接至 相应像素单元的像素电极，源极连接至数据线。本实施例中，每两列 像素单元为一组连接至同一条数据线，即像素单元的列数是数据线的 两倍；其中，第一奇数列像素单元和第一偶数列像素单元通过像素单 元薄膜晶体管连接至第一数据线，第二奇数列像素单元和第二偶数列 像素单元通过像素单元薄膜晶体管连接至第二数据线。其它栅极线与 移位寄存器组中的移位寄存器单元和像素单元阵列中的像素单元的 连接方式、像素单元通过所述像素单元薄膜晶体管与其它数据线的连 接方式类同，在此就不再赘述。
下面结合图2和图3说明本发明提出的栅极驱动电路的工作原理：
当前帧扫描，第一控制线101输出高电位，第二控制线102输出 低电位，由于第一薄膜晶体管T1和第四薄膜晶体管T4的栅极与第一 控制线101相连，而第二薄膜晶体管T2和第三薄膜晶体管T3与第二 控制线102相连，因此第一薄膜晶体管T1和第四薄膜晶体管T4被打 开。帧扫描开始，级联的移位寄存器单元逐个开启和关闭。当前帧的 第一扫描周期，第一移位寄存器SR1开启并输出脉冲信号，其输出的 脉冲信号经过第一薄膜晶体管T1输出至第一栅极线Gate1，使得第 一栅极线Gate1与第一行奇数列像素单元之间的第一像素单元薄膜 晶体管开启，对应的数据线对第一行奇数列像素单元进行充电；当前 帧的第二扫描周期，第一移位寄存器SR1关闭，而第二移位寄存器 SR2开启并输出脉冲信号，其输出的脉冲信号经过第四薄膜晶体管T4 输出至第二栅极线Gate2，使得第二栅极线Gate2与第一行偶数列像 素单元之间的第二像素单元薄膜晶体管开启，对应的数据线对第一行 偶数列像素单元进行充电。依次类推，第三扫描周期，第二移位寄存 器SR2关闭，第三移位寄存器单元SR3开启并输出脉冲信号，输出的 脉冲信号输出至第三栅极线Gate3，使得第三栅极线Gate3与第二行 奇数列像素单元之间的像素单元薄膜晶体管开启，对应的数据线对第 二行奇数列像素单元进行充电；第四扫描周期，第三移位寄存器SR3 关闭，而第四移位寄存器SR4开启并输出脉冲信号，其输出的脉冲信 号输出至第四栅极线Gate4，使得第四栅极线Gate4与第二行偶数列 像素单元之间的像素单元薄膜晶体管开启，对应的数据线对第二行偶 数列像素单元进行充电。之后，第五扫描周期，第六扫描周期……， 第五移位寄存器单元SR5、第六移位寄存器单元SR6……，依次开启 并输出脉冲信号，配合对应的数据线为对应的像素单元充电，直至当 前帧扫描完成。该帧扫描过程中，以第一列和第二列像素单元为例说 明，其扫描顺序为奇，偶，奇，偶，奇，偶……，形同正“Z”字型 扫描。其它相邻列具有同样的扫描顺序。
下一帧扫描，第一控制线101和第二控制线102输出的驱动信号 电位与前一帧的相反，第一控制线101输出低电位驱动信号，第二控 制线102输出高电位驱动信号，由于第一薄膜晶体管T1和第四薄膜 晶体管T4的栅极与第一控制线101相连，而第二薄膜晶体管T2和第 三薄膜晶体管T3与第二控制线102相连，因此第二薄膜晶体管T2和 第三薄膜晶体管T3被打开。帧扫描开始，级联的移位寄存器单元逐 个开启和关闭。第一扫描周期，第一移位寄存器SR1开启并输出脉冲 信号，其输出的脉冲信号经过第二薄膜晶体管T2输出至第二栅极线 Gate2，使得第二栅极线Gate2与第一行偶数列像素单元之间的第二 像素单元薄膜晶体管开启，对应的数据线对第一行偶数列像素单元进 行充电；第二扫描周期，第一移位寄存器SR1关闭，而第二移位寄存 器SR2开启并输出脉冲信号，其输出的脉冲信号经过第三薄膜晶体管 T3输出至第一栅极线Gate1，使得第一栅极线Gate1与第一行奇数列 像素单元之间的第一像素单元薄膜晶体管开启，对应的数据线对第一 行奇数列像素单元进行充电。依次类推，第三扫描周期，第二移位寄 存器SR2关闭，第三移位寄存器单元SR3开启并输出脉冲信号，输出 的脉冲信号输出至第四栅极线Gate4，使得第四栅极线Gate4与第二 行偶数列像素单元之间的像素单元薄膜晶体管开启，对应的数据线对 第二行偶数列像素单元进行充电；第四扫描周期，第三移位寄存器 SR3关闭，而第四移位寄存器SR4开启并输出脉冲信号，其输出的脉 冲信号输出至第三栅极线Gate3，使得第三栅极线Gate3与第二行奇 数列像素单元之间的像素单元薄膜晶体管开启，对应的数据线对第二 行奇数列像素单元进行充电。之后，第五扫描周期，第六扫描周期……， 第五移位寄存器单元SR5、第六移位寄存器单元SR6……，依次开启 并输出脉冲信号，配合对应的数据线为对应的像素单元充电，直至当 前帧扫描完成。该帧扫描过程中，以第一列和第二列像素单元为例说 明，其扫描顺序为偶，奇，偶，奇，偶，奇……，形同反“Z”字型 扫描。其它相邻列具有同样的扫描顺序。
可见，本发明提出的上述栅极驱动电路，其通过控制单元可以改 变相邻两列像素单元的充电顺序，以此达到均匀充电的目的。下面依 然结合图2和图3说明利用本发明提出的栅极驱动电路如何达到均匀 充电的目的。像素的极性反转方式为1+2点反转为例加以说明。
1+2点反转中，数据线输出不同极性的数据信号，以公共电压作 为参考，电压高于公共电压的数据信号为正极性数据信号，而电压低 于公共电压的数据信号为负极性数据信号。第一扫描周期数据线输出 负极性/正极性数据信号，接收其数据信号的像素单元充电后的极性 为负/正，而第二扫描周期数据线输出的数据信号极性反转，接收其 数据信号的像素单元充电后的极性发生反转，为正/负；第三扫描周 期数据线输出的数据信号极性不变，接收其数据信号的像素单元充电 后的极性也不变，为正/负，第四扫描周期数据线输出的数据信号极 性发生反转，接收其数据信号的像素单元充电后的极性也发生反转， 为负/正。依次类推，除了第一扫描周期外，数据线每两个扫描周期 输出的数据信号极性反转一次，第二扫描周期数据线输出的数据信号 的极性与第一扫描周期的不同。另外，相邻两条数据线在同一扫描周 期输出的数据信号的极性不同，例如第一数据线输出正极性数据信号， 则相邻的第二数据线输出负极性数据信号。
将本发明提出的上述栅极驱动电路应用在1+2点反转驱动方式 中，且第一控制线101输出高电位驱动信号，第二控制线102输出低 电位驱动信号的情况下，一帧扫描完成后，像素单元阵列中像素单元 的极性如图3所示。其中，“+”号表示该像素单元的像素电极极性为 正，“一”表示该像素单元的像素电极极性为负。以第一奇数列像素单 元和第一偶数列像素单元为例，这种情况下可以看出，第一行偶数列 像素单元的极性与第一行奇数列像素单元的极性相反，由于对第一行 偶数列像素单元充电时，其极性发生了发转，而这种反转过程中必然 会造成部分电子的丢失，使得第一行偶数列像素单元充电不充分；第 二行奇数列像素单元的极性和第一行偶数列像素单元的极性相同，其 充电较为充分，而第二行偶数列像素单元的极性与第二行奇数列像素 单元的极性相反，其充电较为不充分。依次类推，本帧扫描完成后， 所有奇数列像素单元的充电较为充分，而偶数列像素单元的充电不充 分。
而在下一帧扫描中，由于第一控制线101和第二控制线102的电 位驱动信号发生变化，即第一控制线101输出低电位驱动信号，而第 二控制线102输出高电位驱动信号，这种情况下，先对偶数列进行充 电，之后再对奇数列进行充电，数据线输出数据信号极性与前一帧扫 描中的输出相同的情况下，第一扫描周期第一行偶数列像素单元进行 充电，且其极性为正，而第二扫描周期第一行奇数列像素单元进行充 电，其极性为负，第三扫描周期第二行偶数列像素单元进行充电，极 性为负，第四扫描周期第二行奇数列像素单元进行充电，极性为 正，……。显然，本帧扫描中所有奇数列像素单元充电不充分，而偶 数列像素单元的充电较为充分。可见，在相邻两帧扫描后，可以均衡 像素单元的充电程度，进而克服V-line等显示不良现象。
上面仅仅是示例性说明，本发明的栅极驱动电路还可以通过控制 第一控制线和第二控制线交替输出高低电位驱动信号，使得每列中奇 偶像素单元的扫描顺序不同，只要能够达到充电均衡的目的即可。例 如，以第一奇数列和第一偶数列像素单元为例，第一奇数列中的每个 像素单元从上到下编号为1，3，5，7，……，第一偶数列中每个像素单元 从上到下编号为2，4，6,8，……，则上述介绍的第一种扫描方式中，前 一帧的扫描顺序为1，2，3，4，5，6，7,8，……，即正“Z”字型扫描，而后 一帧的扫描顺序为2，1，4，3，6，5，8，7，……，即反“Z”字型扫描。但是 上述扫描方式也可以变形为第二种扫描方式：前一帧扫描顺序为 1，2，4，3，5，6，8，7，……，即正“弓”字型扫描，后一帧扫描顺序为： 2，1，3，4，6,5,7,8，……，即反“弓”字型扫描。本发明还可以采用其他 的扫描顺序，或者是不同扫描方式的组合，如第一、二帧采用第一种 扫描方式，而第三、四帧采用第二种扫描方式等，只要是采用本发明 提出的上述栅极电路实现充电均衡目的的技术方案都涵盖在本发明 的保护范围之内。
本发明还提出了一种显示装置，其包括如上所述的栅极驱动电路。 所述显示装置还包括N行×M列像素单元，2N条栅极线和M/2条数 据线，所述2N条栅极线与所述M/2条数据线交叉限定出所述像素单 元，奇数栅极线连接奇数列像素单元，偶数栅极线连接偶数列像素单 元，相邻奇数像素单元与偶数像素单元连接同一数据线所述两条栅极 线为相邻的奇数栅极线和偶数栅极线。
依然以图3为例进行说明。本发明提出的显示装置包括栅极驱动 电路、N×M个像素单元构成的像素单元阵列、2N条栅极线和M/2 条数据线，图3示意性地示出了4×8(N＝4，M＝8)个像素单元，4条 数据线，8条栅极线Gate1～Gate8。其中，奇数栅极线(Gate1、Gate3、 Gate5、Gate7)连接奇数列像素单元，偶数栅极线(Gate2、Gate4、 Gate6、Gate8)连接至偶数列像素单元，每条数据线连接相邻两列像 素单元，如第一数据线连接第一奇数列像素单元和第一偶数列像素单 元，第二数据线连接第二奇数列像素单元和第二偶数列像素单元等。 所述栅极驱动电路中每个移位寄存器组中的移位寄存器单元通过控 制单元连接相邻的奇数栅极线和偶数栅极线，如第一移位寄存器单元 SR1和第二移位寄存器单元SR2通过控制单元连接至第一栅极线 Gate1和第二栅极线Gate2。
由于该显示装置在栅极驱动电路下的工作原理在上面已经介绍， 此处不再赘述。
本发明还提出了一种上述显示装置的驱动方法，其包括：
当前帧扫描，依次开启和关断级联的移位寄存器单元，通过所述 控制控制单元控制开启的移位寄存器单元向所述两条栅极线中的奇 数栅极线或偶数栅极线提供驱动信号；
下一帧扫描，依次开启和关断级联的移位寄存器单元，通过所述 控制控制单元控制所述开启的移位寄存器单元向所述两条栅极线中 偶数栅极线或奇数栅极线提供驱动信号。
其中，所述当前帧扫描包括：
开启第n个移位寄存器组中的第一移位寄存器单元，通过控制单 元控制所开启的第一移位寄存器单元向与其相连的所述两条栅极线 中的奇数栅极线提供驱动信号，通过数据线向第n行奇数列像素单元 充电；
开启第n个移位寄存器组中的第二移位寄存器单元，通过控制单 元控制所开启的第二移位寄存器单元向所述两条栅极线中的偶数栅 极线提供驱动信号，通过数据线向第n行偶数列像素单元充电；
所述下一帧扫描包括：
开启第n个移位寄存器组中的第一移位寄存器单元，通过控制单 元控制所开启的第一移位寄存器单元向与其相连的所述两条栅极线 中的偶数栅极线提供驱动信号，通过数据线向第n行偶数列像素单元 充电；
开启第n个移位寄存器组中的第二移位寄存器单元，通过控制单 元控制所开启的第二移位寄存器单元向所述两条栅极线中的奇数栅 极线提供驱动信号，通过数据线向第n行奇数列像素单元充电；
其中，相邻两行像素单元的充电极性相反，连接至同一数据线的 相邻两列像素单元充电极性相反，连接至不同数据线的相邻两列像素 单元充电极性相同，n为小于等于N的自然数。
由于前面介绍栅极驱动电路时详细介绍了利用栅极驱动电路驱 动显示装置的工作原理，具体细节请参阅上文，此处不再详细展开说 明。
综合所述，利用本发明公开的上述栅极驱动电路、显示装置和驱 动方法中，在前一帧扫描时，奇数列像素单元的充电率较偶数列像素 单元充分，而在下一帧扫描时，偶数列像素单元较奇数列像素单元充 电充分，考虑视觉效果，二者可在一定程度上进行弥补，从而能够改 善V-line等产生明暗条纹的不良现象。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果 进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实 施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所 做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之 内。

Claims (11)

  1. 一种栅极驱动电路，包括级联的多个移位寄存器单元和控制 单元，两个相邻的移位寄存器单元为一移位寄存器组，通过所述控制 单元连接至两条栅极线；所述控制单元控制所述移位寄存器组中的移 位寄存器单元分别向所述两条栅极线提供驱动信号。
  2. 如权利要求1所述的栅极驱动电路，其中，所述控制单元包 括第一控制线、第二控制线以及与所述移位寄存器单元相连的薄膜晶 体管。
  3. 如权利要求2所述的栅极驱动电路，其中，所述移位寄存器 组中的每个移位寄存器单元通过两个薄膜晶体管分别与所述第一控 制线和第二控制线连接，所述两个薄膜晶体管的栅极分别连接至所述 第一控制线和第二控制线，漏极分别连接至所述两条栅极线，源极分 别连接所述移位寄存器单元的输出端。
  4. 如权利要求1-3任一项所述的栅极驱动电路，其中，控制单 元控制移位寄存器组中的移位寄存器单元向所述两条栅极线中的不 同栅极线提供驱动信号。
  5. 如权利要求3所述的栅极驱动电路，其中，所述第一控制线 和第二控制线交替输出高电位驱动信号。
  6. 如权利要求1-3任一项所述的栅极驱动电路，其中，所述两 条栅极线分别与像素单元阵列中的奇数列和偶数列像素单元相连。
  7. 如权利要求6所述的栅极驱动电路，其中，所述栅极线与像 素单元之间通过像素单元薄膜晶体管相连；所述像素单元薄膜晶体管 的栅极连接至所述栅极线，漏极连接至像素单元的像素电极，源极连 接至数据线。
  8. 一种显示装置，其中，包括如权利要求1-7任一项所述的栅 极驱动电路。
  9. 如权利要求8所述的显示装置，其中，所述显示装置包括N 行×M列像素单元，2N条栅极线和M/2条数据线，所述2N条栅极 线与所述M/2条数据线交叉限定出所述像素单元，奇数栅极线连接 奇数列像素单元，偶数栅极线连接偶数列像素单元，相邻奇数像素单 元与偶数像素单元连接同一数据线，所述两条栅极线为相邻的奇数栅 极线和偶数栅极线。
  10. 一种如权利要求9所述的显示装置的驱动方法，其中，
    当前帧扫描，依次开启和关断级联的移位寄存器单元，通过所述 控制单元控制开启的移位寄存器单元向所述两条栅极线中的奇数栅 极线或偶数栅极线提供驱动信号；
    下一帧扫描，依次开启和关断级联的移位寄存器单元，通过所述 控制控制单元控制所述开启的移位寄存器单元向所述两条栅极线中 偶数栅极线或奇数栅极线提供驱动信号。
  11. 如权利要求10所述的驱动方法，其中，
    所述当前帧扫描包括：
    开启第n个移位寄存器组中的第一移位寄存器单元，通过控制单 元控制所开启的第一移位寄存器单元向与其相连的所述两条栅极线 中的奇数栅极线提供驱动信号，通过数据线向第n行奇数列像素单元 充电；
    开启第n个移位寄存器组中的第二移位寄存器单元，通过控制单 元控制所开启的第二移位寄存器单元向所述两条栅极线中的偶数栅 极线提供驱动信号，通过数据线向第n行偶数列像素单元充电；
    所述下一帧扫描包括：
    开启第n个移位寄存器组中的第一移位寄存器单元，通过控制单 元控制所开启的第一移位寄存器单元向与其相连的所述两条栅极线 中的偶数栅极线提供驱动信号，通过数据线向第n行偶数列像素单元 充电；
    开启第n个移位寄存器组中的第二移位寄存器单元，通过控制单 元控制所开启的第二移位寄存器单元向所述两条栅极线中的奇数栅 极线提供驱动信号，通过数据线向第n行奇数列像素单元充电；
    其中，相邻两行像素单元的充电极性相反，连接至同一数据线的 相邻两列像素单元充电极性相反，连接至不同数据线的相邻两列像素 单元充电极性相同，n为小于等于N的自然数。
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