WO2015103816A1 - 一种时钟恢复方法、装置、系统及计算机存储介质 - Google Patents
一种时钟恢复方法、装置、系统及计算机存储介质 Download PDFInfo
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- WO2015103816A1 WO2015103816A1 PCT/CN2014/074566 CN2014074566W WO2015103816A1 WO 2015103816 A1 WO2015103816 A1 WO 2015103816A1 CN 2014074566 W CN2014074566 W CN 2014074566W WO 2015103816 A1 WO2015103816 A1 WO 2015103816A1
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6162—Compensation of polarization related effects, e.g., PMD, PDL
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/06—Control of transmission; Equalising by the transmitted signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6165—Estimation of the phase of the received optical signal, phase error estimation or phase error correction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0058—Detection of the synchronisation error by features other than the received signal transition detection of error based on equalizer tap values
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0075—Arrangements for synchronising receiver with transmitter with photonic or optical means
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
Definitions
- the chromatic dispersion and polarization mode dispersion are generally divided into two parts: First, the static dispersion is compensated, usually using Fast Fourier Transformation (FFT) technique for fast frequency convolution in the frequency domain. Compensate for static dispersion; then compensate for residual chromatic dispersion and polarization mode dispersion, usually with finite impulse response
- FFT Fast Fourier Transformation
- the Finite Impulse Response (FI) butterfly equalizer implements the FIR butterfly filter to update the coefficients with an adaptive algorithm to track and compensate for the polarization mode dispersion that changes dynamically with time.
- the FIR butterfly adaptive equalizer has the functions of equalization, matched filtering and phase adjustment.
- a clock phase recovery device is placed to estimate the phase error of the input/time domain signal and phase adjustment of the input/frequency domain signal to ensure a stable and suitable phase for the adaptive equalizer.
- the clock balancing pre-filtering is performed on the input frequency domain signal according to the currently input adaptive equalization coefficient, and the specific manner is as follows:
- phase error of the input frequency domain signal is obtained according to the equalization pre-filtering signal, and the specific manner is as follows:
- the phase adjustment of the input frequency domain signal according to the phase error includes:
- JT(t) is the first polarization sub-signal in the frequency domain, and is the second polarization sub-signal in the frequency domain
- X cr (k) is the frequency domain signal obtained after phase adjustment.
- the phase adjustment of the input time domain signal according to the phase error includes:
- phase adjustment of the input time domain signal is performed by using a three-time Lagrangian interpolation algorithm, which is specifically used as follows:
- the timing error extracting unit is configured to obtain a phase error of the input time/frequency domain signal according to the equalized pre-filtering signal, and the obtained phase error is input to the phase adjusting unit;
- the time/frequency domain signal includes a time/frequency domain first sub-signal according to a first optical polarization and a time/frequency domain second sub-signal according to a second optical polarization, and the time domain signal passes the time-frequency.
- the conversion becomes the frequency domain signal.
- the device further includes:
- a timing error filtering unit is connected between the timing error extracting unit and the phase adjusting unit, configured to filter the phase error, and the filtered phase error is input to the phase adjusting unit;
- the timing error filtering unit is implemented by a loop filter, a digital oscillator, and a subtractor.
- the equalization filter pre-wave unit is implemented by a finite-length unit impulse response FIR filter of a single polarization system or a FIR filter of a polarization multiplexing system.
- An embodiment of the present invention provides a clock recovery system, where the system includes: a clock recovery device and an adaptive equalization device as described above;
- the adaptive equalization device outputs a new adaptive equalization coefficient based on the phase adjusted time/frequency domain signal and feeds back to the input of the clock recovery device.
- Figure 1 is a block diagram of a conventional digital coherent receiver
- FIG. 2 is a schematic structural diagram of a clock recovery system 1 according to an embodiment of the present invention.
- FIG. 5 is a schematic flowchart of an implementation process of a clock recovery method 2 according to an embodiment of the present invention
- 6 is a schematic structural diagram of realizing filtering of a phase error by a timing error filtering unit according to an embodiment of the present invention
- FIG. 8 is a schematic structural diagram of a clock recovery system according to Embodiment 2 of the present invention.
- FIG. 9 is a schematic structural diagram of a clock recovery apparatus according to an embodiment of the present invention. detailed description
- the currently input adaptive equalization coefficient is adaptively equalized by the adaptive equalization device to perform adaptive equalization processing on the input phase-adjusted time/frequency domain signal, and is output and fed back.
- the initial input adaptive equalization coefficient is determined by the system.
- the time/frequency domain signal includes a time/frequency domain first sub-signal according to a first optical polarization and a time/frequency domain second sub-signal according to a second optical polarization; the time domain signal passes a time-frequency The conversion becomes the frequency domain signal.
- FIG. 2 is a schematic structural diagram of a clock recovery system according to an embodiment of the present invention. As shown in FIG. 2, the system includes: a clock recovery device 20 and an adaptive equalization device 21; wherein the clock recovery device 20 includes an equalization pre-connected sequence.
- the filtering unit 200, the timing error extracting unit 201, and the phase adjusting unit 202 may be a software function module or a hardware device.
- the clock recovery device 20 inputs the phase adjusted time/frequency domain signal to the adaptive
- the equalization device 21 outputs the new adaptive equalization coefficient according to the phase-adjusted time/frequency domain signal and feeds back to the input end of the clock recovery device 20.
- the equalization pre-filtering unit 200 is configured to perform clock equalization pre-filtering on the input time/frequency domain signal according to the currently input adaptive equalization coefficient, and the obtained equalization pre-filtering signal is input to the Timing error extraction unit 201;
- the adaptive equalization coefficient of the current input is adaptively equalized by the adaptive equalization device to perform adaptive equalization processing on the input phase-adjusted time/frequency domain signal, and is output and fed back.
- the initial input adaptive equalization coefficient is determined by the system.
- the time/frequency domain signal includes a time/frequency domain first sub-signal according to a first optical polarization and a time/frequency domain second sub-signal according to a second optical polarization, the time-domain signal passing the time-frequency Converting to the frequency domain signal;
- the timing error extraction unit 201 is configured to obtain a phase error of the input/time domain signal according to the input equalization pre-filtering signal, and the obtained phase error is input to the phase adjustment unit 201;
- the phase adjustment unit 202 is configured to perform phase adjustment on the input/time domain signal according to the input phase error, and input the phase adjusted time/frequency domain signal to the adaptive equalization device 21, and further
- the adaptive equalization device 21 outputs a new adaptive equalization coefficient and feeds back to the equalization pre-filtering unit 200.
- clock recovery process provided by the embodiment of the present invention is specifically implemented as follows:
- the equalization pre-filtering unit 200 performs clock equalization pre-filtering on the input time/frequency domain signal according to the currently input adaptive equalization coefficient, and inputs the obtained equalized pre-filtered signal to the timing error extraction unit 201;
- the timing error extraction unit 201 obtains the phase error of the input time/frequency domain signal according to the equalization pre-filtering signal, and inputs the obtained phase error to the phase adjustment unit 202; Finally, the phase adjustment unit 202 performs phase adjustment on the input/time domain signal according to the phase error, and inputs the phase adjusted time/frequency domain signal to the adaptive equalization device 21, The adaptive equalization means 21 feeds back the updated adaptive equalization coefficients to the input of the equalization pre-filtering unit 200.
- the clock recovery device further includes a timing error filtering unit 203, as shown in FIG. 3: a timing error filtering unit 203 is connected between the timing error extraction unit 201 and the phase adjustment unit 202, and is configured to be The phase error is filtered, and the filtered phase error is input to the phase adjustment unit 202;
- the phase adjustment unit 202 is further configured to perform phase adjustment on the input/time domain signal according to the filtered phase error, and input the phase adjusted time/frequency domain signal to the adaptive equalization device 21
- the new adaptive equalization coefficient is output by the adaptive equalization device 21.
- the embodiment of the present invention provides a clock recovery method. As shown in FIG. 4, the method includes the following steps:
- Step S400 Perform clock equalization pre-filtering on the input time/frequency domain signal according to the currently input adaptive equalization coefficient to obtain an equalized pre-filtered signal.
- This step can be implemented by the equalization pre-filtering unit 200 in the clock recovery device 20;
- the time domain signal needs to be converted into the frequency domain signal by a module or device having a time-frequency conversion function, such as a Fourier transform module, before the time domain signal is input to the equalization pre-filtering unit 200. And then inputting the obtained frequency domain signal into the equalization pre-filtering unit 200; if the adaptive equalization coefficient fed back by the adaptive equalization device is a time domain coefficient, and the frequency domain coefficient is needed, the adaptive equalization device is needed. And adding a time-frequency conversion unit to the equalization pre-filtering unit 200; or adding a module having a time-frequency conversion function to the equalization pre-filtering unit 200, and converting the time-domain coefficients fed back by the adaptive equalization device into frequency-domain coefficients.
- a module or device having a time-frequency conversion function such as a Fourier transform module
- the equalization filtering unit 200 can be implemented by using a FIR filter of a single polarization system or an FIR filter of a polarization multiplexing system.
- the equalization pre-filtering unit 200 performs clock equalization pre-filtering on the input frequency domain signal according to the adaptive equalization coefficient when inputting the frequency domain signal and the frequency domain adaptive equalization coefficient, and specifically adopts the following manner:
- the polarization sub-signal, X, Y pd (k) is an equalization pre-filtered signal obtained by pre-filtering the clock equalization, and the obtained equalization pre-filtered signal is input to the timing error extraction unit 201.
- the equalization pre-filtering unit 200 uses the adaptive equalization coefficient fed back by the adaptive equalization device to perform clock equalization pre-filtering on the time/frequency domain signal, which can better track the dynamic change of the channel and accurately compensate the channel distortion. So that the effect of clock equalization pre-filtering is better, and thus Quickly and accurately extract the phase error of the input time/frequency signal to better restore the phase of the input time/frequency signal.
- Step S401 Acquire a phase error of the input/time domain signal according to the equalization filtered signal. This step can be implemented by the timing error extracting unit 201 in the clock recovery device;
- the error extraction implementation of the timing error extraction unit 201 may be implemented in the time domain or in the frequency domain; the input time/frequency signal may be a time domain signal or a frequency domain signal, and the corresponding output may be It is a time domain signal or a frequency domain signal.
- timing error extracting unit 201 extracts the phase error of the input time domain signal
- an algorithm such as square timing error extraction may be used; when extracting the phase error of the input frequency domain signal, a Godard algorithm may be used.
- the extraction algorithm of the phase error is not specifically limited.
- the equalization pre-filtering signal is the frequency domain equalization pre-filtering signal obtained in the above step S400. Therefore, the timing error extraction unit 201 acquires the phase error of the input frequency domain signal according to the equalization pre-filtering signal, and the Godard algorithm can be used.
- the specific implementation is as follows:
- X pd k is an equalized pre-filtered signal obtained by pre-filtering the clock equalization
- X* pd (k, , is the complex conjugate signal of the equalized pre-filtered signal; the phase value of C is calculated according to the following formula to obtain the phase error of the input frequency domain signal
- the phase error has a value range of [0, 1), and the obtained phase error is input to the phase adjustment unit 202.
- the timing error extraction unit 201 acquires a phase error of the input/time domain signal according to the equalization pre-filtering signal, wherein the equalization pre-filtering signal is fed back by the equalization pre-filtering unit 200 using the adaptive equalization device 21.
- the adaptive equalization coefficient is a signal obtained by performing clock equalization pre-filtering on the input/time domain signal, so that the timing error extracting unit 201 can more accurately The phase error of the input/frequency domain signal is taken.
- Step S403 Perform phase adjustment on the input/time domain signal according to the phase error, and output the phase-adjusted time/frequency domain signal to a new adaptive equalization coefficient through adaptive equalization processing.
- This step can be implemented by the phase adjustment unit 202 in the clock recovery device 20;
- the phase error of the input frequency domain signal is adjusted according to the phase error obtained in the above step S401, and the following method is specifically used:
- phase error is ⁇
- phase adjustment is performed according to the phase adjustment angle according to the following formula: (), ):
- JT( ) is the first sub-signal in the frequency domain, and is the second sub-signal in the frequency domain
- XH Y cr (k) is a frequency domain signal obtained after phase adjustment.
- the input time domain signal is interpolated according to the phase error obtained in the above step S401 to adjust the phase of the input time domain signal;
- the interpolation algorithm can be A fractional interpolation algorithm, such as a cubic Lagrangian interpolation algorithm, is used, and the interpolation algorithm is not specifically limited herein.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Optical Communication System (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
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Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016555874A JP6317467B2 (ja) | 2014-01-10 | 2014-04-01 | クロックリカバリ方法、装置、システムおよびコンピュータ記憶媒体 |
| KR1020167013711A KR101821510B1 (ko) | 2014-01-10 | 2014-04-01 | 클럭 복원 방법, 장치, 시스템 및 컴퓨터 기록 매체 |
| EP14878145.3A EP3094037B1 (en) | 2014-01-10 | 2014-04-01 | Clock recovery method, device and system and computer storage medium |
| US15/104,425 US10135543B2 (en) | 2014-01-10 | 2014-04-01 | Clock recovery method, device and system and computer storage medium |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410012704.0 | 2014-01-10 | ||
| CN201410012704.0A CN104780037B (zh) | 2014-01-10 | 2014-01-10 | 一种时钟恢复方法、装置及系统 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2015103816A1 true WO2015103816A1 (zh) | 2015-07-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2014/074566 Ceased WO2015103816A1 (zh) | 2014-01-10 | 2014-04-01 | 一种时钟恢复方法、装置、系统及计算机存储介质 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US10135543B2 (zh) |
| EP (1) | EP3094037B1 (zh) |
| JP (1) | JP6317467B2 (zh) |
| KR (1) | KR101821510B1 (zh) |
| CN (1) | CN104780037B (zh) |
| WO (1) | WO2015103816A1 (zh) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111342905A (zh) * | 2018-12-18 | 2020-06-26 | 深圳市中兴微电子技术有限公司 | 一种信号处理方法、装置和计算机存储介质 |
| CN117311300A (zh) * | 2023-11-29 | 2023-12-29 | 西安热工研究院有限公司 | 分散控制系统动态调整采样频率的方法、装置及电子设备 |
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| CN104780037B (zh) * | 2014-01-10 | 2019-04-30 | 深圳市中兴微电子技术有限公司 | 一种时钟恢复方法、装置及系统 |
| CN108141282B (zh) * | 2015-10-26 | 2019-12-13 | 华为技术有限公司 | 一种时钟性能监控系统、方法及装置 |
| US9882709B2 (en) * | 2016-05-10 | 2018-01-30 | Macom Connectivity Solutions, Llc | Timing recovery with adaptive channel response estimation |
| CN109478929B (zh) * | 2016-07-11 | 2021-01-29 | 华为技术有限公司 | 一种频谱检测装置和检测方法 |
| CN109218237B (zh) * | 2017-07-07 | 2021-02-19 | 扬智科技股份有限公司 | 实体层电路、时钟恢复电路与其频偏纠正方法 |
| CN110351066B (zh) * | 2018-04-02 | 2022-03-08 | 华为技术有限公司 | 时钟相位恢复装置、方法和芯片 |
| EP3857809B1 (en) * | 2018-11-08 | 2024-04-24 | Huawei Technologies Co., Ltd. | Clock extraction in systems affected by strong intersymbol interference |
| GB2579230B (en) * | 2018-11-26 | 2021-04-07 | Cisco Tech Inc | Digital resampling method and apparatus |
| CN111262634B (zh) * | 2018-11-30 | 2020-11-17 | 深圳市中兴微电子技术有限公司 | 色散估计方法、装置、接收机及存储介质 |
| CN109931967B (zh) * | 2019-02-21 | 2021-04-20 | 电子科技大学 | 一种光电探测器频率响应测量的频率配置方法 |
| CN112787662A (zh) * | 2019-11-08 | 2021-05-11 | 深圳市中兴微电子技术有限公司 | 时钟数据恢复系统及装置、存储介质、电子装置 |
| CN113132020B (zh) * | 2019-12-31 | 2023-07-28 | 华为技术有限公司 | 相干光接收装置和采用相干光接收装置的光系统 |
| CN118041442B (zh) * | 2024-04-08 | 2024-06-14 | 江苏时同源科技有限公司 | 基于光纤授时系统的时间频率信号质量检测系统 |
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2014
- 2014-01-10 CN CN201410012704.0A patent/CN104780037B/zh active Active
- 2014-04-01 WO PCT/CN2014/074566 patent/WO2015103816A1/zh not_active Ceased
- 2014-04-01 JP JP2016555874A patent/JP6317467B2/ja active Active
- 2014-04-01 EP EP14878145.3A patent/EP3094037B1/en active Active
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| CN1131604C (zh) * | 1997-10-07 | 2003-12-17 | 松下电器产业株式会社 | 信号波形均衡装置 |
| CN1280434A (zh) * | 1999-07-12 | 2001-01-17 | 三星电子株式会社 | 数字信号接收器和接收数字信号的方法 |
| CN101636928A (zh) * | 2007-03-21 | 2010-01-27 | 飞思卡尔半导体公司 | 用于通信信道的自适应均衡器 |
| CN101599929A (zh) * | 2008-06-06 | 2009-12-09 | 富士通株式会社 | 自适应均衡装置和方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111342905A (zh) * | 2018-12-18 | 2020-06-26 | 深圳市中兴微电子技术有限公司 | 一种信号处理方法、装置和计算机存储介质 |
| CN117311300A (zh) * | 2023-11-29 | 2023-12-29 | 西安热工研究院有限公司 | 分散控制系统动态调整采样频率的方法、装置及电子设备 |
| CN117311300B (zh) * | 2023-11-29 | 2024-02-13 | 西安热工研究院有限公司 | 分散控制系统动态调整采样频率的方法、装置及电子设备 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017503446A (ja) | 2017-01-26 |
| EP3094037B1 (en) | 2019-01-02 |
| JP6317467B2 (ja) | 2018-04-25 |
| CN104780037A (zh) | 2015-07-15 |
| KR101821510B1 (ko) | 2018-01-23 |
| US20160329970A1 (en) | 2016-11-10 |
| CN104780037B (zh) | 2019-04-30 |
| US10135543B2 (en) | 2018-11-20 |
| EP3094037A4 (en) | 2017-08-23 |
| EP3094037A1 (en) | 2016-11-16 |
| KR20160103976A (ko) | 2016-09-02 |
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