WO2015120719A1 - 信息处理方法及装置 - Google Patents

信息处理方法及装置 Download PDF

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Publication number
WO2015120719A1
WO2015120719A1 PCT/CN2014/085949 CN2014085949W WO2015120719A1 WO 2015120719 A1 WO2015120719 A1 WO 2015120719A1 CN 2014085949 W CN2014085949 W CN 2014085949W WO 2015120719 A1 WO2015120719 A1 WO 2015120719A1
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parity check
check matrix
matrix
basic parity
elements
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English (en)
French (fr)
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李立广
徐俊
袁志锋
许进
田开波
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ZTE Corp
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ZTE Corp
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Priority to US15/118,287 priority patent/US20170033804A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H04L1/0058—Block-coded modulation

Definitions

  • the present invention relates to the field of communications, and in particular to an information processing method and apparatus.
  • the current digital communication system is generally divided into three parts: a transmitting end, a channel, and a receiving end.
  • the transmitting end usually includes a source, a channel coder and a modulator (or a writing unit); the receiving end usually includes a demodulator (or readout unit), a channel decoder and a sink; and between the transmitting end and the receiving end There is a channel (or storage medium) and there is a source of noise in the channel.
  • the channel coding link (including channel coding and decoding, modulation and demodulation, etc.) is the key to the entire digital communication physical layer, which determines the effectiveness and reliability of the underlying transmission of the digital communication system.
  • the main function of the channel coder is to resist the influence of various noises and interferences in the channel on the useful signal. By artificially adding some redundant information, the system has the ability to automatically correct errors, thus ensuring reliable information transmission. Sex.
  • LDPC Low Density Parity Check
  • turbo code turbo code
  • convolutional code RS code
  • the LDPC code is the most excellent channel coding under the Additive White Gaussian Noise (AWGN) channel, and the performance is very close to the Shannon limit.
  • AWGN Additive White Gaussian Noise
  • LDPC code is a linear block code that can be defined by a very sparse parity check matrix or bipartite graph. It is the sparseness of its check matrix that can realize low complexity codec, which makes LDPC practical. .
  • LDPC code performance is very good.
  • the hardware complexity of the LDPC code is very high.
  • the LDPC code is a linear block code, so there is also a lack of flexibility in the design of the code rate and code length.
  • the code length supports 19 kinds, and the code rate supports 4 types (1/2, 2/3, 3/4, and 5/6), which needs to be adopted.
  • each standard is a check matrix that requires multiple LDPC codes to support the need for flexibility. Since the parity check matrix corresponding to each code rate is basically not associated, the receiving decoder side needs multiple decoders to decode each code rate, or a decoder is used to support so many check matrix requirements. Either way, it requires very high hardware costs and it is not convenient to make specific optimizations for certain units in the decoder.
  • the present invention provides an information processing method and apparatus to solve at least the above problems.
  • an information processing apparatus comprising: one or more memories arranged to store parameters of a base parity check matrix group; one or more processors configured to use the base parity
  • the check matrix group Hb decodes the information bits to be encoded or the data to be decoded, wherein the basic parity check matrix in the basic parity check matrix group Hb other than Hb j0
  • the short 4 ring of at least 50% of the matrix Hb j1 is the same as the short 4 ring of Hb j0
  • j0 is a fixed positive integer between 0 and L-1
  • L is the basis contained in the basic parity check matrix group
  • the number of parity check matrices, j1 0,1,...,j0-1,j0+1,...,L-1.
  • each basic parity check matrix in the basic parity check matrix group is Mb ⁇ Nb, the number of columns Nb is a fixed value nb0, the number of rows Mb is a value mbi, and each row number mbi corresponds to one code.
  • the short 4-ring is the four non-1 elements of the c-th column and the d-th column in the base parity check matrix intersecting the a-th row and the b-th row [h ac , h bc , h bd , h ad
  • a, b, c, and d are any integers greater than or equal to 0 and less than nb0, and c ⁇ d, a ⁇ b.
  • the non--1 elements in the c-th column of the basic parity check matrix Hb j1 other than Hb j0 form a set Scj1 on the same column as Hb j0 from the top to the bottom. a subset of the set Scj0 of the non-1 element from the top to the bottom; wherein the Hb j0 is a basic parity check matrix whose number of matrix rows is equal to the maximum column weight MaxW, and the maximum column weight MaxW refers to the basic checksum
  • MaxW is a positive integer
  • c is an integer greater than or equal to 0 and less than nb0.
  • all elements in the set Scj1 are in the same order from top to bottom as the top-down order of the elements in the set Scj0.
  • each of the basic parity check matrices Hbi [Abi Bbi] in the basic parity check matrix group, wherein the matrix Abi is a system bit partial matrix, the dimension is Mb ⁇ (Nb ⁇ Mb), and the matrix Bbi is a checksum Bit partial matrix, The dimension is Mb ⁇ Mb, the number of rows of the matrix Abi and the matrix Bbi is equal, and the row is greater than or equal to 1, and the matrix Bbi is a strictly lower triangular structure matrix or a double diagonal structure matrix.
  • the number of -1 elements on different rows of the system bit portion matrix of each basic parity check matrix in the basic parity check matrix group is equal or different by two or less.
  • the value of the nb0 includes: 8, 16, 24, 32, 40 or 48.
  • the short 4 ring in the Hb j1 is the same as the short 4 ring in the Hb j0 includes: a value of an element corresponding to each of the short 4 ring in the Hb j1 and the short 4 ring in the Hb j0 Equal, and the two elements of the short 4-ring on the Hb j1 line are identical to the two elements of the upper short 4-ring of the Hb j0 line, and the two elements of the short 4-ring on the Hb j1 column are Hb j0
  • the two elements of the upper short 4-ring of a column are equivalent one by one.
  • any four elements [h ac , h bc , h bd , h ad ] capable of forming 4 rings in each basic parity check matrix of the basic parity check matrix group satisfy the inequality (h ac -h Bc +h bd -h ad )%zf ⁇ 0, where % is the remainder operator, zf is the expansion factor, and a, b, c, and d are any integers greater than or equal to 0 and less than nb0, and a ⁇ b, c ⁇ d.
  • the parity check matrix based group, j is less than the maximum number of rows in the matrix column weight basis MaxW matrix of parity check matrix Hb j0 is equal to the j-th row constituted, wherein said matrix row Hb j0 The number is equal to the base parity check matrix of the maximum column weight MaxW, where MaxW and j are positive integers.
  • one or more elements of any four elements [h ai , h bi , h bj , h aj ] constituting the four rings It belongs to a column weight of 2, and satisfies the inequality (h ai -h bi +h bj -h aj )%zf ⁇ 0; and, in all the basic parity check matrices of the basic parity check matrix group, constitutes a short 6 Any 6 elements of the ring In the middle, one or more elements belong to the column weight of 2, and satisfy the inequality (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0, where % is the remainder operation , zf is an expansion factor, and a, b, c, i, j, and k are arbitrary integers greater than or equal to 0 and less than nb0,
  • any four elements [h ai , h bi , h bj , h aj ] constituting the four rings satisfy the inequality (h ai -h bi +h bj -h aj )%zf ⁇ 0, and the basis
  • the parity check matrix Hb0 any six elements constituting a short 6 ring , both satisfy the inequality (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0, where % is the remainder operator, zf is the expansion factor, a, b, c, i, j and k are arbitrary integers greater than or equal to 0 and less than nb0, and a ⁇ b ⁇ c, i ⁇ j ⁇ k.
  • the one or more processors decode the information bits to be encoded or the data to be coded by determining a packet of the information bits to be encoded or the data to be decoded. And grouping, selecting, according to the group of information bits to be encoded or the group of data to be coded, a basic parity check matrix from the basic parity check matrix group, based on the selected basic parity check matrix Encoding the packet of the information bits to be encoded or decoding the packet of the data to be decoded.
  • each basic parity check matrix in the basic parity check matrix group is Mb ⁇ Nb, the number of columns Nb is a fixed value nb0, the number of rows Mb is a value mbi, and each row number mbi corresponds to one code.
  • the short 4-ring is the four non-1 elements of the c-th column and the d-th column in the base parity check matrix intersecting the a-th row and the b-th row [h ac , h bc , h bd , h ad
  • a, b, c, and d are any integers greater than or equal to 0 and less than nb0, and c ⁇ d, a ⁇ b.
  • the non--1 elements in the c-th column of the basic parity check matrix Hb j1 other than Hb j0 form a set Scj1 on the same column as Hb j0 from the top to the bottom. a subset of the set Scj0 of the non-1 element from the top to the bottom; wherein the Hb j0 is a basic parity check matrix whose number of matrix rows is equal to the maximum column weight MaxW, and the maximum column weight MaxW refers to the basic checksum
  • MaxW is a positive integer
  • c is an integer greater than or equal to 0 and less than nb0.
  • all elements in the set Scj1 are in the same order from top to bottom as the top-down order of the elements in the set Scj0.
  • each of the basic parity check matrices Hbi [Abi Bbi] in the basic parity check matrix group, wherein the matrix Abi is a system bit partial matrix, the dimension is Mb ⁇ (Nb ⁇ Mb), and the matrix Bbi is a checksum
  • the bit partial matrix has a dimension of Mb ⁇ Mb, the number of rows of the matrix Abi and the matrix Bbi is equal, and the row is greater than or equal to 1, and the matrix Bbi is a strictly lower triangular structure matrix or a double diagonal structure matrix.
  • the number of -1 elements on different rows of the system bit portion matrix of each basic parity check matrix in the basic parity check matrix group is equal or different by two or less.
  • the value of the nb0 includes 8, 16, 24, 32, 40 or 48.
  • the short 4 ring in the Hb j1 is the same as the short 4 ring in the Hb j0 includes: a value of an element corresponding to each of the short 4 ring in the Hb j1 and the short 4 ring in the Hb j0 Equal, and the two elements of the short 4-ring on the Hb j1 line are identical to the two elements of the upper short 4-ring of the Hb j0 line, and the two elements of the short 4-ring on the Hb j1 column are Hb j0
  • the two elements of the upper short 4-ring of a column are equivalent one by one.
  • any four elements [h ac , h bc , h bd , h ad ] capable of forming 4 rings in each basic parity check matrix of the basic parity check matrix group satisfy the inequality (h ac -h Bc +h bd -h ad )%zf ⁇ 0, where % is the remainder operator, zf is the expansion factor, and a, b, c, and d are any integers greater than or equal to 0 and less than nb0, and a ⁇ b, c ⁇ d.
  • the parity check matrix based group, j is less than the maximum number of rows in the matrix column weight basis MaxW matrix of parity check matrix Hb j0 is equal to the j-th row constituted, wherein said matrix row Hb j0 The number is equal to the base parity check matrix of the maximum column weight MaxW, where MaxW and j are positive integers.
  • one or more elements of any four elements [h ai , h bi , h bj , h aj ] constituting the four rings It belongs to a column weight of 2, and satisfies the inequality (h ai -h bi +h bj -h aj )%zf ⁇ 0; and, in all the basic parity check matrices of the basic parity check matrix group, constitutes a short 6 Any 6 elements of the ring Among them, one or more elements belonging to the column weight of 2 can satisfy the inequality (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0, where % is the remainder
  • zf is an expansion factor
  • a, b, c, i, j, and k are arbitrary integers greater than or equal to 0 and less than nb0,
  • any four elements [h ai , h bi , h bj , h aj ] constituting the four rings satisfy the inequality (h ai -h bi +h bj -h aj )%zf ⁇ 0;
  • the basic parity check matrix Hb0 any six elements constituting a short 6 ring , both satisfy the inequality (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0, where % is the remainder operator, zf is the expansion factor, a, b, c, i, j and k are arbitrary integers greater than or equal to 0 and less than nb0, and a ⁇ b ⁇ c, i ⁇ j ⁇ k.
  • encoding the information bits to be encoded or decoding the data to be coded using a preset basic parity check matrix group Hb includes: determining a packet of the information bits to be encoded or And the grouping of the data to be decoded, selecting a basic parity check matrix from the basic parity check matrix group according to the packet of the information bits to be encoded or the data of the data to be decoded, based on the selection
  • the base parity check matrix encodes a packet of the information bits to be encoded or decodes a packet of the data to be decoded.
  • FIG. 1 is a schematic structural diagram of a digital communication system according to the related art
  • FIG. 2 is a schematic structural diagram of an information processing apparatus according to an embodiment of the present invention.
  • FIG. 3 is a block diagram of a simple communication link model in an embodiment of the present invention.
  • FIG. 4 is a block diagram of encoding of an LDPC code according to an embodiment of the present invention.
  • FIG. 5 is a block diagram of decoding of an LDPC code according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of an information processing method according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of encoding an LDPC code according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of decoding an LDPC code according to an embodiment of the present invention.
  • FIG. 9 is a diagram showing the structure of a basic parity check matrix of an LDPC code according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing the occurrence of four rings in a bipartite graph of an LDPC code according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram showing the occurrence of 6 rings in a bipartite graph of an LDPC code according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram showing the occurrence of four rings in a parity check matrix of an LDPC code according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing the occurrence of 6 rings in a parity check matrix of an LDPC code according to an embodiment of the present invention
  • FIG. 14 is a schematic diagram of an LDPC code extended check matrix uniquely determined by a base matrix, a spreading factor, and a permutation matrix according to an embodiment of the present invention.
  • an information processing apparatus is provided.
  • each basic parity check matrix in the basic parity check matrix group is Mb ⁇ Nb
  • the number of columns Nb is a fixed value nb0
  • the number of rows Mb is Mbi
  • nb0 is an integer greater than zero.
  • the short 4-ring is a fourth non--1 element in which the c-th column and the d-th column of the basic parity check matrix intersect with the a-th row and the b-th row.
  • h ac , h bc , h bd , h ad h ac , h bc , h bd , h ad ] wherein a, b, c and d are any integers greater than or equal to 0 and less than nb0, and c ⁇ d, a ⁇ b.
  • non--1 elements in the c- th column of the basic parity check matrix Hb j1 except Hb j0 are from top to bottom.
  • the set Scj1 formed by the order is a subset of the set Scj0 of the non--1 elements on the same column of Hb j0 from top to bottom;
  • the Hb j0 is a basic parity check matrix whose number of matrix rows is equal to the maximum column weight MaxW
  • the maximum column weight MaxW refers to the column weight of the largest column of all columns of all the basic check matrices in the basic check matrix group
  • j0 is an integer between 0 and L-1
  • MaxW is a positive integer
  • c is greater than An integer equal to 0 and less than nb0.
  • the column weight refers to the number of non-1 elements in a column in the basic check matrix.
  • all the elements in the set Scj1 are in the same order from the top to the bottom of the elements in the set Scj0.
  • each basic parity check matrix Hbi [Abi Bbi] in the basic parity check matrix group, wherein the matrix Abi is a system bit partial matrix, and the dimension is Mb ⁇ (Nb-Mb), the matrix Bbi is a checkpoint partial matrix, the dimension is Mb ⁇ Mb, the number of rows of the matrix Abi and the matrix Bbi is equal, and the row is greater than or equal to 1, and the matrix Bbi is a strictly lower triangular structure matrix or a double diagonal structure matrix.
  • the number of -1 elements on different rows of the systematic bit portion matrix of each basic parity check matrix in the basic parity check matrix group is equal or the difference is less than or equal to 2.
  • the system bit portion matrix of the system bit portion matrix of each basic parity check matrix in the basic parity check matrix group does not have two consecutive columns or More than 3 consecutive -1 elements.
  • the value of the nb0 includes but is not limited to: 8, 16, 24, 32, 40 or 48.
  • the short 4 ring in the Hb j1 is the same as the short 4 ring in the Hb j0 , including: the short 4 ring in the Hb j1 and the Hb j0
  • the corresponding elements of the short 4 ring have the same value, and the 2 elements of the short 4 ring on the Hb j1 line are equal to the 2 elements of the upper 4 ring of the Hb j0 line, respectively, on the Hb j1 column.
  • the two elements of the short four-ring are in one-to-one correspondence with the two elements of the upper short four-ring of the Hb j0 column.
  • the four elements of the short four-ring of the matrix Hb j1 are equal to the four elements of the short four-ring of the matrix Hb j0 ; in the two elements of the short-ring of four rings in Hb j1 , the two elements are also in Hb j0 On a line; in Hb j1 , two elements of 4 rings are short on one column, then the 2 elements are also in one column in Hb j0 .
  • any four elements of the four rings [h ac , h bc , h bd , h ad ], satisfying the inequality (h ac -h bc +h bd -h ad )%zf ⁇ 0, where % is the remainder operator, zf is the expansion factor, and a, b, c, and d are any greater than or equal to 0 And less than the integer of nb0, and a ⁇ b, c ⁇ d.
  • the expansion factor zf is the dimension of the permutation matrix (general unit matrix), and the value must be greater than zero.
  • the spreading factors, a, b, c, i, j, and k are arbitrary integers greater than or equal to 0 and less than nb0, and a ⁇ b ⁇ c, i ⁇ j ⁇ k.
  • a matrix parity number j is smaller than a maximum column weight MaxW, and a basic parity check matrix is equal to the Hb j0 and j rows.
  • all the basic parity check matrices of the basic parity check matrix group constitute any four elements of the four rings [h ai , h bi , h bj , h aj
  • one or more elements belong to a column weight of 2, and satisfy the inequality (h ai -h bi +h bj -h aj )%zf ⁇ 0; and, all of the basic parity check matrix group
  • Any six elements constituting a short 6 ring in the base parity check matrix In the middle, one or more elements belong to the column weight of 2, and satisfy the inequality (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0, where % is the remainder operation , zf is an expansion factor, and a, b, c, i, j, and k are arbitrary integers greater than or equal to 0 and less than nb0, and a
  • the basic parity check matrix Hb0 of 1/2 any four elements [h ai , h bi , h bj , h aj ] constituting the four rings satisfy the inequality (h ai -h bi +h bj -h aj %zf ⁇ 0, and any of the six elements constituting the short 6 ring in the basic parity check matrix Hb0 , both satisfy the inequality (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0, where % is the remainder operator, zf is the expansion factor, a, b, c, i, j and k are arbitrary integers greater than or equal to 0 and less than nb0, and a ⁇ b ⁇ c,
  • the one or more processors decode the information bits to be encoded or the data to be coded by: determining the information bits to be encoded. a packet or a packet of the data to be decoded, selecting a basic parity check matrix from the basic parity check matrix group according to the packet of the information bit to be encoded or the packet of the data to be decoded. And encoding, according to the selected basic parity check matrix, a packet of the information bit to be encoded or decoding a packet of the data to be decoded.
  • the code rates supported by the LDPC code are R 0 , R 1 , . . . , R L-1 , respectively, and the corresponding parity check matrix is Hb 0 , Hb 1 , respectively. ..., Hb (L-1) , the number of rows of the basic parity check matrix are M 0 , M 1 , ..., M L-1 , and the number of columns is Nb, L is the number of code rates to be constructed, and each basis
  • the parity check matrix can be encoded or decoded by using the same encoder or decoder, which solves the problem of high hardware complexity and poor flexibility, reduces hardware complexity and improves the flexibility of the compiled code.
  • an information processing method which can be implemented by the above information processing apparatus.
  • FIG. 3 is a flowchart of an information processing method according to an embodiment of the present invention. As shown in FIG. 3, the method mainly includes the following steps S302-S304.
  • Step S302 Acquire information bits to be encoded or data to be decoded.
  • Step 304 encode the information bits to be encoded or decode the data to be decoded by using a preset basic parity check matrix group Hb, where the basic parity check matrix group Hb is used.
  • Hb basic parity check matrix group
  • j0 is a fixed positive between 0 to L-1
  • each basic parity check matrix in the basic parity check matrix group is Mb ⁇ Nb
  • the number of columns Nb is a fixed value nb0
  • the number of rows Mb is mbi, each row
  • the short 4-ring is the four non--1 elements [h ac , h bc , h bd , h ad ] of the c-th column and the d-th column intersecting the a-th row and the b-th row in the basic parity check matrix.
  • a, b, c, and d are any integers greater than or equal to 0 and less than nb0, and c ⁇ d, a ⁇ b.
  • the non--1 elements in the c-th column of the basic parity check matrix Hb j1 other than Hb j0 form a set Scj1 from the top to the bottom.
  • Hb j0 is a subset of the set Scj0 of the non--1 elements from the top to the bottom of the same column; wherein, the Hb j0 is a basic parity check matrix whose number of matrix rows is equal to the maximum column weight MaxW, and the maximum column weight MaxW is The column weight of the largest column of all columns of all the basic check matrices in the basic check matrix group, MaxW is a positive integer, and c is an integer greater than or equal to 0 and less than nb0.
  • all elements in the set Scj1 are in the same order from top to bottom as the top-down order of the elements in the set Scj0.
  • each basic parity check matrix Hbi [Abi Bbi] in the basic parity check matrix group, wherein the matrix Abi is a system bit partial matrix, and the dimension is Mb ⁇ (Nb ⁇ Mb),
  • the matrix Bbi is a matrix of check digits, the dimension is Mb ⁇ Mb, the number of rows of the matrix Abi and the matrix Bbi is equal, and the row is greater than or equal to 1, and the matrix Bbi is a strictly lower triangular structure matrix or a double diagonal structure matrix.
  • the number of -1 elements on different rows of the system bit portion matrix of each basic parity check matrix in the basic parity check matrix group are equal or different by two or less.
  • system bit portion matrix of the system bit portion matrix of each basic parity check matrix in the basic parity check matrix group does not have two consecutive or three consecutive ones in each column - 1 element.
  • nb0 includes, but is not limited to, 8, 16, 24, 32, 40 or 48.
  • the short 4 ring in the Hb j1 is the same as the short 4 ring in the Hb j0 includes: a short 4 ring in the Hb j1 and a short 4 ring in the Hb j0
  • the values of the elements are equal, and the two elements of the short 4-ring on the Hb j1 line are identical to the two elements of the upper short 4-ring of the Hb j0 line, and the short 4 rings on the Hb j1 column are 2
  • the two elements are in one-to-one correspondence with the two elements of the upper short 4-ring of the Hb j0 column. .
  • any four elements [h ac , h bc , h bd , h ad ] capable of forming 4 rings in each basic parity check matrix of the basic parity check matrix group satisfy the inequality (h ac -h bc +h bc -h ad )%zf ⁇ 0, where % is the remainder operator, zf is the expansion factor, and a, b, c, and d are any integers greater than or equal to 0 and less than nb0, And a ⁇ b, c ⁇ d.
  • the parity check matrix based group, j is less than the maximum number of rows in the matrix column weight MaxW basis matrix is equal to the parity check matrix composed of rows j j0 after the Hb, wherein said Hb j0 is a basic parity check matrix whose number of matrix rows is equal to the maximum column weight MaxW, where MaxW and j are positive integers.
  • any one of the four elements [h ac , h bc , h bd , h ad ] constituting the four rings has 1 One or more elements belonging to a column weight of 2, and satisfying the inequality (h ac -h bc +h bc -h ad )%zf ⁇ 0; and, all the basic parity check matrices of the basic parity check matrix group In the middle, constitute any 6 elements of the short 6 ring Among them, one or more elements belonging to the column weight of 2 can satisfy the inequality (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0.
  • any four elements [h ac , h bc , h bd , h ad ] constituting the four rings satisfy the inequality (h ac -h bc +h bc -h ad )%zf ⁇ 0
  • any six elements constituting a short 6 ring Both satisfy the inequality (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0.
  • encoding the information bits to be encoded or coding the data to be decoded using a preset basic parity check matrix group Hb includes: determining the to-be-encoded a packet of information bits or a packet of the data to be decoded, and selecting a basic parity from the group of basic parity check matrix according to the packet of information bits to be encoded or the packet of data to be decoded And determining, according to the selected basic parity check matrix, a packet of the information bit to be encoded or a packet of the data to be decoded.
  • a simple communication link model is illustrated in Figure 4.
  • Information can be transmitted from the A side to the B side, or from the B side to the A side.
  • a and B may be one or more of a device type such as a base station, a transit node, an access node, and a terminal device, or multiple devices of the same device type.
  • Data can be transmitted between A and B at any time, or data can be communicated only when conditions permit.
  • the above information processing apparatus provided by the embodiment of the present invention can apply any data transmission between A to B and B to A.
  • the A side can be equipped with t1 transmitting antennas and r1 receiving antennas
  • the B end can also be equipped with t2 transmitting antennas and r2 receiving antennas.
  • t1 ⁇ 1 and r1 ⁇ 1 At terminal A, t1 ⁇ 1 and r1 ⁇ 1, and at terminal B, t2 ⁇ 1 and r2 ⁇ 1.
  • the A-end antenna may be fixed or movable; at the same time, the B-end antenna may be fixed or movable.
  • the communication between A and B also needs a channel to be transmitted, and the channel may be a wireless channel, such as microwave communication, electromagnetic wave communication, acoustic wave communication, optical communication, etc., or may be a wired channel.
  • a wireless channel such as microwave communication, electromagnetic wave communication, acoustic wave communication, optical communication, etc.
  • a wired channel such as fiber optic communication, cable, etc.
  • fiber optic communication, cable, etc. can also be a variety of storage media.
  • the data information transmitted from one device a1 on the A side to one device b1 on the B side will be described as an example.
  • a1 needs to be read by the processor from the source and grouped, and then processed (encoded, modulated, etc.) the data packet, and then transmitted through the transmitting antenna; a device b1 at the B end
  • the processor needs to receive signals from the receiving antenna and process them to obtain the original data.
  • the principle of data transmission from the B end to the A end is the same as described above.
  • LDPC coding can be employed to increase the reliability of data transmission.
  • An LDPC code is a linear block code that can be defined with a very sparse parity check matrix or a bipartite graph.
  • the encoder at the A or B end is shown in Figure 5, and the decoder is shown in Figure 6.
  • the processor in the encoder/decoder is primarily responsible for various logic operations. As shown in FIG. 5, the processor in the encoder is mainly responsible for processing data, that is, acquiring information to be transmitted from a source, grouping information bits of the source, and then cooperating with the memory to perform information bit grouping.
  • the LDPC is encoded, then modulated and transmitted.
  • the processor of the decoder acquires information from the antenna, and then configures the memory to perform LDPC decoding on the information, and then performs information combining and transmitting to the sink; and the memory of the encoder/decoder is mainly responsible for storing the A end. Or all the data and program code needed on the B side. That is, the memory is mainly responsible for storing the LDPC code basic parity check matrix information, and storing other data information.
  • the LDPC encoder groups the information bits to obtain a 1 ⁇ k information bit packet, which is denoted by a here.
  • the a-information bit block is encoded by an encoder to obtain a 1 ⁇ n codeword bit block, denoted by x.
  • the basic matrix of the LDPC code is Hb, and the corresponding extended check matrix is H.
  • the LDPC code is a linear block code, and the corresponding extended check matrix is H. For each codeword x, the relationship can be satisfied.
  • the extended check matrix H can be divided into two parts: a system bit portion matrix A and a check bit portion matrix B, as shown in FIG. 9, that is,
  • the LDPC codeword x is also divided into a system bit portion vector a and a check bit portion vector b, as follows
  • the LDPC encoding flowchart corresponding to the encoder shown in FIG. 7 is as shown in FIG. 7.
  • the LDPC encoding in this embodiment mainly includes the following steps 1 - 4.
  • Step 1 Block the data to be encoded to obtain a 1 ⁇ k information bit packet, that is, a.
  • LDPC decoder In an LDPC decoder, two modules are also required: a processor (CPU) and a memory.
  • the processor is mainly responsible for various logic operations, and the memory is mainly responsible for storing the basic parity check matrix information of the LDPC code and storing other decoded data information.
  • the LDPC decoder is shown in Figure 6.
  • LDPC decoding methods such as probability domain BP decoding algorithm, log domain BP decoding algorithm and hierarchical minimum and decoding algorithm.
  • Probability domain BP decoding algorithm has the best performance, but the disadvantage is that because it involves a large number of multiplication operations, the computational complexity is very large, so the required hardware cost is very high, and the dynamic range of the numerical value is not stable, so it is generally in practice. Not used in the app.
  • the log-domain BP decoding algorithm reduces many computational units, but still requires a lot of multiplication operations, and the hardware costs required are also quite large.
  • the layered minimum and decoding algorithm converts the key computation (log operation and multiplication) units of the log-domain BP decoding algorithm into minimum and minimum values, and the required hardware resources are greatly reduced, and the performance will have a small loss. But you can reduce a lot of hardware resources. Therefore, the more practical applications are the layered minimum and decoding algorithms.
  • the decoding module is mainly divided into two parts: check node update module and variable node update module.
  • the LDPC decoder is shown in Figure 6, and the corresponding LDPC decoding flow chart is shown in Figure 8. As shown in FIG. 8, the LDPC decoding mainly includes the following steps 1 - 4.
  • Step 1 Initialize.
  • step 2 a check node update is performed.
  • Step 3 Perform a variable node update.
  • LDPC encoding and decoding in order to ensure excellent performance, high throughput, high flexibility and low complexity, it is closely related to the designed LDPC code check matrix. Conversely, if the design of the LDPC check matrix is not good, it will degrade its performance, and it may also affect the complexity and flexibility. Therefore, how to obtain a suitable LDPC code check matrix is very important.
  • the basic parity check matrix of the LDPC code appears to have a short 4 ring and a short 6 ring form a girth.
  • a method for constructing a plurality of code rate LDPC code basic parity check matrix according to an embodiment of the present invention is analyzed by a specific embodiment.
  • the encoder/decoder there are two parts: a processor and a memory.
  • the processor is mainly responsible for performing various logic operations
  • the memory is mainly responsible for storing various information, in particular, the storage of the basic parity check matrix which is very important in LDPC encoding and decoding.
  • the numbers of Hb 0 , Hb 1 , Hb 2 , and Hb 3 are 16 columns.
  • the number of basic parity check matrix lines corresponding to the respective code rates is (h ai -h bi +h bj -h cj +h ck -h ak )%zf ⁇ 0, respectively.
  • the maximum column weight MaxW is 4, and for other basic parity check matrices whose matrix row numbers are greater than or equal to the maximum column weight 4, the sets of non-1 elements on the same column are equal.
  • the number of -1 elements on different rows are equal, such as Hb0 and Hb1, or the maximum difference is only within 2 (including 2), Such as Hb2 and Hb3.
  • any six elements [h ai , h bi , h bj , h cj , h ck , h ak ] of the short 6 ring can be formed, which can satisfy the inequality (h).
  • % is the remainder operator
  • zf is the expansion factor
  • zf 256.
  • the basic parity check matrix of all code rates has a mutual relationship, and has the following beneficial effects:
  • the basic parity check matrix of all code rates is basically in the same form, so the same decoder can be completely shared, so that hardware resources can be greatly reduced. There is no need to waste a lot of resources to make a decoder for each code rate (check matrix) or make a huge adjustment to one decoder to support other code rates.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the LDPC coding code when used, multiple check matrices corresponding to multiple code rates are associated, so that the same encoder or decoder can be used for encoding or decoding, which solves the high hardware complexity.
  • the problem of poor flexibility reduces hardware complexity and increases the flexibility of the compiled code. It has industrial applicability.

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Abstract

本发明公开了一种信息处理方法及装置。其中，该装置包括：一个或多个存储器，设置为存储一个基础奇偶校验矩阵组的参数；一个或多个处理器，设置为使用基础奇偶校验矩阵组Hb对待编码的信息比特进行编码或对待译码的数据进行译码，其中，基础奇偶校验矩阵组Hb中，除了Hbj0以外其他的基础奇偶校验矩阵中基础奇偶校验矩阵Hbj1的至少50％的短4环与Hbj0中短4环相同，j0为0到L-1之间的一个固定正整数，L为基础奇偶校验矩阵组中包含的基础奇偶校验矩阵的数量，j1＝0，1，...，j0-1，j0+1，...，L-1。

Description

信息处理方法及装置 技术领域
本发明涉及通信领域，具体而言，涉及一种信息处理方法及装置。
背景技术
如图1所示，目前的数字通信系统一般分为三个部分：发送端、信道和接收端。发送端通常包括信源、信道编码器和调制器(或写入单元)等部分；接收端通常包括解调器(或读出单元)、信道译码器和信宿；发送端和接收端之间存在信道(或存储介质)，并且信道中存在噪声源。而信道编码链路(包括信道编译码、调制解调等)是整个数字通信物理层的关键，其决定了数字通信系统底层传输的有效性和可靠性。
信道编码器的主要作用是抗击信道中存在的各种各样噪声和干扰对有用信号的影响，它通过人为地增加一些冗余信息，使得系统具有自动纠正差错的能力，从而保证信息传输的可靠性。在相关技术中已有多种信道编码，例如，低密度奇偶校验(Low Density Parity Check，LDPC)码、turbo码、卷积码、RS码等。经过各种实践和理论证明，LDPC码是在加性高斯白噪声(Additive White Gaussian Noise，AWGN)信道下性能最为优良的信道编码，性能非常靠近香农极限。LDPC码是一种可以用非常稀疏的奇偶校验矩阵或者二分图定义的线性分组码，正是利用它的校验矩阵的稀疏性，才能实现低复杂度的编译码，从而使得LDPC走向实用化。
从性能上来看，LDPC码性能非常优异。但是从硬件复杂度来看，由于LDPC译码是一个迭代译码过程，所以LDPC码的硬件复杂度非常高。而且LDPC码是一种线性分组码，所以在码率和码长设计上也缺少一定的灵活性。在802.16e标准中，为了让码长和码率支持一定的灵活性，码长支持19种，码率支持4种(1/2、2/3、3/4和5/6)，需要采用6个校验矩阵来实现；在802.11ad标准中，采用了4种校验矩阵，提供4种固定码长但不同码率的编码方案；在802.11n/ac标准中，采用了12种校验矩阵，提供4种码率、3种码长的编码方案。在以上的标准中，每个标准都是需要多个LDPC码的校验矩阵以支持灵活性需要。由于每种码率对应的校验矩阵基本不相关联，因此，接收译码端要么需要多个译码器对应译码各个码率，或者采用一个译码器来支持这么多的校验矩阵要求，不管是哪种方法，都需要非常高的硬件成本，而且不便于对该译码器中某些单元进行特定优化。
针对相关技术中LDPC码编译码系统的硬件复杂度高及灵活性差的问题，目前尚未提出有效的解决方案。
发明内容
针对相关技术中LDPC码编译码系统的硬件复杂度高及灵活性差的问题，本发明提供了一种信息处理方法及装置，以至少解决上述问题。
根据本发明的一个方面，提供了一种信息处理装置，包括：一个或多个存储器，设置为存储一个基础奇偶校验矩阵组的参数；一个或多个处理器，设置为使用所述基础奇偶校验矩阵组Hb对待编码的信息比特进行编码或对待译码的数据进行译码，其中，所述基础奇偶校验矩阵组Hb中，除了Hbj0以外其他的基础奇偶校验矩阵中基础奇偶校验矩阵Hbj1的至少50％的短4环与Hbj0中短4环相同，j0为0到L-1之间的一个固定正整数，L为所述基础奇偶校验矩阵组中包含的基础奇偶校验矩阵的数量，j1＝0，1，...，j0-1，j0+1，...，L-1。
优选地，所述基础奇偶校验矩阵组中每个基础奇偶校验矩阵的维度为Mb×Nb，列数Nb为固定取值nb0，行数Mb取值mbi，每个行数mbi对应一个码率ri，其中，ri是0至1之间的实数，i＝0，1，2，......，L-1，mbi为大于0的整数，nb0为大于0的整数。
优选地，所述短4环为基础奇偶校验矩阵中第c列和第d列与第a行和第b行交叉的4个非-1元素[hac，hbc，hbd，had]，其中，a、b、c和d是任意大于等于0且小于nb0的整数，且c<d，a<b。
优选地，所述基础奇偶校验矩阵组中，除了Hbj0以外其他的基础奇偶校验矩阵Hbj1中第c列中非-1元素从上往下顺序所构成集合Scj1为Hbj0相同列上非-1元素从上往下顺序构成的集合Scj0的子集；其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，最大列重MaxW是指所述基础校验矩阵组中所有基础校验矩阵的所有列的重量最大列的列重量，MaxW为正整数，c为大于等于0且小于nb0的整数。
优选地，所述集合Scj1中的所有元素从上往下顺序与这些元素在所述集合Scj0中的从上往下顺序完全相同。
优选地，所述基础奇偶校验矩阵组中各个基础奇偶校验矩阵Hbi＝[Abi Bbi]，其中，矩阵Abi为系统位部分矩阵，维度为Mb×(Nb-Mb)，矩阵Bbi为校验位部分矩阵， 维度为Mb×Mb，矩阵Abi和矩阵Bbi的行数相等以及行重大于等于1，矩阵Bbi为严格下三角形结构矩阵或者双对角形结构矩阵。
优选地，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的不同行上的-1元素个数相等或者相差小于等于2。
优选地，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的系统位部分矩阵的每列上不存在连续2个或者连续3个以上的-1元素。
优选地，所述基础奇偶校验矩阵组中的系统位部分矩阵的每行上不存在连续2个或者连续3个以上的-1元素。
优选地，所述nb0的取值包括：8，16，24，32，40或48。
优选地，所述Hbj1中的短4环与所述Hbj0中短4环相同包括：所述Hbj1中的短4环与所述Hbj0中短4环的各个对应的元素的取值相等，且在Hbj1一行上的短4环的2个元素与Hbj0一行的上短4环的2个元素一一对应相等，在Hbj1一列上的短4环的2个元素与Hbj0一列的上短4环的2个元素一一对应相等。
优选地，所述基础奇偶校验矩阵组的每个基础奇偶校验矩阵中能够构成4环的任意4个元素[hac，hbc，hbd，had]，满足不等式(hac-hbc+hbd-had)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c和d是任意大于等于0且小于nb0的整数，且a≠b，c≠d。
优选地，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中能够构成6环的任意6个元素
Figure PCTCN2014085949-appb-000001
，满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf＝＝0的数量最少，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
优选地，所述基础奇偶校验矩阵组中，矩阵行数j小于最大列重MaxW的基础奇偶校验矩阵等于所述Hbj0后j行所构成的矩阵，其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，其中，MaxW和j为正整数。
优选地，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成4环的任意4个元素[hai，hbi，hbj，haj]中，有1个或者多个元素属于列重为2的，且满足不等式(hai-hbi+hbj-haj)％zf≠0；以及，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成短6环的任意6个元素
Figure PCTCN2014085949-appb-000002
中，有1个或者多个元素属于列 重为2的，且满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
优选地，ri取值为[1/2，5/8，3/4，13/16]，i＝0，1，2，3，对应码率为r0＝1/2的基础奇偶校验矩阵Hb0中，构成4环的任意4个元素[hai，hbi，hbj，haj]，都满足不等式(hai-hbi+hbj-haj)％zf≠0，且所述基础奇偶校验矩阵Hb0中，构成短6环的任意6个元素
Figure PCTCN2014085949-appb-000003
，都满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
优选地，所述一个或多个处理器通过以下方式对待编码的信息比特进行编码或对待译码的数据进行译码：确定所述待编码的信息比特的分组或者所述待译码的数据的分组，根据所述待编码的信息比特的分组或者所述待译码的数据的分组从所述基础奇偶校验矩阵组中选择一个基础奇偶校验矩阵，基于选择的所述基础奇偶校验矩阵对所述待编码的信息比特的分组进行编码或者对所述待译码的数据的分组进行译码。
根据本发明的另一个方面，提供了一种信息处理方法，包括：获取待编码的信息比特或待译码的数据；使用预先设定的基础奇偶校验矩阵组Hb对所述待编码的信息比特进行编码或对所述待译码的数据进行译码，其中，所述基础奇偶校验矩阵组Hb中，除了Hbj0以外其他的基础奇偶校验矩阵中基础奇偶校验矩阵Hbj1的至少50％的短4环与Hbj0中短4环相同，j0为0到L-1之间的一个固定正整数，L为所述基础奇偶校验矩阵组中包含的基础奇偶校验矩阵的数量，j1＝0，1，...，j0-1，j0+1，...，L-1。
优选地，所述基础奇偶校验矩阵组中每个基础奇偶校验矩阵的维度为Mb×Nb，列数Nb为固定取值nb0，行数Mb取值mbi，每个行数mbi对应一个码率ri，其中，ri是一个大于0的实数，i＝0，1，2，......，L-1，mbi为大于0的整数，nb0为大于0的整数。
优选地，所述短4环为基础奇偶校验矩阵中第c列和第d列与第a行和第b行交叉的4个非-1元素[hac，hbc，hbd，had]，其中，a、b、c和d是任意大于等于0且小于nb0的整数，且c<d，a<b。
优选地，所述基础奇偶校验矩阵组中，除了Hbj0以外其他的基础奇偶校验矩阵Hbj1中第c列中非-1元素从上往下顺序所构成集合Scj1为Hbj0相同列上非-1元素从上往下顺序构成的集合Scj0的子集；其中，所述Hbj0为矩阵行数等于最大列重MaxW的 基础奇偶校验矩阵，最大列重MaxW是指所述基础校验矩阵组中所有基础校验矩阵的所有列的重量最大列的列重量，MaxW为正整数，c为大于等于0且小于nb0的整数。
优选地，所述集合Scj1中的所有元素从上往下顺序与这些元素在所述集合Scj0中的从上往下顺序完全相同。
优选地，所述基础奇偶校验矩阵组中各个基础奇偶校验矩阵Hbi＝[Abi Bbi]，其中，矩阵Abi为系统位部分矩阵，维度为Mb×(Nb-Mb)，矩阵Bbi为校验位部分矩阵，维度为Mb×Mb，矩阵Abi和矩阵Bbi的行数相等以及行重大于等于1，矩阵Bbi为严格下三角形结构矩阵或者双对角形结构矩阵。
优选地，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的不同行上的-1元素个数相等或者相差小于等于2。
优选地，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的系统位部分矩阵的每列上不存在连续2个或者连续3个以上的-1元素。
优选地，所述基础奇偶校验矩阵组中的系统位部分矩阵的每行上不存在连续2个或者连续3个以上的-1元素。
优选地，所述nb0的取值包括8，16，24，32，40或48。
优选地，所述Hbj1中的短4环与所述Hbj0中短4环相同包括：所述Hbj1中的短4环与所述Hbj0中短4环的各个对应的元素的取值相等，且在Hbj1一行上的短4环的2个元素与Hbj0一行的上短4环的2个元素一一对应相等，在Hbj1一列上的短4环的2个元素与Hbj0一列的上短4环的2个元素一一对应相等。
优选地，所述基础奇偶校验矩阵组的每个基础奇偶校验矩阵中能够构成4环的任意4个元素[hac，hbc，hbd，had]，满足不等式(hac-hbc+hbd-had)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c和d是任意大于等于0且小于nb0的整数，且a≠b，c≠d。
优选地，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中能够构成6环的任意6个元素
Figure PCTCN2014085949-appb-000004
，满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf＝＝0的数量最少，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
优选地，所述基础奇偶校验矩阵组中，矩阵行数j小于最大列重MaxW的基础奇偶校验矩阵等于所述Hbj0后j行所构成的矩阵，其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，其中，MaxW和j为正整数。
优选地，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成4环的任意4个元素[hai，hbi，hbj，haj]中，有1个或者多个元素属于列重为2的，且满足不等式(hai-hbi+hbj-haj)％zf≠0；而且，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成短6环的任意6个元素
Figure PCTCN2014085949-appb-000005
中，有1个或者多个元素属于列重为2的，都能满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
优选地，ri取值为[1/2，5/8，3/4，13/16]，i＝0，1，2，3，对应码率为r0＝1/2的基础奇偶校验矩阵Hb0中，构成4环的任意4个元素[hai，hbi，hbj，haj]，都满足不等式(hai-hbi+hbj-haj)％zf≠0；而且，所述基础奇偶校验矩阵Hb0中，构成短6环的任意6个元素
Figure PCTCN2014085949-appb-000006
，都满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
优选地，使用预先设定的基础奇偶校验矩阵组Hb对所述待编码的信息比特进行编码或对所述待译码的数据进行译码包括：确定所述待编码的信息比特的分组或者所述待译码的数据的分组，根据所述待编码的信息比特的分组或者所述待译码的数据的分组从所述基础奇偶校验矩阵组中选择一个基础奇偶校验矩阵，基于选择的所述基础奇偶校验矩阵对所述待编码的信息比特的分组进行编码或者对所述待译码的数据的分组进行译码。
通过本发明，采用LDPC编译码时，多个码率对应的多个校验矩阵相关联，从而可以使用同一个编码器或译码器进行编码或译码，解决了硬件复杂度高及灵活性差的问题，降低了硬件复杂度提高了编译码的灵活性。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据相关技术的数字通信系统的结构示意图；
图2是根据本发明实施例的信息处理装置的结构示意图；
图3是本发明实施例中的一种简单的通信链路模型框图；
图4为根据本发明实施例的LDPC码的编码框图；
图5为根据本发明实施例的LDPC码的译码框图；
图6为根据本发明实施例的信息处理方法的流程图；
图7为根据本发明实施例的LDPC码的编码流程图；
图8为根据本发明实施例的LDPC码的译码流程图；
图9为根据本发明实施例的LDPC码的基础奇偶校验矩阵的结构；
图10为本发明实施例中LDPC码二分图中出现4环的示意图；
图11为本发明实施例中LDPC码二分图中出现6环的示意图；
图12为本发明实施例中LDPC码基础奇偶校验矩阵中出现4环的示意图；
图13为本发明实施例中LDPC码基础奇偶校验矩阵中出现6环的示意图；
图14为本发明实施例中由基础矩阵、扩展因子和置换矩阵唯一确定的LDPC码扩展校验矩阵示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
根据本发明实施例，提供了一种信息处理装置。
图2为根据本发明实施例的信息处理装置的结构示意图，如图2所示，根据本发明实施例的信息处理装置主要包括：一个或多个存储器20，设置为存储一个基础奇偶校验矩阵组的参数；一个或多个处理器22，设置为使用所述基础奇偶校验矩阵组Hb对待编码的信息比特进行编码或对待译码的数据进行译码，其中，所述基础奇偶校验矩阵组Hb中，除了Hbj0以外其他的基础奇偶校验矩阵中基础奇偶校验矩阵Hbj1的至少50％的短4环与Hbj0中短4环相同，j0为0到L-1之间的一个固定正整数，L为所述基础奇偶校验矩阵组中包含的基础奇偶校验矩阵的数量，j1＝0，1，...，j0-1，j0+1，...，L-1。
在本发明实施例的一个可选实施方式中，所述基础奇偶校验矩阵组中每个基础奇偶校验矩阵的维度为Mb×Nb，列数Nb为固定取值nb0，行数Mb取值mbi，每个行数mbi对应一个码率ri，其中，ri为0至1之间的实数，i＝0，1，2，......，L-1，mbi为大于0的整数，nb0为大于0的整数。
在本发明实施例的一个可选实施例方式中，所述短4环为基础奇偶校验矩阵中第c列和第d列与第a行和第b行交叉的4个非-1元素[hac，hbc，hbd，had]，其中，a、b、c和d是任意大于等于0且小于nb0的整数，且c<d，a<b。
在本发明实施例的一个可选实施例方式中，所述基础奇偶校验矩阵组中，除了Hbj0以外其他的基础奇偶校验矩阵Hbj1中第c列中非-1元素从上往下顺序所构成集合Scj1为Hbj0相同列上非-1元素从上往下顺序构成的集合Scj0的子集；其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，最大列重MaxW是指所述基础校验矩阵组中所有基础校验矩阵的所有列的重量最大列的列重量，j0是0和L-1之间一个整数，MaxW为正整数，c为大于等于0且小于nb0的整数。其中，列重量是指基础校验矩阵中一列中非-1元素个数。
在本发明实施例的一个可选实施例方式中，所述集合Scj1中的所有元素从上往下顺序与这些元素在所述集合Scj0中的从上往下顺序完全相同。
在本发明实施例的一个可选实施例方式中，所述基础奇偶校验矩阵组中各个基础奇偶校验矩阵Hbi＝[Abi Bbi]，其中，矩阵Abi为系统位部分矩阵，维度为Mb×(Nb-Mb)，矩阵Bbi为校验位部分矩阵，维度为Mb×Mb，矩阵Abi和矩阵Bbi的行数相等以及行重大于等于1，矩阵Bbi为严格下三角形结构矩阵或者双对角形结构矩阵。
在本发明实施例的一个可选实施例方式中，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的不同行上的-1元素个数相等或者相差小于等于2。
在本发明实施例的一个可选实施例方式中，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的系统位部分矩阵的每列上不存在连续2个或者连续3个以上的-1元素。
在本发明实施例的一个可选实施例方式中，所述基础奇偶校验矩阵组中的系统位部分矩阵的每行上不存在连续2个或者连续3个以上的-1元素。
在本发明实施例的一个可选实施例方式中，所述nb0的取值包括但不限于：8，16，24，32，40或48。
在本发明实施例的一个可选实施例方式中，所述Hbj1中的短4环与所述Hbj0中短4环相同包括：所述Hbj1中的短4环与所述Hbj0中短4环的各个对应的元素的取值相等，且在Hbj1一行上的短4环的2个元素与Hbj0一行的上短4环的2个元素一一对应相等，在Hbj1一列上的短4环的2个元素与Hbj0一列的上短4环的2个元素一一对应相等。即矩阵Hbj1短4环的4个元素与矩阵Hbj0短4环的4个元素是相等的；在Hbj1中在一行上短4环的2个元素，则该2元素在Hbj0中也是在一行上；在Hbj1中在一列上短4环的2个元素，则该2元素在Hbj0中也是在一列上。
在本发明实施例的一个可选实施例方式中，所述基础奇偶校验矩阵组的每个基础奇偶校验矩阵中能够构成4环的任意4个元素[hac，hbc，hbd，had]，满足不等式(hac-hbc+hbd-had)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c和d是任意大于等于0且小于nb0的整数，且a≠b，c≠d。其中，扩展因子zf为置换矩阵(一般单位阵)的维度，取值必须大于0。
在本发明实施例的一个可选实施例方式中，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中能够构成6环的任意6个元素[hai，hbi，hbj，hcj，hck，hak]，满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf＝＝0的数量最少，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
在本发明实施例的一个可选实施例方式中，所述基础奇偶校验矩阵组中，矩阵行数j小于最大列重MaxW的基础奇偶校验矩阵等于所述Hbj0后j行所构成的矩阵，其 中，Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，其中，MaxW和j为正整数。
在本发明实施例的一个可选实施方式中，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成4环的任意4个元素[hai，hbi，hbj，haj]中，有1个或者多个元素属于列重为2的，且满足不等式(hai-hbi+hbj-haj)％zf≠0；以及，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成短6环的任意6个元素
Figure PCTCN2014085949-appb-000007
中，有1个或者多个元素属于列重为2的，且满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
在本发明实施例的一个可选实施方式中，ri取值为[1/2，5/8，3/4，13/16]，i＝0，1，2，3，对应码率为r0＝1/2的基础奇偶校验矩阵Hb0中，构成4环的任意4个元素[hai，hbi，hbj，haj]，都满足不等式(hai-hbi+hbj-haj)％zf≠0，且所述基础奇偶校验矩阵Hb0中，构成短6环的任意6个元素
Figure PCTCN2014085949-appb-000008
，都满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
在本发明实施例的一个可选实施例方式中，所述一个或多个处理器通过以下方式对待编码的信息比特进行编码或对待译码的数据进行译码：确定所述待编码的信息比特的分组或者所述待译码的数据的分组，根据所述待编码的信息比特的分组或者所述待译码的数据的分组从所述基础奇偶校验矩阵组中选择一个基础奇偶校验矩阵，基于选择的所述基础奇偶校验矩阵对所述待编码的信息比特的分组进行编码或者对所述待译码的数据的分组进行译码。
通过本发明实施例提供的上述信息处理装置，LDPC码可以支持的码率分别为R0，R1，…，RL-1，所对应的基础奇偶校验矩阵分别为Hb0，Hb1，…，Hb(L-1)，基础奇偶校验矩阵的行数分别为M0，M1，…，ML-1，列数都为Nb，L是所要构造的码率数目，且各个基础奇偶校验矩阵，从而可以使用同一个编码器或译码器进行编码或译码，解决了硬件复杂度高及灵活性差的问题，降低了硬件复杂度提高了编译码的灵活性。
根据本发明实施例，还提供了一种信息处理方法，该方法可以通过上述信息处理装置实现。
图3为根据本发明实施例的信息处理方法的流程图，如图3所示，主要包括以下步骤S302-步骤S304。
步骤S302，获取待编码的信息比特或待译码的数据。
步骤304，使用预先设定的基础奇偶校验矩阵组Hb对所述待编码的信息比特进行编码或对所述待译码的数据进行译码，其中，所述基础奇偶校验矩阵组Hb中，除了Hbj0以外其他的基础奇偶校验矩阵中基础奇偶校验矩阵Hbj1的至少50％的短4环与Hbj0中短4环相同，j0为0到L-1之间的一个固定正整数，L为所述基础奇偶校验矩阵组中包含的基础奇偶校验矩阵的数量，j1＝0，1，...，j0-1，j0+1，...，L-1。
在一个可选实施方案中，所述基础奇偶校验矩阵组中每个基础奇偶校验矩阵的维度为Mb×Nb，列数Nb为固定取值nb0，行数Mb取值mbi，每个行数mbi对应一个码率ri，其中，ri是一个大于0的实数，i＝0，1，2，......，L-1，mbi为大于0的整数，nb0为大于0的整数。
其中，所述短4环为基础奇偶校验矩阵中第c列和第d列与第a行和第b行交叉的4个非-1元素[hac，hbc，hbd，had]，其中，a、b、c和d是任意大于等于0且小于nb0的整数，且c<d，a<b。
在一个可选实施方案中，所述基础奇偶校验矩阵组中，除了Hbj0以外其他的基础奇偶校验矩阵Hbj1中第c列中非-1元素从上往下顺序所构成集合Scj1为Hbj0相同列上非-1元素从上往下顺序构成的集合Scj0的子集；其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，最大列重MaxW是指所述基础校验矩阵组中所有基础校验矩阵的所有列的重量最大列的列重量，MaxW为正整数，c为大于等于0且小于nb0的整数。
在一个可选实施方案中，所述集合Scj1中的所有元素从上往下顺序与这些元素在所述集合Scj0中的从上往下顺序完全相同。
在一个可选实施方案中，所述基础奇偶校验矩阵组中各个基础奇偶校验矩阵Hbi＝[Abi Bbi]，其中，矩阵Abi为系统位部分矩阵，维度为Mb×(Nb-Mb)，矩阵Bbi为校验位部分矩阵，维度为Mb×Mb，矩阵Abi和矩阵Bbi的行数相等以及行重大于等于1，矩阵Bbi为严格下三角形结构矩阵或者双对角形结构矩阵。
在一个可选实施方案中，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的不同行上的-1元素个数相等或者相差小于等于2。
在一个可选实施方案中，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的系统位部分矩阵的每列上不存在连续2个或者连续3个以上的-1元素。
在一个可选实施方案中，所述基础奇偶校验矩阵组中的系统位部分矩阵的每行上不存在连续2个或者连续3个以上的-1元素。
在一个可选实施方案中，所述nb0的取值包括但不限于8，16，24，32，40或48。
在一个可选实施方案中，所述Hbj1中的短4环与所述Hbj0中短4环相同包括：所述Hbj1中的短4环与所述Hbj0中短4环的各个对应的元素的取值相等，且在Hbj1一行上的短4环的2个元素与Hbj0一行的上短4环的2个元素一一对应相等，在Hbj1一列上的短4环的2个元素与Hbj0一列的上短4环的2个元素一一对应相等。。
在一个可选实施方案中，所述基础奇偶校验矩阵组的每个基础奇偶校验矩阵中能够构成4环的任意4个元素[hac，hbc，hbd，had]，满足不等式(hac-hbc+hbc-had)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c和d是任意大于等于0且小于nb0的整数，且a≠b，c≠d。
在一个可选实施方案中，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中能够构成6环的任意6个元素
Figure PCTCN2014085949-appb-000009
，满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf＝＝0的数量最少，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b，i≠j≠k。
在一个可选实施方案中，所述基础奇偶校验矩阵组中，矩阵行数j小于最大列重MaxW的基础奇偶校验矩阵等于所述Hbj0后j行所构成的矩阵，其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，其中，MaxW和j为正整数。
在一个可选实施方案中，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成4环的任意4个元素[hac，hbc，hbd，had]中，有1个或者多个元素属于列重为2的，且满足不等式(hac-hbc+hbc-had)％zf≠0；而且，所述基础奇偶校验矩阵组的所有基础 奇偶校验矩阵中，构成短6环的任意6个元素
Figure PCTCN2014085949-appb-000010
中，有1个或者多个元素属于列重为2的，都能满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0。
在一个可选实施方案中，ri取值为[1/2，5/8，3/4，13/16]，i＝0，1，2，3，对应码率为r0＝1/2的基础奇偶校验矩阵Hb0中，构成4环的任意4个元素[hac，hbc，hbd，had]，都满足不等式(hac-hbc+hbc-had)％zf≠0；而且，所述基础奇偶校验矩阵Hb0中，构成短6环的任意6个元素
Figure PCTCN2014085949-appb-000011
，都满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0。
在一个可选实施方案中，使用预先设定的基础奇偶校验矩阵组Hb对所述待编码的信息比特进行编码或对所述待译码的数据进行译码包括：确定所述待编码的信息比特的分组或者所述待译码的数据的分组，根据所述待编码的信息比特的分组或者所述待译码的数据的分组从所述基础奇偶校验矩阵组中选择一个基础奇偶校验矩阵，基于选择的所述基础奇偶校验矩阵对所述待编码的信息比特的分组进行编码或者对所述待译码的数据的分组进行译码。
为了进一步理解本发明实施例所提供的方案，下面以图4所示的简单通信链路模型为例进行描述。
图4中示意了一个简单的通信链路模型，信息可以从A端传输到B端，亦可从B端传输到A端。A和B可以是基站、中转节点、接入节点、终端设备等设备类型中的一种或多种，或者同一种设备类型的多个设备。A和B之间可以在任意时刻相互传输数据，也可以只在条件允许的情况下进行数据通信。本发明实施例所提供的上述信息处理装置可以应用在A到B和B到A的任意数据传输。
在图4所示的通信链路中，可以看出在A端可以配备有t1根发射天线和r1根接收天线，在B端也可以配备有t2根发射天线和r2根接收天线，一般的，A端的t1≥1和r1≥1，而且B端的t2≥1和r2≥1。所述的A端天线可以是固定的也可以是可移动的；同时，所述的B端天线可以是固定的也可以是可移动的。
在图4所示的通信链路中，A与B之间的通信还需要信道来传输，该信道可以是无线信道，如微波通信、电磁波通信、声波通信、光通信等，也可以是有线信道，如光纤通信，线缆等，也可以是各种存储媒介。
为了简单起见，在此以从A端的一台设备a1发送数据信息到B端的某一台设备b1为例进行说明。这时，a1需要由处理器从信源读取数据并进行分组，然后对该数据分组进行处理(编码、调制等)，然后通过发射天线发射出去；B端的某一台设备b1 的处理器需从接收天线处接收信号，并进行处理，得到原始数据。反之，从B端到A端的数据传输原理与如上所述是一样的。
在以上所述的链路通信或系统通信中，可以采用LDPC编码来增加数据传输的可靠性。LDPC码是一种可以用非常稀疏的奇偶校验矩阵或者二分图定义的线性分组码。
A端或者B端的编码器如图5所示，译码器如图6所示。编/译码器中的处理器主要负责各种逻辑运算。如图5所示，编码器中的处理器主要负责对数据进行处理，即从信源处获取待发送的信息，对信源的信息比特进行分组，然后与存储器相配合，对信息比特分组进行LDPC编码，然后进行调制并发射出去。如图6所示，译码器的处理器从天线处获取信息，然后配置存储器对信息进行LDPC译码，然后执行信息合并后传输给信宿；而编/译码器的存储器主要负责存储A端或者B端的所需要的所有数据和程序代码。即存储器主要负责存储LDPC码基础奇偶校验矩阵信息，以及其他数据信息的存储。
如图5所示，LDPC编码器对信息比特进行分组，得到一个1×k的信息比特分组，这里用a表示。通过编码器，将该a信息比特块进行编码得到1×n的码字比特块，用x表示。LDPC码的基础矩阵为Hb，对应的扩展校验矩阵为H。
其中，LDPC码的扩展校验矩阵H是由基础矩阵Hb、扩展因子zf和置换矩阵唯一确定，置换矩阵一般是一个zf×zf的单位阵。如果基础奇偶校验矩阵中某一个元素值hij＝-1，则该地方的置换矩阵为一个zf×zf的全0方阵，如果hij≠-1，则该地方为置换矩阵的循环右移hij得到的矩阵。例如，在图14所示的具体实例中，通过基础矩阵Hb(2×3)、扩展因子zf(＝3)和置换矩阵(3×3单位阵)确定的LDPC码的扩展校验矩阵H。
LDPC码作为一种线性分组码，对应的扩展校验矩阵为H，对于每个码字x，都能满足关系式
H×xT＝0T
其中，这里的“0”是一个全0向量，由于所有的运算都是在二元域上进行的，因此在这里的所有加减运算都是异或运算，相乘运算都是与运算。根据该关系式，可以把扩展校验矩阵H分成两个部分：系统位部分矩阵A和校验位部分矩阵B，如图9所示，即，
H＝[A B]
同时也把LDPC码字x分为系统位部分矢量a和校验位部分矢量b，如下
x＝[a b]
则可以得到如下关系式：
A×aT＝B×bT
可以看出，只要把校验部分的b求出即可。由于可以对B矩阵进行特殊处理，如把其设计成下三角形或者双下三角形结构等，从而可以通过简单地计算，得到校验位部分b。然后将信息部分a和校验部分合并c＝[a b]，即得到LDPC码字x。
图7所示的编码器对应的LDPC编码流程图，如图7所示。如图7所示，在本实施例中的LDPC编码主要包括以下步骤1-步骤4。
步骤1，对待编码的数据进行分块，得到一个1×k的信息比特分组，即a。
步骤2，计算v＝A×a。
步骤3，计算b＝(B)-1×a，得到校验部分。
步骤4，将信息部分a和校验部分合并c＝[a b]，即得到LDPC码字x。
在LDPC译码器中，同时也需要两个模块：处理器(CPU)和存储器。处理器主要负责各种逻辑运算，存储器主要负责存储LDPC码基础奇偶校验矩阵信息，以及存储其他译码数据信息。LDPC译码器如图6所示。
在LDPC译码方法有多种，如概率域BP译码算法，对数域BP译码算法和分层最小和译码算法等。概率域BP译码算法性能最好，但是缺点在于由于其涉及到大量乘法运算，运算量非常大，从而所需的硬件成本非常高，并且数值的动态范围大稳定性不好，所以一般在实际应用中不会使用。相对于概率域BP译码算法，对数域BP译码算法减少了很多计算单元，但还是需要很多乘法运算，所需的硬件成本也不少。分层最小和译码算法将对数域BP译码算法的关键计算(log运算和乘法运算)单元转化成求最小值和次最小值，需要的硬件资源大量减少，性能会有一小点损失，但可以减少很多硬件资源。所以，在实际应用比较多的是分层最小和译码算法。
不管是哪种译码方法，都是需要进行迭代译码，译码模块主要分为两个部分：校验节点更新模块和变量节点更新模块。LDPC译码器如图6所示，相应的LDPC译码流程图如图8所示。如图8所示，LDPC译码主要包括以下步骤1-步骤4。
步骤1，进行初始化。
步骤2，执行校验节点更新。
步骤3，执行变量节点更新。
步骤4，判断H×s＝＝0|Iter＞max，如果是，则结束，否则，返回步骤2。
在LDPC编码和译码中，为了保证得到性能优异、吞吐量高、灵活性高和复杂度低等特性，与设计的LDPC码校验矩阵是息息相关的。反之，如果设计LDPC校验矩阵不好，将使得其性能下降，同时也可能会使得复杂度和灵活性受到影响。因此，如何获得合适的LDPC编码校验矩阵是非常关键的。
为了更好理解本发明思想，下面介绍一下LDPC码基础奇偶校验矩阵出现短4环和短6环形成girth的情况。
基础奇偶校验矩阵中，短4环出现girth＝4的充分必要条件是：在基础矩阵中，任意能构成4环的4个元素[hai，hbi，hbj，haj]满足
(hai-hbi+hbj-haj)％zf＝＝0。
其中，zf为扩展因子，则该4个位置的元素之间会导致girth＝4的出现，在二分图中表现如图10所示。这样由于信息只在这4个节点(2个变量节点+2个校验节点)之间交换传递，在进行多次迭代后由于不断地交换的信息大部分来自自身反馈的信息，外部信息较少，则最终码字性能就会变差。具体在基础奇偶校验矩阵中这些元素体现如图12所示，在二分图中如图10所示。所以，在进行LDPC码基础奇偶校验矩阵设计时，必须让以上等式不成立，即
(hai-hbi+hbj-haj)％zf≠0
基础奇偶校验矩阵中，短6环出现girth＝6的充分必要条件是：在基础矩阵中，任意能构成6环的6个元素[hai，hbi，hbj，hcj，hck，hak]满足
(hai-hbi+hbj-hcj+hck-hak)％zf＝0
zf为扩展因子，则该6个位置的元素之间会导致girth＝6的出现，在二分图中表现如图9所示。这样由于信息大部分在这6个节点(3个变量节点+3个校验节点)之间交换传递，由于与girth＝4同样原因交换的外来信息较少，其最终码字性能也会变差(不过比存在短4环的要好一些)。具体在校验矩阵中这些元素体现如图13所示，在二分 图中如图11所示。所以，在进行LDPC码基础奇偶校验矩阵设计时，必须让以上等式不成立(或者尽量少出现)，即
(hai-hbi+hbj-hcj+hck-hak)％zf≠0
按照本发明实施例所提供的多种码率LDPC码基础奇偶校验矩阵构建方法，下面通过具体实施例进行分析。在该编码/译码器的具体实施例中都包含两个部分：处理器和存储器。处理器主要负责进行各种逻辑运算，存储器主要负责各种信息的存储，特别是LDPC编码和译码中非常重要的基础奇偶校验矩阵的存储。
在该具体实施例中，所有的码率分别为R0＝1/2，R1＝5/8，R2＝3/4，R3＝13/16，所对应的基础奇偶校验矩阵分别为Hb0，Hb1，Hb2，Hb3，列数都为16列。对应各个码率的基础奇偶校验矩阵行数分别为(hai-hbi+hbj-hcj+hck-hak)％zf≠0。根据以上的发明内容，在此提供这4个基础奇偶校验矩阵，扩展因子zf＝256，基本行重为4。
码率为R0＝13/16的基础奇偶校验矩阵Hb0：
Figure PCTCN2014085949-appb-000012
码率为R1＝3/4的基础奇偶校验矩阵Hb1：
Figure PCTCN2014085949-appb-000013
码率为R2＝5/8的基础奇偶校验矩阵Hb2：
Figure PCTCN2014085949-appb-000014
Figure PCTCN2014085949-appb-000015
码率为R3＝1/2的基础奇偶校验矩阵Hb3：
Figure PCTCN2014085949-appb-000016
从以上所有基础奇偶校验矩阵中，可以看出具有如下特性：
(1).从以上提供的所有码率的校验矩阵来看，所有基础奇偶校验矩阵的列数完全一样，都是16列，而且对应的校验位部分矩阵都是严格下三角形结构。
(2).最大列重MaxW为4，对于矩阵行数都大于等于最大列重4的其他基础奇偶校验矩阵中，它们相同列上的非-1元素所构成的集合相等。
(3).最大列重MaxW为4，码率为R1＝3/4的基础奇偶校验矩阵Hb1的行数也等于4，所以其他基础奇偶校验矩阵行数小于最大列重4的基础奇偶校验矩阵，如码率为R0＝13/16的基础奇偶校验矩阵Hb0，矩阵行数为3，则该基础奇偶校验矩阵等于Hb1的后3行所构成的矩阵。
(4).在同一个基础奇偶校验矩阵的系统位部分矩阵中，不同行上的-1元素个数都相等，如Hb0和Hb1，或者相差值最大也只在2以内(包括2)，如Hb2和Hb3。
(5).在同一个基础奇偶校验矩阵的系统位部分矩阵中，在同一行上不存在连续2个或者连续3个以上的-1元素。
(6).在同一个基础奇偶校验矩阵的系统位部分矩阵中，在同一列上不存在连续2个或者连续3个以上的-1元素。
(7).从以上提供的所有码率的校验矩阵来看，除了Hb1以外其他的每个基础奇偶校验矩阵中构成的所有短4环中有50％以上与Hb1所构成的短4环是相同的。
(8).所述的基础奇偶校验矩阵中，可以构成短4环的任意4个元素[hai，hbi，hbj，haj]，都能满足不等式(hai-hbi+hbj-haj)％zf≠0。其中，％为求余运算符，zf为扩展因子，zf＝256。
(9).所述的基础奇偶校验矩阵中，可以构成短6环的任意6个元素[hai，hbi，hbj，hcj，hck，hak]，都能满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，或者满足该不等式的短6环的数目最大。其中，％为求余运算符，zf为扩展因子，zf＝256。
从以上的描述中，通过本发明实施例提供的技术方案，所有码率的基础奇偶校验矩阵相互关系，具有以下有益效果：
(1).所有码率的基础奇偶校验矩阵可以保持矩阵短环特性基本一致。所以，在其中一个基础奇偶校验矩阵(在本实施例中码率为R1＝3/4)的性能非常优异时，就可以保证其他码率的基础奇偶校验矩阵的性能也会很好。
(2).所有码率的基础奇偶校验矩阵的形式基本一致，所以可以完全共用同一个译码器，从而可以大量减少硬件资源。不需要浪费大量资源来对每个码率(校验矩阵)做一个译码器或者对一个译码器做出巨大调整以支持其他码率。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明实施例中，采用LDPC编译码时，多个码率对应的多个校验矩阵相关联，从而可以使用同一个编码器或译码器进行编码或译码，解决了硬件复杂度高及灵活性差的问题，降低了硬件复杂度提高了编译码的灵活性。具有工业实用性。

Claims (34)

  1. [根据细则26改正27.10.2014]　
    一种信息处理装置，包括：
    一个或多个存储器，设置为存储一个基础奇偶校验矩阵组的参数；
    一个或多个处理器，设置为使用所述基础奇偶校验矩阵组Hb对待编码的信息比特进行编码或对待译码的数据进行译码，其中，所述基础奇偶校验矩阵组Hb中，除了Hbj0以外其他的基础奇偶校验矩阵中基础奇偶校验矩阵Hbj1的至少50％的短4环与Hbj0中短4环相同，j0为0到L-1之间的一个固定正整数，L为所述基础奇偶校验矩阵组中包含的基础奇偶校验矩阵的数量，j1＝0，1，...，j0-1，j0+1，...，L-1。
  2. [根据细则26改正27.10.2014]　
    根据权利要求1所述的装置，其中，所述基础奇偶校验矩阵组中每个基础奇偶校验矩阵的维度为Mb×Nb，列数Nb为固定取值nb0，行数Mb取值mbi，每个行数mbi对应一个码率ri，其中，ri是0至1之间的实数，i＝0，1，2，......，L-1，mbi为大于0的整数，nb0为大于0的整数。
  3. [根据细则26改正27.10.2014]　
    根据权利要求2所述的装置，其中，所述短4环为基础奇偶校验矩阵中第c列和第d列与第a行和第b行交叉的4个非-1元素[hac，hbc，hbd，had]，其中，a、b、c和d是任意大于等于0且小于nb0的整数，且c<d，a<b。
  4. [根据细则26改正27.10.2014]　
    根据权利要求2所述的装置，其中，所述基础奇偶校验矩阵组中，除了Hbj0以外其他的基础奇偶校验矩阵Hbj1中第c列中非-1元素从上往下顺序所构成集合Scj1为Hbj0相同列上非-1元素从上往下顺序构成的集合Scj0的子集；其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，最大列重MaxW是指所述基础校验矩阵组中所有基础校验矩阵的所有列的重量最大列的列重量，MaxW为正整数，c为大于等于0且小于nb0的整数。
  5. [根据细则26改正27.10.2014]　
    根据权利要求4所述的装置，其中，所述集合Scj1中的所有元素从上往下顺序与这些元素在所述集合Scj0中的从上往下顺序完全相同。
  6. [根据细则26改正27.10.2014]　
    根据权利要求2所述的装置，其中，所述基础奇偶校验矩阵组中各个基础奇偶校验矩阵Hbi＝[Abi Bbi]，其中，矩阵Abi为系统位部分矩阵，维度为Mb×(Nb-Mb)，矩阵Bbi为校验位部分矩阵，维度为Mb×Mb，矩阵Abi和矩 阵Bbi的行数相等以及行重大于等于1，矩阵Bbi为严格下三角形结构矩阵或者双对角形结构矩阵。
  7. [根据细则26改正27.10.2014]　
    根据权利要求6所述的装置，其中，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的不同行上的-1元素个数相等或者相差小于等于2。
  8. [根据细则26改正27.10.2014]　
    根据权利要求6所述的装置，其中，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的系统位部分矩阵的每列上不存在连续2个或者连续3个以上的-1元素。
  9. [根据细则26改正27.10.2014]　
    根据权利要求6所述的装置，其中，所述基础奇偶校验矩阵组中的系统位部分矩阵的每行上不存在连续2个或者连续3个以上的-1元素。
  10. [根据细则26改正27.10.2014]　
    根据权利要求2至9中任一项所述的装置，其中，所述nb0的取值包括：8，16，24，32，40或48。
  11. [根据细则26改正27.10.2014]　
    根据权利要求1所述的装置，其中，所述Hbj1中的短4环与所述Hbj0中短4环相同包括：所述Hbj1中的短4环与所述Hbj0中短4环的各个对应的元素的取值相等，且在Hbj1一行上的短4环的2个元素与Hbj0一行的上短4环的2个元素一一对应相等，在Hbj1一列上的短4环的2个元素与Hbj0一列的上短4环的2个元素一一对应相等。
  12. [根据细则26改正27.10.2014]　
    根据权利要求1所述的装置，其中，所述基础奇偶校验矩阵组的每个基础奇偶校验矩阵中能够构成4环的任意4个元素[hac，hbc，hbd，had]，满足不等式(hac-hbc+hbd-had)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c和d是任意大于等于0且小于nb0的整数，且a≠b，c≠d。
  13. [根据细则26改正27.10.2014]　
    根据权利要求1所述的装置，其中，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中能够构成6环的任意6个元素
    Figure PCTCN2014085949-appb-100001
    ，满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf＝＝0的数量最少，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
  14. [根据细则26改正27.10.2014]　
    根据权利要求1所述的装置，其中，所述基础奇偶校验矩阵组中，矩阵行数j小于最大列重MaxW的基础奇偶校验矩阵等于所述Hbj0后j行所构成的矩阵， 其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，其中，MaxW和j为正整数。
  15. [根据细则26改正27.10.2014]　
    根据权利要求1所述的装置，其中，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成4环的任意4个元素[hai，hbi，hbj，haj]中，有1个或者多个元素属于列重为2的，且满足不等式(hai-hbi+hbj-haj)％zf≠0；以及，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成短6环的任意6个元素
    Figure PCTCN2014085949-appb-100002
    中，有1个或者多个元素属于列重为2的，且满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
  16. [根据细则26改正27.10.2014]　
    根据权利要求2所述的装置，其中，ri取值为[1/2，5/8，3/4，13/16]，i＝0，1，2，3，对应码率为r0＝1/2的基础奇偶校验矩阵Hb0中，构成4环的任意4个元素[hai，hbi，hbj，haj]，都满足不等式(hai-hbi+hbj-haj)％zf≠0，且所述基础奇偶校验矩阵Hb0中，构成短6环的任意6个元素
    Figure PCTCN2014085949-appb-100003
    ，都满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
  17. [根据细则26改正27.10.2014]　
    根据权利要求1所述的装置，其中，所述一个或多个处理器通过以下方式对待编码的信息比特进行编码或对待译码的数据进行译码：确定所述待编码的信息比特的分组或者所述待译码的数据的分组，根据所述待编码的信息比特的分组或者所述待译码的数据的分组从所述基础奇偶校验矩阵组中选择一个基础奇偶校验矩阵，基于选择的所述基础奇偶校验矩阵对所述待编码的信息比特的分组进行编码或者对所述待译码的数据的分组进行译码。
  18. [根据细则26改正27.10.2014]　
    一种信息处理方法，包括：
    获取待编码的信息比特或待译码的数据；
    使用预先设定的基础奇偶校验矩阵组Hb对所述待编码的信息比特进行编码或对所述待译码的数据进行译码，其中，所述基础奇偶校验矩阵组Hb中，除了Hbj0以外其他的基础奇偶校验矩阵中基础奇偶校验矩阵Hbj1的至少50％的短4环与Hbj0中短4环相同，j0为0到L-1之间的一个固定正整数，L为所述基础奇偶校验矩阵组中包含的基础奇偶校验矩阵的数量，j1＝0，1，...，j0-1，j0+1，...，L-1。
  19. [根据细则26改正27.10.2014]　
    根据权利要求18所述的方法，其中，所述基础奇偶校验矩阵组中每个基础奇偶校验矩阵的维度为Mb×Nb，列数Nb为固定取值nb0，行数Mb取值mbi，每个行数mbi对应一个码率ri，其中，ri是一个大于0的实数，i＝0，1，2，......，L-1，mbi为大于0的整数，nb0为大于0的整数。
  20. [根据细则26改正27.10.2014]　
    根据权利要求19所述的方法，其中，所述短4环为基础奇偶校验矩阵中第c列和第d列与第a行和第b行交叉的4个非-1元素[hac，hbc，hbd，had]，其中，a、b、c和d是任意大于等于0且小于nb0的整数，且c<d，a<b。
  21. [根据细则26改正27.10.2014]　
    根据权利要求19所述的方法，其中，所述基础奇偶校验矩阵组中，除了Hbj0以外其他的基础奇偶校验矩阵Hbj1中第c列中非-1元素从上往下顺序所构成集合Scj1为Hbj0相同列上非-1元素从上往下顺序构成的集合Scj0的子集；其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，最大列重MaxW是指所述基础校验矩阵组中所有基础校验矩阵的所有列的重量最大列的列重量，MaxW为正整数，c为大于等于0且小于nb0的整数。
  22. [根据细则26改正27.10.2014]　
    根据权利要求21所述的方法，其中，所述集合Scj1中的所有元素从上往下顺序与这些元素在所述集合Scj0中的从上往下顺序完全相同。
  23. [根据细则26改正27.10.2014]　
    根据权利要求19所述的方法，其中，所述基础奇偶校验矩阵组中各个基础奇偶校验矩阵Hbi＝[Abi Bbi]，其中，矩阵Abi为系统位部分矩阵，维度为Mb×(Nb-Mb)，矩阵Bbi为校验位部分矩阵，维度为Mb×Mb，矩阵Abi和矩阵Bbi的行数相等以及行重大于等于1，矩阵Bbi为严格下三角形结构矩阵或者双对角形结构矩阵。
  24. [根据细则26改正27.10.2014]　
    根据权利要求23所述的方法，其中，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的不同行上的-1元素个数相等或者相差小于等于2。
  25. [根据细则26改正27.10.2014]　
    根据权利要求23所述的方法，其中，所述基础奇偶校验矩阵组中的各个基础奇偶校验矩阵的系统位部分矩阵的系统位部分矩阵的每列上不存在连续2个或者连续3个以上的-1元素。
  26. [根据细则26改正27.10.2014]　
    根据权利要求23所述的方法，其中，所述基础奇偶校验矩阵组中的系统位部分矩阵的每行上不存在连续2个或者连续3个以上的-1元素。
  27. [根据细则26改正27.10.2014]　
    根据权利要求19至26中任一项所述的方法，其中，所述nb0的取值包括8，16，24，32，40或48。
  28. [根据细则26改正27.10.2014]　
    根据权利要求18所述的方法，其中，所述Hbj1中的短4环与所述Hbj0中短4环相同包括：所述Hbj1中的短4环与所述Hbj0中短4环的各个对应的元素的取值相等，且在Hbj1一行上的短4环的2个元素与Hbj0一行的上短4环的2个元素一一对应相等，在Hbj1一列上的短4环的2个元素与Hbj0一列的上短4环的2个元素一一对应相等。
  29. [根据细则26改正27.10.2014]　
    根据权利要求18所述的方法，其中，所述基础奇偶校验矩阵组的每个基础奇偶校验矩阵中能够构成4环的任意4个元素[hac，hbc，hbd，had]，满足不等式(hac-hbc+hbd-had)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c和d是任意大于等于0且小于nb0的整数，且a≠b，c≠d。
  30. [根据细则26改正27.10.2014]　
    根据权利要求18所述的方法，其中，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中能够构成6环的任意6个元素
    Figure PCTCN2014085949-appb-100004
    ，满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf＝＝0的数量最少，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
  31. [根据细则26改正27.10.2014]　
    根据权利要求18所述的方法，其中，所述基础奇偶校验矩阵组中，矩阵行数j小于最大列重MaxW的基础奇偶校验矩阵等于所述Hbj0后j行所构成的矩阵，其中，所述Hbj0为矩阵行数等于最大列重MaxW的基础奇偶校验矩阵，其中，MaxW和j为正整数。
  32. [根据细则26改正27.10.2014]　
    根据权利要求18所述的方法，其中，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成4环的任意4个元素[hai，hbi，hbj，haj]中，有1个或者多个元素属于列重为2的，且满足不等式(hai-hbi+hbj-haj)％zf≠0；而且，所述基础奇偶校验矩阵组的所有基础奇偶校验矩阵中，构成短6环的任意6个元素
    Figure PCTCN2014085949-appb-100005
    中，有1个或者多个元素属于列重为2的，都能满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
  33. [根据细则26改正27.10.2014]　
    根据权利要求19所述的方法，其中，ri取值为[1/2，5/8，3/4，13/16]，i＝0，1，2，3，对应码率为r0＝1/2的基础奇偶校验矩阵Hb0中，构成4环的任意4个元素[hai，hbi，hbj，haj]，都满足不等式(hai-hbi+hbj-haj)％zf≠0；而且，所述基础奇偶校验矩阵Hb0中，构成短6环的任意6个元素
    Figure PCTCN2014085949-appb-100006
    ，都满足不等式(hai-hbi+hbj-hcj+hck-hak)％zf≠0，其中，％为求余运算符，zf为扩展因子，a、b、c，i，j和k是任意大于等于0且小于nb0的整数，且a≠b≠c，i≠j≠k。
  34. [根据细则26改正27.10.2014]　
    根据权利要求18所述的方法，其中，使用预先设定的基础奇偶校验矩阵组Hb对所述待编码的信息比特进行编码或对所述待译码的数据进行译码包括：确定所述待编码的信息比特的分组或者所述待译码的数据的分组，根据所述待编码的信息比特的分组或者所述待译码的数据的分组从所述基础奇偶校验矩阵组中选择一个基础奇偶校验矩阵，基于选择的所述基础奇偶校验矩阵对所述待编码的信息比特的分组进行编码或者对所述待译码的数据的分组进行译码。
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