WO2015161626A1 - 开关控制方法、开关控制电路及调控器、存储介质 - Google Patents

开关控制方法、开关控制电路及调控器、存储介质 Download PDF

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Publication number
WO2015161626A1
WO2015161626A1 PCT/CN2014/088154 CN2014088154W WO2015161626A1 WO 2015161626 A1 WO2015161626 A1 WO 2015161626A1 CN 2014088154 W CN2014088154 W CN 2014088154W WO 2015161626 A1 WO2015161626 A1 WO 2015161626A1
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Prior art keywords
switch
error amplifier
control circuit
state
compensation network
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PCT/CN2014/088154
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English (en)
French (fr)
Inventor
韦东
耿玮生
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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Priority to US15/306,340 priority Critical patent/US9935595B2/en
Priority to EP14889847.1A priority patent/EP3136575B1/en
Publication of WO2015161626A1 publication Critical patent/WO2015161626A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from DC input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/78—A comparator being used in a controlling circuit of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2178—Class D power amplifiers; Switching amplifiers using more than one switch or switching amplifier in parallel or in series

Definitions

  • the invention relates to circuit control technology, in particular to a switch control method, a switch control circuit and a controller, and a computer storage medium.
  • the error amplifier is the core part of the voltage control loop in the buck converter circuit (BUCK).
  • the operation of the error amplifier will directly affect the stability of the entire BUCK circuit.
  • Figure 1 is a schematic diagram of the structure of the BUCK circuit. As shown in Figure 1, in the voltage control loop, the inverting input of the error amplifier is connected to the output sampling voltage V FB , and the non-inverting input is connected to the reference voltage V REF ; when the BUCK circuit is working In the Pulse Width Modulation (PWM) mode, the output voltage V c of the error amplifier and the sawtooth wave are compared with each other, and the state of the set end of the SR latch is affected by the PWM voltage comparator, thereby changing the switching duty ratio. The purpose and ultimately to stabilize the output voltage of the circuit.
  • PWM Pulse Width Modulation
  • the circuit switches between the Pulse Skip Modulation (PSM) mode and the PWM mode through the PWM_PSM control circuit.
  • PSM Pulse Skip Modulation
  • the error amplifier is turned off by the enable signal PWM_PSM, so that the output of the error amplifier is set to a very low level, so that when the BUCK circuit is switched from the PSM mode to the PWM mode, due to the switch Too small a duty cycle causes the output voltage of the circuit to continue to drop, causing large and undetermined ripple.
  • the circuit output voltage will generate a large ripple when the BUCK circuit switches from the PSM mode to the PWM mode under light load conditions. .
  • embodiments of the present invention are expected to provide a switch control method based on an error amplifier, a switch control circuit, a governor, and a computer storage medium, which can effectively control errors when the PSM mode and the PWM mode are switched to each other.
  • the amplifier and compensation network effectively reduces the ripple of the circuit's output voltage.
  • An embodiment of the present invention provides a switch control circuit including an error amplifier, a compensation network, and a control circuit; the compensation network is connected to an output end of the error amplifier;
  • the control circuit includes first to fifth switches configured to control an operating state of the error amplifier and the compensation network by controlling opening and closing states of the first to fifth switches.
  • the control circuit controls the opening and closing states of the first switch to the fifth switch by using the same enable signal;
  • the compensation network includes a resistor and a capacitor;
  • the control circuit controls the first switch and the second switch to be in a closed state, and when the third switch to the fifth switch are in an open state, the error amplifier operates in an amplified state, and the compensation network operates in a mutual resistance and capacitance Compensation status
  • the control circuit controls the first switch and the second switch to be in an open state, and when the third switch to the fifth switch are in a closed state, the error amplifier operates in a voltage follow state, and the compensation network operates in a self-compensation state of the capacitor .
  • the first to fifth switches employ one of a P-channel metal oxide semiconductor PMOS, an N-channel metal oxide semiconductor NMOS, and a triode.
  • the first switch to the fifth switch use PMOS or NMOS
  • the first switch has a source and a drain, one pole is connected to the output sampling voltage, the other pole is connected to the inverting input terminal of the error amplifier
  • the second switch has a source and a drain, one pole is connected to the reference voltage, and the other pole is connected to the reference voltage, and the other pole Connecting the non-inverting input terminal of the error amplifier
  • the source and the drain of the third switch one pole connected to the circuit output voltage, the other pole connected to the non-inverting input terminal of the error amplifier
  • the source and the drain of the fourth switch One pole is connected to the inverting input terminal of the error amplifier, and the other pole is connected to the output end of the error amplifier
  • the source and the drain of the fifth switch are respectively connected to both ends of the resistor in the compensation network.
  • the emitter and the collector of the first switch when the first switch and the fifth switch use a triode, the emitter and the collector of the first switch have one pole connected to the output sampling voltage and the other pole connected to the inverting input end of the error amplifier;
  • the emitter and the collector of the second switch have one pole connected to the reference voltage and the other pole connected to the non-inverting input terminal of the error amplifier;
  • the emitter and the collector of the third switch one pole connected to the circuit output voltage, and the other pole connected a non-inverting input terminal of the error amplifier;
  • an emitter and a collector of the fourth switch one pole connected to the inverting input terminal of the error amplifier, and the other pole connected to the output end of the error amplifier;
  • the emitter and the set of the fifth switch The electrodes are respectively connected to both ends of the resistor in the compensation network.
  • the embodiment of the invention further provides a switch control method, the method comprising: controlling the working state of the error amplifier and the compensation network by controlling the opening and closing states of the first switch to the fifth switch.
  • control circuit controls the working states of the error amplifier and the compensation network by controlling the opening and closing states of the first switch to the fifth switch, including:
  • the embodiment of the invention further provides a controller, including the above switch control circuit.
  • the present invention also provides a computer storage medium having stored therein computer executable instructions for performing the aforementioned switch control method.
  • the switch control method, the switch control circuit, the controller, and the computer storage medium provided by the embodiments of the present invention control the operation of the error amplifier and the compensation network by controlling the opening and closing states of the first switch to the fifth switch by the control circuit.
  • a state in which the first switch and the second switch are in a closed state, and the third switch to the fifth switch are in an open state the error amplifier is operated in an amplified state, and the compensation network operates in a mutual compensation state of the resistor and the capacitor;
  • the first switch and the second switch are in an open state, and the third switch to the fifth switch are in a closed state, the error amplifier is operated in a voltage follow state, and the compensation network operates in a capacitance self-compensation state.
  • the BUCK circuit can effectively control the output of the error amplifier when the PSM mode and the PWM mode are switched to each other, thereby reducing the ripple of the circuit output voltage.
  • the embodiment of the present invention can effectively improve the stability of the error amplifier and the BUCK circuit by controlling the compensation network connected to the output end of the error amplifier.
  • the switch control circuit has a simple implementation scheme. Convenient and easy to implement.
  • FIG. 1 is a schematic structural diagram of a BUCK circuit
  • FIG. 2 is a waveform diagram of a circuit output voltage and a part of an operating point when an error amplifier operates in a conventional BUCK circuit
  • FIG. 3 is a schematic structural diagram of a switch control circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a switch control circuit in an actual application according to an embodiment of the present invention.
  • FIG. 5 is a waveform diagram of a circuit output voltage of a BUCK circuit and a corresponding operation of five switches thereof during light load according to an embodiment of the present invention
  • FIG. 6 is a circuit output voltage of an error amplifier operating in a BUCK circuit according to an embodiment of the present invention. And the waveform diagram of some working points.
  • the operating state of the error amplifier and the compensation network is controlled by the control circuit by controlling the opening and closing states of the first to fifth switches.
  • control circuit controls the first switch and the second switch to be in a closed state by using the same enable signal, and the third switch to the fifth switch are in an off state, so that the error amplifier operates in an amplified state, and the compensation network Working in a mutual compensation state of the resistor and the capacitor;
  • control circuit controls the first switch and the second switch to be in an off state by the same enable signal, and the third switch to the fifth switch are in a closed state, so that the error The amplifier operates in a voltage follow state, and the compensation network operates in a self-compensating state of the capacitor.
  • the same enable signal is the enable signal PWM_PSM in the BUCK circuit shown in FIG. 1.
  • the switch control circuit includes: an error amplifier 10, a compensation network 11, and a control circuit 12;
  • the compensation network 11 is connected to an output end of the error amplifier 10;
  • the control circuit 12 includes first to fifth switches configured to control an operating state of the error amplifier 10 and the compensation network 11 by controlling opening and closing states of the first to fifth switches.
  • control circuit controls the opening and closing states of the first switch to the fifth switch by using the same enable signal;
  • compensation network includes a resistor and a capacitor.
  • the compensation network 11 includes a resistor R 1 and a capacitor C 1
  • the control circuit 12 includes a first switch K 1 , a second switch K 2 , and a third switch K 3 , The fourth switch K 4 and the fifth switch K 5 ; the control circuit 12 controls the open/close state of the first switch K 1 to the fifth switch K 5 by the same enable signal to control the error amplifier (EA) 10 and the compensation The working state of the network 11.
  • EA error amplifier
  • the control circuit 12 controls the first switch K 1 and the second switch K 2 to be in a closed state by the same enable signal, and the third switch K 3 , the fourth switch K 4 , and the fifth switch K 5 are in a closed state.
  • the open state causes the EA 10 to operate in an amplified state, the compensation network 11 operates in a mutual compensation state of a resistor and a capacitor;
  • the control circuit 12 controls the first switch K 1 and the second switch by the same enable signal K 2 is in an open state, and the third switch K 3 , the fourth switch K 4 , and the fifth switch K 5 are in a closed state such that the EA 10 operates in a voltage following state, and the compensation network 11 operates in a capacitor self Compensation status.
  • the first to fifth switches K 1 to K5 are PMOS (Positive Channel Metal Oxide Semiconductor), N-channel MOS (Negative Channel Metal Oxide Semiconductor), and One of the triodes.
  • the first switch K 1 to K 5 of the fifth switch a PMOS or the NMOS
  • EA 10 is further connected An inverting input terminal; a source and a drain of the second switch K 2 , one pole connected to the reference voltage V REF , the other pole connected to the non-inverting input terminal of the EA 10 ; the source and the drain of the third switch K 3 a pole connected to the circuit output voltage V out , the other pole connected to the non-inverting input of the error amplifier 10; the fourth switch K 4 has a source and a drain, one pole connected to the inverting input of the EA 10, and the other The pole is connected to the output of the EA 10; the source and the drain of the fifth switch K 5 are respectively connected to both ends of the resistor R 1 in the compensation network 11.
  • the emitter and the collector of the first switch K 1 are connected to the output sampling voltage V FB and the other end is connected to the reverse phase of the EA 10 An input end; an emitter and a collector of the second switch K 2 , one pole connected to the reference voltage V REF and the other pole connected to the non-inverting input end of the EA 10 ; the emitter and the collector of the third switch K 3 , One pole is connected to the circuit output voltage V out , the other pole is connected to the non-inverting input of the EA 10 , the emitter and collector of the fourth switch K 4 are connected to the inverting input of the EA 10 and the other is connected to the EA
  • the output terminal of the fifth switch K 5 is connected to the two ends of the resistor R 1 in the compensation network 11 respectively.
  • the enable signal may be inverted by adding an inverter, thereby ensuring the first switch K 1 and The second switch K 2 is simultaneously turned on or off, the third switch K 3 to the fifth switch K 5 are simultaneously turned on or off, and the first switch K 1 and the second switch K 2 and the third switch K 3 to the fifth switch are simultaneously turned on or off.
  • the K 5 is turned on or off just the opposite.
  • the BUCK circuit switches between the PWM mode and the PSM mode. In these two different modes, the operating state of the EA 10 and the compensation network 11 are different.
  • the first switch K 1 and the second switch K 2 are controlled to be turned off by the same enable signal PWM_PSM, and the third switch K 3 , the fourth switch K 4 , and the fifth switch K 5 are closed.
  • the compensation network 11 operates in the self-compensation state of the capacitor, and the resistor R 1 is short-circuited by the fifth switch K 5 .
  • the capacitor C 1 acts as a self-compensating capacitor of the error amplifier, which can improve the closed-loop stability of the error amplifier.
  • the first switch K 1 and the second switch K 2 are controlled to be closed by the PWM_PSM, and the third switch K 3 , the fourth switch K 4 , and the fifth switch K 5 are turned off, the error amplifier Working in the open loop mode, the difference between the reference voltage V REF and the output sampling voltage V FB is amplified, and the output voltage V c is compared with the sawtooth wave to achieve the purpose of changing the switching duty ratio.
  • the compensation network 11 operates in the mutual compensation state of the resistor and the capacitor, and the interaction of the resistor R 1 and the capacitor C 1 introduces a zero point at 1/R 1 C 1 to compensate the LC pole of the BUCK circuit to obtain sufficient Large phase margin, which improves the stability of the entire BUCK circuit.
  • the embodiment of the present invention further provides a switch control method, the method comprising: controlling the operation of the error amplifier and the compensation network by controlling an open/close state of the first switch to the fifth switch status.
  • the control circuit controls the first switch and the second switch to be in a closed state by using the same enable signal, and the third switch, the fourth switch, and the fifth switch are in an off state, so that the error amplifier operates in an amplified state.
  • the compensation network operates in a mutual compensation state of the resistor and the capacitor; the control circuit controls the first switch and the second switch to be in an off state by the same enable signal, the third switch, the fourth switch, and the fifth The switch is in a closed state, the error amplifier is operated in a voltage follow state, and the compensation network operates in a self-compensating state of the capacitor.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the foregoing switch control method.
  • the embodiment of the present invention further provides a governor, including a switch control circuit, a specific composition structure of the switch control circuit, and functions performed by each component structure, and the functions shown in FIG. 3 and FIG.
  • the composition is the same as the completed function.
  • FIG. 5 is a waveform diagram of a circuit output voltage of a BUCK circuit and a corresponding operation of five switches thereof during light load according to an embodiment of the present invention.
  • the circuit section AB output voltage V out rises, the inductor current decreases, when the zero-crossing detection circuit detects zero-crossing signal, i.e., the reverse current comparator
  • the output value of the device V ZCD becomes high level, then the circuit is switched to the PSM operating mode, at which time the circuit output voltage V out rises to point B; at this time, the first switch K 1 and the first switch are controlled by the enable signal PWM_PSM
  • the second switch K 2 is turned off, and the third switch K 3 , the fourth switch K 4 , and the fifth switch K 5 are closed, and as a result, the non-inverting input terminal of the EA is directly connected to the circuit output voltage V out , and the inverting input terminal of the EA Connected to the output
  • the error amplifier has a unity gain follower amplifier circuit changes the output voltage, since the circuit operation time in PSM mode long enough , so it is fully able to meet the response time of the error amplifier. At this time, other modules in the PWM mode, such as the SR latch, the voltage comparator, etc., are all off.
  • the first switch K 1 and the second switch K 2 are controlled to be closed by the enable signal PWM_PSM, and the third switch K 3 , the fourth switch K 4 , and the fifth switch K 5 are disconnected, the EA
  • the difference between the output sampling voltage V FB and the reference voltage V REF is amplified, and the obtained output voltage V c is compared with the sawtooth wave to achieve the purpose of changing the duty ratio of the switching tube.
  • the preset PWM_PSM controls the BUCK circuit to enter the PWM mode when the level is low
  • the first switch to the fifth switch K 1 - K 5 are simultaneously turned on when the same enable signal is low.
  • any input/output device having a switching logic or a combination circuit is within the scope of the present invention.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may employ hardware embodiments, software embodiments, or junctions. In the form of an embodiment of the software and hardware aspects. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the switch control method, the switch control circuit, the governor, and the computer storage medium provided by the embodiment of the invention are controlled by the control circuit by controlling the opening and closing states of the first switch to the fifth switch.
  • the working state of the error amplifier and the compensation network; the first switch and the second switch are in a closed state, and the third switch to the fifth switch are in an open state, so that the error amplifier operates in an amplified state, and the compensation network works In the mutual compensation state of the resistor and the capacitor; the first switch and the second switch are in an open state, and the third switch to the fifth switch are in a closed state, so that the error amplifier operates in a voltage follow state, and the compensation network operates in Capacitor self-compensation state.
  • the BUCK circuit can effectively control the output of the error amplifier when the PSM mode and the PWM mode are switched to each other, thereby reducing the ripple of the circuit output voltage.

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Abstract

一种开关控制电路，包括误差放大器、补偿网络、以及控制电路；其中，所述补偿网络连接于所述误差放大器的输出端；所述控制电路包括第一开关至第五开关，用于通过控制第一开关至第五开关的开闭状态来控制所述误差放大器和补偿网络的工作状态。还提供了一种开关控制方法、包括有前述开关控制电路的调控器及计算机存储介质。

Description

开关控制方法、开关控制电路及调控器、存储介质 技术领域
本发明涉及电路控制技术，尤其涉及一种开关控制方法、开关控制电路及调控器、计算机存储介质。
背景技术
误差放大器是降压式变换电路(BUCK)中电压控制环路的核心部分，误差放大器的工作方式将会直接影响整个BUCK电路的稳定性。图1为BUCK电路的组成结构示意图，如图1所示，在电压控制环路中，误差放大器的反相输入端连接输出采样电压VFB，同相输入端连接参考电压VREF；当BUCK电路工作在脉冲宽度调制(Pulse Width Modulation，PWM)模式时，误差放大器的输出电压Vc和锯齿波相互比较，通过PWM电压比较器来影响SR锁存器置位端的状态，从而达到改变开关占空比的目的，并最终来稳定电路的输出电压。
当BUCK电路处在轻载模式的情况下，电路会通过PWM_PSM控制电路在脉冲跳跃调制(Pulse Skip Modulation，PSM)模式和PWM模式之间相互切换。为了降低功耗，在PSM模式时，利用使能信号PWM_PSM将误差放大器关闭，使得误差放大器的输出端置为一个很低的电平，这样在BUCK电路从PSM模式切换到PWM模式时，由于开关占空比过小，会使得电路输出电压继续下降造成很大且无法确定的纹波。如果在PSM模式时，不关闭误差放大器，这样会使负载的输出电压逐渐降低，从而误差放大器的输出电压不断升高，这样在BUCK电路从PSM模式切换到PWM模式时，误差放大器的输出电平很高，PWM调整输出电压时会造成很大的纹波，如图2所示，为现有的BUCK电路中误差放大器工作时的电路输出电压Vout 及部分工作点的波形图。
因此，如果不能够很好的设计误差放大器和补偿网络的控制电路，则在轻载情况下，BUCK电路从PSM模式和PWM模式之间相互切换时，电路输出电压将会产生较大的纹波。
发明内容
为解决现有存在的技术问题，本发明实施例期望提供一种基于误差放大器的开关控制方法、开关控制电路及调控器、计算机存储介质，能在PSM模式和PWM模式相互切换时有效地控制误差放大器和补偿网络，有效地减小电路输出电压的纹波。
本发明的技术方案是这样实现的：
本发明实施例提供一种开关控制电路，包括误差放大器、补偿网络、以及控制电路；所述补偿网络连接于所述误差放大器的输出端；其中，
所述控制电路包括第一开关至第五开关，配置为通过控制第一开关至第五开关的开闭状态来控制所述误差放大器和补偿网络的工作状态。
上述方案中，所述控制电路通过同一使能信号控制第一开关至第五开关的开闭状态；所述补偿网络包括电阻和电容；
所述控制电路控制第一开关和第二开关处于闭合状态，且第三开关至第五开关处于断开状态时，所述误差放大器工作在放大状态，所述补偿网络工作在电阻和电容的互补偿状态；
所述控制电路控制第一开关和第二开关处于断开状态，且第三开关至第五开关处于闭合状态时，所述误差放大器工作在电压跟随状态，所述补偿网络工作在电容自补偿状态。
上述方案中，所述第一开关至第五开关采用P沟道金属氧化物半导体PMOS、N沟道金属氧化物半导体NMOS、以及三极管中的一种。
上述方案中，所述第一开关至第五开关采用PMOS或NMOS时，所述 第一开关的源极和漏极，一极连接输出采样电压，另一极连接误差放大器的反相输入端；所述第二开关的源极和漏极，一极连接参考电压，另一极连接误差放大器的同相输入端；所述第三开关的源极和漏极，一极连接电路输出电压，另一极连接误差放大器的同相输入端；所述第四开关的源极和漏极，一极连接误差放大器的反相输入端，另一极连接误差放大器的输出端；所述第五开关的源极和漏极分别连接所述补偿网络中电阻的两端。
上述方案中，所述第一开关和第五开关采用三极管时，所述第一开关的发射极和集电极，一极连接输出采样电压，另一极连接误差放大器的反相输入端；所述第二开关的发射极和集电极，一极连接参考电压，另一极连接误差放大器的同相输入端；所述第三开关的发射极和集电极，一极连接电路输出电压，另一极连接误差放大器的同相输入端；所述第四开关的发射极和集电极，一极连接误差放大器的反相输入端，另一极连接误差放大器的输出端；所述第五开关的发射极和集电极分别连接所述补偿网络中电阻的两端。
本发明实施例还提供一种开关控制方法，该方法包括：控制电路通过控制第一开关至第五开关的开闭状态，来控制误差放大器和补偿网络的工作状态。
上述方案中，所述控制电路通过控制第一开关至第五开关的开闭状态，来控制误差放大器和补偿网络的工作状态包括：
通过同一使能信号控制第一开关和第二开关处于闭合状态，且第三开关至第五开关处于断开状态，使所述误差放大器工作在放大状态，所述补偿网络工作在电阻和电容的互补偿状态；
通过所述同一使能信号控制第一开关和第二开关处于断开状态，且第三开关至第五开关处于闭合状态，使所述误差放大器工作在电压跟随状态，所述补偿网络工作在电容自补偿状态。
本发明实施例又提供一种调控器，包括上述开关控制电路。
本发明还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行前述的开关控制方法。
本发明实施例所提供的开关控制方法、开关控制电路及调控器、计算机存储介质，由控制电路通过控制第一开关至第五开关的开闭状态，来控制所述误差放大器和补偿网络的工作状态；第一开关和第二开关处于闭合状态，且第三开关至第五开关处于断开状态，使所述误差放大器工作在放大状态，所述补偿网络工作在电阻和电容的互补偿状态；第一开关和第二开关处于断开状态，且第三开关至第五开关处于闭合状态，使所述误差放大器工作在电压跟随状态，所述补偿网络工作在电容自补偿状态。如此，通过控制误差放大器和补偿网络，当负载较轻的情况下，BUCK电路在PSM模式和PWM模式相互切换时，能够有效控制误差放大器的输出，从而减小电路输出电压的纹波。
另外，本发明实施例通过控制连接于所述误差放大器的输出端的补偿网络，能有效地提高误差放大器和BUCK电路的稳定性；而且，本发明实施例中，所述开关控制电路，实现方案简单、方便，易于实现。
附图说明
图1为BUCK电路的组成结构示意图；
图2为现有的BUCK电路中误差放大器工作时的电路输出电压及部分工作点的波形图；
图3为本发明实施例开关控制电路的组成结构示意图；
图4为本发明实施例实际应用中开关控制电路的组成结构示意图；
图5为本发明实施例在轻载时BUCK电路的电路输出电压的波形图及其对应的五个开关的工作情况示意图；
图6为本发明实施例BUCK电路中误差放大器工作时的电路输出电压 及部分工作点的波形图。
具体实施方式
在本发明实施例中，由控制电路通过控制第一开关至第五开关的开闭状态，来控制所述误差放大器和补偿网络的工作状态。
具体的，所述控制电路通过同一使能信号控制第一开关和第二开关处于闭合状态，第三开关至第五开关处于断开状态，使所述误差放大器工作在放大状态，所述补偿网络工作在电阻和电容的互补偿状态；所述控制电路通过所述同一使能信号控制第一开关和第二开关处于断开状态，且第三开关至第五开关处于闭合状态，使所述误差放大器工作在电压跟随状态，所述补偿网络工作在电容自补偿状态。
这里，所述同一使能信号为图1所示的BUCK电路中的使能信号PWM_PSM。
下面结合附图及具体实施例对本发明再作进一步详细的说明。
图3为本发明实施例开关控制电路的组成结构示意图，如图3所示，所述开关控制电路包括：误差放大器10、补偿网络11、以及控制电路12；其中，
所述补偿网络11连接于所述误差放大器10的输出端；
所述控制电路12包括第一开关至第五开关，配置为通过控制第一开关至第五开关的开闭状态，来控制所述误差放大器10和补偿网络11的工作状态。
较佳的，所述控制电路通过同一使能信号控制第一开关至第五开关的开闭状态；所述补偿网络包括电阻和电容。
在实际应用中，如图4所示，所述补偿网络11包括电阻R1和电容C1，所述控制电路12包括第一开关K1、第二开关K2、第三开关K3、第四开关K4、第五开关K5；所述控制电路12通过同一使能信号控制第一开关K1至 第五开关K5的开闭状态，来控制所述误差放大器(EA)10和补偿网络11的工作状态。
具体地，所述控制电路12通过同一使能信号控制第一开关K1和第二开关K2处于闭合状态，且第三开关K3、第四开关K4、以及第五开关K5处于断开状态，使得所述EA 10工作在放大状态，所述补偿网11工作在电阻和电容的互补偿状态；所述控制电路12通过所述同一使能信号控制第一开关K1和第二开关K2处于断开状态，且第三开关K3、第四开关K4、以及第五开关K5处于闭合状态，使得所述EA 10工作在电压跟随状态，所述补偿网络11工作在电容自补偿状态。
这里，所述第一开关K1至第五开关K5采用P沟道金属氧化物半导体(PMOS，Positive channel Metal Oxide Semiconductor)、N沟道金属氧化物半导体(NMOS，Negative channel Metal Oxide Semiconductor)、以及三极管中的一种。
当所述第一开关K1至第五开关K5采用PMOS或NMOS时，所述第一开关K1的源极和漏极，一极连接输出采样电压VFB，另一极连接EA 10的反相输入端；所述第二开关K2的源极和漏极，一极连接参考电压VREF，另一极连接EA 10的同相输入端；所述第三开关K3的源极和漏极，一极连接电路输出电压Vout，另一极连接误差放大器10的同相输入端；所述第四开关K4的源极和漏极，一极连接EA 10的反相输入端，另一极连接EA 10的输出端；所述第五开关K5的源极和漏极分别连接所述补偿网络11中电阻R1的两端。
当所述第一开关K1至第五开关K5采用三极管时，所述第一开关K1的发射极和集电极，一极连接输出采样电压VFB，另一极连接EA 10的反相输入端；所述第二开关K2的发射极和集电极，一极连接参考电压VREF，另一极连接EA 10的同相输入端；所述第三开关K3的发射极和集电极，一极连 接电路输出电压Vout，另一极连接EA 10的同相输入端，所述第四开关K4的发射极和集电极，一极连接EA 10的反相输入端，另一极连接EA 10的输出端；所述第五开关K5的发射极和集电极分别连接所述补偿网络11中电阻R1的两端。
这里，需要说明的是，针对第一开关K1至第五开关K4所采用的器件类型的选择，可以通过增加反相器的方式将使能信号反相，从而保证第一开关K1和第二开关K2同时开启或者关断，第三开关K3至第五开关K5同时开启或者关断，以及第一开关K1和第二开关K2与第三开关K3至第五开关K5的开启或者关断状态刚好相反。
如此，在负载较轻时，为了提高电源效率，BUCK电路会在PWM模式和PSM模式相互切换。在这两种不同模式下，所述EA 10的工作状态和补偿网络11是不相同的。
当BUCK电路工作在PSM模式时，通过同一使能信号PWM_PSM控制第一开关K1和第二开关K2断开，而第三开关K3、第四开关K4、以及第五开关K5闭合，误差放大器工作在闭环模式下，其输出电压Vc跟随输入电压的变化，Vc＝Vout，即误差放大器作为单位增益运算放大器工作，其输出跟随输入电压的变化。同时，补偿网络11工作在电容自补偿状态，电阻R1被第五开关K5短路，此时电容C1作为误差放大器的自补偿电容，可以很好得提高误差放大器的闭环稳定性。
当BUCK电路切换为PWM模式工作时，通过PWM_PSM控制第一开关K1和第二开关K2闭合，而第三开关K3、第四开关K4、以及第五开关K5断开，误差放大器工作在开环模式下，将参考电压VREF与输出采样电压VFB的差值进行放大，其输出电压Vc与锯齿波比较，从而达到改变开关占空比的目的。同时，补偿网络11工作在电阻和电容的互补偿状态，电阻R1和电容C1的共同作用引入一个在1/R1C1处的零点，用以补偿BUCK电路 的LC极点，以得到足够大的相位裕度，从而提高整个BUCK电路的稳定性。
基于上述开关控制电路，本发明实施例还提供了一种开关控制方法，该方法包括：控制电路通过控制第一开关至第五开关的开闭状态，来控制所述误差放大器和补偿网络的工作状态。
具体的，所述控制电路通过同一使能信号控制第一开关和第二开关处于闭合状态，第三开关、第四开关、以及第五开关处于断开状态，使所述误差放大器工作在放大状态，所述补偿网络工作在电阻和电容的互补偿状态；所述控制电路通过所述同一使能信号控制第一开关和第二开关处于断开状态，第三开关、第四开关、以及第五开关处于闭合状态，使所述误差放大器工作在电压跟随状态，所述补偿网络工作在电容自补偿状态。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行前述的开关控制方法。
基于上述开关控制电路，本发明实施例又提供了一种调控器，包括开关控制电路，所述开关控制电路的具体组成结构、以及各组成结构完成的功能，与图3、图4所示的组成结构和所完成的功能相同。
图5为本发明实施例在轻载时BUCK电路的电路输出电压的波形图及其对应的五个开关的工作情况示意图。当BUCK电路切换到PWM时，结合图1和图4所示，在电路输出电压Vout上升的AB段，电感电流减小，当过零检测电路检测到过零信号时，即反向电流比较器的输出值VZCD变为高电平，则电路转入到PSM工作模式，此时电路输出电压Vout升高到B点；这时，通过使能信号PWM_PSM控制第一开关K1和第二开关K2断开，而第三开关K3、第四开关K4、以及第五开关K5闭合，结果使得EA的同相输入端与电路输出电压Vout直接相连，EA的反相输入端与输出端相连，误差 放大器工作在闭环模式下，误差放大器的输出电压Vc跟随输入电压的变化。
如图5所示，在电路输出电压Vout下降的BC段，BUCK电路工作在PSM模式下，误差放大器作为单位增益放大器一直跟随电路输出电压的变化，由于电路工作在PSM模式下的时间足够长，所以完全能够满足误差放大器的响应时间。此时PWM模式中的其它模块，如SR锁存器，电压比较器等都处于关闭状态。
当电路输出电压Vout降低到C点时，电路输出电压Vout同预置参考电压VSET进行比较，使得图1中所示开关管M1闭合，M2管断开，电感两端电流上升，BUCK电路从PSM模式切换到PWM模式工作。此时，EA的输出电压Vc仍等于电路输出电压Vout。当电路切换到PWM模式时，通过使能信号PWM_PSM控制第一开关K1和第二开关K2闭合，而第三开关K3、第四开关K4、以及第五开关K5断开，EA将输出采样电压VFB和参考电压VREF的差值进行放大，得到的输出电压Vc同锯齿波比较，达到改变开关管占空比的目的。
需要说明的是，预设PWM_PSM在低电平时控制BUCK电路转入PWM模式，则当所述第一开关至第五开关K1～K5同时采用在同一使能信号为低电平时才导通的PMOS或PNP型三极管的情况下，需要在第三开关、第四开关、以及第五开关所采用的PMOS或PNP型三极管上增加一个反向器。
另外，除上述所述五个开关所采用的器件外，任意输入/输出具有开关逻辑的器件或组合电路均属于本发明的保护范围。
本发明实施例BUCK电路中误差放大器工作时的电路输出电压及部分工作点的波形图，如图6所示。通过对比图2和图6中的电路输出电压波形，可以明显地看出电路输出电压的纹波得到了很好地改善。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结 合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例提供的开关控制方法、开关控制电路及调控器、计算机存储介质，由控制电路通过控制第一开关至第五开关的开闭状态，来控制 所述误差放大器和补偿网络的工作状态；第一开关和第二开关处于闭合状态，且第三开关至第五开关处于断开状态，使所述误差放大器工作在放大状态，所述补偿网络工作在电阻和电容的互补偿状态；第一开关和第二开关处于断开状态，且第三开关至第五开关处于闭合状态，使所述误差放大器工作在电压跟随状态，所述补偿网络工作在电容自补偿状态。如此，通过控制误差放大器和补偿网络，当负载较轻的情况下，BUCK电路在PSM模式和PWM模式相互切换时，能够有效控制误差放大器的输出，从而减小电路输出电压的纹波。

Claims (9)

  1. 一种开关控制电路，包括误差放大器、补偿网络、以及控制电路；所述补偿网络连接于所述误差放大器的输出端；其中，
    所述控制电路包括第一开关至第五开关，配置为通过控制第一开关至第五开关的开闭状态来控制所述误差放大器和补偿网络的工作状态。
  2. 根据权利要求1所述的开关控制电路，其中，所述控制电路通过同一使能信号控制第一开关至第五开关的开闭状态；所述补偿网络包括电阻和电容；
    所述控制电路控制第一开关和第二开关处于闭合状态，且第三开关至第五开关处于断开状态时，所述误差放大器工作在放大状态，所述补偿网络工作在电阻和电容的互补偿状态；
    所述控制电路控制第一开关和第二开关处于断开状态，且第三开关至第五开关处于闭合状态时，所述误差放大器工作在电压跟随状态，所述补偿网络工作在电容自补偿状态。
  3. 根据权利要求1或2所述的开关控制电路，其中，所述第一开关至第五开关采用P沟道金属氧化物半导体PMOS、N沟道金属氧化物半导体NMOS、以及三极管中的一种。
  4. 根据权利要求3所述的开关控制电路，其中，所述第一开关至第五开关采用PMOS或NMOS时，所述第一开关的源极和漏极，一极连接输出采样电压，另一极连接误差放大器的反相输入端；所述第二开关的源极和漏极，一极连接参考电压，另一极连接误差放大器的同相输入端；所述第三开关的源极和漏极，一极连接电路输出电压，另一极连接误差放大器的同相输入端；所述第四开关的源极和漏极，一极连接误差放大器的反相输入端，另一极连接误差放大器的输出端；所述第五开关的源极和漏极分别 连接所述补偿网络中电阻的两端。
  5. 根据权利要求3所述的开关控制电路，其中，所述第一开关和第五开关采用三极管时，所述第一开关的发射极和集电极，一极连接输出采样电压，另一极连接误差放大器的反相输入端；所述第二开关的发射极和集电极，一极连接参考电压，另一极连接误差放大器的同相输入端；所述第三开关的发射极和集电极，一极连接电路输出电压，另一极连接误差放大器的同相输入端；所述第四开关的发射极和集电极，一极连接误差放大器的反相输入端，另一极连接误差放大器的输出端；所述第五开关的发射极和集电极分别连接所述补偿网络中电阻的两端。
  6. 一种开关控制方法，所述方法包括：控制电路通过控制第一开关至第五开关的开闭状态，来控制误差放大器和补偿网络的工作状态。
  7. 根据权利要求6所述的方法，其中，所述控制电路通过控制第一开关至第五开关的开闭状态，来控制误差放大器和补偿网络的工作状态，包括：
    通过同一使能信号控制第一开关和第二开关处于闭合状态，且第三开关至第五开关处于断开状态，使所述误差放大器工作在放大状态，所述补偿网络工作在电阻和电容的互补偿状态；
    通过所述同一使能信号控制第一开关和第二开关处于断开状态，且第三开关至第五开关处于闭合状态，使所述误差放大器工作在电压跟随状态，所述补偿网络工作在电容自补偿状态。
  8. 一种调控器，包括：权利要求1至5任一项所述的开关控制电路。
  9. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求6或7所述的方法。
PCT/CN2014/088154 2014-04-25 2014-10-08 开关控制方法、开关控制电路及调控器、存储介质 Ceased WO2015161626A1 (zh)

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