WO2016015583A1 - 一种内存管理方法、装置以及内存控制器 - Google Patents

一种内存管理方法、装置以及内存控制器 Download PDF

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Publication number
WO2016015583A1
WO2016015583A1 PCT/CN2015/084798 CN2015084798W WO2016015583A1 WO 2016015583 A1 WO2016015583 A1 WO 2016015583A1 CN 2015084798 W CN2015084798 W CN 2015084798W WO 2016015583 A1 WO2016015583 A1 WO 2016015583A1
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Prior art keywords
virtual address
memory
page
page table
address
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PCT/CN2015/084798
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English (en)
French (fr)
Inventor
刘垚
陈荔城
崔泽汉
陈明宇
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to ES15828139T priority Critical patent/ES2704751T3/es
Priority to KR1020177003800A priority patent/KR101893966B1/ko
Priority to EP15828139.4A priority patent/EP3163451B1/en
Publication of WO2016015583A1 publication Critical patent/WO2016015583A1/zh
Priority to US15/415,344 priority patent/US10108553B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling

Definitions

  • the present invention relates to the field of computers, and in particular, to a memory management method, apparatus, and memory controller.
  • the memory controller is mainly responsible for data interaction between the CPU and the memory, and the real address management of the memory is implemented by the operating system.
  • the operating system allocates a virtual address to a process. If the virtual address is not cached in the Translation Look-aside Buffer (TLB), the memory management unit (MMU) does not find the virtual address.
  • TLB Translation Look-aside Buffer
  • MMU memory management unit
  • the page table entry causes a page fault and the CPU is trapped in the operating system kernel. After the page fault is interrupted, the operating system enters the interrupt service routine, performs on-site protection, pushes various status information of the current instruction such as the program counter onto the stack, and then checks the validity of the virtual address. If it is determined that the access is illegal, the operating system usually The process feeds back a signal or kills the process directly.
  • Embodiments of the present invention provide a memory management method, apparatus, and memory controller for improving memory management efficiency.
  • the present invention provides a memory management method, which is applied to a memory management device, and the memory management device is located in a memory controller, and the method includes:
  • the virtual address is determined to be legal, and when the virtual address is determined to be valid, a blank page is applied.
  • the method further includes: if the application for the blank page is successful, starting the memory reading and writing; if the application for the blank page fails, selecting the replacement page and providing the operating system to the operating system to the page Replace it.
  • determining whether the virtual address is legal specifically, determining whether the virtual address falls in the allocated virtual address space If yes, it is determined that the virtual address is legal; if not, it is found whether there is a virtual address in the virtual memory address VMA space, and if so, it is determined that the virtual address is legal.
  • the method further includes: counting each blank page of the cache The frequency of use within the preset time; when applying for a blank page, select the blank page with the lowest frequency used within the preset time.
  • the method further includes: updating the page table to make the page table include the virtual address carried by the memory access request, and The page table is stored in the TLB.
  • the method further includes: depositing the page table into the TLB.
  • the present invention provides a memory management device, where the memory management device is located in a memory controller, and the memory management device includes: a fast translation buffer TLB, a memory management unit MMU, and a microcontroller;
  • the TLB is configured to receive a memory access request sent by the processor, and the memory access request carries a virtual address, and searches whether the page table corresponding to the virtual address carried by the memory access request is cached in the TLB, and if yes, obtains the virtual page from the page table. a real address corresponding to the address, where the page table includes a correspondence between the virtual address and the real address;
  • the MMU is configured to: when the page table corresponding to the virtual address carried by the access request is not cached in the TLB, obtain a base address field of the page table and look up the page table, and obtain a virtual address corresponding to the virtual address when the page table has a virtual address Real address
  • the microcontroller is configured to determine whether the virtual address is legal when the page table has no virtual address, and apply for a blank page when determining that the virtual address is legal.
  • the microcontroller is further configured to start memory reading and writing when the blank page is successfully applied, and if the blank page fails to be applied, the replacement page is selected and provided to the operating system to enable the operation. The system replaces the page.
  • the microcontroller is specifically configured to determine whether the virtual address falls in the allocated virtual address space, if The virtual address is determined to be valid. If not, the virtual memory address is found to have a virtual address in the VMA space. If it exists, the virtual address is determined to be valid.
  • the microcontroller is further configured to receive a memory access request, obtain a visit
  • the base address field of the page table of the process corresponding to the virtual address carried by the request is stored, and the base address field is sent to the MMU, so that the MMU searches the page table according to the base address field.
  • the micro controller is further configured to count each blank page of the cache at a preset time The frequency of use inside, when applying for a blank page, select the blank page with the lowest frequency in the preset time.
  • the present invention provides a memory controller, comprising: any one of the memory management devices provided by the second aspect.
  • the memory is managed by the storage management device, which can reduce the burden on the operating system.
  • the storage management device determines that there is no virtual address carried in the page table in the page table, the interrupt of the operating system is not triggered, but The memory management device manages the memory.
  • the virtual address is determined to be valid, a blank page is applied.
  • the memory management device is located in the memory controller and is closer to the physical memory, which can effectively improve the memory management efficiency.
  • FIG. 2 is a schematic flowchart of a memory management method according to an embodiment of the present invention.
  • FIG. 3 is another schematic flowchart of a memory management method provided in an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a memory management apparatus according to an embodiment of the present invention.
  • the memory management method provided by the embodiment of the present invention can be applied to a communication system, and the memory management method can be applied to a memory management device, where the memory management device is located in a memory controller.
  • FIG. 1 is a schematic structural diagram of an applicable embodiment of the present invention.
  • the memory controller 100 proposed by the present invention may include a memory management device 101, a mapping scheduler 102, and a physical layer protocol PHY 103.
  • the mapping scheduler 102 is mainly responsible for address mapping (such as translation of linear addresses into ranks, banks, rows, and columns of dynamic random access memory), request scheduling, refresh control, etc.
  • the PHY 103 is responsible for the memory controller 100 and the memory chip.
  • the mapping scheduler 102 and the PHY 103 can be referred to the prior art, and details are not described herein again.
  • the memory can be accessed by sending a memory access request to the memory controller 100 through the request path, which is mainly managed by the memory management device 101 in the memory controller 100 according to the cache request. .
  • a memory management method is applied to the memory management device 101.
  • the memory management device 101 is located in the memory controller 100.
  • the method includes: receiving a memory access request sent by the processor, the memory access request carrying a virtual address; and searching for a fast translation buffer ( Whether the page table corresponding to the virtual address carried by the memory access request is cached in the TLB (Translation Look-aside Buffer), and if so, the real address corresponding to the virtual address is obtained from the page table, and if not, the base of the page table is obtained.
  • the address field finds a page table.
  • the page table has a virtual address carried by the memory access request, the real address corresponding to the virtual address is obtained, where the page table includes a correspondence between the virtual address and the real address, and the TLB is located in the memory management device; If there is no virtual address carried in the page table, the virtual address is determined to be legal, and when the virtual address is determined to be valid, a blank page is applied.
  • FIG. 2 is a schematic flowchart of a memory management method according to an embodiment of the present invention. Methods can include:
  • Step S201 Receive a memory access request sent by the processor, where the memory access request carries a virtual address.
  • the memory may be accessed by sending a memory access request to the memory management device 101 in the memory controller 100, where the memory access request carries a virtual address.
  • the Quick Look Buffer (TLB) and the microcontroller in the memory management apparatus 101 can receive the memory access request sent by the processor, and the TLB is mainly responsible for fast address translation and page table searching, and the micro control
  • the device is mainly responsible for memory management (including checking the legitimacy of the memory access request, etc.), that is, when the relevant page table is not cached in the TLB, the memory management operation by the microcontroller is required.
  • the processor may be a CPU core.
  • Step S202 Query whether the page table corresponding to the virtual address carried in the memory access request is cached in the fast translation buffer TLB. If not, execute step S203. If yes, execute step S205, where the page table includes the virtual address and the real page. Correspondence of addresses;
  • the page table is generally stored in the main memory, and the correspondence between the virtual address and the real address is stored in the page table.
  • the TLB can cache the page table file. Therefore, if the TLB is cached in the TLB, the real address corresponding to the virtual address can be directly obtained from the TLB. If the page table is not cached in the TLB, the memory management device 101 can be used.
  • the Memory Management Unit (MMU) looks up the page table.
  • the page table corresponding to the virtual address carried in the cache access request is not cached, and the page table is obtained. Take the base address field of the page table;
  • the MMU may not be able to know the base address field of the page table and thus cannot directly search the page table.
  • the base address field of the page table can be provided by the microcontroller to the MMU.
  • the page table entry address base address field + the high number of virtual addresses.
  • the microcontroller obtains the base address field of the page table of the process corresponding to the virtual address carried by the memory access request after receiving the cache request, and provides the base address field of the page table to the page address table.
  • the MMU causes the MMU to look up the page table based on the base address field of the page table.
  • the microcontroller can search the process table, obtain a base address field of the page table of the process corresponding to the virtual address, and send the page table base address field to the MMU.
  • Step S204 according to the base address field of the page table to find the page table, if the page table is found to have a virtual address carried by the memory access request, step S205 is performed, if not, step S206 is performed;
  • step 205 is performed to obtain the real address corresponding to the virtual address, and then the memory data can be read according to the real address. If the page table does not have a virtual address carried by the memory access request, step 206 is performed.
  • Step S205 Obtain a real address corresponding to the virtual address carried in the memory access request.
  • step S202 the page table corresponding to the virtual address carried by the memory access request cached in the fast translation buffer TLB is searched, and in step S205, the real address corresponding to the virtual address is obtained from the page table by the TLB; in step S204, the MMU The page table is found to have a virtual address carried by the memory access request. In step S205, the MMU obtains the real address corresponding to the virtual address carried in the memory access request.
  • step S206 if the virtual address carried by the access request is not found in the page table, it is determined whether the virtual address is legal, and when the virtual address is determined to be legal, a blank page is applied.
  • the microcontroller may determine whether the virtual address carried in the memory access request is legal.
  • the content of the virtual address carried in the memory access request is legal, including:
  • VMA virtual memory address
  • the page fault interrupt can be fed back. Give the operating system, and then apply for a blank page by the microcontroller.
  • the microcontroller requests a blank page. If the blank page of the application is successful, the memory can be directly read and written. If the application for a blank page fails, the replacement page is selected and the replacement page is provided to the operating system, and the operating system writes the data from the memory to the hard disk. If the eliminated page is "clean”, the operating system can modify its page table item and use it directly; if the page is "dirty”, the operating system needs to write the "dirty" page back to disk and generate context. Switching, suspending the process until the end of the disk operation; then the state before the page fault interrupt occurs will pop up the stack, since the process enters the ready state, ready to be executed by the operating system.
  • the method may further include: determining whether the blank page of the application is the first legal access, and if so, directly starting the memory read and write operation; if not, the feedback operating system blank page is ready, Causes the operating system in the processor to write data from the hard disk to the memory.
  • step S206 If it is found that there is no virtual address in the VMA space in step S206, it is determined that the virtual address is illegal, that is, the memory access request is determined to be an illegal access, and the interrupt is fed back to the operating system, and the next step is performed by the operating system.
  • the storage management device determines that there is no virtual address carried in the page table in the page table, the interrupt of the operating system is not triggered, but the memory management device manages the memory, and determines the virtual When the address is legal, apply for a blank page.
  • the memory management device is located in the memory controller and is closer to the physical memory, which can effectively improve the memory management efficiency.
  • FIG. 3 is another schematic flowchart of a memory management method according to an embodiment of the present invention.
  • Step S301 The TLB receives a memory access request sent by the processor, where the memory access request carries a virtual address.
  • Step S302 the TLB searches whether the page table corresponding to the virtual address carried in the memory access request is cached in the TLB, if not, executing step S303, if yes, executing step S305;
  • Step S303 The microcontroller receives the memory access request sent by the processor, and the memory access request carries the virtual address, and the microcontroller searches the process table to obtain the page table base of the process corresponding to the virtual address. Address field, and send the page table base address field to the MMU; step S304;
  • the process table refers to a data structure table maintained locally by the memory management processor core, and can be stored in the on-chip SRAM, and specifically includes: a process ID, a processor core ID, a physical space quota, and a management policy. These entries are transmitted to the memory controller through the interactive channel when the operating system switches processes. The entry base address of the page table is created and maintained by the memory management processor, and the process table is invisible to the operating system.
  • Table 1 The specific implementation can be seen in Table 1:
  • the microcontroller receives the memory access request sent by the processor, and the cache request can carry the process ID, and the microcontroller can find the location of the page table corresponding to the process according to the process ID, obtain the base address field of the page table, and provide the MMU to the MMU.
  • the MMU can find the page table according to the virtual address carried by the memory access request.
  • steps S301 and S303 are time-independent, and the microcontroller and the TLB can simultaneously receive the memory access request sent by the processor.
  • Step S304 the MMU searches the page table according to the base address field of the page table sent by the microcontroller, if it hits, step S305 is performed, if not, step S306 is performed;
  • the MMU searches the page table according to the base address field of the page table sent by the microcontroller, and the hit indicates that the virtual address carried by the memory access request is included in the page table, and the real address corresponding to the virtual address can be obtained.
  • Step S305 Obtain a real address corresponding to the virtual address.
  • the real address corresponding to the virtual address can be used to access the memory data; if the step 304 is to the step S305, the MMU obtains the virtual address corresponding to the virtual address. The real address can be used to access the memory data.
  • Step S306 the microcontroller checks whether the virtual address carried in the memory access request falls in the recently allocated virtual address space, if not, then proceeds to step S307, and if so, determines that the virtual address is legal, then step S310;
  • a memory allocation table may be integrated in the memory controller, and the contents of the entry of the memory allocation table may include: a process ID, a virtual address of the process Malloc, and a virtual address size. This information is passed to the memory controller by the operating system through the interactive interface when the process calls the Malloc function.
  • the microcontroller looks up the memory allocation table.
  • the microcontroller can also look up the memory allocation table after receiving the memory access request, that is, during the processing of the TLB and the MMU, the microcontroller simultaneously processes.
  • the memory allocation table hits, it indicates that the memory access request is legal and is accessed for the first time. The page has not been allocated yet, and the microcontroller can directly apply for a blank page for the request.
  • step S307 is executed, and the microcontroller needs to go to the memory to view the VMA space of the process, thereby further determining the cause of the MMU miss.
  • the memory allocation table can implement certain replacement strategies, such as the simplest first-in-first-out (FIFO) strategy.
  • FIFO first-in-first-out
  • Step S307 the microcontroller finds the virtual memory address VMA space of the process in memory, determines whether the virtual address exists, and if so, proceeds to step S309, and if not, proceeds to step S308;
  • Step S308 the microcontroller determines that the request is an illegal access, and feeds back an interrupt to the operating system
  • the next step is performed by the operating system to end the process.
  • Step S309 the microcontroller determines that the request virtual address data is in the SWAP partition or file, feedback operating system page fault interrupt, and step S310;
  • Step S310 the microcontroller searches for the free list, apply for a blank page, if the application fails, then go to step S311, if the application is successful, then go to step S313;
  • Step S311 the microcontroller runs a page replacement algorithm, and selects a page to swap out the memory
  • Step S312 the microcontroller updates the page table entry and the TLB, and the selected page to be replaced is selected.
  • the address is written into the register of the feedback space, and the operating system replaces the signal that the page has been prepared;
  • the operating system After the operating system replaces the signal that the page has been prepared, the operating system performs the next step to end the process.
  • Step S313 the microcontroller updates the TLB and the page table entry
  • Step S314 the microcontroller determines whether it is the first time to apply for a blank page, if the memory access request is not the first legal access, skip to step S315, and if so, proceed to step S316;
  • Step S315 the microcontroller writes the register value to the feedback space, and sends a signal that the blank page has been prepared to the operating system;
  • the operating system determines the next step by reading various information in the feedback space.
  • step S316 the microcontroller directly starts the memory read and write operation.
  • the embodiment of the present invention further provides an apparatus based on the foregoing memory management method.
  • the meaning of the noun is the same as that in the above memory management.
  • a memory management device 101 is located in the memory controller.
  • the memory management device 101 specifically includes a fast translation buffer TLB 1011, a memory management unit MMU 1012, and a microcontroller 1013. Please refer to FIG. 4, which is a schematic structural diagram of the memory management device. .
  • the TLB1011 is configured to receive a memory access request sent by the processor, and the memory access request carries a virtual address, and searches whether the page table corresponding to the virtual address carried by the memory access request is cached in the TLB, and if yes, obtains the virtual page from the page table. a real address corresponding to the address, where the page table includes a correspondence between the virtual address and the real address;
  • the MMU 1012 is configured to: when the page table corresponding to the virtual address carried by the access request is not cached in the TLB, obtain a base address field of the page table and look up the page table, and obtain a virtual address corresponding to the virtual address when the page table has a virtual address Real address
  • the microcontroller 1013 is configured to determine whether the virtual address is legal when the page table has no virtual address, and apply for a blank page when determining that the virtual address is legal.
  • the microcontroller 1013 is further configured to select a replacement page and provide the operating system to cause the operating system to replace the page when the application for the blank page fails.
  • the microcontroller 1013 is specifically configured to determine whether the virtual address falls within the allocated virtual address space. If yes, the virtual address is determined to be valid. If not, the virtual memory address is found to have a virtual space in the VMA space. The address, if it exists, determines that the virtual address is valid.
  • the microcontroller 1013 is further configured to receive a memory access request, obtain a base address field of a page table of a process corresponding to the virtual address carried by the memory access request, and send the base address field to the MMU, so that The MMU looks up the page table based on the base address field.
  • the microcontroller 1013 is further configured to count the frequency of use of each blank page of the cache in a preset time. When applying for a blank page, select a blank page with the lowest frequency used in the preset time.
  • the memory management apparatus 101 may further include: a configuration space 1014 and a feedback space 1015, wherein the configuration space and the feedback space are spaces for direct information interaction between the operating system and the memory controller.
  • the implementation of configuration space and feedback space can be a bunch of addressable registers.
  • the operating system can send information to the configuration space through the interactive path, and can also obtain information from the feedback space.
  • the microcontroller can read configuration space information directly or write information to the feedback space.
  • the memory management apparatus 101 may further include: a data buffering module 1016, configured to buffer read and write bidirectional data.
  • the code of the microcontroller can run on an on-chip SRAM.
  • the TLB and the MMU in the embodiment of the present invention are all located in the memory controller, which is closer to the physical memory, and is convenient for hardware to implement memory management.
  • the storage management device manages the memory, which can reduce the burden on the operating system, and when the storage management device determines that there is no memory access request in the page table.
  • the virtual address is carried, the interruption of the operating system is not triggered, but the memory management device manages the memory.
  • the virtual address is determined to be valid, a blank page is applied, and the memory management device is located in the memory controller, closer to the physical Memory can effectively improve the efficiency of memory management.
  • the present invention further provides a memory controller.
  • the memory controller may include any of the memory management devices provided above, and the memory management device may include: a fast translation buffer TLB, a memory management unit.
  • TLB fast translation buffer
  • the MMU and the microcontroller, and the specific implementation thereof can be referred to the foregoing embodiment, and details are not described herein again.
  • the memory controller in the embodiment of the present invention may be integrated into the CPU or may be a separate chip.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

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Abstract

一种内存管理方法和装置。方法包括：由存储管理装置对内存进行管理，当存储管理装置确定页表中没有所述访存请求携带的虚地址时，不触发操作系统的中断，而是由内存管理装置对内存进行管理，可以减轻操作系统的负担，其中，在确定所述虚地址合法时，申请空白页，该内存管理装置位于内存控制器中，更靠近物理内存，可以有效提高内存的管理效率。

Description

一种内存管理方法、装置以及内存控制器 技术领域
本发明涉及计算机领域，尤其涉及一种内存管理方法、装置以及内存控制器。
背景技术
在计算机系统中，内存控制器主要负责CPU与内存之间的数据交互，而内存的实地址管理则由操作系统来实现。操作系统为某个进程分配虚地址，若在快速翻译缓冲器(TLB，Translation Look-aside Buffer)中未缓存有该虚地址，且内存管理单元(MMU，Memory Management Unit)未查找到该虚地址的页表项，则产生缺页中断(page fault)，CPU陷入操作系统内核。缺页中断后，操作系统进入中断服务程序，进行现场保护，将程序计数器等当前指令的各种状态信息压入栈，然后检查虚地址的合法性，如果判断该访问非法，操作系统通常会向进程反馈一个信号或直接杀死该进程。
现有技术中，一旦MMU未查找到该虚地址的页表项，直接触发缺页中断(page fault)，使CPU长时间陷入操作系统内核。缺页中断后，操作系统要进行一系列的处理，加重操作系统的负荷，并且管理效率较低。
发明内容
本发明实施例提供了一种内存管理方法、装置以及内存控制器，用于提高内存的管理效率。
第一方面，本发明提供了一种内存管理方法，该方法应用在内存管理装置上，内存管理装置位于内存控制器中，方法包括：
接收处理器发送的访存请求，访存请求携带虚地址；
查找快速翻译缓冲器TLB中是否缓存有访存请求携带的虚地址对应的页表，若有，则从页表中获取与虚地址对应的实地址，若无，则获取页表的基地址域并查找页表，若页表有访存请求携带的虚地 址，则获取与虚地址对应的实地址，其中，页表包括虚地址与实地址的对应关系，TLB位于内存管理装置中；
若页表中没有访存请求携带的虚地址，则确定虚地址是否合法，并在确定虚地址合法时，申请空白页。
在第一方面的第一种可能的实现方式中，还包括：若申请空白页成功，则启动内存读写；若申请空白页失败，则选择替换页并提供给操作系统以使得操作系统对页面进行替换。
结合第一方面，或第一方面的第一种可能的实现方式，在第二种可能的实现方式中，确定虚地址是否合法，具体包括：确定虚地址是否落在已分配的虚地址空间中，若是，则确定虚地址合法；若否，则查找虚拟内存地址VMA空间中是否存在虚地址，若存在，则确定虚地址合法。
结合第一方面、第一方面的第一种可能的实现方式或第二种可能的实现方式，在第三种可能的实现方式中，申请空白页之前，还包括：统计缓存的每个空白页在预置时间内的使用频率；当申请空白页时，选择在预置时间内使用频率最低的空白页。
结合第一方面的第一种可能的实现方式，在第四种可能的实现方式中，申请空白页成功之后，还包括：更新页表以使得页表包括访存请求携带的虚地址，并将页表存入TLB。
结合第一方面、第一方面的第一至第四任一种可能的实现方式，在第五种可能的实现方式中，若查找到页表有访存请求携带的虚地址，则在获取与虚地址对应的实地址的步骤之前，还包括：将页表存入TLB。
第二方面，本发明提供了一种内存管理装置，该内存管理装置位于内存控制器中，内存管理装置包括：快速翻译缓冲器TLB、内存管理单元MMU和微控制器；
TLB，用于接收处理器发送的访存请求，访存请求携带虚地址，并查找TLB中是否缓存有访存请求携带的虚地址对应的页表，若有，则从页表中获取与虚地址对应的实地址，其中，页表包括虚地址与实地址的对应关系；
MMU，用于当TLB中未缓存有访存请求携带的虚地址对应的页表时，获取页表的基地址域并查找页表，并在页表有虚地址时，获取与虚地址对应的实地址；
微控制器，用于当页表无虚地址时，确定虚地址是否合法，并在确定虚地址合法时，申请空白页。
在第二方面的第一种可能的实现方式中，微控制器，还用于当申请空白页成功，则启动内存读写，申请空白页失败，则选择替换页并提供给操作系统以使得操作系统对页面进行替换。
结合第二方面，或第二方面的第一种可能的实现方式，在第二种可能的实现方式中，微控制器，具体用于确定虚地址是否落在已分配的虚地址空间中，若是，则确定虚地址合法，若否，则查找虚拟内存地址VMA空间中是否存在虚地址，若存在，则确定虚地址合法。
结合第二方面、第二方面的第一种可能的实现方式或第二种可能的实现方式，在第三种可能的实现方式中，微控制器，还用于接收访存请求，获得与访存请求携带的虚地址对应的进程的页表的基地址域，并将基地址域发送给MMU，以使得MMU根据基地址域查找页表。
结合第二方面、第二方面的第一至第三任一种可能的实现方式，在第四种可能的实现方式中，微控制器，还用于统计缓存的每个空白页在预置时间内的使用频率，当申请空白页时，选择在预置时间内使用频率最低的空白页。
第三方面，本发明提供了一种内存控制器，其包括：如第二方面提供的任一种内存管理装置。
从以上技术方案可以看出，本发明实施例具有以下优点：
本发明的技术方案中，由存储管理装置对内存进行管理，可以减轻操作系统的负担，当存储管理装置确定页表中没有访存请求携带的虚地址时，不触发操作系统的中断，而是由内存管理装置对内存进行管理，其中，在确定虚地址合法时，申请空白页，该内存管理装置位于内存控制器中，更靠近物理内存，可以有效提高内存的管理效率。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例可应用的架构示意图；
图2是本发明实施例提供的内存管理方法的一个流程示意图；
图3是本发明实施例中提供的内存管理方法的另一个流程示意图；
图4是本发明实施例中提供的内存管理装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
首先，本发明实施例提供的内存管理方法可适用于通信系统，该内存管理方法可应用在内存管理装置上，该内存管理装置位于内存控制器中。
具体可参阅图1，图1是本发明实施例可应用的架构示意图。本发明提出的内存控制器100可包括内存管理装置101、映射调度器102和物理层协议PHY103。其中，映射调度器102主要负责地址映射(如将线性地址翻译成动态随机存取存储器的rank、bank、row和column等)、请求调度、刷新控制等功能，PHY103负责内存控制器100与内存芯片建立物理链路，映射调度器102和PHY103的具体实施可参见现有技术，此处不再赘述。
当处理器请求的资源缓存未命中，则可以通过请求通路向内存控制器100发送访存请求来访问内存，其主要是通过内存控制器100中的内存管理装置101根据该缓存请求对内存进行管理。
一种内存管理方法，应用在内存管理装置101上，内存管理装置101位于内存控制器100中，方法包括：接收处理器发送的访存请求，访存请求携带虚地址；查找快速翻译缓冲器(TLB，Translation Look-aside Buffer)中是否缓存有访存请求携带的虚地址对应的页表，若有，则从页表中获取与虚地址对应的实地址，若无，则获取页表的基地址域并查找页表，若页表有访存请求携带的虚地址，则获取与虚地址对应的实地址，其中，页表包括虚地址与实地址的对应关系，TLB位于内存管理装置中；若页表中没有访存请求携带的虚地址，则确定虚地址是否合法，并在确定虚地址合法时，申请空白页。
请参阅图2，图2是本发明实施例提供的内存管理方法的一个流程示意图。方法可包括：
步骤S201、接收处理器发送的访存请求，访存请求携带虚地址；
当处理器请求的资源缓存未命中，可以通过请求通路向内存控制器100中的内存管理装置101发送访存请求来访问内存，其中，该访存请求携带虚地址。内存管理装置101中的快速翻译缓冲器(TLB，Translation Look-aside Buffers)和微控制器均可以接收到处理器发送的该访存请求，TLB主要负责快速地址翻译和查找页表，而微控制器主要负责做内存管理(其中包括检查该访存请求的合法性等)，即TLB中没有缓存有相关页表时，才需要由微控制器进行内存管理等操作。
其中，若以本发明应用在计算机系统中为例，该处理器可以是CPU核。
步骤S202、查找快速翻译缓冲器TLB中是否缓存有访存请求携带的虚地址对应的页表，若无，则执行步骤S203，若有，则执行步骤S205，其中，页表包括虚地址与实地址的对应关系；
页表一般储存在主存储器中，页表中存储有虚地址和实地址的对应关系。而TLB可以缓存页表文件，因此，若TLB中缓存TLB，则可以从TLB中直接获取与虚地址对应的实地址，若TLB中未缓存有该页表，则可以由内存管理装置101中的内存管理单元(MMU，Memory Management Unit)查找页表。
S203、TLB中没有缓存访存请求携带的虚地址对应的页表，则获 取页表的基地址域；
由于页表一般储存在主存储器中，MMU可能无法获知页表的基地址域从而无法直接查找页表，此时，可以由微控制器将该页表的基地址域提供给MMU。其中，页表入口地址＝基地址域+虚地址的高几位。
具体的，可以在MMU查找页表之前，微控制器接收到缓存请求后，获取与访存请求携带的虚地址对应的进程的页表的基地址域，并将页表的基地址域提供给MMU，使得MMU根据页表的基地址域查找页表。一种实现方式中，微控制器可以查找进程表，获得与虚地址对应的进程的页表的基地址域，并将该页表基地址域发送给MMU。
步骤S204、根据页表的基地址域查找页表，若查找到页表有访存请求携带的虚地址，则执行步骤S205，若无，则执行步骤S206；
若页表有访存请求携带的虚地址，则执行步骤205，获取与虚地址对应的实地址后，则可以根据该实地址读取内存数据。若页表没有访存请求携带的虚地址，则执行步骤206。
步骤S205、获取与访存请求携带的虚地址对应的实地址；
在步骤S202中，查找快速翻译缓冲器TLB中缓存有访存请求携带的虚地址对应的页表，步骤S205则由TLB从页表中获取与虚地址对应的实地址；在步骤S204中，MMU查找到页表有访存请求携带的虚地址，步骤S205则由MMU获取与访存请求携带的虚地址对应的实地址。
步骤S206、查找到页表没有访存请求携带的虚地址，则确定虚地址是否合法，并在确定虚地址合法时，申请空白页。
若TLB中未缓存有页表，且MMU中的该页表也未命中，则可以由微控制器来判断该访存请求携带的虚地址是否合法。其中，判断该访存请求携带的虚地址是否合法，具体包括：
确定虚地址是否落在已分配的虚地址空间中，若是，则确定虚地址是首次访问，该虚地址合法；若否，则查找虚拟内存地址(VMA，virtual memory Address)空间中是否存在虚地址，若存在，则确定虚地址合法。
其中，在确定了VMA空间中存在虚地址后，可以反馈缺页中断 给操作系统，然后再由微控制器来申请空白页。
若虚地址合法，则由微控制器申请空白页，若申请的空白页成功，则可以直接启动内存读写。若申请空白页失败了，则选择替换页并将该替换页提供给操作系统，由操作系统将数据从内存写入硬盘。其中，若被淘汰的页面“干净”，则操作系统可以修改其页表项后直接使用；如果被淘汰页面“脏”了，则需要操作系统先将“脏”页面写回磁盘，并产生上下文切换，挂起该进程，直到磁盘操作结束；然后将发生缺页中断以前的状态弹出栈，自此进程进入就绪态，随时可以被操作系统调度执行。
此外，在申请空白页成功后，还可以包括，判断该申请的空白页是否是首次合法访问，若是，则可以直接启动内存读写操作，若不是，则反馈操作系统空白页已经准备好了，使得处理器中的操作系统将数据从硬盘写入内存。
若步骤S206中查找到VMA空间中不存在虚地址时，确定该虚地址非法，即判断该访存请求为非法访问，则向操作系统反馈中断，由操作系统执行下一步。
由上可知，本发明的技术方案中，当存储管理装置确定页表中没有访存请求携带的虚地址时，不触发操作系统的中断，而是由内存管理装置对内存进行管理，在确定虚地址合法时，申请空白页，该内存管理装置位于内存控制器中，更靠近物理内存，可以有效提高内存的管理效率。
为了更好的理解上述方案，本发明实施例以一具体应用例进行详细说明，具体可参阅图3，图3是本发明实施例提供的内存管理方法的另一个流程示意图。
步骤S301、TLB接收处理器发送的访存请求，访存请求携带虚地址；
步骤S302、TLB查找TLB中是否缓存有访存请求携带的虚地址对应的页表，若无，则执行步骤S303，若有，则执行步骤S305；
步骤S303、微控制器接收处理器发送的访存请求，访存请求携带虚地址，微控制器查找进程表，获得与虚地址对应的进程的页表基地 址域，并将该页表基地址域发送给MMU；执行步骤S304；
其中，进程表是指由内存管理处理器核本地维护的一种数据结构表，可存放于片上SRAM中，其具体可包括：进程ID、处理器核ID、物理空间配额和管理策略等表项，这些表项是操作系统在切换进程时通过交互通道传给内存控制器的，页表的入口基地址是由内存管理处理器创建并维护，进程表对操作系统是不可见。具体实现形式可参见表一：
表一
Figure PCTCN2015084798-appb-000001
微控制器接收处理器发送的访存请求，该缓存请求可携带进程ID，微控制器可根据该进程ID找到该进程对应的页表的位置，获取页表的基地址域并提供给MMU，使得MMU可以根据访存请求携带的虚地址查找页表。
可以理解的是，步骤S301和步骤S303时序无关，微控制器和TLB可以同时接收到处理器发送的访存请求。
步骤S304、MMU根据微控制器发送的页表的基地址域查找页表，若命中，则执行步骤S305，若不命中，则执行步骤S306；
MMU根据微控制器发送的页表的基地址域查找页表，命中，则说明该页表中包括有该访存请求携带的虚地址，则可以获取与该虚地址对应的实地址。
步骤S305、获取与虚地址对应的实地址；
如果由步骤S302跳转到步骤S305，则由TLB获取与虚地址对应的实地址，则可以采用该实地址访问内存数据；若由步骤304跳转到步骤S305，则由MMU获取与虚地址对应的实地址，则可以采用该实地址访问内存数据。
步骤S306、微控制器检查访存请求携带的虚地址是否落在最近分配的虚地址空间中，若不是，则执行步骤S307，若是，则确定该虚地址合法，则执行步骤S310；
例如，可以通过在内存控制器内部集成一个内存分配表，该内存分配表的表项记录的内容可包括：进程ID、进程Malloc的虚地址和虚地址大小。这些信息由操作系统在进程调用Malloc函数时通过交互接口传给内存控制器。
当TLB和MMU均不命中时，由微控制器查找查内存分配表。此外，微控制器也可以在接收到访存请求后，查找内存分配表，即在TLB和MMU的处理过程中，微控制器同时进行处理。当TLB和MMU均不命中，而内存分配表命中，则说明此访存请求合法且首次被访问，还尚未分配过页面，微控制器可以直接为该请求申请空白页使用。
如果TLB、MMU和内存分配表均不命中，则执行步骤S307，微控制器需要到内存中查看该进程的VMA空间，从而进一步判断MMU未命中的原因。
这样占用资源少，逻辑简单，判断快速。当Malloc项数增多以后，内存分配表可以实现一定的替换策略，比如最简单的先进先出(FIFO)策略。
步骤S307、微控制器在内存中查找该进程的虚拟内存地址VMA空间，确定该虚地址是否存在，若是，则执行步骤S309，若否，则执行步骤S308；
步骤S308，微控制器判断该请求为非法访问，向操作系统反馈中断；
由操作系统执行下一步操作，结束流程。
步骤S309、微控制器判断该请求虚地址数据在SWAP分区或文件中，反馈操作系统缺页中断，并执行步骤S310；
步骤S310、微控制器搜索空闲列表，申请空白页，如果申请失败，则跳到步骤S311，如果申请成功，则跳到步骤S313；
步骤S311、微控制器运行页面替换算法，选出一个页面换出内存；
步骤S312，微控制器更新页表项和TLB，将选出的待替换页面的 地址写入反馈空间的寄存器中，并反馈操作系统替换页面已经准备好的信号；
选择了替换页面，则需要为该新的页面构建页表项，则微控制器需要更新页表和TLB。
并反馈操作系统替换页面已经准备好的信号后，由操作系统执行下一步操作，结束流程。
步骤S313、微控制器更新TLB及页表项；
申请空白页成功了，需要为该空白页构建页表项，则微控制器需要更新页表和TLB。
步骤S314、微控制器判断是否是首次申请空白页，若该访存请求不是首次合法访问，跳到步骤S315，若是，则执行步骤S316；
步骤S315，微控制器向反馈空间的写寄存器值，向操作系统发出空白页已经准备好的信号；
操作系统通过阅读反馈空间的各种信息，决定下一步操作。
步骤S316，微控制器直接启动内存读写操作。
由上可知，本发明的技术方案中，当操作系统需要修改或查找页表的时候，只需要向内存控制器发送指令，内存控制器就可以通过进程ID找到页表在内存的位置，自动完成相应的操作，其中，内存的管理由内存管理装置来实现，可以减轻操作系统的负担，可以有效提高内存的管理效率。
为便于更好的实施本发明实施例提供的内存管理方法，本发明实施例还提供一种基于上述内存管理方法的装置。其中名词的含义与上述内存管理中相同，具体实现细节可以参考方法实施例中的说明。
一种内存管理装置101，位于内存控制器中，内存管理装置101具体包括快速翻译缓冲器TLB1011、内存管理单元MMU1012和微控制器1013，请参阅图4，图4是内存管理装置的一个结构示意图。
TLB1011，用于接收处理器发送的访存请求，访存请求携带虚地址，并查找TLB中是否缓存有访存请求携带的虚地址对应的页表，若有，则从页表中获取与虚地址对应的实地址，其中，页表包括虚地址与实地址的对应关系；
MMU1012，用于当TLB中未缓存有访存请求携带的虚地址对应的页表时，获取页表的基地址域并查找页表，并在页表有虚地址时，获取与虚地址对应的实地址；
微控制器1013，用于当页表无虚地址时，确定虚地址是否合法，并在确定虚地址合法时，申请空白页。
在一个实施例中，微控制器1013，还用于当申请空白页失败，则选择替换页并提供给操作系统以使得操作系统对页面进行替换。
在一个实施例中，微控制器1013，具体用于确定虚地址是否落在已分配的虚地址空间中，若是，则确定虚地址合法，若否，则查找虚拟内存地址VMA空间中是否存在虚地址，若存在，则确定虚地址合法。
在一个实施例中，微控制器1013，还用于接收访存请求，获得与访存请求携带的虚地址对应的进程的页表的基地址域，并将基地址域发送给MMU，以使得MMU根据基地址域查找页表。
在一个实施例中，微控制器1013，还用于统计缓存的每个空白页在预置时间内的使用频率，当申请空白页时，选择在预置时间内使用频率最低的空白页。
此外，该内存管理装置101还可以包括：配置空间1014和反馈空间1015，其中，配置空间和反馈空间是操作系统与内存控制器之间的直接进行信息交互的空间。例如，配置空间和反馈空间的实现形式可以是一堆可寻址的寄存器。操作系统可以通过交互通路向配置空间发送信息，也可以从反馈空间获取信息。微控制器可以直接读取配置空间信息，也可以向反馈空间写信息。
此外，该内存管理装置101还可以包括：数据缓冲模块1016，用于缓冲读、写双向数据。
一种实现方式中，微控制器的代码可运行在片上SRAM上。
本发明实施例中的TLB和MMU均位于内存控制器中，更接近物理内存，方便硬件实现内存管理。
由上可知，本发明实施例中，由存储管理装置对内存进行管理，可以减轻操作系统的负担，当存储管理装置确定页表中没有访存请求 携带的虚地址时，不触发操作系统的中断，而是由内存管理装置对内存进行管理，其中，在确定虚地址合法时，申请空白页，该内存管理装置位于内存控制器中，更靠近物理内存，可以有效提高内存的管理效率。
本发明还提供了一种内存控制器，具体可参阅图1，该内存控制器可包括上述所提供的任一种内存管理装置，该内存管理装置可包括：快速翻译缓冲器TLB、内存管理单元MMU和微控制器，其中，其具体实施可参见上述实施例，此处不再赘述。
其中，本发明实施例中的内存控制器可集成于CPU内部，也可以是独立的芯片。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上对本发明所提供的一种内存管理方法、装置以及内存控制器进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明实施例的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (12)

  1. 一种内存管理方法，其特征在于，所述方法应用在内存管理装置上，所述内存管理装置位于内存控制器中，所述方法包括：
    接收处理器发送的访存请求，所述访存请求携带虚地址；
    查找快速翻译缓冲器TLB中是否缓存有所述访存请求携带的虚地址对应的页表，若有，则从所述页表中获取与所述虚地址对应的实地址，若无，则获取所述页表的基地址域并查找所述页表，若所述页表有所述访存请求携带的虚地址，则获取与所述虚地址对应的实地址，其中，所述页表包括虚地址与实地址的对应关系，所述TLB位于所述内存管理装置中；
    若所述页表中没有所述访存请求携带的虚地址，则确定所述虚地址是否合法，并在确定所述虚地址合法时，申请空白页。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    若申请空白页成功，则启动内存读写；
    若申请空白页失败，则选择替换页并提供给操作系统以使得所述操作系统对页面进行替换。
  3. 根据权利要求1或2所述的方法，其特征在于，所述确定所述虚地址是否合法，具体包括：
    确定所述虚地址是否落在已分配的虚地址空间中，若是，则确定所述虚地址合法；
    若否，则查找虚拟内存地址VMA空间中是否存在所述虚地址，若存在，则确定所述虚地址合法。
  4. 根据权利要求1-3任一所述的方法，其特征在于，所述申请空白页之前，还包括：
    统计缓存的每个空白页在预置时间内的使用频率；
    当申请空白页时，选择在所述预置时间内使用频率最低的空白页。
  5. 根据权利要求2所述的方法，其特征在于，申请空白页成功之后，还包括：
    更新所述页表以使得所述页表包括所述访存请求携带的虚地址， 并将所述页表存入所述TLB。
  6. 根据权利要求1-5任一所述的方法，其特征在于，若查找到所述页表有所述访存请求携带的虚地址，则在所述获取与所述虚地址对应的实地址的步骤之前，还包括：
    将所述页表存入所述TLB。
  7. 一种内存管理装置，其特征在于，所述内存管理装置位于内存控制器中，所述内存管理装置包括：快速翻译缓冲器TLB、内存管理单元MMU和微控制器；
    所述TLB，用于接收处理器发送的访存请求，所述访存请求携带虚地址，并查找所述TLB中是否缓存有所述访存请求携带的虚地址对应的页表，若有，则从所述页表中获取与所述虚地址对应的实地址，其中，所述页表包括虚地址与实地址的对应关系；
    所述MMU，用于当所述TLB中未缓存有所述访存请求携带的虚地址对应的页表时，获取所述页表的基地址域并查找所述页表，并在所述页表有所述虚地址时，获取与所述虚地址对应的实地址；
    所述微控制器，用于当所述页表无所述虚地址时，确定所述虚地址是否合法，并在确定所述虚地址合法时，申请空白页。
  8. 根据权利要求7所述的装置，其特征在于，
    所述微控制器，还用于当申请空白页成功，则启动内存读写，申请空白页失败，则选择替换页并提供给操作系统以使得所述操作系统对页面进行替换。
  9. 根据权利要求7或8所述的装置，其特征在于，
    所述微控制器，具体用于确定所述虚地址是否落在已分配的虚地址空间中，若是，则确定所述虚地址合法，若否，则查找虚拟内存地址VMA空间中是否存在所述虚地址，若存在，则确定所述虚地址合法。
  10. 根据权利要求7-9任一所述的装置，其特征在于，
    所述微控制器，还用于接收所述访存请求，获得与所述访存请求携带的虚地址对应的进程的页表的基地址域，并将所述基地址域发送给MMU，以使得所述MMU根据所述基地址域查找页表。
  11. 根据权利要求7-10任一所述的装置，其特征在于，
    所述微控制器，还用于统计缓存的每个空白页在预置时间内的使用频率，当申请空白页时，选择在所述预置时间内使用频率最低的空白页。
  12. 一种内存控制器，其特征在于，包括：如权利要求7-11所述的任一种内存管理装置。
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