WO2016029601A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2016029601A1
WO2016029601A1 PCT/CN2014/094223 CN2014094223W WO2016029601A1 WO 2016029601 A1 WO2016029601 A1 WO 2016029601A1 CN 2014094223 W CN2014094223 W CN 2014094223W WO 2016029601 A1 WO2016029601 A1 WO 2016029601A1
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Prior art keywords
common electrode
line
array substrate
peripheral
electrode line
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Ceased
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PCT/CN2014/094223
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English (en)
French (fr)
Inventor
冯伟
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP14882150.7A priority Critical patent/EP3187929B1/en
Priority to US14/766,831 priority patent/US9865623B2/en
Publication of WO2016029601A1 publication Critical patent/WO2016029601A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H10H20/833—Transparent materials
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the embodiment of the present invention relates to an array substrate, a preparation method thereof, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, thin film transistor-liquid crystal display
  • the ground is used.
  • the TFT-LCD is composed of an array substrate and a color film substrate.
  • a liquid crystal layer is arranged between the array substrate and the color filter substrate, and an electric field is formed in the liquid crystal layer by respectively applying voltage to the pixel electrode provided on the array substrate and the common electrode provided on the color filter substrate or the array substrate. Then, the transmittance of light passing through the liquid crystal layer is adjusted by adjusting the amplitude of the electric field to obtain a desired display image.
  • the common electrode and the pixel electrode can be arranged in different layers, wherein the electrode located in the upper layer is a slit electrode, and the electrode located in the lower layer is a plate electrode (or Slit electrode).
  • the display device composed of the above-mentioned array substrate is an AD-SDS (Advanced-Super Dimensional Switching, ADS for short) type display device.
  • the common electrode 10a is a plate-shaped electrode
  • the pixel electrode 11a is a slit-shaped electrode
  • the pixel electrode 11a is located above the common electrode 10a.
  • the display device uses the electric field generated by the edge of the slit electrode (pixel electrode 11a) in the same plane and the formation of a multi-dimensional electric field between the slit electrode (pixel electrode 11a) and the plate electrode (common electrode 10a) to narrow the liquid crystal layer. All oriented liquid crystal molecules between the slit electrodes and directly above the electrodes can rotate, thereby improving the working efficiency of the liquid crystal and increasing the light transmittance. Therefore, the ADS type display device has the advantages of high picture quality, high resolution, high transmittance, low power consumption, and wide viewing angle.
  • a common electrode line 101a parallel to the gate line 100a is generally arranged on at least one side of the gate line 100a to connect a plurality of common electrode lines in the same row.
  • the common electrode 10a of the pixel unit 1a is provided with a common voltage through the above-mentioned common electrode line 101a.
  • an array substrate includes a peripheral common electrode line for supplying a common voltage and a plurality of pixel units.
  • the array substrate further includes a plurality of first connection parts and second connection parts.
  • the first connecting portion is arranged along the first direction between the peripheral common electrode line and the common electrode of the pixel unit on the side close to the peripheral common electrode line, and is used to connect the peripheral common electrode line to the common electrode.
  • the electrodes are electrically connected.
  • the second connecting portion is disposed between the common electrodes of every two adjacent pixel units along the first direction, and is used to electrically connect the common electrodes of the two adjacent pixel units.
  • a display device includes the array substrate as described above.
  • a method for manufacturing an array substrate includes a method of manufacturing a peripheral common electrode line for supplying a common voltage and a plurality of pixel units.
  • the method further includes: along the first direction, forming a first connection portion between the peripheral common electrode line and the common electrode of the pixel unit on the side close to the peripheral common electrode line for connecting the peripheral common electrode line Is electrically connected to the common electrode; along the first direction, a second connecting portion is formed between the common electrodes of every two adjacent pixel units for connecting the common electrodes of the two adjacent pixel units Electric connection.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by the prior art
  • FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention.
  • 3a is a schematic structural diagram of another array substrate provided by an embodiment of the present invention.
  • 3b is a partial cross-sectional view of another array substrate provided by an embodiment of the present invention.
  • FIG. 4a is a schematic structural diagram of another array substrate provided by an embodiment of the present invention.
  • 4b is a partial structural cross-sectional view of another array substrate provided by an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present invention.
  • 6a-6d are schematic diagrams of a manufacturing process of a partial structure of an array substrate provided by an embodiment of the present invention.
  • FIGS 7a-7h are schematic diagrams of the manufacturing process of another partial structure of an array substrate provided by an embodiment of the present invention.
  • the embodiment of the present invention provides an array substrate.
  • the array substrate includes a display area and a non-display area located outside the display area.
  • a plurality of gate lines 100 and a plurality of data lines 101 intersect horizontally and vertically to define a plurality of arrays arranged in a matrix.
  • the pixel unit 01 in the non-display area is provided with a peripheral common electrode line 02 for providing a common voltage Vcom.
  • the array substrate may further include a plurality of first connection parts 110 and second connection parts 120.
  • the first connecting portion 110 is provided between the peripheral common electrode line 02 and the common electrode 10 of the pixel unit 01 on the side close to the peripheral common electrode line 02, and is used to connect the peripheral common electrode line 02 and the common electrode 10 (that is, near the peripheral The common electrode of the pixel unit 01 on the side of the common electrode line 02 is electrically connected.
  • the first connection part 110 is along the first direction.
  • the second connecting portion 120 is provided between the common electrodes of every two adjacent pixel units 01 and is used to electrically connect the common electrodes 10 of the two adjacent pixel units.
  • the second connection part 120 is along the first direction.
  • first and the above-mentioned first direction may be a direction parallel to the gate line 100, and the second direction may be a direction perpendicular to the gate line 100, that is, a direction parallel to the data line 101; or, the first direction may be It is a direction parallel to the data line 101, and the second direction may be a direction parallel to the gate line 100.
  • the present invention does not limit this.
  • the first direction is a direction parallel to the gate line 100 and the second direction is a direction parallel to the data line 101 as an example.
  • the peripheral common electrode line 02 is arranged around the array substrate, it is close to the periphery To
  • the pixel unit 01 on the side of the common electrode line 02 may refer to a plurality of pixel units 01 located on the four edges of the array substrate and closest to the peripheral common electrode line 02 among all the pixel units 01 on the array substrate. Since the common electrode 10 of the pixel unit 01 and the peripheral common electrode line 02 are electrically connected through the first connecting portion 110, the common electrode 10 of the pixel unit 01 can receive the common voltage Vcom input by the peripheral common electrode line 02.
  • the above-mentioned pixel unit 01 further includes a pixel electrode 11.
  • the embodiment of the present invention does not limit the upper and lower positions of the common electrode 10 and the pixel electrode 11 arranged in different layers in the multiple stacked thin film layers on the array substrate.
  • the common electrode 10 is located at the lowest layer of the multiple stacked thin film layers on the array substrate, and the pixel electrode 11 is located at the top layer of the multiple stacked thin film layers on the array substrate; and the common electrode 10 It is a plate-shaped electrode and the pixel electrode 11 is a slit-shaped electrode as an example.
  • the embodiment of the present invention does not limit the upper and lower positions of the first connecting portion 110 and the second connecting portion 120 in the pixel unit 01 along the second direction.
  • the position of the first connecting portion 110 or the second connecting portion 120 may be set at the top of the pixel unit 01, or may be set at the center position of the pixel unit 01, or may be set Located at the bottom of pixel unit 01.
  • FIG. 2 the description is made with an example in which the first connecting portion 110 is provided at the bottom of the pixel unit 01 and the second connecting portion 120 is provided at the center of the pixel unit 01.
  • the first connection can be reduced as much as possible
  • the width of the first connecting portion 110 or the second connecting portion 120 in the second direction ie, the longitudinal dimension of the first connecting portion 110 or the second connecting portion 120.
  • the width of the first connecting portion 110 or the second connecting portion 120 in the second direction is 1/40 to 1/15 of the width of the pixel unit 10 in the second direction. Therefore, the larger the size of the pixel unit 10, the wider the width of the first connecting portion 110 or the second connecting portion 120, and vice versa.
  • the first connecting portion 110 may be extended to the peripheral common electrode line 02 as shown in FIG.
  • the peripheral common electrode line 02 is connected.
  • the array substrate may also include an additional line 150 as shown in FIG. 5, the additional line 150 being along the second direction (ie Parallel to the data line) is arranged on the peripheral common electrode line 02 and close to the outside To The common electrode 10 of the pixel unit 01 on the side surrounding the common electrode line 02 is connected to the peripheral common electrode line 02.
  • the above-mentioned first connecting portion 110 may be connected to the additional line 150 to achieve the purpose of electrically connecting the peripheral common electrode line 01 and the common electrode 10.
  • via holes may be made on the surface of the additional line 150 of the adjacent pixel unit 01 in the second direction, and conductive connecting lines may be formed at the via hole, so that the additional line 150 of the adjacent pixel unit 01 is electrically connected.
  • the above-mentioned connecting wire may include a transparent conductive material or a metal material.
  • the common electrode 10 and the additional line 150 can be separately produced through a common mask, so that the common electrode 10 and the additional line 150 located in the same pixel unit 01 have no overlapping part. In this way, the additional line 150 will be located in the non-display area of the pixel unit 01, so that the aperture ratio of the display device can be increased.
  • the first connection portion 110 and the additional wire 150 may be formed of a metal material.
  • the first connection part 110 and the additional line 150 may be the same layer and the same material as the gate line 100. Since the gate metal layer used to fabricate the gate line 100 is a common metal material in the art, the manufacturing process of the first connection portion 110 and the additional line 150 is easy to implement.
  • a patterning process can be used to complete the production of the first connection portion 110 and the additional line 150 while forming the gate line 100 .
  • the array substrate provided by the embodiment of the present invention includes a peripheral common electrode line for providing a common voltage and a plurality of pixel units, and also includes a plurality of first connection parts and second connection parts.
  • the first connecting portion is arranged along the first direction between the peripheral common electrode line and the common electrode of the pixel unit on the side close to the peripheral common electrode line (corresponding to the non-display area of the pixel unit), and is used to connect the peripheral common electrode line It is electrically connected to the above-mentioned common electrode.
  • the second connecting portion is disposed between the common electrodes of two adjacent pixel units (corresponding to the non-display area of the pixel unit) along the above-mentioned first direction, and is used to electrically connect the common electrodes of the two adjacent pixel units. . Because the common electrodes of all the pixel units are electrically connected to each other through the above-mentioned second connection portion, and the common electrode close to the peripheral common electrode line is electrically connected to the peripheral common electrode line through the first connection portion. Therefore, the peripheral common electrode line can provide the common voltage to all the common electrodes through the first connection part and the second connection part, so as to realize the purpose of applying the common voltage to the common electrode and controlling the deflection of the liquid crystal.
  • the first connecting part and the second To The connecting portions are all arranged in the non-display area of the pixel unit, so the aperture ratio of the display device will not be reduced.
  • a display device manufactured by using the above-mentioned array substrate can increase the aperture ratio while applying a common voltage to the common electrode, thereby improving product quality and display effect.
  • the common electrode 10 is generally made of a transparent conductive material.
  • a transparent conductive material For example, indium tin oxide (ITO) or indium zinc oxide. Since the conductivity of the above-mentioned transparent conductive material is lower than that of a metal material, the above-mentioned first connection portion 110 and the second connection portion 120 can be made of a metal material to increase the distance between the common electrode 10 and the peripheral common electrode line 02, as well as between the two The conductivity between the common electrodes 10 of different pixel units 01.
  • the first connection portion 110 and the second connection portion 120 may be the same layer and the same material as the gate line 100.
  • the gate metal layer used to fabricate the gate line 100 is a commonly used metal material in the art, the preparation process of the first connection portion 110 and the second connection portion 120 can be easily realized.
  • the first connection portion 110 and the second connection portion 120 can be formed with the same layer and the same material as the gate line 100, a patterning process can be used to complete the first connection portion 110, the second connection portion 110 and the second connection portion 110 while forming the gate line 100. Fabrication of the connecting portion 120.
  • the patterning process may be a process used to form a predetermined pattern such as photolithography, printing, and inkjet;
  • the photolithography process refers to processes including film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present invention.
  • the one-time patterning process in the embodiment of the present invention refers to a process in which a required layer structure is formed through one exposure using a mask.
  • the common voltage Vcom provided by the peripheral common electrode line 02 can be input to all the common electrodes 10 on the array substrate by providing the first connection portion 110 and the second connection portion 120 described above.
  • the first connection portion 110 and the second connection portion 120 both input the common voltage Vcom to the common electrode 10 along the first direction, the voltage input to different regions on the surface of the common electrode 10 may be uneven.
  • an area closer to the first connection portion 110 or the second connection portion 120 has a higher voltage
  • an area farther from the first connection portion 110 or the second connection portion 120 has a lower voltage.
  • it may cause the liquid crystal molecules that should be deflected at the same angle. Due to the uneven electric field between the common electrode 10 and the pixel electrode 11, there is a difference between the deflection angles. Therefore, it will cause the display screen to appear uneven brightness or flicker and other undesirable phenomena.
  • the embodiments of the present invention provide the following technical solutions.
  • the array substrate may further include a plurality of third connecting portions 130 along the second direction, To It is arranged between two adjacent pixel units 01 and is used to electrically connect the common electrodes 10 of the two adjacent pixel units 01.
  • the third connecting portion 130 may be made of a transparent conductive material.
  • a via hole (not shown in the figure) can be formed on the surface of the pixel electrode 11 at a position corresponding to the third connection portion 130, and then a third connection made of a transparent conductive material can be made.
  • the portion 130 electrically connects the common electrodes 10 of two adjacent pixel units 01 through the above-mentioned via holes.
  • the pixel electrode 11 is also made of transparent conductive material.
  • the above-mentioned third connecting portion 130 may also be made of a metal material.
  • the array substrate includes the data line 101, as shown in FIG. 3b (a cross-sectional view along A-A' in FIG. 3a).
  • the third connection portion 130 may include at least one first island 1301 of the same layer and the same material as the gate line 100, respectively disposed on the surface of the common electrode 10 of two adjacent pixel units. Specifically, the production of the first island 1301 and the second connection portion 120 can be completed while forming the gate line 100 through a single patterning process;
  • the first via 1302 located on the surface of the first island 1301;
  • a first jumper 1303 made of the same layer and the same material as the data line 101.
  • the data line 101 is generally made of a source-drain metal layer, so it is possible to complete the fabrication of the first jumper 1303 while forming the data line 101 through one patterning process.
  • the first jumper 1303 is along the second direction through the first via 1302 to electrically connect the common electrodes 10 of the two adjacent pixel units 01.
  • the array substrate may further include a plurality of fourth connecting portions 140, which are arranged on the peripheral common electrode line 02 and adjacent to the peripheral common electrode line 02 along the second direction. Between the common electrodes 10 of the pixel unit 01 on the side, the peripheral common electrode line 02 is electrically connected to the common electrode 10 of the aforementioned pixel unit 01.
  • the fourth connecting portion 140 can also be made of transparent conductive material.
  • the fourth connecting portion 140 may also be made of a metal material.
  • the array substrate includes the data line 101, as shown in FIG. 4b (a cross-sectional view along B-B' in FIG. 4a).
  • the fourth connection portion 140 may include a second island 1401 of the same layer and the same material as the gate line 100 and disposed on the surface of the common electrode 10 of the pixel unit 01 on the side close to the peripheral common electrode line 02.
  • a second jumper 1404 made of the same layer and the same material as the data line 101.
  • the data line 101 is generally made of a source-drain metal layer. Therefore, the second jumper 1404 can be completed while forming the data line 101 through one patterning process.
  • the second jumper 1404 is along the second direction, and electrically connects the peripheral common electrode line 02 with the common electrode 10 of the pixel unit 01 on the side of the peripheral common electrode line 02 through the second via 1402 and the third via 1403. .
  • the peripheral common electrode line 02 can not only provide the common voltage Vcom to the common electrode 10 of the pixel unit 01 on the side close to the peripheral common electrode line 02 in the second direction, but can also provide the common voltage Vcom to the peripheral common electrode line in the first direction.
  • the common electrode 10 of the pixel unit 01 on the side 02 provides a common voltage Vcom.
  • the uniformity of the voltage input to the common electrode 10 is further improved.
  • An embodiment of the present invention provides a display device, which includes any of the array substrates described above. It has the same beneficial effects as the array substrate in the foregoing embodiments. Since the detailed structure and beneficial effects of the array substrate have been described in detail in the foregoing embodiments, the details are not repeated here.
  • the display device may at least include a liquid crystal display device.
  • the display device can be any product or component with a display function, such as a liquid crystal display, a liquid crystal TV, a digital photo frame, a mobile phone or a tablet computer.
  • the embodiment of the present invention provides a manufacturing method of an array substrate, including a method of manufacturing a peripheral common electrode line 02 for providing a common voltage Vcom and a plurality of pixel units 01 arranged in a matrix.
  • the method includes the following steps.
  • a first connection is provided between the peripheral common electrode line 02 and the common electrode 10 of the pixel unit 01 on the side close to the peripheral common electrode line 02.
  • the portion 110 is used to electrically connect the peripheral common electrode line 02 and the above-mentioned common electrode 10 (ie, the common electrode of the pixel unit 01 on the side close to the peripheral common electrode line 02).
  • the above-mentioned method of providing the first connecting portion 110 between the peripheral common electrode line 02 and the common electrode 10 of the pixel unit 01 on the side close to the peripheral common electrode line 02 may include:
  • a first connecting portion 110 connected to the peripheral common electrode line 02 is formed.
  • an additional line connected to the peripheral common electrode line 02 can be formed between the peripheral common electrode line 02 and the common electrode 10 of the pixel unit 01 on the side close to the peripheral common electrode line 02 in the second direction.
  • 150 Specifically, via holes can be made on the surface of the additional lines 150 of adjacent pixel units 01 in the second direction, and conductive connecting lines can be formed at the via holes, wherein the above connecting lines may include transparent conductive materials or metal. material.
  • the additional lines 150 of the two adjacent pixel units 01 are electrically connected.
  • a first connecting portion 110 connected to the additional line 150 is formed between the additional line 150 and the common electrode 10 of the pixel unit 01 on the side close to the additional line 150, so as to electrically connect the peripheral common electrode line 01 and the common electrode 10. the goal of.
  • the first connection portion 110 and the additional wire 150 may be formed of a metal material.
  • the first connection part 110 and the additional line 150 may be the same layer and the same material as the gate line 100. Since the gate metal layer used to fabricate the gate line 100 is a common metal material in the art, the manufacturing process of the first connection portion 110 and the additional line 150 is easy to implement. Also, when the first connection part 110 and the additional line 150 can be the same as the gate line 100 To When the layers are formed with the same material, a patterning process can be used to form the gate line 100 while completing the production of the first connecting portion 110 and the additional line 150.
  • the common electrode 10 and the additional line 150 can be separately manufactured through a common mask, so that the common electrode 10 and the additional line 150 in the same pixel unit 01 have no overlapping part. In this way, the additional line 150 will be located in the non-display area of the pixel unit 01, so that the aperture ratio of the display device can be increased.
  • a second connecting portion 120 is formed between the common electrodes 10 of every two adjacent pixel units 01 for electrically connecting the common electrodes 10 of the foregoing two adjacent pixel units.
  • Step S101 may be performed first, and then step S102 may be performed.
  • step S102 may be performed first, and then step S101 may be performed.
  • step S101 and step S102 can also be performed at the same time.
  • the embodiment of the present invention provides a manufacturing method of an array substrate, including a method of manufacturing a peripheral common electrode line for providing a common voltage and a plurality of pixel units arranged in a matrix. It also includes forming a first connection part along the first direction between the peripheral common electrode line and the common electrode of the pixel unit on the side close to the peripheral common electrode line (corresponding to the non-display area of the pixel unit) to connect the peripheral common electrode line with the common electrode. The electrodes are electrically connected. In addition, in the first direction, a second connecting portion is formed between the common electrodes of every two adjacent pixel units (corresponding to the non-display area of the pixel unit) for electrically connecting the common electrodes of two adjacent pixel units .
  • the peripheral common electrode line can provide the common voltage to all the common electrodes through the first connection part and the second connection part, so as to realize the purpose of applying the common voltage to the common electrode and controlling the deflection of the liquid crystal.
  • the first connecting portion and the second connecting portion are formed in the non-display area of the pixel unit, the aperture ratio of the display device will not be reduced. In this way, a display device manufactured by using the above-mentioned array substrate can increase the aperture ratio while applying a common voltage to the common electrode, thereby improving product quality and display effect.
  • the common electrode 10 is generally made of a transparent conductive material.
  • a transparent conductive material For example, indium tin oxide (Indium Tin Oxide, ITO for short), indium zinc oxide, and the like. Due to the above-mentioned transparent conductive materials To The conductivity is lower than that of metal materials. Therefore, metal materials can be used to make the first connecting portion 110 and the second connecting portion 120 to increase the distance between the common electrode 10 and the peripheral common electrode line 02, and the common area between the two different pixel units 01.
  • the first connection portion 110 and the second connection portion 120 may be formed of the same layer and the same material as the gate line 100.
  • the gate metal layer used to fabricate the gate line 100 is a commonly used metal material in the art, the preparation process of the first connection portion 110 and the second connection portion 120 is easy to implement. Moreover, when the first connection portion 110 and the second connection portion 120 can be formed of the same layer and the same material as the gate line 100, a patterning process can be used to complete the first connection portion 110 and the second connection portion while forming the gate line 100. The production of section 120.
  • the method may include the following steps.
  • a common electrode layer 04 is formed on a base substrate 03.
  • the above-mentioned common electrode layer 04 may be made of a transparent conductive material, such as ITO.
  • the common electrode layer 04 can be deposited on the surface of the above-mentioned base substrate 03 by using a magnetron sputtering method.
  • the gate metal layer 05 may be formed on the surface of the common electrode layer 04 by coating or magnetron sputtering.
  • FIGS. 6b-6d are cross-sectional views along CC' of FIG. 3a, taking the second connecting portion 120 as an example for description, and the manufacturing process of the first connecting portion 110 can be similarly To obtain
  • a layer of photoresist 06 is coated on the surface of the gate metal layer 05, and a two-tone mask or a single-slit mask is used to form a first photoresist completely reserved area 200 after a single exposure and development process.
  • the first photoresist partially reserved area 201 and the first photoresist completely removed area (not shown in the figure).
  • the first photoresist fully reserved area 200 corresponds to the gate line 100 to be formed, the gate of a thin film transistor (TFT for short) (not shown in the figure), the first connection portion 110, and the second connection portion 120 patterns.
  • the first photoresist partially reserved area 201 corresponds to the pattern of the common electrode 10 to be formed.
  • the first photoresist completely removed area corresponds to the remaining area on the surface of the gate metal layer 05.
  • the two-tone mask is a semi-transparent mask, which can form two different thicknesses of photoresist 06 on the surface of the gate metal layer 05 (the first photoresist completely retains the photoresist in the region 200). Resist, the photoresist in the first photoresist partially reserved area 201).
  • the two-tone mask may include: gray-tone mask and half-tone mask.
  • an ashing process is used to remove the photoresist 06 in the first photoresist partially reserved area 201, and the gate metal layer 05 corresponding to the first photoresist partially reserved area 201 is etched.
  • the pattern of the common electrode 10 is formed. In this process, the thickness of the photoresist in the first photoresist completely reserved area 200 becomes thinner.
  • the common voltage Vcom provided by the peripheral common electrode line 02 can be input to all the common electrodes 10 on the array substrate.
  • the first connection portion 110 and the second connection portion 120 both input the common voltage Vcom to the common electrode 10 along the first direction, the voltage input to different regions on the surface of the common electrode 10 may be uneven. For example, an area closer to the first connection portion 110 or the second connection portion 120 has a higher voltage, and an area farther from the first connection portion 110 or the second connection portion 120 has a lower voltage.
  • it may cause the liquid crystal molecules that should be deflected at the same angle. Due to the uneven electric field between the common electrode 10 and the pixel electrode 11, there is a difference between the deflection angles. Therefore, it will cause the display screen to appear uneven brightness or flicker and other undesirable phenomena.
  • the embodiments of the present invention provide the following technical solutions.
  • the manufacturing method of the aforementioned array substrate may further include:
  • a plurality of third connecting portions 130 are formed between two adjacent pixel units 01 for electrically connecting the common electrodes 10 of the two adjacent pixel units 01.
  • the above-mentioned third connecting portion 130 may be made of a transparent conductive material.
  • a via hole (not shown in the figure) can be formed on the surface of the pixel electrode 11 at a position corresponding to the third connecting portion 130, and then a third connecting portion made of a transparent conductive material can be made 130. Electrically connect the common electrodes 10 of two adjacent pixel units 01 through the above-mentioned via holes.
  • the pixel electrode 11 is also made of transparent conductive material.
  • the above-mentioned third connecting portion 130 may also be made of a metal material.
  • the method of manufacturing the third connection portion 130 may include:
  • the first island 1301, the first via 1302, and the first jumper 1303 constitute the third connecting portion 130.
  • the first jumper 1303 electrically connects the common electrodes 10 of the two adjacent pixel units 01 along the second direction through the first via 1302.
  • the method of manufacturing the third connecting portion 130 may include:
  • Figure 7a (wherein Figures 7b-7d are cross-sectional views along AA' of Figure 3a, the cross-sectional view does not include the first connecting portion 110, but the same can be derived from the manufacturing method of the first connecting portion 110 )
  • Coat a layer of photoresist 06 on the surface of the gate metal layer 05 and form a second photoresist fully reserved area 300, a second photoresist partially reserved area 301, and a second photoresist after a single exposure and development process.
  • the resist completely removes the area (not shown in the figure).
  • the second photoresist fully reserved area 300 corresponds to the pattern of the gate line 100 to be formed, the gate of the TFT, the first connection portion 110, the second connection portion 120, and the first island 1301, and the second photoresist portion is reserved
  • the area 301 corresponds to the pattern of the common electrode 10 to be formed, and the second photoresist completely removed area corresponds to the remaining area on the surface of the gate metal layer 05.
  • the gate metal layer 05 and the common electrode layer 04 corresponding to the completely removed area of the second photoresist are etched.
  • an ashing process is used to remove the photoresist 06 in the second photoresist partially reserved area 301, and the gate metal layer 05 corresponding to the second photoresist partially reserved area 301 is etched , The pattern of the common electrode 10 is formed. In this process, the thickness of the second photoresist completely reserved area 300 is reduced.
  • the photoresist in the second photoresist completely reserved area 300 is stripped, and finally the gate line, the gate of the TFT, the first connection portion 110, the second connection portion 120, and the first connection portion are formed.
  • a gate insulating layer 07 is formed on the surface of the substrate on which the above-mentioned structure is formed.
  • an active layer 08 is formed on the surface of the gate insulating layer 07.
  • the above-mentioned active layer 08 may be composed of an a-Si layer and an n+a-Si layer.
  • the a-Si layer can be formed by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD) using the reactive gas silane (SiH4) and hydrogen (H2); then the reactive gas silane (SiH4) and phosphorus Hydrogen (PH3) forms an n+a-Si layer.
  • PECVD plasma enhanced chemical vapor deposition
  • n+a-Si layer is a phosphorus-doped semiconductor, it has the characteristics of high conductivity, which can reduce the active layer 8 and the source and drain metals formed on the surface of the active layer 8 in the following steps. Resistance between layers.
  • the above-mentioned active layer 08 may also be made of an oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide, which is indium gallium zinc oxide).
  • IGZO Indium Gallium Zinc Oxide, which is indium gallium zinc oxide.
  • ESL etching stop layer
  • a layer of photoresist 06 is coated on the surface of the active layer 08, and a third photoresist completely reserved area (not shown in the figure) is formed after a single exposure and development process.
  • the photoresist partially reserved area (not shown in the figure) and the third photoresist completely removed area 400.
  • the third photoresist completely reserved area corresponds to the pattern of the semiconductor active layer (not shown in the figure, located at the channel of the TFT) of the TFT to be formed.
  • the third photoresist completely removed area 400 corresponds to the pattern of the first via hole 1302 to be formed; the third photoresist partially reserved area corresponds to the remaining area on the surface of the active layer 08.
  • the active layer 08 and the gate insulating layer 07 corresponding to the third photoresist completely removed region 400 are etched.
  • the gate metal layer 07 is exposed to form a pattern of the first via 1302.
  • an ashing process is used to remove the photoresist 06 in the third photoresist partially reserved area, and then dry etching is used to etch the active layer of the third photoresist partially reserved area 400.
  • 08 is etched to expose the gate insulating layer film 07.
  • the photoresist in the completely reserved area of the third photoresist is stripped to form the semiconductor active layer of the TFT.
  • the source and drain metal layers are formed on the surface of the substrate forming the above structure, and the source and drain electrodes (not shown in the figure) of the TFT, the data line 101 and the first jumper 1303 are formed through a patterning process. picture of.
  • the preparation method of the array substrate may further include:
  • a plurality of fourth connecting portions 140 are formed between the peripheral common electrode line 02 and the pixel unit 01 on the side close to the peripheral common electrode line 02 for electrically connecting the peripheral common electrode line 02 and the above-mentioned common electrode 10 .
  • the fourth connecting portion 140 can also be made of a transparent conductive material.
  • the fourth connecting portion 140 may also be made of a metal material.
  • the method of manufacturing the fourth connection portion 140 may include:
  • the second island 1041, the second via hole 1042, the third via hole 1043, and the second jumper 1044 constitute the fourth connecting portion 140.
  • the second jumper 140 electrically connects the peripheral common electrode line 01 with the common electrode 10 of the pixel unit 01 on the side close to the peripheral common electrode line 02 through the second via hole 1042 and the third via hole 1043 along the second direction.
  • the detailed manufacturing process of the fourth connecting portion 140 can refer to the manufacturing process of the third connecting portion 130, which will not be repeated here.
  • the peripheral common electrode line 02 can not only provide the common voltage Vcom to the common electrode 10 of the pixel unit 01 on the side close to the peripheral common electrode line 02 in the second direction, but can also provide the common voltage Vcom to the peripheral common electrode line in the first direction.
  • the common electrode 10 of the pixel unit 01 on the side 02 provides a common power To Press Vcom.
  • the uniformity of the voltage input to the common electrode 10 is further improved.

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Abstract

提供一种阵列基板及其制备方法、显示装置。阵列基板包括用于提供公共电压的外围公共电极线（02）和多个像素单元（01），阵列基板还包括多个第一连接部（110）和第二连接部（120）。第一连接部（110）沿第一方向，设置于外围公共电极线（02）与靠近外围公共电极线（02）一侧像素单元（01）的公共电极（10）之间，用于将外围公共电极线（02）与公共电极（10）电连接。第二连接部（120）沿第一方向，设置于每两个相邻像素单元（01）的公共电极（10）之间，用于将两个相邻像素单元（01）的公共电极（10）电连接。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法、显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被使用。
TFT-LCD由阵列基板和彩膜基板构成。在阵列基板和彩膜基板之间设置液晶层，通过分别向设置于阵列基板上的像素电极、设置于彩膜基板或阵列基板上的公共电极施加电压，从而在液晶层中形成电场。然后，通过调节电场的幅值来调节穿过液晶层的光线的透射率，以获得预期的显示图像。
当上述公共电极和像素电极均设置在阵列基板上时，所述公共电极和所述像素电极可以异层设置，其中位于上层的电极为狭缝状电极，位于下层的电极为板状电极(或狭缝状电极)。采用上述阵列基板构成的显示装置为AD-SDS(Advanced-Super Dimensional Switching，简称为ADS，高级超维场开关)型显示装置。例如，如图1所示，公共电极10a为板状电极，像素电极11a为狭缝状电极，像素电极11a位于公共电极10a的上方。该显示装置通过同一平面内狭缝状电极(像素电极11a)边缘所产生的电场以及狭缝状电极(像素电极11a)与板状电极(公共电极10a)间形成多维电场，使液晶层内狭缝状电极间、电极正上方的所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光率。因此ADS型显示装置具有高画面品质、高分辨率、高透过率、低功耗、宽视角等优点。
在向每个像素单元1a的公共电极10a输入公共电压时，一般采用在栅线100a的至少一侧设置一条与所述栅线100a相平行的公共电极线101a，以连接位于同一行的多个像素单元1a的公共电极10a。通过上述公共电极线101a向所述公共电极10a提供公共电压。
然而，上述像素单元1a的显示区域的一部分被公共电极线101a占据， 从而降低了显示装置的开口率，对显示效果造成不利的影响。
发明内容
根据本发明的实施例，提供一种阵列基板。该阵列基板包括用于提供公共电压的外围公共电极线和多个像素单元。所述阵列基板还包括多个第一连接部和第二连接部。所述第一连接部沿第一方向，设置于所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间，用于将所述外围公共电极线与所述公共电极电连接。所述第二连接部沿所述第一方向，设置于每两个相邻所述像素单元的公共电极之间，用于将所述两个相邻像素单元的公共电极电连接。
根据本发明的实施例，提供一种显示装置。该显示装置包括如上所述的阵列基板。
根据本发明的实施例，提供一种阵列基板的制备方法。该制备方法包括制作用于提供公共电压的外围公共电极线和多个像素单元的方法。所述方法还包括：沿第一方向，在所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间形成第一连接部，用于将所述外围公共电极线与所述公共电极电连接；沿所述第一方向，在每两个相邻所述像素单元的公共电极之间形成第二连接部，用于将所述两个相邻像素单元的公共电极电连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为现有技术提供的一种阵列基板的结构示意图；
图2为本发明实施例提供的一种阵列基板的结构示意图；
图3a为本发明实施例提供的另一种阵列基板的结构示意图；
图3b为本发明实施例提供的另一种阵列基板的局部结构剖视图；
图4a为本发明实施例提供的另一种阵列基板的结构示意图；
图4b为本发明实施例提供的另一种阵列基板的局部结构剖视图；
图5为本发明实施例提供的又一种阵列基板的结构示意图；
图6a-6d为本发明实施例提供的一种阵列基板的局部结构的制作过程示意图；
图7a-7h为本发明实施例提供的另一种阵列基板的局部结构的制作过程示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种阵列基板。如图2所示，该阵列基板包括显示区域和位于显示区域外侧的非显示区域，在所述显示区域中多条栅线100和多条数据线101横纵交叉界定出多个呈矩阵形式排列的像素单元01，在非显示区域中设置有用于提供公共电压Vcom的外围公共电极线02。进一步地，该阵列基板还可以包括多个第一连接部110和第二连接部120。
上述第一连接部110设置于外围公共电极线02与靠近该外围公共电极线02一侧像素单元01的公共电极10之间，用于将外围公共电极线02与上述公共电极10(即靠近外围公共电极线02一侧像素单元01的公共电极)电连接。例如，第一连接部110沿第一方向。
上述第二连接部120设置于每两个相邻像素单元01的公共电极之间，用于将上述两个相邻像素单元的公共电极10电连接。例如，第二连接部120沿第一方向。
需要说明的是，第一、上述第一方向可以是平行于栅线100的方向，第二方向可以是垂直于栅线100的方向，即平行于数据线101的方向；或者，第一方向可以是平行于数据线101的方向，第二方向可以是平行于栅线100的方向。本发明对此不作限制。但在以下的实施例中，均是以，第一方向为平行于栅线100的方向，第二方向为平行于数据线101的方向为例进行的说明。
第二、由于外围公共电极线02设置于阵列基板的四周，因此靠近该外围 公共电极线02一侧像素单元01可以是指，阵列基板上的所有像素单元01中位于所述阵列基板四个边缘且距离上述外围公共电极线02最近的多个像素单元01。由于，上述像素单元01的公共电极10与外围公共电极线02通过第一连接部110电连接，因此通过上述像素单元01的公共电极10可以接收外围公共电极线02输入的公共电压Vcom。
第三、上述像素单元01还包括像素电极11，本发明实施例对异层设置的公共电极10和像素电极11在阵列基板上多个堆叠的薄膜层中的上、下位置不作限定。但是在本发明的实施例中，均是以公共电极10位于阵列基板上多个堆叠的薄膜层的最下层，像素电极11位于阵列基板上多个堆叠的薄膜层的最上层；且公共电极10为板状电极，像素电极11为狭缝状电极为例进行的说明。
第四、本发明实施例对第一连接部110和第二连接部120在像素单元01内沿第二方向的上、下位置不做限定。例如，对于第一行的像素单元01而言，第一连接部110或第二连接部120的位置可以设置于像素单元01的最上方，也可以设置于像素单元01的中心位置，还可以设置于像素单元01的最下方。图2中，是以第一连接部110设置于像素单元01的最下方，第二连接部120设置于像素单元01的中心位置为例进行的说明。
第五、在保证不同的像素单元01的公共电极10之间电连接稳定性，以及公共电极10与外围公共电极线02之间电连接稳定性的前提下，可以尽可能的减小第一连接部110或第二连接部120沿第二方向的宽度(即第一连接部110或第二连接部120的纵向尺寸)。优选的，第一连接部110或第二连接部120沿第二方向的宽度为像素单元10沿第二方向宽度的1/40～1/15。因此，像素单元10的尺寸越大，第一连接部110或第二连接部120的宽度可以越宽，反之同理。
第六、为了使得第一连接部110能够将外围公共电极线01与公共电极10电连接，可以如图2所示，将第一连接部110延伸至所述外围公共电极线02处，并与外围公共电极线02相连接。
或者，为了使得第一连接部110能够将外围公共电极线01与公共电极10电连接，还可以如图5所示使阵列基板包括附加线150，该附加线150沿所述第二方向(即平行于数据线的方向)设置于外围公共电极线02与靠近外 围公共电极线02一侧像素单元01的公共电极10之间且与外围公共电极线02相连接。上述第一连接部110可以与该附加线150相连接，以达到将外围公共电极线01与公共电极10电连接的目的。
例如，可以分别在第二方向上的相邻像素单元01的附加线150的表面制作过孔，并在过孔处形成能够导电的连接线，使得所述相邻像素单元01的附加线150电连接。例如，上述连接线可以包括透明导电材料或金属材料。
需要说明的是，可以通过普通的掩膜版分别制作公共电极10和附加线150，使得位于同一个像素单元01中的公共电极10与附加线150无重叠的部分。这样一来，附加线150就会位于像素单元01的非显示区域，从而能够增大显示装置的开口率。
进一步地，为了提高第一连接部110以及附加线150的导电率，可以采用金属材料构成上述第一连接部110以及附加线150。例如，第一连接部110和附加线150可以与栅线100同层同材料。由于，用于制作栅线100的栅极金属层为本领域的常用金属材料，因此使得第一连接部110和附加线150的制备过程容易实现。并且，当第一连接部110和附加线150与栅线100同层同材料设置形成时，能够采用一次构图工艺，在形成栅线100的同时，完成第一连接部110和附加线150的制作。
以上仅仅是对通过第一连接部110将外围公共电极线01与公共电极10进行电连接的举例说明，其它电连接方式在此不再一一举例。
本发明实施例提供的阵列基板包括用于提供公共电压的外围公共电极线和多个像素单元,还包括多个第一连接部和第二连接部。其中，第一连接部沿第一方向，设置于上述外围公共电极线与靠近外围公共电极线一侧像素单元的公共电极之间(对应像素单元的非显示区域)，用于将外围公共电极线与上述公共电极电连接。此外，第二连接部沿上述第一方向，设置于两个相邻像素单元的公共电极之间(对应像素单元的非显示区域)，用于将上述两个相邻像素单元的公共电极电连接。由于，所有像素单元的公共电极均通过上述第二连接部相互电连接，而靠近所述外围公共电极线的公共电极通过第一连接部与所述外围公共电极线电连接。因此，外围公共电极线可以将公共电压通过第一连接部、第二连接部提供至所有公共电极，以实现向公共电极施加公共电压，控制液晶偏转的目的。与此同时，因为上述第一连接部与第二 连接部均设置于像素单元的非显示区域，因此不会降低显示装置的开口率。这样一来，采用上述阵列基板制作的显示装置，在向公共电极施加公共电压的同时，能够增大开口率，提高产品质量和显示效果。
公共电极10一般采用透明导电材料构成。例如，氧化铟锡(Indium Tin Oxide，简称ITO)或氧化铟锌等。由于上述透明导电材料的导电率小于金属材料，因此，可以采用金属材料制作上述第一连接部110和第二连接部120，以增加公共电极10与外围公共电极线02之间，以及位于两个不同像素单元01的公共电极10之间的导电率。例如，第一连接部110、第二连接部120可以与栅线100同层同材料。由于，用于制作栅线100的栅极金属层为本领域的常用金属材料，因此可以使得第一连接部110、第二连接部120的制备过程容易实现。并且，当第一连接部110、第二连接部120可以与栅线100同层同材料设置形成时，能够采用一次构图工艺，在形成栅线100的同时，完成第一连接部110、第二连接部120的制作。
需要说明的是，在本发明的实施例中，构图工艺可以是光刻工艺、打印、喷墨等用于形成预定图形的工艺；光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明实施例中所形成的结构选择相应的构图工艺。本发明实施例中的一次构图工艺是指采用一块掩模板经过一次曝光形成所需要的层结构的工艺。
综上所述，通过设置上述第一连接部110和第二连接部120可以将所述外围公共电极线02提供的公共电压Vcom输入至阵列基板上的所有公共电极10。然而，由于第一连接部110和第二连接部120均是沿第一方向将公共电压Vcom输入至公共电极10，因此会使得公共电极10表面上的不同区域输入的电压不均匀。例如，距离第一连接部110或第二连接部120较近的区域电压大，距离第一连接部110或第二连接部120较远的区域电压小。这样一来，在控制液晶发生偏转时，可能会使得应当偏转同一角度的液晶分子，由于公共电极10与像素电极11之间电场的不均匀，而使其偏转角度之间存在差异。因此会导致显示画面出现亮度不均或闪烁等等的不良现象。
为了解决上述问题，本发明实施例提供了以下技术方案。
实施例一
如图3a所示，阵列基板还可以包括多个第三连接部130，沿第二方向， 设置于两个相邻像素单元01之间，用于将上述两个相邻像素单元01的公共电极10电连接。
具体的，上述第三连接部130可以采用透明导电材料构成。当第三连接部130采用透明导电材料构成时，可以在像素电极11的表面对应第三连接部130的位置形成过孔(图中未示出)，然后制作采用透明导电材料构成的第三连接部130，通过上述过孔将两个相邻的像素单元01的公共电极10电连接。但是由于像素电极11同样为透明导电材料构成。因此还需要在第三连接部130与像素电极11之间形成绝缘层，并且为了防止过孔处的像素电极与第三连接部130电连接，还需要通过构图工艺将上述过孔周边的一部分像素电极去除掉。
或者，为了提高第三连接部130的导电率，上述第三连接部130还可以由金属材料构成。
例如，在阵列基板包括数据线101的情况下，如图3b(图3a沿A—A’的剖视图)所示。
第三连接部130可以包括分别设置于两个相邻像素单元的公共电极10表面，与栅线100同层同材料的至少一个第一孤岛1301。具体的，可以通过一次构图工艺在形成栅线100的同时完成第一孤岛1301和第二连接部120的制作；
位于第一孤岛1301表面的第一过孔1302；
以及与数据线101同层同材料的第一跨线1303。具体的，数据线101一般采用源漏金属层制成，因此可以通过一次构图工艺在形成数据线101的同时，完成第一跨线1303的制作。
其中，第一跨线1303沿第二方向，通过第一过孔1302，将上述两个相邻像素单元01的公共电极10电连接。
这样一来，不仅沿第一方向上的相邻两个像素单元01的公共电极10电连接，沿第二方向上的相邻两个像素单元01的公共电极10也电连接。从而使得输入至公共电极10的公用电压Vcom更加的均匀。解决了上述由于公用电压Vcom不均匀而导致显示画面出现亮度不均或闪烁等等的不良现象的问题。
实施例二
如图4a所示，可以在实施例一的基础上，所述阵列基板还可以包括多个第四连接部140，沿第二方向，设置于外围公共电极线02与靠近外围公共电极线02一侧的像素单元01的公共电极10之间，用于将外围公共电极线02与上述像素单元01的公共电极10电连接。
如同实施例一的第三连接部130，第四连接部140也可以采用透明导电材料构成。
或者，为了提高第四连接部140的导电率，上述第四连接部140还可以由金属材料构成。
例如，在所述阵列基板包括数据线101的情况下，如图4b(图4a沿B—B’的剖视图)所示。
第四连接部140可以包括设置于靠近外围公共电极线02一侧像素单元01的公共电极10表面，与栅线100同层同材料的第二孤岛1401。
位于第二孤岛1401表面的第二过孔1402以及位于外围公共电极线02表面的第三过孔1403；
以及与数据线101同层同材料的第二跨线1404。具体的，数据线101一般采用源漏金属层制成，因此可以通过一次构图工艺在形成数据线101的同时，完成第二跨线1404的制作。
其中，第二跨线1404沿第二方向，通过第二过孔1402、第三过孔1403，将外围公共电极线02与靠近该外围公共电极线02一侧像素单元01的公共电极10电连接。
这样一来，外围公共电极线02不仅可以向沿第二方向靠近该外围公共电极线02一侧像素单元01的公共电极10提供公共电压Vcom，还可以向沿第一方向靠近该外围公共电极线02一侧像素单元01的公共电极10提供公共电压Vcom。从而更进一步地提高了输入公共电极10电压的均匀性。解决了上述由于公用电压Vcom不均匀而导致显示画面出现亮度不均或闪烁等等的不良现象的问题。
本发明实施例提供一种显示装置，包括如上所述的任意一种阵列基板。具有与前述实施例中的阵列基板相同的有益效果，由于阵列基板的详细结构以及有益效果已在前述实施例中做了详细的描述，此处不再赘述。
需要说明的是，在本发明实施例中，显示装置至少可以包括液晶显示装 置和有机发光二极管显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本发明实施例提供一种阵列基板的制备方法，包括制作用于提供公共电压Vcom的外围公共电极线02和呈矩阵形式排列的多个像素单元01的方法。例如，该方法包括以下步骤。
S101、如图2所示，沿第一方向(平行于栅线100的方向)，在外围公共电极线02与靠近外围公共电极线02一侧像素单元01的公共电极10之间设置第一连接部110，用于将外围公共电极线02与上述公共电极10(即靠近外围公共电极线02一侧像素单元01的公共电极)电连接。
需要说明的是，为了使得第一连接部110能够将外围公共电极线01与公共电极10电连接。上述在外围公共电极线02与靠近外围公共电极线02一侧像素单元01的公共电极10之间设置第一连接部110的方法可以包括：
如图2所示，在外围公共电极线02与靠近外围公共电极线02一侧像素单元01的公共电极10之间，形成与外围公共电极线02相连接的第一连接部110。
或者，
如图5所示，可以先沿第二方向，在外围公共电极线02与靠近外围公共电极线02一侧像素单元01的公共电极10之间，形成与外围公共电极线02相连接的附加线150。具体的，可以分别在第二方向上的相邻像素单元01的附加线150的表面制作过孔，并在过孔处形成能够导电的连接线，其中，上述连接线可以包括透明导电材料或金属材料。使得所述两个相邻像素单元01的附加线150电连接。
然后，在附加线150与靠近附加线150一侧像素单元01的公共电极10之间形成与附加线150相连接的第一连接部110，以达到将外围公共电极线01与公共电极10电连接的目的。
此外、为了提高第一连接部110以及附加线150的导电率，可以采用金属材料构成上述第一连接部110以及附加线150。例如，第一连接部110和附加线150可以与栅线100同层同材料。由于，用于制作栅线100的栅极金属层为本领域的常用金属材料，因此使得第一连接部110和附加线150的制备过程容易实现。并且，当第一连接部110和附加线150可以与栅线100同 层同材料设置形成时，能够采用一次构图工艺，在形成栅线100的同时，完成第一连接部110和附加线150的制作。
需要说明的是，在制作过程中，可以通过普通的掩膜版分别制作公共电极10和附加线150，使得位于同一个像素单元01中的公共电极10与附加线150无重叠的部分。这样一来，附加线150就会位于像素单元01的非显示区域，从而能够增大显示装置的开口率。
上述仅仅是对第一连接部110的制作方法的举例说明，其它制作方法在此不再一一举例。
S102、沿上述第一方向，在每两个相邻像素单元01的公共电极10之间形成第二连接部120，用于将上述两个相邻像素单元的公共电极10电连接。
需要说明的是，本发明实施例对上述步骤S101和步骤S102制作顺序不作限制。可以先进行步骤S101，后进行步骤S102。或者，可以先进行步骤S102，后进行步骤S101。或者当第一连接部110和第二连接部120为同层同材料形成时，还可以同时进行步骤S101和步骤S102。
本发明实施例提供一种阵列基板的制备方法，包括制作用于提供公共电压的外围公共电极线和呈矩阵形式排列的多个像素单元的方法。还包括沿第一方向，在外围公共电极线与靠近外围公共电极线一侧像素单元的公共电极之间(对应像素单元的非显示区域)形成第一连接部，以将外围公共电极线与公共电极电连接。此外，所述第一方向，在每两个相邻像素单元的公共电极之间(对应像素单元的非显示区域)形成第二连接部，用于将两个相邻像素单元的公共电极电连接。由于，所有像素单元的公共电极均通过上述第二连接部相互电连接，而靠近所述外围公共电极线的公共电极通过第一连接部与所述外围公共电极线电连接。因此，外围公共电极线可以将公共电压通过第一连接部、第二连接部提供至所有公共电极，以实现向公共电极施加公共电压，控制液晶偏转的目的。与此同时，因为上述第一连接部与第二连接部均形成于像素单元的非显示区域，因此不会降低显示装置的开口率。这样一来，采用上述阵列基板制作的显示装置，在向公共电极施加公共电压的同时，能够增大开口率，提高产品质量和显示效果。
需要说明的是，公共电极10一般采用透明导电材料构成。例如，氧化铟锡(Indium Tin Oxide，简称ITO)、氧化铟锌等。由于上述透明导电材料的 导电率小于金属材料，因此，可以采用金属材料制作上述第一连接部110和第二连接部120，以增加公共电极10与外围公共电极线02之间，以及位于两个不同像素单元01的公共电极10之间的导电率。例如，第一连接部110、第二连接部120可以与栅线100同层同材料形成。由于，用于制作栅线100的栅极金属层为本领域的常用金属材料，因此使得第一连接部110、第二连接部120的制备过程容易实现。并且，当第一连接部110、第二连接部120可以与栅线100同层同材料形成时，能够采用一次构图工艺，在形成栅线100的同时，完成第一连接部110、第二连接部120的制作。
具体的，当第一连接部110、第二连接部120与栅线100同层同材料形成时，所述方法可以包括以下步骤。
S201、如图6a所示，在衬底基板03上形成公共电极层04。
上述公共电极层04可以为透明导电材料，例如ITO构成。可以采用磁控溅射法将公共电极层04沉积于上述衬底基板03的表面。
S202、在上述公共电极层04的表面形成栅极金属层05。
上述栅极金属层05可以通过涂覆或磁控溅射法形成于公共电极层04的表面。
S203、如图6b所示(其中，图6b—6d为沿图3a的C—C’的剖视图，是以第二连接部120为例进行的说明，第一连接部110的制作过程同理可得)，在栅极金属层05的表面涂覆一层光刻胶06，采用双色调掩膜版或单狭缝掩膜版通过一次曝光显影工艺后形成第一光刻胶完全保留区域200、第一光刻胶部分保留区域201和第一光刻胶完全去除区域(图中未示出)。
其中，第一光刻胶完全保留区域200对应待形成的栅线100、薄膜晶体管(Thin Film Transistor，简称TFT)的栅极(图中未示出)、第一连接部110以及第二连接部120的图案。所述第一光刻胶部分保留区域201对应待形成的公共电极10的图案。所述第一光刻胶完全去除区域对应该栅极金属层05表面的其余区域。
需要说明的是，双色调掩膜版为一种半透式掩膜版，可以在栅极金属层05表面形成两种不同厚度的光刻胶06(第一光刻胶完全保留区域200的光刻胶、第一光刻胶部分保留区域201的光刻胶)。该双色调掩膜版可以包括：灰色调掩膜版(Gray-tone mask)和半色调掩膜版(Half-tone mask)。
S204、刻蚀对应第一光刻胶完全去除区域的栅极金属层05、所述公共电极层04。
S205、如图6c所示，采用灰化工艺去除第一光刻胶部分保留区域201的光刻胶06，并对第一光刻胶部分保留区域201对应的栅极金属层05进行刻蚀，形成公共电极10的图案。在此过程中，第一光刻胶完全保留区域200的光刻胶的厚度变薄。
S206、如图6d所示，对第一光刻胶完全保留区域200的光刻胶06进行剥离，最终形成栅线100、TFT的栅极、第一连接部110(如图3a所示)以及第二连接部120的图案。
综上所述，通过形成上述第一连接部110和第二连接部120可以将所述外围公共电极线02提供的公共电压Vcom输入至阵列基板上的所有公共电极10。然而，由于第一连接部110和第二连接部120均是沿第一方向将公共电压Vcom输入至公共电极10，因此会使得公共电极10表面上的不同区域输入的电压不均匀。例如，距离第一连接部110或第二连接部120较近的区域电压大，距离第一连接部110或第二连接部120较远的区域电压小。这样一来，在控制液晶发生偏转时，可能会使得应当偏转同一角度的液晶分子，由于公共电极10与像素电极11之间电场的不均匀，而使其偏转角度之间存在差异。因此会导致显示画面出现亮度不均或闪烁等等的不良现象。
为了解决上述问题，本发明实施例提供如下技术方案。
实施例三
例如，上述阵列基板的制备方法还可以包括：
如图3a所示，沿第二方向，在两个相邻像素单元01之间形成多个第三连接部130，用于将上述两个相邻像素单元01的公共电极10电连接。
例如，上述第三连接部130可以采用透明导电材料构成。当第三连接部130采用透明导电材料构成时可以在像素电极11的表面对应第三连接部130的位置形成过孔(图中未示出)，然后制作采用透明导电材料构成的第三连接部130，通过上述过孔将两个相邻的像素单元01的公共电极10电连接。但是由于像素电极11同样为透明导电材料构成。因此还需要在第三连接部130与像素电极11之间形成绝缘层，并且为了防止过孔处的像素电极与第三连接部130电连接，还需要通过构图工艺将上述过孔周边的一部分像素电极 去除掉。
或者，为了提高第三连接部130的导电率，上述第三连接部130还可以由金属材料构成。例如在阵列基板包括数据线101的情况下，制作上述第三连接部130的方法可以包括：
S301、在两个相邻像素电极01的公共电极10的表面，分别形成与栅线100同层同材料的第一孤岛1301；
S302、在第一孤岛1301的表面形成第一过孔1302；
S303、在第一过孔1302的表面形成与数据线101同层同材料的第一跨线1303。
其中，上述第一孤岛1301、第一过孔1302以及第一跨线1303构成上述第三连接部130。第一跨线1303沿第二方向，通过第一过孔1302，将上述两个相邻像素单元01的公共电极10电连接。
这样一来，不仅沿第一方向上的相邻两个像素单元01的公共电极10电连接，沿第二方向上的相邻两个像素单元01的公共电极10也电连接。从而使得输入至公共电极10的公用电压Vcom更加的均匀。解决了上述由于公用电压Vcom不均匀而导致显示画面出现亮度不均或闪烁等等的不良现象的问题。
实施例四
上述步骤S202之后，制作第三连接部130的方法，可以包括：
首先、如图7a所示(其中，图7b—7d为沿图3a的A—A’的剖视图，剖视图中未包含第一连接部110，但同理可得出第一连接部110的制作方法)在所述栅极金属层05的表面涂覆一层光刻胶06，通过一次曝光显影工艺后形成第二光刻胶完全保留区域300、第二光刻胶部分保留区域301和第二光刻胶完全去除区域(图中未示出)。
其中，第二光刻胶完全保留区域300对应待形成的栅线100、TFT的栅极、第一连接部110、第二连接部120以及第一孤岛1301的图案，第二光刻胶部分保留区域301对应待形成的公共电极10的图案，第二光刻胶完全去除区域对应栅极金属层05表面的其余区域。
接下来、刻蚀对应第二光刻胶完全去除区域的栅极金属层05、公共电极层04。
接下来、如图7b所示，采用灰化工艺去除第二光刻胶部分保留区域301的光刻胶06，并对第二光刻胶部分保留区域301对应的栅极金属层05进行刻蚀，形成公共电极10的图案。在此过程中，第二光刻胶完全保留区域300的厚度减薄。
接下来、如图7c所示，对第二光刻胶完全保留区域300的光刻胶进行剥离，最终形成栅线、TFT的栅极、第一连接部110、第二连接部120以及第一孤岛1301的图案。
接下来、如图7d所示，在形成有上述结构的基板表面制作栅极绝缘层07。
接下来、在上述栅极绝缘层07的表面制作有源层08。其中，上述有源层08可以由a-Si层和n+a-Si层构成。具体的可以通过等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)采用反应气体硅烷(SiH4)和氢气(H2)形成上述a-Si层；然后采用反应气体硅烷(SiH4)和磷化氢(PH3)形成n+a-Si层。这样一来，由于n+a-Si层为磷掺杂半导体， 因此其具有导电率高的特点，能够减少有源层8与接下来的步骤中形成于该有源层8表面的源漏金属层之间的电阻。
此外，上述有源层08还可以由氧化物半导体材料构成，例如IGZO(Indium Gallium Zinc Oxide，为铟镓锌氧化物)。当采用IGZO制作有源层08时，由于IGZO对氧气或氢离子较为敏感，并且对位于有源层08表面的源漏金属层进行湿法刻蚀时，会对IGZO产生影响。因此一般需要在IGZO的表面制作刻蚀阻挡层(Etch Stopper Lay，简称ESL)以对IGZO进行保护。
接下来、如图7e所示，在有源层08的表面涂覆一层光刻胶06，通过一次曝光显影工艺后形成第三光刻胶完全保留区域(图中未示出)、第三光刻胶部分保留区域(图中未示出)和第三光刻胶完全去除区域400。
其中，第三光刻胶完全保留区域对应待形成的TFT的半导体有源层(图中未示出，位于TFT的沟道处)的图案。第三光刻胶完全去除区域400对应待形成的第一过孔1302的图案；第三光刻胶部分保留区域对应有源层08表面的其余区域。
接下来、如图7f所示，刻蚀对应第三光刻胶完全去除区域400的有源层08和栅极绝缘层07。露出栅极金属层07以形成第一过孔1302的图案。
接下来、如图7g所示，利用灰化工艺去除第三光刻胶部分保留区域的光刻胶06，然后采用干法刻蚀法对上述第三光刻胶部分保留区域400的有源层08进行刻蚀，露出栅极绝缘层薄膜07。最后对第三光刻胶完全保留区域的光刻胶进行剥离，以形成TFT的半导体有源层。
最后、如图7h所示，在形成上述结构的基板表面制作源漏金属层，通过一次构图工艺形成TFT的源极、漏极(图中未示出)、数据线101以及第一跨线1303的图案。
在上述实施例四的基础上，所述阵列基板的制备方法还可以包括：
沿第二方向，在外围公共电极线02与靠近外围公共电极线02一侧的像素单元01之间形成多个第四连接部140，用于将外围公共电极线02与上述公共电极10电连接。
如同第三连接部130，第四连接部140也可以采用透明导电材料构成。
或者，为了提高第四连接部140的导电率，上述第四连接部140还可以由金属材料构成。例如，在阵列基板包括数据线101的情况下，制作第四连接部140的方法可以包括：
S401、在靠近外围公共电极线02一侧像素单元01的公共电极10表面，形成与栅线100同层同材料的第二孤岛1041。
S402、在第二孤岛1041的表面形成第二过孔1042。
S403、在外围公共电极线02表面形成第三过孔1043。
S404、在第二过孔1042和第三过孔1043的表面形成与数据线101同层同材料的第二跨线1044。
其中，第二孤岛1041、第二过孔1042、第三过孔1043以及第二跨线1044构成上述第四连接部140。第二跨线140沿第二方向，通过第二过孔1042、第三过孔1043，将外围公共电极线01与靠近外围公共电极线02一侧像素单元01的公共电极10电连接。
其中，第四连接部140的详细制作过程可以参考第三连接部130的制作过程，此处不再赘述。
这样一来，外围公共电极线02不仅可以向沿第二方向靠近该外围公共电极线02一侧像素单元01的公共电极10提供公共电压Vcom，还可以向沿第一方向靠近该外围公共电极线02一侧像素单元01的公共电极10提供公共电 压Vcom。从而更进一步地提高了输入公共电极10电压的均匀性。解决了上述由于公用电压Vcom不均匀而导致显示画面出现亮度不均或闪烁等等的不良现象的问题。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年8月28日递交的第201410431286.9号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种阵列基板，包括用于提供公共电压的外围公共电极线和多个像素单元，其中
    所述阵列基板还包括多个第一连接部和第二连接部；
    所述第一连接部沿第一方向，设置于所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间，用于将所述外围公共电极线与所述公共电极电连接；
    所述第二连接部沿所述第一方向，设置于每两个相邻所述像素单元的公共电极之间，用于将所述两个相邻像素单元的公共电极电连接。
  2. 根据权利要求1所述的阵列基板，其中
    所述阵列基板还包括栅线，所述第一连接部、所述第二连接部与所述栅线同层同材料。
  3. 根据权利要求1或2所述的阵列基板，其中
    所述阵列基板还包括多个第三连接部，沿第二方向，设置于两个相邻所述像素单元之间，用于将所述两个相邻像素单元的公共电极电连接。
  4. 根据权利要求3所述的阵列基板，其中
    所述阵列基板还包括数据线；
    所述第三连接部包括：分别设置于所述两个相邻像素单元的公共电极表面，与所述栅线同层同材料的第一孤岛；位于所述第一孤岛表面的第一过孔；与所述数据线同层同材料的第一跨线；
    所述第一跨线沿所述第二方向，通过所述第一过孔，将所述两个相邻像素单元的公共电极电连接。
  5. 根据权利要求1或2所述的阵列基板，其中
    所述阵列基板还包括多个第四连接部，沿所述第二方向，设置于所述外围公共电极线与靠近所述外围公共电极线一侧的像素单元的公共电极之间，用于将所述外围公共电极线与所述公共电极电连接。
  6. 根据权利要求5所述的阵列基板，其中
    所述阵列基板还包括数据线；
    所述第四连接部包括：设置于靠近所述外围公共电极线一侧像素单元的 公共电极表面，与所述栅线同层同材料的第二孤岛；位于所述第二孤岛表面的第二过孔以及位于所述外围公共电极线表面的第三过孔；与所述数据线同层同材料的第二跨线；
    所述第二跨线沿第二方向，通过所述第二过孔、第三过孔，将所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极电连接。
  7. 根据权利要求1所述的阵列基板，其中所述第一连接部与所述外围公共电极线直接相连接。
  8. 根据权利要求1所述的阵列基板，其中
    所述阵列基板还包括沿所述第二方向，设置于所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间的，与所述外围公共电极线相连接的附加线；
    所述第一连接部与所述附加线相连接。
  9. 根据权利要求1所述的阵列基板，其中
    所述第一连接部或第二连接部沿所述第二方向的宽度为所述像素单元沿所述第二方向宽度的1/40～1/15。
  10. 一种显示装置，包括如权利要求1-9任一项所述的阵列基板。
  11. 一种阵列基板的制备方法，包括制作用于提供公共电压的外围公共电极线和多个像素单元的方法，其中所述方法还包括：
    沿第一方向，在所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间形成第一连接部，用于将所述外围公共电极线与所述公共电极电连接；
    沿所述第一方向，在每两个相邻所述像素单元的公共电极之间形成第二连接部，用于将所述两个相邻像素单元的公共电极电连接。
  12. 根据权利要求11所述的阵列基板的制备方法，其中
    所述阵列基板还包括栅线，
    所述第一连接部和所述第二连接部与所述栅线同层同材料形成。
  13. 根据权利要求11或12所述的阵列基板的制备方法，其中
    所述阵列基板还包括：沿第二方向，在两个相邻所述像素单元之间形成多个第三连接部，用于将所述两个相邻像素单元的公共电极电连接。
  14. 根据权利要求13所述的阵列基板的制备方法，其中
    所述阵列基板还包括数据线；
    制作所述第三连接部的方法包括：在所述两个相邻像素电极的公共电极的表面，分别形成与所述栅线同层同材料的第一孤岛；在所述第一孤岛的表面形成第一过孔；在所述第一过孔的表面形成与所述阵列基板的数据线同层同材料的第一跨线；
    所述第一孤岛、所述第一过孔以及所述第一跨线构成所述第三连接部；所述第一跨线沿第二方向，通过所述第一过孔，将所述两个相邻像素单元的公共电极电连接。
  15. 根据权利要求11或12所述的阵列基板的制备方法，其中
    所述方法还包括：沿所述第二方向，在所述外围公共电极线与靠近所述外围公共电极线一侧的像素单元的公共电极之间形成多个第四连接部，用于将所述外围公共电极线与所述公共电极电连接。
  16. 根据权利要求15所述的阵列基板的制备方法，其中
    所述阵列基板包括所述数据线；
    制作所述第四连接部的方法包括：在靠近所述外围公共电极线一侧像素单元的公共电极表面，形成与所述栅线同层同材料的第二孤岛；在所述第二孤岛的表面形成第二过孔；在所述外围公共电极线表面形成第三过孔；在所述第二过孔和所述第三过孔的表面形成与所述数据线同层同材料的第二跨线；
    所述第二孤岛、所述第二过孔、所述第三过孔以及所述第二跨线构成所述第四连接部；所述第二跨线沿第二方向，通过所述第二过孔、所述第三过孔，将所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极电连接。
  17. 根据权利要求11所述的阵列基板的制备方法，其中所述在所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间形成第一连接部的方法包括：
    在所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间形成与所述外围公共电极线直接相连接的所述第一连接部。
  18. 根据权利要求11所述的阵列基板的制备方法，其中所述在所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间形成第 一连接部的方法包括：
    沿第二方向，在所述外围公共电极线与靠近所述外围公共电极线一侧像素单元的公共电极之间，形成与所述外围公共电极线相连接的附加线；
    在所述附加线与靠近所述附加线一侧像素单元的公共电极之间形成与所述附加线相连接的所述第一连接部。
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