WO2016029830A1 - 薄膜晶体管装置、显示器及其制造方法 - Google Patents

薄膜晶体管装置、显示器及其制造方法 Download PDF

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WO2016029830A1
WO2016029830A1 PCT/CN2015/087934 CN2015087934W WO2016029830A1 WO 2016029830 A1 WO2016029830 A1 WO 2016029830A1 CN 2015087934 W CN2015087934 W CN 2015087934W WO 2016029830 A1 WO2016029830 A1 WO 2016029830A1
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Prior art keywords
conductive layer
layer
thin film
film transistor
transistor device
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English (en)
French (fr)
Inventor
魏鹏
余晓军
袁泽
赵继刚
罗浩俊
刘自鸿
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to CN201580001765.XA priority Critical patent/CN105637645B/zh
Priority to EP15836971.0A priority patent/EP3185306A4/en
Priority to KR1020177008128A priority patent/KR101990712B1/ko
Publication of WO2016029830A1 publication Critical patent/WO2016029830A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials

Definitions

  • the present invention relates to a transistor, and more particularly to a thin film transistor device and its use in a display, and a method of fabricating the same.
  • Flat panel displays for use in, for example, televisions, monitors, mobile phones, smart phones, personal digital assistants (PDAs), etc., have appeared on the market.
  • active matrix flat panel displays are used in large-sized televisions and high-resolution portable devices due to their large size and high resolution.
  • Active matrix flat panel displays typically include a thin film transistor (TFT) array for controlling the light emitting device.
  • TFT thin film transistor
  • a TFT device 100 as an example is shown in FIG. Referring to FIG. 1 , the TFT device 100 includes a substrate 102 , a gate 104 on the substrate 102 , a dielectric layer 106 on the substrate 102 and the gate 104 , a semiconductor layer 108 on the dielectric layer 106 , and a semiconductor layer 108 .
  • the gate 104, the semiconductor layer 108, the etch stop layer 110, the source 114 and the drain 112, the contact holes 118, 120, and the pixel electrode 122 and the data electrode 124 each require a photomask.
  • the etch stop layer 110 is introduced to protect the semiconductor layer 108 from being damaged by the etchant during the patterning and etching steps of forming the source 114 and the drain 112. This structure requires an additional mask to pattern the etch stop layer 110 itself, which increases manufacturing costs and reduces processing power. Further, the introduction of the passivation layer 116 is to protect the underlying device layers 104 to 114 from the environment.
  • the present invention provides a thin film transistor (TFT) device.
  • TFT thin film transistor
  • the TFT device includes a first conductive layer including a gate and a connection pad.
  • the TFT device also includes a first dielectric layer overlying the gate.
  • the connection pad is exposed from the first dielectric layer.
  • the TFT device further includes a semiconductor layer disposed on the first dielectric layer and overlapping the gate.
  • the TFT device further includes a second dielectric layer disposed on the semiconductor layer and the first dielectric layer to expose the first portion and the second portion of the semiconductor layer and the connection pad.
  • the TFT device further includes a second conductive layer including a source portion covering the first portion of the semiconductor layer, a pixel electrode portion extending to the source portion, a drain portion covering the second portion of the semiconductor layer, and An interconnect disposed on the connection pad and extending to the drain portion.
  • the present invention provides a method of fabricating a thin film transistor device.
  • the manufacturing method of the thin film transistor device includes: depositing a first conductive layer on a substrate; patterning the first conductive layer with a first mask to form a gate and a connection pad; depositing a first dielectric layer over the substrate to cover a gate electrode and the connection pad; depositing a semiconductor layer on the first dielectric layer; patterning the semiconductor layer with a second mask to form a semiconductor region overlapping the gate; depositing a second dielectric on the substrate The second dielectric layer is patterned by a third mask to expose the first portion and the second portion of the semiconductor region and a dielectric region is formed on the semiconductor region, and the second mask is patterned by the third mask And an electrical layer and the first dielectric layer to expose the connection pad; forming a second conductive layer on the substrate such that the second conductive layer contacts the connection pad; and patterning the second conductive layer with a fourth mask.
  • Figure 1 is a conventional TFT device
  • FIG 3 is another TFT device in accordance with some embodiments of the present invention.
  • 5A-5K show a method of fabricating a TFT device as an example, in accordance with some embodiments of the present invention.
  • 6A-6D show a method of fabricating a TFT device as an example, in accordance with some embodiments of the present invention.
  • FIG. 7A-7D show a method of fabricating a TFT device as an example, in accordance with some embodiments of the present invention.
  • FIGS. 8A-8D show a method of fabricating a TFT device as an example, according to some embodiments of the present invention.
  • 9 is an example of an active matrix organic light emitting diode device in accordance with some embodiments of the present invention.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include one or more of the described features either explicitly or implicitly.
  • the meaning of "a plurality" is two or more unless specifically and specifically defined otherwise.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; may be mechanically connected, or may be electrically connected or may communicate with each other; may be directly connected or indirectly connected through an intermediate medium, may be internal communication of two elements or interaction of two elements relationship. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • FIG. 2 shows a TFT device 200 as an example.
  • the TFT device 200 can be applied to a liquid crystal display, an organic light emitting diode (OLED) device, or other electronic device.
  • the TFT device 200 includes a light-emitting region 201a, a TFT device region 201b, an interconnection region 201c, and a storage capacitor region 201d formed on a substrate 202.
  • Substrate 202 can be fabricated from glass, silicon, stainless steel, or a polymer or any combination of the above.
  • the polymer substrate may be polyimide (PI), polynaphthalene (PEN), polyethylene terephthalate (PET), polystyrene (PS), polyethersulfone (PES), polyethylene (PE) or poly Manufactured from vinyl chloride (PVC).
  • PI polyimide
  • PEN polynaphthalene
  • PET polyethylene terephthalate
  • PS polystyrene
  • PS polyethersulfone
  • PE polyethylene
  • PVC poly Manufactured from vinyl chloride
  • the TFT device 200 includes a first conductive layer 204, a first dielectric layer 206, a semiconductor layer 208, a second dielectric layer 210, and a second conductive layer 212 formed on a substrate 202.
  • a buffer or barrier layer is formed on the substrate 202 prior to depositing the first conductive layer 204 on the substrate 202.
  • the first conductive layer 204 includes a gate 204a of the TFT device region 201b, a connection pad 204b of the interconnection region 201c, and a first electrode 204c of the capacitance region 201d.
  • the first conductive layer 204 may be a metal (Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn or Ag), a conductive metal oxide (a zinc (Zn) ), indium (In), tin (Sn), gallium (Ga), hafnium (Hf), aluminum (Al), arsenic (As), cadmium (Cd), mercury (Hg), thallium (Tl), lead (Pb) ), oxides of silver (Ag), gold (Au), germanium (Ge), antimony (Sb), antimony (Bi), hafnium (Hf) or zirconium (Zr), such as ITO, IZO, AZO, GZ
  • the first dielectric layer 206 covers the gate 204a and the first electrode 204c, but does not completely cover the connection pad 204b to expose at least a portion of the connection pad 204b from the first dielectric layer 206.
  • the first dielectric layer 206 may be SiO x , SiN x , SiO x N y , AlO x , Y 2 O 3 , HfO x , ZrO x , AlN, AlNO, TiO x , BaTiO 3 , PbTiO 3 , polymer, spin coating Glass (SOG) or spin-on dielectric (SOD), etc., or a mixture or multilayer or composition of the above materials.
  • SOG spin coating Glass
  • SOD spin-on dielectric
  • the semiconductor layer 208 is formed on the first dielectric layer 206 and disposed to overlap the gate 204a.
  • the semiconductor layer 208 can be an island-like pattern region having a width greater than the width of the gate 204a.
  • the semiconductor layer 208 may be amorphous silicon (a-Si), polycrystalline silicon, or a metal oxide such as zinc (Zn), indium (In), tin (Sn), gallium (Ga), hafnium (Hf), aluminum (Al).
  • arsenic Ar
  • Cd cadmium
  • Tl thallium
  • Pb lead
  • silver Ag
  • gold Au
  • germanium Ge
  • Sb antimony
  • Bi antimony
  • yttrium Hf
  • zirconium Zr
  • oxide of a composition of the above elements arsenic (As), cadmium (Cd), mercury (Hg), thallium (Tl), lead (Pb), silver (Ag), gold (Au), germanium (Ge), antimony (Sb), antimony (Bi) , yttrium (Hf) or zirconium (Zr), or the like, or an oxide of a composition of the above elements.
  • the second dielectric layer 210 is disposed on the semiconductor layer 208 and the first dielectric layer 206.
  • the second dielectric layer 210 includes a dielectric region 210a that overlaps a portion of the semiconductor layer 208.
  • the second dielectric layer 210 has openings to expose the connection pads 204b and the first and second portions of the semiconductor layer 208 on both sides of the dielectric region 210a.
  • a portion of the second dielectric layer 210 is further disposed to cover the first electrode 204c.
  • the first dielectric layer 206 or the second dielectric layer 210 on the first electrode 204c can be omitted.
  • the second dielectric layer 210 may be SiO x , SiN x , SiO x N y , AlO x , Y 2 O 3 , HfO x , ZrO x , AlN, AlNO, TiO x , BaTiO 3 , PbTiO 3 , polymer, SOG or SOD or the like, or a mixture or multilayer or composition of the above materials.
  • the second conductive layer 212 is disposed on the substrate 202.
  • the second conductive layer 212 includes a pixel electrode portion 212a on the second dielectric layer 210, a source portion 212b disposed on and covering an exposed surface of the semiconductor layer 208 to form a source contact, and a semiconductor layer 208 disposed on and covering the semiconductor layer 208.
  • the other exposed surface forms a drain contact drain portion 212c, an interconnection portion 212d disposed on the connection pad 204b, and a second electrode 212e disposed in the capacitance region 201d.
  • the pixel electrode portion 212a extends to the source portion 212b.
  • the interconnect 212d extends to the drain portion 212c.
  • the second electrode 212e, the first electrode 204c, and the first and second dielectric layers form a capacitor.
  • the second conductive layer 212 can be a metal layer having a structure selected from the group consisting of Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn, Ag. Or a mixture of the above materials or a multilayer or composition.
  • the second conductive layer 212 may be a transparent conductor having a selected from the group consisting of In, Zn, Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, An oxide of Hf, Zr or the like, such as ITO, IZO, AZO, GZO, In 2 O 3 , ZnO, or the like, or a mixture of the above materials or a metal oxide material in a multilayer or composition.
  • the second conductive layer 212 can comprise a mixture of a metal and a metal oxide.
  • the second conductive layer 212 may include a metal material (such as Zn) and a metal oxide material (such as ZnO) selected from the above materials.
  • the TFT device can include a third conductive layer 214 disposed on the second conductive layer 212.
  • the TFT device 300 as an example is shown in FIG. Referring to FIG. 3, the third conductive layer 214 is disposed to cover the second conductive layer 212 such that they are aligned with each other.
  • This third conductive layer 214 can be selected from materials that achieve better surface smoothness and have a better work function match with the top layer, such as the OLED layer in the pixel electrode region.
  • the third conductive layer 214 may include a material different from the second conductive layer 212.
  • the second conductive layer 212 and the third conductive layer 214 include a reflective material (such as a metal) and a transparent conductor (such as a metal oxide), respectively.
  • the second conductive layer 212 may be selected from the group consisting of Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn, Ag, etc., or a mixture or multilayer of the above materials or A metal material is produced in the composition.
  • the third conductive layer 214 may be an oxide selected from In, Zn, Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, etc., such as ITO, IZO , AZO, GZO, In 2 O 3 , ZnO, etc., or a mixture of the above materials or a metal oxide material in a multilayer or composition. Metal oxide materials have better surface smoothness and better work function matching with OLED layers. Other structures and materials in FIG. 3 are similar to those in FIG. 2, and therefore, the corresponding description is omitted.
  • the third conductive layer 214 can be disposed on a portion of the second conductive layer 212, but is not fully aligned with the second conductive layer 212.
  • the TFT device 400 as an example is shown in FIG. Referring to FIG. 4, the third conductive layer 214 is disposed on the pixel electrode portion 212a and the source portion 212b of the second conductive layer 212, and is aligned with the pixel electrode portion 212a and the source portion 212b of the second conductive layer 212, but It is not provided on the drain portion 212c, the interconnection portion 212d, and the second electrode portion 212e.
  • the structure of the third conductive layer 214 is not limited to the configuration of FIG.
  • the third conductive layer 214 may be disposed on the pixel electrode portion 212a of the second conductive layer 212 and aligned with the pixel electrode portion 212a of the second conductive layer 212, but not disposed on other portions of the second conductive layer 212.
  • Other structures and materials in FIG. 4 are similar to those in FIG. 2, and therefore, the corresponding description is omitted.
  • a substrate 202 is provided.
  • Substrate 202 can be fabricated from glass, silicon, stainless steel, or a polymer.
  • the polymer substrate may be polyimide (PI), polynaphthalene (PEN), polyethylene terephthalate (PET), polystyrene (PS), polyethersulfone (PES), polyethylene (PE). Or made of polyvinyl chloride (PVC).
  • PI polyimide
  • PEN polynaphthalene
  • PET polyethylene terephthalate
  • PS polystyrene
  • PS polyethersulfone
  • PE polyethylene
  • PVC polyvinyl chloride
  • the first conductive layer 204 may include a metal (Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn or Ag), a conductive metal oxide (selected from In, Zn) An oxide of Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, etc., such as ITO, IZO, AZO, GZO, In 2 O 3 , ZnO, etc.), or a mixture or layers or any combination of the above materials.
  • a metal Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn or Ag
  • a conductive metal oxide selected from In, Zn
  • An oxide of Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, etc. such as ITO
  • the first conductive layer 204 can be deposited by various deposition techniques such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), sputtering, evaporation, or solution coating. Solution coating and curing.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • ALD atomic layer deposition
  • sputtering evaporation
  • solution coating evaporation
  • the first conductive layer 204 is patterned by the first photomask 252 by a photolithographic process to form the gate 204a, the connection pad 204b, and the first electrode 204c.
  • a detailed description of a lithography process includes coating a photoresist layer on a layer, exposing the photoresist layer, developing the photoresist layer, and etching the layer with the patterned photoresist layer , as disclosed in Figures 5G, 5H, and 5I, related textual descriptions will be omitted herein.
  • the first mask 252 can include patterns 252a, 252b, and 252c for a photolithography process.
  • a first dielectric layer 206 is formed on the substrate 202, the gate 204a of the first conductive layer 204, the connection pad 204b, and the first electrode 204c, as shown in FIG. 5D.
  • the first dielectric layer 206 can be formed on the substrate 202 by various deposition techniques such as CVD, PECVD, ALD, sputtering, evaporation or solution coating and curing.
  • the material of the first dielectric layer 206 may include SiO x , SiN x , SiO x N y , AlO x , Y 2 O 3 , HfO x , ZrO x , AlN, AlNO, TiO x , BaTiO 3 , PbTiO 3 , polymer, SOG, SOD, etc., or a mixture or layers or compositions of the above materials.
  • a semiconductor layer 208 is formed over the first dielectric layer 206 by various deposition techniques as described above.
  • the semiconductor layer 208 may be made of amorphous silicon (a-Si), polycrystalline silicon or a metal oxide such as In, Zn, Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, An oxide of Hf or Zr or the like is produced.
  • the semiconductor layer 208 is then patterned using a second photomask 254 using a photolithography process to form a semiconductor region 208a, as shown in FIG. 5F.
  • the second mask 254 can include a pattern (eg, pattern 254a) for a photolithography process.
  • a second dielectric layer 210 is formed to cover the semiconductor region 208a and the first dielectric layer 206.
  • the second dielectric layer 210 can be formed by various deposition techniques such as CVD, PECVD, ALD, sputtering, evaporation or solution coating and curing.
  • the material of the second dielectric layer 210 may include SiO x , SiN x , SiO x N y , AlO x , Y 2 O 3 , HfO x , ZrO x , AlN, AlNO, TiO x , BaTiO 3 , PbTiO 3 , polymer , SOG, SOD, etc., or a mixture or layers or compositions of the above materials.
  • a photoresist layer 255 is formed on the second dielectric layer 210 to effect patterning of the second dielectric layer 210. Referring to FIG.
  • the second dielectric layer 210 is then patterned by the third mask 256 and through the photoresist layer 255.
  • the photoresist layer 255 is exposed and developed by light through the third mask 256 to form openings 255a-255c.
  • the openings 255a-255c are formed at predetermined positions of the photoresist layer 255 through the third mask 256.
  • openings 255a-255c may be formed on top of semiconductor region 208a and connection pads 204b, as shown in Figure 5H.
  • the second dielectric layer 210 is patterned through the photoresist layer 255 with openings 225a-255c. For example, referring to FIG.
  • the second dielectric layer 210 is patterned by an etching process to remove the material of the second dielectric layer 210 at the openings 255a-255c, thereby forming a dielectric region 210a and exposing over the semiconductor region 208a.
  • the first portion and the second portion of the semiconductor region 208a are formed to form source/drain contacts.
  • the exposed portion of the semiconductor region 208a can be used for the source and drain regions of the TFT.
  • the etching process exposes a portion of the connection pads 204b by removing portions of the second dielectric layer 210 and the first dielectric layer 206 to form openings 260 on the connection pads 204b.
  • the etching process can be wet or dry etching, or a combination of the two.
  • the etchant of the second dielectric layer can be selected to have good etch selectivity on the semiconductor layer to further etch the first dielectric layer 206 without damaging the semiconductor layer.
  • the etch process may continue to remove a portion of the first dielectric layer 206 over the connection pads 204a, while portions of the semiconductor regions 208a are exposed to the etch solvent or etch gas.
  • the metal oxide has good selectivity (resistance) to the etching gas CH x F y /O 2 , and when the materials of the first and second dielectric layers 206, 210 are SiOx, the metal oxide can be used as The material of the semiconductor region 208a.
  • a second conductive layer 212 is formed on the substrate 202 to cover the second dielectric layer 210, the exposed portion of the semiconductor region 208a, and the exposed portion of the connection pad 204b.
  • the second conductive layer 212 may include a metal (Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn or Ag), a conductive metal oxide (In, Zn, Sn) , oxides of Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, etc., such as ITO, IZO, AZO, GZO, In 2 O 3 , ZnO, etc.) Or any composition of the above materials.
  • the second conductive layer 212 can be formed by various deposition techniques such as CVD, PECVD, ALD, sputtering, evaporation or solution coating and curing.
  • the material of the second conductive layer 212 when applied to a bottom-emission active matrix OLED (AMOLED) device, can be transparent.
  • the transparent conductive material as an example may include conductive metal oxides such as In, Zn, Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, etc., such as ITO , IZO, AZO, GZO, In 2 O 3 , ZnO or any combination of these materials.
  • the material of the second conductive layer 212 can be reflective.
  • the reflective conductive material as an example may include a metal such as Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn or Ag, or any combination of these materials.
  • the second conductive layer 212 is patterned by the fourth mask 258 to form a pixel electrode portion 212a on the second dielectric layer 210, and a source portion disposed on and covering an exposed portion of the semiconductor region 208a. 212b, a drain portion 212c disposed on and covering another exposed portion of the semiconductor region 208a, an interconnection portion 212d disposed on the connection pad 204b, and a second electrode 212e opposite to the first electrode 204c.
  • the pixel electrode portion 212a extends to and connects to the source portion 212b.
  • the interconnection portion 212d extends to and connects the drain portion 212c.
  • the arrangement of these sections is not limited to these configurations.
  • the interconnect portion 212d and the drain portion 212c may be separated from each other or coupled to each other by other wiring patterns (not shown).
  • the TFT device 200 can be formed using four photomasks, thereby reducing manufacturing costs. Further, the dielectric region 210a and the opening 260 leading to the connection pad 204b (FIG. 5I) can be formed in the same etching step to reduce process time and increase processing capability. As described above in connection with FIG. 5K, the same conductive layer 212 can form a pixel electrode, a source and a drain, an interconnect, and an electrode of a capacitor, which can further reduce the process steps. Additionally, the passivation layer 116 of FIG. 1 can be omitted to further reduce cost compared to the device of FIG.
  • a third conductive layer 214 can be formed on the second conductive layer 212 after the second conductive layer 212 is formed on the substrate 202 and before the second conductive layer 212 is patterned.
  • An example is shown in Figure 6A.
  • the third conductive layer 214 can be formed on the second conductive layer 212 by various deposition techniques such as CVD, PECVD, ALD, sputtering, evaporation, or solution coating and curing.
  • the third conductive layer 214 may include a metal (Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn or Ag), a conductive metal oxide (In, Zn, Sn) , oxides of Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, etc., such as ITO, IZO, AZO, GZO, In 2 O 3 , ZnO, etc.) Or any mixture or composition of the above materials.
  • a metal Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn or Ag
  • a conductive metal oxide In, Zn, Sn
  • oxides of Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, etc. such as ITO, IZO, AZ
  • the third conductive layer 214 comprises a different material than the second conductive layer 212.
  • the third conductive layer 214 can include a metal material different from the second conductive layer 212 metal material; the third conductive layer 214 can include a metal oxide and the second conductive layer 212 can include a metal; the third conductive layer 214 can include a metal The mixture of oxide and metal and the second metal layer 212 comprises a metal.
  • the third conductive layer 214 may be composed of a metal material different from the metal material of the second conductive layer 212; the third conductive layer 214 may be composed of a metal oxide and the second conductive layer 212 may be composed of a metal; and the third conductive layer 214 may be composed of a metal
  • the metal oxide (or oxides) and one metal (or metals) are composed of and the second conductive layer 212 may be composed of one metal (or metals).
  • the third conductive layer 214 can be transparent (such as a metal oxide) and the second conductive layer 212 can be reflective (such as a metal) and vice versa.
  • the material of the third conductive layer 214 may be selected to match a light-emitting layer (such as an OLED layer) disposed on top of the pixel electrode region to achieve a better carrier injection effect.
  • the second conductive layer 212 and the third conductive layer 214 are patterned by the fourth mask 258 to form the pixel electrode portions 212a and 214a, the source portions 212b and 214b, the drain portions 212c and 214c, and the mutual Connecting portions 212d and 214d and second electrodes 212e and 214e.
  • the pixel electrode portions 212a and 214a are provided to extend to and connect the source portions 212b and 214b.
  • the interconnections 212d, 214d are disposed to extend to and connect the drain portions 212c, 214c.
  • the settings of these sections are not limited to these configurations.
  • the interconnects 212d, 214d and the drain portions 212c, 214c can be separated from each other or coupled to each other by other wiring patterns (not shown).
  • the third conductive layer 214 is patterned such that its patterns are all substantially aligned in a one-to-one correspondence with the pattern of the second conductive layer 212.
  • the pattern edges of the second conductive layer 212 and the third conductive layer 214 may be offset from each other due to the etching process.
  • a TFT device having three conductive layers can be formed using four photomasks.
  • the second conductive layer 212 and the third conductive layer 214 may be patterned using a gray-tone mask or a half-tone mask.
  • a semi-transmissive cover as an example is shown in Figure 6C.
  • the mask 260 includes three regions: a region 260a having the lowest light transmittance, a region 260b having the highest light transmittance, and light having a light transmittance between the region 260a and the region 260b.
  • the photoresist layer is exposed to light passing through the mask 260 and then subjected to a development process.
  • photoresist layers 261a and 261c are formed.
  • the photoresist layer 261a under the mask region 260a has the greatest thickness because it accepts less exposure.
  • the photoresist layer under the mask region 260b is removed from the surface of the third conductive layer 214 during development as it is thoroughly exposed.
  • the photoresist layer 261c under the mask region 260c has a smaller thickness than the photoresist layer 261A because it receives a larger exposure than the photoresist layer 261a.
  • the second conductive layer 212 and the third conductive layer 214 with the photoresist layers 261a and 261c are etched.
  • the area under the photoresist layer 261a is protected such that the second conductive layer 212 and the third conductive layer 214 are both retained, thereby forming the pixel electrode portions 212a, 214a and the source portion 212b, 214b.
  • the region under the photoresist layer 216c is partially protected such that only the second conductive layer 212 remains, thereby forming the drain portion 212c, the interconnect portion 212c, and the second electrode portion 212e.
  • the regions of the second conductive layer 212 and the third conductive layer 214 that are not covered by the photoresist layer are etched away to form openings separating the source portions 212b, 214b and the drain portion 212c, and the separation interconnection portion 212d and the second The opening of the electrode portion 212e.
  • the material selection of the second conductive layer 212 and the third conductive layer 214 in FIGS. 6C and 6D is similar to the material selection of FIGS. 6A and 6B, and therefore, is omitted here.
  • a TFT device having three conductive layers can be formed using four photomasks.
  • FIG. 7A-7D illustrate pixel layouts of the present invention as an example. Similar to that shown in Figure 5B, a first conductive layer is deposited on the substrate.
  • FIG. 7A shows, as an example, a pattern of a first conductive layer after patterning with a first reticle.
  • the pattern of the first conductive layer includes a first row/gate line 702a, a pad region 702b, a second row/gate line 702c, and a gate portion 702d coupled to the second row line 702c.
  • a first dielectric layer and a semiconductor layer are then deposited over the substrate to cover the pattern of the first conductive layer.
  • FIG. 7B shows, as an example, a pattern of a semiconductor layer after patterning with a second mask.
  • the pattern of the semiconductor layer includes the first semiconductor region 704a and the second semiconductor region 704b.
  • FIG. 7C illustrates, as an example, a pattern of first and second dielectric layers after patterning with a third mask.
  • a pattern of dielectric layers is included in the second dielectric layer to reach the first and second openings 706a, 706b of the first semiconductor region 704a, and both in the first and second dielectric layers to reach the pad region, respectively.
  • opening 706a, 706b exposes a plurality of surfaces of first semiconductor region 704a
  • opening 706c exposes one surface of pad region 702b
  • opening 706d exposes one surface of first row line 702a
  • openings 706e, 706f expose portions of second semiconductor region 704b .
  • FIG. 7D shows, as an example, a pattern of a second conductive layer after patterning with a fourth mask.
  • the pattern of the second conductive layer includes a column/data line 708a, pad regions 708b, 708c, 708d, and a pixel electrode portion 708e.
  • Column line 708a covers first opening 706a and connects first semiconductor region 704a.
  • the pad region 708b covers the second opening 706d and the third opening 706c, and connects the first semiconductor region 704a and the pad region 702b of the first conductive layer.
  • pad region 708b overlaps a portion of first row line 702a to form a capacitor.
  • the pad region 708c covers the fourth opening 706d and the fifth opening 706e, and connects the first row line 702a and the second semiconductor region 704b.
  • the pad region 708d covers the sixth opening 706f and extends to the pixel electrode portion 708e.
  • a TFT device having two conductive layers can be formed using four photomasks.
  • column line 708a, pad regions 708b, 708c, 708d, and pixel electrode portion 708e can comprise two conductive layers having different materials, similar to that shown in FIG. 6B.
  • a TFT device having three conductive layers can also be formed using four photomasks.
  • some of column lines 708a, pad regions 708b, 708c, 708d, and pixel electrode portion 708e may include two conductive layers, while others include one conductive layer.
  • pad region 708d and pixel electrode portion 708e include two different conductive layers
  • column line 708a and pad regions 708b, 708c comprise a single conductive layer.
  • such a configuration is also formed using four reticles including a translucent cover.
  • the first conductive layer can form portions of the row and column lines.
  • a pixel layout as an example is shown in Figures 8A-8D.
  • a first conductive layer is deposited on the substrate.
  • FIG. 8A shows, as an example, a pattern of a first conductive layer after patterning with a first mask.
  • the pattern of the first conductive layer includes a first row line 802a, a pad region 802b, a second row line 802c, a gate region 802d, and a plurality of line segments (connection pads) 802e extending in the column direction. Line segment 802e does not intersect row lines 802a and 802c. Similar to that shown in FIG.
  • FIG. 8B shows a pattern of a semiconductor layer after patterning with a second mask as an example.
  • the pattern of the semiconductor layer includes the first semiconductor region 804a and the second semiconductor region 804b.
  • FIG. 8C illustrates, as an example, a pattern of first and second dielectric layers after patterning with a third mask.
  • the pattern of dielectric layers includes a first opening 806a in the second dielectric layer to reach the semiconductor regions 804a, 804b, and a second opening in the first and second dielectric layers to reach the first conductive layer. 806b. Therefore, the first opening 806a exposes the first semiconductor region The surface of the domain 804a and the second semiconductor region 804b, the second opening 806b exposes the surfaces of the first row line 802a, the pad region 802b, and the line segment 802e. In particular, at least one opening 806b is provided on each line segment 802e.
  • FIG. 8D shows, as an example, a pattern of a second conductive layer after patterning with a fourth mask.
  • the pattern of the second conductive layer includes column lines 808a, pad regions 808b, 808c, 808d, and pixel electrode portions 808e.
  • Column line 808a covers second opening 806b and first opening 806a on line segment 802e to connect first semiconductor region 804a.
  • the pad region 808b covers the first opening 806a and the second opening 806b above the pad region 806b to connect the first semiconductor region 804a and the pad region 802b of the first conductive layer.
  • pad region 808b overlaps a portion of first row line 802a to form a capacitor.
  • the pad region 808c covers the first opening 808a on the second semiconductor region 804b and the second opening 806b over the first row line 802a to connect the first row line 802a and the second semiconductor region 804b.
  • the pad region 808d covers the first opening 806a on the second semiconductor region 804b and extends to the pixel electrode portion 808e.
  • the lines extending in the column direction include two conductive layers, and thus, may have a lower impedance to reduce a single delay in the column lines.
  • a TFT device having such a configuration can also be formed using four photomasks.
  • a TFT device can be used for a display device such as an AMOLED device and a liquid crystal display device.
  • Figure 9 shows an AMOLED device with a TFT device.
  • the AMOLED device 900 includes a light-emitting region 901a, a TFT device region 901b, an interconnection region 901c, and a film capacitor region 901d formed on a substrate 902.
  • Substrate 902 can be fabricated from glass, silicon, stainless steel, or a polymer.
  • the polymer substrate may be polyimide (PI), polynaphthalene (PEN), polyethylene terephthalate (PET), polystyrene (PS), polyethersulfone (PES), polyethylene (PE) or poly Manufactured from vinyl chloride (PVC).
  • PI polyimide
  • PEN polynaphthalene
  • PET polyethylene terephthalate
  • PS polystyrene
  • PS polyethersulfone
  • PE polyethylene
  • PVC poly Manufactured from vinyl chloride
  • the AMOLED device 900 includes a first conductive layer 904, a first dielectric layer 906, a semiconductor layer 908a, a second dielectric layer 910, and a second conductive layer 912 formed on a substrate 902.
  • a buffer layer is formed on substrate 902 prior to deposition of the first conductive layer on substrate 902.
  • the first conductive layer 904 includes a gate 904a of the TFT device region 901b, a connection pad 904b of the interconnection region 901c, and a first electrode 904c of the capacitance region 901d.
  • the first conductive layer 904 may be a metal (Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn or Ag), a conductive metal oxide (an In, Zn) , oxides of Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, etc., such as ITO, IZO, AZO, GZO, In 2 O 3 or ZnO Or a mixture or layers or any combination of the above materials.
  • the first dielectric layer 906 covers the gate 904a and the first electrode 904c, but does not completely cover the connection pad 904b to expose at least a portion of the connection pad 904b from the first dielectric layer 906.
  • the first dielectric layer 906 may be SiO x , SiN x , SiO x N y , AlO x , Y 2 O 3 , HfO x , ZrO x , AlN, AlNO, TiO x , BaTiO 3 , PbTiO 3 , polymer, SOG or SOD or the like, or a mixture or multilayer or composition of the above materials.
  • the semiconductor layer 908a is formed on the first dielectric layer 906 and disposed to overlap the gate 904a. In some embodiments, the semiconductor layer 908a can have a width that is greater than the width of the gate 904a.
  • the semiconductor layer 908a may be amorphous silicon (a-Si) or a metal oxide such as In, Zn, Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf or Oxide production of Zr et al.
  • the second dielectric layer 910 is disposed on the semiconductor layer 908a and the first dielectric layer 906.
  • the second dielectric layer 910 includes a dielectric region 910a that overlaps a portion of the semiconductor layer 908a.
  • the second dielectric layer 910 has openings to expose the connection pads 904b and the first and second portions of the semiconductor layer 908a on both sides of the dielectric region 910a.
  • a portion of the second dielectric layer 910 is further disposed to cover the first electrode 904c.
  • the first dielectric layer 906 or the second dielectric layer 910 on the first electrode 904c can be omitted.
  • the second dielectric layer 910 may be SiO x , SiN x , SiO x N y , AlO x , Y 2 O 3 , HfO x , ZrO x , AlN, AlNO, TiO x , BaTiO 3 , PbTiO 3 , polymer, SOG or SOD or the like, or a mixture or multilayer or composition of the above materials.
  • a second conductive layer 912 is disposed on the substrate 902.
  • the second conductive layer 912 includes a pixel electrode portion 912a on the dielectric layer, a source portion 912b disposed on and covering a portion of the exposed semiconductor layer, and a drain portion 912c disposed on and covering another portion of the exposed semiconductor layer, An interconnection portion 912d provided on the connection pad 904b and a second electrode 912e disposed in the capacitance region 901d.
  • the pixel electrode portion 912a extends to the source portion 912b.
  • the interconnect 912d extends to the drain portion 912c.
  • the second electrode 912e, the first electrode 904c, and the first and second dielectric layers form a capacitor.
  • the second conductive layer 912 can be a metal layer having a structure selected from the group consisting of Al, Cu, Mo, Ti, Ni, W, Au, Pd, Pt, Cr, Nd, Zn, Co, Mn, Ag. Or a mixture of the above materials or a material of the layers or compositions.
  • the second conductive layer 912 may be a transparent conductor having one selected from the group consisting of In, Zn, Sn, Ga, Al, As, Cd, Hg, Tl, Pb, Ag, Au, Ge, Sb, Bi, Hf, Zr, and the like.
  • the second conductive layer 912 can comprise a mixture of a metal and a metal oxide.
  • the second conductive layer 912 includes a metal material (such as Zn) selected from the above materials and a metal oxide material (such as ZnO).
  • the AMOLED device 900 further includes a pixel defining layer 918, an OLED layer 920, an OLED cathode layer 922, and an encapsulation layer 924.
  • the pixel defining layer 918 is disposed in a region outside the position where the pixel electrode 912a is disposed.
  • the OLED layer 920 is disposed on the pixel electrode 912a and the pixel defining layer 918.
  • the pixel electrode 912a and the OLED cathode layer 922 sandwich the OLED layer 920 to supply current to the OLED layer 902.
  • An encapsulation layer 924 is disposed over the OLED cathode layer 922 to protect the underlying layers.

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Abstract

一种薄膜晶体管(TFT)装置（200），显示器及薄膜晶体管装置（200）的制造方法。该TFT装置（200）包括第一导电层（204），其包括栅极（204a）及连接垫（204b）。该TFT装置还包括覆盖该栅极（204a）的第一介电层（206）。该连接垫（204b）从该第一介电层（206）暴露。该TFT装置（200）还包括设置在该第一介电层（206）上且与该栅极（204a）重叠的半导体层（208）。该TFT装置（200）还包括设置在该半导体层（208）及该第一介电层（206）上以暴露该半导体层（208）的第一部分及第二部分及该连接垫（204b）的第二介电层（210）。该TFT装置（200）还包括第二导电层（212），其包括覆盖该半导体层（208）的该第一部分的源极部（212b）、延伸至该源极部（212b）的像素电极部（212a）、覆盖该半导体层（208）的该第二部分的漏极部（212c）及设置在该连接垫（204b）上并延伸至该漏极部（212c）的互连部（212d）。

Description

薄膜晶体管装置、显示器及其制造方法
相关申请的交叉引用
本发明请求在美国专利和商标局于2014年8月24日申请的，题为“薄膜晶体管及其制造方法”，申请号为62/041,129的临时申请的优先权和权益，及在美国专利和商标局于2015年1月9日申请的，题为“薄膜晶体管、显示器及其制造方法”，申请号为14/593,812的专利申请的优先权和权益，并且通过参照将其全文并入此处。
技术领域
本发明涉及一种晶体管，特别地，涉及一种薄膜晶体管装置及其在显示器的应用，及其制造方法。
背景技术
应用在如电视、监视器、手提电话、智能电话、个人数字助理(PDA)等的平板显示器已出现在市场上。特别地，因其具有大尺寸及高分辨率的优点，主动矩阵式平板显示器(active matrix flat panel display)被应用于大尺寸电视及高分辨率的手提装置。
主动矩阵式平板显示器通常包括用于控制光发射装置的薄膜晶体管(TFT)阵列。作为示例的一个TFT装置100展示在图1中。请参图1，TFT装置100包括基底102、位于基底102上的栅极104、位于基底102及栅极104上的介电层106、位于介电层106上的半导体层108、位于半导体层108上的刻蚀阻挡层(etching stop)110、位于半导体层108一侧且与半导体层108接触的漏极112、位于半导体层108另一侧且与半导体层108接触的源极114、位于上述层顶部的钝化层116、形成在钝化层116中并到达源极114的第一接触孔118、形成在钝化层116中并到达漏极112的第二接触孔120、位于第一接触孔118内的像素电极122及位于第二接触孔120内的数据电极124。
为形成图1所示的TFT装置，至少需6个光罩来完成整个器件的图案化。特别地，栅极104、半导体层108、刻蚀阻挡层110、源极114及漏极112、接触孔118、120及像素电极122及数据电极124各需要一个光罩。
刻蚀阻挡层110的引入是为了保护半导体层108，在形成源极114及漏极112的图案化及刻蚀步骤中，防止被刻蚀剂破坏。这种结构需要额外的光罩来图案化刻蚀阻挡层110本身，如此增加制造成本及降低了处理能力。进一步地，钝化层116的引入是为了保护下面的装置层104至114免受环境影响。
因此，有必要减少引入到制造TFT装置的光罩的数量，以增加制造能力及降低成本。
发明内容
为此，本发明提供一种薄膜晶体管(TFT)装置。
该TFT装置包括第一导电层，其包括栅极及连接垫。该TFT装置还包括覆盖该栅极的第一介电层。该连接垫从该第一介电层暴露。该TFT装置还包括设置在该第一介电层上且与该栅极重叠的半导体层。该TFT装置还包括设置在该半导体层及该第一介电层上以暴露该半导体层的第一部分及第二部分及该连接垫的第二介电层。该TFT装置还包括第二导电层，其包括覆盖该半导体层的该第一部分的源极部、延伸至该源极部的像素电极部、覆盖该半导体层的该第二部分的漏极部及设置在该连接垫上并延伸至该漏极部的互连部。
为此，本发明提供一种薄膜晶体管装置的制造方法。该薄膜晶体管装置的制造方法包括：在基底上沉积第一导电层；利用第一光罩图案化该第一导电层以形成栅极及连接垫；在该基底上方沉积第一介电层以覆盖该栅极及该连接垫；在该第一介电层上沉积半导体层；利用第二光罩图案化该半导体层以形成与该栅极重叠的半导体区域；在该基底上沉积第二介电层；利用第三光罩图案化该第二介电层以暴露该半导体区域的第一部分及第二部分及在该半导体区域上形成介电区域，利用该第三光罩图案化该第二介电层及该第一介电层以暴露该连接垫；在该基底上形成第二导电层使得该第二导电层与该连接垫接触；及利用第四光罩图案化该第二导电层。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1为传统的TFT装置；
图2为根据本发明某些实施方式的TFT装置；
图3为根据本发明某些实施方式的另一TFT装置；
图4为根据本发明某些实施方式的又一TFT装置；
图5A-5K展示根据本发明某些实施方式的作为示例的TFT装置的制造方法；
图6A-6D展示根据本发明某些实施方式的作为示例的TFT装置的制造方法；
图7A-7D展示根据本发明某些实施方式的作为示例的TFT装置的制造方法；
图8A-8D展示根据本发明某些实施方式的作为示例的TFT装置的制造方法；及
图9为根据本发明某些实施方式的作为示例的主动矩阵式有机发光二极管装置。
具体实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设定进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设定之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
图2展示作为示例的一种TFT装置200。TFT装置200可应用在液晶显示器、有机发光二极管(OLED)装置或其它电子装置。TFT装置200包括形成在基底202上的发光区201a、TFT装置区201b、互连区201c及储能电容区201d。基底202可由玻璃、硅、不锈钢或聚合物或上述材料的任意组合物制造。聚合物基底可由聚酰亚胺(PI)、聚萘(PEN)、聚对苯二甲酸乙酯(PET)、聚苯乙烯(PS)、聚醚砜(PES)、聚乙烯(PE)或聚氯乙烯(PVC)等制造。
TFT装置200包括形成在基底202上的第一导电层204、第一介电层206、半导体层208、第二介电层210及第二导电层212。在某些实施方式中，在基底202上沉积第一导电层204前，在基底202上形成缓冲层(buffer)或阻挡层(barrier layer)。
第一导电层204包括TFT装置区201b的栅极204a、互连区201c的连接垫204b及电容区201d的第一电极204c。第一导电层204可为金属(Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn或Ag)、导电金属氧化物(一种锌(Zn)、铟(In)、锡(Sn)、镓(Ga)、铪(Hf)、铝(Al)、砷(As)、镉(Cd)、汞(Hg)、铊(Tl)、铅(Pb)、银(Ag)、金(Au)、锗(Ge)、锑(Sb)、铋(Bi)、铪(Hf)或锆(Zr)等的氧化物，如ITO、IZO、AZO、GZO、In2O3或ZnO)或上述材料的混合物或多层或任意组合物。
第一介电层206覆盖栅极204a及第一电极204c，但不完全覆盖连接垫204b，以使连接垫204b的至少一部分从第一介电层206暴露。第一介电层206可由SiOx、SiNx、SiOxNy、AlOx、Y2O3、HfOx、ZrOx、AlN、AlNO、TiOx、BaTiO3、PbTiO3、聚合物、旋涂玻璃(SOG)或旋涂电介质(SOD)等，或上述材料的混合物或多层或组合物制造。
半导体层208形成在第一介电层206上及设置成与栅极204a重叠。在某些实施方式中，半导体层208可为一个岛状的图案区域，其宽度大于栅极204a的宽度。半导体层208可由非晶硅(a-Si)、多晶硅，或金属氧化物，如锌(Zn)、铟(In)、锡(Sn)、镓(Ga)、铪(Hf)、铝(Al)、砷(As)、镉(Cd)、汞(Hg)、铊(Tl)、铅(Pb)、银(Ag)、金(Au)、锗(Ge)、锑(Sb)、铋(Bi)、铪(Hf)或锆(Zr)等，或上述元素的组合物中的一种氧化物制造。
第二介电层210设置在半导体层208及第一介电层206上。第二介电层210包括重叠半导体层208一部分的介电区域210a。第二介电层210具有开口以暴露在介电区域210a两侧的连接垫204b及半导体层208的第一部分及第二部分。请参图2，第二介电层210的一部分进一步地设置以覆盖第一电极204c。在某些实施方式中，可以省略位于第一电极204c上的第一介电层206或第二介电层210。第二介电层210可由SiOx、SiNx、SiOxNy、AlOx、Y2O3、HfOx、ZrOx、AlN、AlNO、TiOx、BaTiO3、PbTiO3、聚合物、SOG或SOD等，或上述材料的混合物或多层或组合物制造。
请参图2，第二导电层212设置在基底202上。第二导电层212包括位于第二介电层210上的像素电极部212a、设置在及覆盖半导体层208的一暴露表面以形成源极接触的源极部212b、设置在及覆盖半导体层208的另一暴露表面以形成漏极接触的漏极部212c、设置在连接垫204b上的互连部212d及设置在电容区201d中的第二电极212e。如图2所示，像素电极部212a延伸至源极部212b。类似地，互连部212d延伸至漏极部212c。第二电极212e、第一电极204c及第一及第二介电层形成电容。
在某些实施方式中，第二导电层212可为金属层，其具有选自Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn、Ag等，或上述材料的混合物或多层或组合物中的一种材料。在其它实施方式中，第二导电层212可为透明导体，其具有选自In、Zn、Sn、 Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf、Zr等的氧化物，如ITO、IZO、AZO、GZO、In2O3、ZnO等，或上述材料的混合物或多层或组合物中的一种金属氧化物材料。在某些实施方式中，第二导电层212可包括一种金属和金属氧化物的混合物。例如，第二导电层212可包括选自上述材料的一种金属材料(如Zn)及一种金属氧化物材料(如ZnO)。
进一步地，在某些实施方式中，TFT装置可包括设置在第二导电层212上的第三导电层214。例如，作为示例的TFT装置300展示在图3中。请参图3，第三导电层214设置成覆盖第二导电层212，使得他们相互对准。这个第三导电层214可选自能够达到更好的表面光滑度及与顶层，如在像素电极区中的OLED层有更好的功函数匹配的材料。第三导电层214可包含不同于第二导电层212的材料。在某些实施方式中，第二导电层212及第三导电层214分别包括反射材料(如金属)及透明导体(如金属氧化物)。例如，第二导电层212可由选自Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn、Ag等，或上述材料的混合物或多层或组合物中的一种金属材料制造。第三导电层214可由选自In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf、Zr等的氧化物，如ITO、IZO、AZO、GZO、In2O3、ZnO等，或上述材料的混合物或多层或组合物中的一种金属氧化物材料制造。金属氧化物材料具有较好的表面光滑度及与OLED层有更好的功函数匹配。图3中的其它结构及材料与图2中相关的结构及材料相类似，因此，省略对应的描述。
在某些实施方式中，第三导电层214可设置在第二导电层212的一部分上，但并不完全与第二导电层212对准。作为示例的TFT装置400展示在图4中。请参图4，第三导电层214设置在第二导电层212的像素电极部212a及源极部212b上，且与第二导电层212的像素电极部212a及源极部212b对准，但不设置在漏极部212c、互连部212d及第二电极部212e上。然而，第三导电层214的结构不限于图4的构造。例如，第三导电层214可设置在第二导电层212的像素电极部212a上，且与第二导电层212的像素电极部212a对准，但不设置在第二导电层212的其它部分上。图4中的其它结构及材料与图2中相关的结构及材料相类似，因此，省略对应的描述。
接下来，描述TFT装置的制造方法。请参图5A，提供基底202。基底202可由玻璃、硅、不锈钢或聚合物制造。所述聚合物基底可由聚酰亚胺(PI)、聚萘(PEN)、聚对苯二甲酸乙酯(PET)、聚苯乙烯(PS)、聚醚砜(PES)、聚乙烯(PE)或聚氯乙烯(PVC)等制造。然后，在基底202上形成第一导电层204，如图5B所示。第一导电层204可包括金属(Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn或Ag)、导电金属氧 化物(选自In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf、Zr等的一种氧化物，如ITO、IZO、AZO、GZO、In2O3、ZnO等)，或上述材料的混合物或多层或任意组合物。第一导电层204可通过各种沉积技术，如化学气相沉积(CVD)、等离子体增强CVD(PECVD)、原子层沉积(ALD)、溅镀(sputtering)、蒸镀(evaporation)，或溶液涂覆及固化(solution coating and curing)。
请参图5C，然后，采用光刻工艺(photolithographic process)利用第一光罩252图案化第一导电层204，以形成栅极204a、连接垫204b及第一电极204c。在本发明中，光刻工艺的详细描述，其包括在一个层上涂布光阻层、曝光该光阻层、显影该光阻层及刻蚀带有被图案化的光阻层的该层，在图5G、5H、5I中揭示，相关的文字描述将在这里省略。第一光罩252可包括用于光刻工艺的图案252a、252b及252c。随后，在基底202、第一导电层204的栅极204a、连接垫204b及第一电极204c上形成第一介电层206，如图5D所示。第一介电层206可通过各种沉积技术，如CVD、PECVD、ALD、溅镀、蒸镀或溶液涂覆及固化形成在基底202上。第一介电层206的材料可包括SiOx、SiNx、SiOxNy、AlOx、Y2O3、HfOx、ZrOx、AlN、AlNO、TiOx、BaTiO3、PbTiO3、聚合物、SOG、SOD等，或上述材料的混合物或多层或组合物。
请参图5E，通过如上所述的各种沉积技术在第一介电层206上形成半导体层208。半导体层208可由非晶硅(a-Si)、多晶硅或金属氧化物，如In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf或Zr等的一种氧化物制造。然后，采用光刻工艺利用第二光罩254图案化半导体层208，以形成半导体区域208a，如图5F所示。第二光罩254可包括用于光刻工艺的图案(如图案254a)。
请参图5G，然后，形成第二介电层210以覆盖半导体区域208a及第一介电层206。第二介电层210可通过各种沉积技术，如CVD、PECVD、ALD、溅镀、蒸镀或溶液涂覆及固化形成。第二介电层210的材料可包括SiOx、SiNx、SiOxNy、AlOx、Y2O3、HfOx、ZrOx、AlN、AlNO、TiOx、BaTiO3、PbTiO3、聚合物、SOG、SOD等，或上述材料的混合物或多层或组合物。请参图5G及5H，在第二介电层210上形成光阻层255以实现第二介电层210的图案化。请参图5H，然后，利用第三光罩256并通过光阻层255图案化第二介电层210。例如，利用光通过第三光罩256曝光及显影光阻层255以形成开口255a-255c。特别地，开口255a-255c是通过第三光罩256形成在光阻层255的预定位置。例如，开口255a-255c可形成在半导体区域208a及连接垫204b的顶部，如图5H所示。之后，通过带有开口225a-255c的光阻层255对第二介电层210图案化。例如，请参图5I，利用刻蚀工艺图案化第二介电层210以移除在开口255a-255c的第二介电层210的材料，进而在半导体区域208a上方形 成介电区域210a及暴露半导体区域208a的第一部分及第二部分以形成源极/漏极接触。半导体区域208a的暴露部分可用于TFT的源极及漏极区域。进一步地，刻蚀工艺通过移除第二介电层210及第一介电层206的一部分也暴露连接垫204b的一部分，以形成连接垫204b上的开口260。刻蚀工艺可为湿式或干式刻蚀，或两者的组合。可选择第二介电层的刻蚀剂以在半导体层上具有好的刻蚀选择性，以在不破坏半导体层的情况下，进一步刻蚀第一介电层206。
在某些实施方式中，因为半导体区域208a中的材料对湿式工艺的刻蚀溶剂或干式工艺的刻蚀气体可具有耐抗性，因此，在移除第二介电层210的一部分后，刻蚀工艺可继续移除在连接垫204a上的第一介电层206的一部分，而半导体区域208a的部分暴露在刻蚀溶剂或刻蚀气体中。例如，金属氧化物对刻蚀气体CHxFy/O2具有好的选择性(耐抗性)，且当第一及第二介电层206、210的材料为SiOx，金属氧化物可作为半导体区域208a的材料。
接下来，请参图5J，在基底202上形成第二导电层212以覆盖第二介电层210、半导体区域208a的暴露部分及连接垫204b的暴露部分。第二导电层212可包括金属(Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn或Ag)、导电金属氧化物(In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf、Zr等的氧化物，如ITO、IZO、AZO、GZO、In2O3、ZnO等)或上述材料的任意组合物。第二导电层212可通过各种沉积技术，如CVD、PECVD、ALD、溅镀、蒸镀或溶液涂覆及固化形成。在某些实施方式中，例如，当应用在底部发射(bottom-emission)主动矩阵式OLED(AMOLED)装置时，第二导电层212的材料可为透明的。作为示例的透明导电材料可包括In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf、Zr等的导电金属氧化物，如ITO、IZO、AZO、GZO、In2O3、ZnO或这些材料的任意组合物。在其它实施方式中，例如，当应用在顶部发射(top-emission)AMOLED装置时，第二导电层212的材料可为反射的。作为示例的反射导电材料可包括金属，如Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn或Ag，或这些材料的任意组合物。
请参图5K，之后，利用第四光罩258图案化第二导电层212以在第二介电层210上形成像素电极部212a、设置在及覆盖半导体区域208a的一暴露部分的源极部212b、设置在及覆盖半导体区域208a的另一暴露部分的漏极部212c、设置在连接垫204b上的互连部212d及与第一电极204c相背的第二电极212e。像素电极部212a延伸至并连接源极部212b。互连部212d延伸至并连接漏极部212c。然而，这些部的设置不限于这些构造。例如，在某些实施方式中，互连部212d及漏极部212c可相互分离，或通过其它布线图案(图未示)相互耦合。
如上结合图5A-5K所述，TFT装置200可利用四个光罩形成，因此，降低了制造成本。进一步地，介电区域210a及通向连接垫204b(图5I)的开口260可在相同的刻蚀步骤中形成，以减少制程时间及增加处理能力。如上结合图5K所述，相同的导电层212可形成像素电极、源极及漏极、互连部及电容的一个电极，如此可进一步减少制程步骤。另外，与图1中的装置相比较，图1的钝化层116可以省略以进一步降低成本。
在某些实施方式中，如图5J所示，在基底202上形成第二导电层212之后及在图案化第二导电层212之前，可在第二导电层212上形成第三导电层214。作为一个例子展示在图6A中。第三导电层214可通过各种沉积技术，如CVD、PECVD、ALD、溅镀、蒸镀或溶液涂覆及固化形成在第二导电层212上。第三导电层214可包括金属(Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn或Ag)、导电金属氧化物(In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf、Zr等的氧化物，如ITO、IZO、AZO、GZO、In2O3、ZnO等)或上述材料的任意混合物或组合物。
在某些实施方式中，第三导电层214包括与第二导电层212材料不同的材料。例如，第三导电层214可包括不同于第二导电层212金属材料的金属材料；第三导电层214可包括金属氧化物而第二导电层212可包括金属；第三导电层214可包括金属氧化物及金属的混合物而第二金属层212包括金属。又例如，第三导电层214可由不同于第二导电层212金属材料的金属材料组成；第三导电层214可由金属氧化物组成而第二导电层212可由金属组成；第三导电层214可由一种金属氧化物(或多种氧化物)及一种金属(或多种金属)组成而第二导电层212可由一种金属(或多种金属)组成。再例如，第三导电层214可为透明的(如金属氧化物)及第二导电层212可为反射的(如金属)，反之亦然。进一步例如，可选择第三导电层214的材料以匹配设置在像素电极区顶部的发光层(如OLED层)，以达到更好的载流子注入(carrier injection)效果。
请参图6B，之后，利用第四光罩258图案化第二导电层212及第三导电层214以形成像素电极部212a、214a、源极部212b、214b、漏极部212c、214c、互连部212d、214d及第二电极212e、214e。像素电极部212a、214a设置为延伸至并连接源极部212b、214b。互连部212d、214d设置为延伸至并连接漏极部212c、214c。然而，这些部的设置并不限于这些构造。例如，在某些实施方式中，互连部212d、214d及漏极部212c、214c可相互分离，或通过其它布线图案(图未示)相互耦合。图案化第三导电层214以使得它的图案全部基本上与第二导电层212的图案一一对应地对准。然而，在某实施方式中，因为刻蚀工艺，第二导电层212及第三导电层214的图案边缘可能会相互偏离。综上，具有三个导电层的TFT装置可利用四个光罩形成。
在其它实施方式中，可利用灰阶光罩(gray-tone mask)或半透光罩(half-tone mask)图案化第二导电层212及第三导电层214。作为示例的半透光罩展示在图6C中。请参图6C，光罩260包括三个区域：具有最低光透过率的区域260a、具有最高光透过率的区域260b及具有介于区域260a的光透过率与区域260b的光透过率之间的光透过率的区域260c。在第二导电层212上沉积第三导电层214之后，在第三导电层214上涂布与图5G中相类似的光阻层。光阻层被穿透光罩260的光曝光，再经过显影过程。请参图6C，显影之后，形成光阻层261a及261c。特别地，位于光罩区域260a下的光阻层261a，因其接受较少的曝光而具有最大的厚度。位于光罩区域260b下的光阻层，因其被彻底曝光而在显影过程中从第三导电层214表面上被移除。位于光罩区域260c下的光阻层261c，因其接受比光阻层261a更大的曝光而具有比光阻层261A更小的厚度。
之后，刻蚀带有光阻层261a及261c的第二导电层212及第三导电层214。请参图6D，刻蚀步骤之后，光阻层261a下面的区域被保护以使得第二导电层212及第三导电层214均保留下来，进而形成像素电极部212a、214a及源极部212b、214b。位于光阻层216c下面的区域被部分地保护以使得只有第二导电层212保留下来，进而形成漏极部212c、互连部212c及第二电极部212e。未被光阻层覆盖的第二导电层212及第三导电层214的区域被刻蚀掉以形成分隔源极部212b、214b及漏极部212c的开口，及分隔互连部212d及第二电极部212e的开口。图6C及6D中的第二导电层212及第三导电层214的材料选择与图6A及6B的材料选择相类似，因此，在此省略。综上，具有三个导电层的TFT装置可利用四个光罩形成。
图7A-7D展示了本发明作为示例的像素布局。与图5B中所示的相类似，在基底上沉积第一导电层。图7A展示了作为示例的在利用第一光罩图案化之后的第一导电层的图案。例如，第一导电层的图案包括第一行(row)/栅极线702a、垫区域702b、第二行/栅极线702c及耦合至第二行线702c的栅极部702d。与图5E中所示的相类似，随后在基底上沉积第一介电层及半导体层以覆盖第一导电层的图案。图7B展示了作为示例的在利用第二光罩图案化之后的半导体层的图案。例如，半导体层的图案包括第一半导体区域704a及第二半导体区域704b。
之后，在基底上沉积第二介电层以覆盖半导体区域704a、704b及第一介电层。图7C展示了作为示例的在利用第三光罩图案化之后的第一及第二介电层的图案。例如，介电层的图案包括在第二介电层中以到达第一半导体区域704a的第一及第二开口706a、706b，及均在第一及第二介电层中以分别到达垫区域702b及第一行线702a的第三及第四开口，及在第二介电层中以到达第二半导体区域704b的第五及第六开口706e、706f。因此，开口 706a、706b暴露第一半导体区域704a的多个表面，开口706c暴露垫区域702b的一个表面，开口706d暴露第一行线702a的一个表面，开口706e、706f暴露第二半导体区域704b的多个表面。
随后，与图5J所示的相类似，在基底上沉积第二导电层。图7D展示了作为示例的在利用第四光罩图案化之后的第二导电层的图案。例如，第二导电层的图案包括列(column)/数据线708a、垫区域708b、708c、708d及像素电极部708e。列线708a覆盖第一开口706a及连接第一半导体区域704a。垫区域708b覆盖第二开口706d及第三开口706c，并连接第一半导体区域704a及第一导电层的垫区域702b。另外，垫区域708b与第一行线702a的一部分重叠以形成电容。垫区域708c覆盖第四开口706d及第五开口706e，并连接第一行线702a和第二半导体区域704b。垫区域708d覆盖第六开口706f并延伸至像素电极部708e。综上，具有二个导电层的TFT装置可利用四个光罩形成。
在某些实施方式中，与图6B所示的相类似，列线708a、垫区域708b、708c、708d及像素电极部708e可包含具有不同材料的两个导电层。综上，具有三个导电层的TFT装置也可利用四个光罩形成。
在其它实施方式中，与图6D所示的相类似，列线708a、垫区域708b、708c、708d及像素电极部708e中的某些可包含两个导电层，而其它包含一个导电层。例如，请参图7，垫区域708d及像素电极部708e包含两个不同的导电层，而列线708a及垫区域708b、708c包含单一导电层。如上结合图6C所述，这样的构造也利用包括一个半透光罩的四个光罩形成。
在某些实施方式中，第一导电层可形成行线及列线的部分。作为示例的像素布局展示在图8A-8D中。如上所述，与图5B所示的相类似，在基底上沉积第一导电层。图8A展示了作为示例的在利用第一光罩图案化之后的第一导电层的图案。例如，第一导电层的图案包括第一行线802a、垫区域802b、第二行线802c、栅极区802d及沿列方向延伸的多个线段(连接垫)802e。线段802e不与行线802a及802c相交。与图5E中所示的相类似，随后在基底上沉积第一介电层及半导体层以覆盖第一导电层的图案。图8B展示了作为示例的在利用第二光罩图案化之后的半导体层的图案。例如，半导体层的图案包括第一半导体区域804a及第二半导体区域804b。
之后，在基底上沉积第二介电层以覆盖半导体区域804a、804b及第一介电层。图8C展示了作为示例的在利用第三光罩图案化之后的第一及第二介电层的图案。例如，介电层的图案包括在第二介电层中以到达半导体区域804a、804b的第一开口806a，及均在第一及第二介电层中以到达第一导电层的第二开口806b。因此，第一开口806a暴露第一半导体区 域804a及第二半导体区域804b的表面，第二开口806b暴露第一行线802a、垫区域802b及线段802e的表面。特别地，至少一个开口806b是设置在每个线段802e上。
接下来，与图5J中所示的相类似，在基底上沉积第二导电层。图8D展示了作为示例的在利用第四光罩图案化之后的第二导电层的图案。例如，第二导电层的图案包括列线808a、垫区域808b、808c、808d及像素电极部808e。列线808a覆盖在线段802e上的第二开口806b及第一开口806a以连接第一半导体区域804a。垫区域808b覆盖第一开口806a及在垫区域806b上方的第二开口806b以连接第一半导体区域804a及第一导电层的垫区域802b。另外，垫区域808b与第一行线802a的一部分重叠以形成电容。垫区域808c覆盖在第二半导体区域804b上的第一开口808a及覆盖在第一行线802a上的第二开口806b以连接第一行线802a和第二半导体区域804b。垫区域808d覆盖在第二半导体区域804b上的第一开口806a，并延伸至像素电极部808e。
如图8D所示，沿列方向延伸的线(如数据线)包括两个导电层，因此，可具有较低的阻抗以减少在列线中的单个延迟。具有这种构造的TFT装置也可利用四个光罩形成。
以上所揭示的TFT装置可应用于各种电子装置。例如，TFT装置可用于显示装置，如AMOLED装置及液晶显示装置。图9展示了一种具有TFT装置的AMOLED装置。请参图9，AMOLED装置900包括形成在基底902上的发光区901a、TFT装置区901b、互连区901c及薄膜电容区901d。基底902可由玻璃、硅、不锈钢或聚合物制造。聚合物基底可由聚酰亚胺(PI)、聚萘(PEN)、聚对苯二甲酸乙酯(PET)、聚苯乙烯(PS)、聚醚砜(PES)、聚乙烯(PE)或聚氯乙烯(PVC)等制造。
AMOLED装置900包括形成在基底902上的第一导电层904、第一介电层906、半导体层908a、第二介电层910及第二导电层912。在某些实施方式中，在基底902上沉积第一导电层前，在基底902上形成缓冲层(buffer layer)。
第一导电层904包括TFT装置区901b的栅极904a、互连区901c的连接垫904b及电容区901d的第一电极904c。第一导电层904可为金属(Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn或Ag)、导电金属氧化物(一种In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf、Zr等的氧化物，如ITO、IZO、AZO、GZO、In2O3或ZnO)或上述材料的混合物或多层或任意组合物。
请参图9，第一介电层906覆盖栅极904a及第一电极904c，但不完全覆盖连接垫904b以使连接垫904b的至少一部分从第一介电层906暴露。第一介电层906可由SiOx、SiNx、SiOxNy、AlOx、Y2O3、HfOx、ZrOx、AlN、AlNO、TiOx、BaTiO3、PbTiO3、聚合物、SOG或SOD等，或上述材料的混合物或多层或组合物制造。
半导体层908a形成在第一介电层906上及设置成与栅极904a重叠。在某些实施方式中，半导体层908a可具有比栅极904a宽度大的宽度。半导体层908a可由非晶硅(a-Si)或金属氧化物，如In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf或Zr等的氧化物制造。
第二介电层910设置在半导体层908a及第一介电层906上。第二介电层910包括重叠半导体层908a的一部分的介电区域910a。第二介电层910具有开口以暴露在介电区域910a两侧的连接垫904b及半导体层908a的第一部分及第二部分。请参图9，第二介电层910的一部分进一步地设置以覆盖第一电极904c。在某些实施方式中，可以省略位于第一电极904c上的第一介电层906或第二介电层910。第二介电层910可由SiOx、SiNx、SiOxNy、AlOx、Y2O3、HfOx、ZrOx、AlN、AlNO、TiOx、BaTiO3、PbTiO3、聚合物、SOG或SOD等，或上述材料的混合物或多层或组合物制造。
请再参图9，第二导电层912设置在基底902上。第二导电层912包括位于介电层上的像素电极部912a、设置在及覆盖暴露的半导体层的一部分的源极部912b、设置在及覆盖暴露的半导体层的另一部分的漏极部912c、设置在连接垫904b上的互连部912d及设置在电容区901d中的第二电极912e。如图9所示，像素电极部912a延伸至源极部912b。类似地，互连部912d延伸至漏极部912c。第二电极912e、第一电极904c及第一及第二介电层形成电容。
在某些实施方式中，第二导电层912可为金属层，其具有选自Al、Cu、Mo、Ti、Ni、W、Au、Pd、Pt、Cr、Nd、Zn、Co、Mn、Ag等或上述材料的混合物或多层或组合物中的一种材料。第二导电层912可为透明导体，其具有选自In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf、Zr等的一种氧化物，如ITO、IZO、AZO、GZO、In2O3、ZnO等，或上述材料的混合物或多层或组合物中的一种金属氧化物材料。在其它实施方式中，第二导电层912可包括一种金属和金属氧化物的混合物。例如，第二导电层912包括选自上述材料的一种金属材料(如Zn)及一种金属氧化物材料(如ZnO)。
AMOLED装置900进一步包括像素限定层918(pixel defining layer)、OLED层920、OLED阴极层922及封装层924。像素限定层918设置在像素电极912a所设置的位置外的区域中。OLED层920设置在像素电极912a及像素限定层918上。像素电极912a及OLED阴极层922夹着OLED层920以向OLED层902提供电流。封装层924设置在OLED阴极层922上以保护下面的层。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施方式或示例描述的具 体特征、结构、材料或者特点包含于本发明的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
尽管已经示出和描述了本发明的实施方式，本领域的普通技术人员可以理解：在不脱离本发明的原理和宗旨的情况下可以对这些实施方式进行多种变化、修改、替换和变型，本发明的范围由权利要求及其等同物限定。

Claims (26)

  1. 一种薄膜晶体管装置，其特征在于，包括：
    包括栅极及连接垫的第一导电层；
    覆盖该栅极的第一介电层，该连接垫从该第一介电层暴露；
    设置在该第一介电层上且与该栅极重叠的半导体层；
    设置在该半导体层及该第一介电层上以暴露该半导体层的第一部分及第二部分及该连接垫的第二介电层；
    第二导电层，包括：
    覆盖该半导体层的该第一部分的源极部；
    延伸至该源极部的像素电极部；
    覆盖该半导体层的该第二部分的漏极部；及
    设置在该连接垫上并延伸至该漏极部的互连部。
  2. 如权利要求1所述的薄膜晶体管装置，其特征在于，该第一导电层还包括：
    耦合至该栅极并沿第一方向延伸的栅极线；
    通过该第二导电层耦合至该连接垫的数据线，该数据线沿不同于该第一方向的第二方向延伸。
  3. 如权利要求1所述的薄膜晶体管装置，其特征在于，该第二导电层包括透明导体。
  4. 如权利要求3所述的薄膜晶体管装置，其特征在于，该透明导体包括至少一种金属氧化物。
  5. 如权利要求4所述的薄膜晶体管装置，其特征在于，该至少一种金属氧化物包括In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf或Zr的氧化物，或其中的组合中的一种氧化物。
  6. 如权利要求3所述的薄膜晶体管装置，其特征在于，该第二导电层还包括一种金属。
  7. 如权利要求1所述的薄膜晶体管装置，其特征在于，还包括设置在该第二导电层上 的第三导电层，该第三导电层与该第二导电层对准。
  8. 如权利要求7所述的薄膜晶体管装置，其特征在于，该第三导电层与该第二导电层一一对应地对准。
  9. 如权利要求8所述的薄膜晶体管装置，其特征在于，该第二导电层包括反射材料，及该第三导电层包括透明材料。
  10. 如权利要求7所述的薄膜晶体管装置，其特征在于，该第三导电层至少与该第二导电层的该源极部及该像素电极部对准。
  11. 如权利要求10所述的薄膜晶体管装置，其特征在于，该第二导电层包括反射材料，及该第三导电层包括透明材料。
  12. 如权利要求1所述的薄膜晶体管装置，其特征在于，该第一导电层还包括电容的第一电极；及
    该第二导电层还包括该电容的第二电极，该第二电极与该第一电极相背，该第二电极及该第一电极夹着该第一介电层和该第二介电层中的至少一个。
  13. 如权利要求1所述的薄膜晶体管装置，其特征在于，该半导体层包括选自非晶硅、多晶硅及In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf或Zr，或其中的组合的氧化物中的一种材料。
  14. 一种薄膜晶体管装置的制造方法，其特征在于，包括：
    在基底上沉积第一导电层；
    利用第一光罩图案化该第一导电层以形成栅极及连接垫；
    在该基底上方沉积第一介电层以覆盖该栅极及该连接垫；
    在该第一介电层上沉积半导体层；
    利用第二光罩图案化该半导体层以形成与该栅极重叠的半导体区域；
    在该基底上沉积第二介电层；
    利用第三光罩图案化该第二介电层以暴露该半导体区域的第一部分及第二部分及在该 半导体区域上形成介电区域，利用该第三光罩图案化该第二介电层及该第一介电层以暴露该连接垫；
    在该基底上形成第二导电层使得该第二导电层与该连接垫接触；及
    利用第四光罩图案化该第二导电层。
  15. 如权利要求14所述的薄膜晶体管装置的制造方法，其特征在于，还包括：
    利用该第一光罩图案化该第一导电层以形成连接该栅极并沿第一方向延伸的栅极线，及沿不同于该第一方向的第二方向延伸的数据线的第一部分；及
    利用该第四光罩图案化该第二导电层以形成该数据线的第二部分，该第二部分通过该连接垫连接该第一部分。
  16. 如权利要求15所述的薄膜晶体管装置的制造方法，其特征在于，该第二导电层包括透明导体。
  17. 如权利要求16所述的薄膜晶体管装置的制造方法，其特征在于，该透明导体包括至少一种金属氧化物。
  18. 如权利要求17所述的薄膜晶体管装置的制造方法，其特征在于，该至少一种金属氧化物包括In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf或Zr，或其中的组合中的一种氧化物。
  19. 如权利要求14所述的薄膜晶体管装置的制造方法，其特征在于，还包括：
    在该第二导电层上沉积第三导电层；及
    利用该第四光罩图案化该第三导电层使得在该第三导电层中的图案与在该第二导电层中的图案对准。
  20. 如权利要求19所述的薄膜晶体管装置的制造方法，其特征在于，该第二导电层包括反射材料，及该第三导电层包括透明材料。
  21. 如权利要求14所述的薄膜晶体管装置的制造方法，其特征在于，还包括：
    在该第二导电层上沉积第三导电层；及
    利用该第四光罩图案化该第三导电层使得该第三导电层的一部分留在该第二导电层上及该第三导电层的另一部分从该第二导电层上移除。
  22. 如权利要求21所述的薄膜晶体管装置的制造方法，其特征在于，该第二导电层包括反射材料，及该第三导电层包括透明材料。
  23. 如权利要求14所述的薄膜晶体管装置的制造方法，其特征在于，还包括：
    利用该第一光罩图案化该第一导电层以形成电容的第一电极；及
    利用该第四光罩图案化该第二导电层以形成该电容的第二电极，该第二电极与该第一电极相背，该第二电极及该第一电极夹着该第一介电层和该第二介电层中的至少一个。
  24. 如权利要求14所述的薄膜晶体管装置的制造方法，其特征在于，该半导体层包括选自非晶硅、多晶硅及In、Zn、Sn、Ga、Al、As、Cd、Hg、Tl、Pb、Ag、Au、Ge、Sb、Bi、Hf或Zr，或其中的组合的氧化物中的一种材料。
  25. 一种显示器，其特征在于，包括如权利要求1～13任一项所述的薄膜晶体管装置。
  26. 如权利要求25所述的显示器，其特征在于，还包括像素限定层、发光层、阴极层及封装层，该像素限定层设置在该像素电极部所设置的位置外的区域中，该发光层设置在像素电极部及该像素限定层上，该像素电极部及该阴极层夹着该发光层，该封装体设置在该阴极层上。
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