WO2016045283A1 - 像素驱动电路、方法、显示面板和显示装置 - Google Patents

像素驱动电路、方法、显示面板和显示装置 Download PDF

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Publication number
WO2016045283A1
WO2016045283A1 PCT/CN2015/071406 CN2015071406W WO2016045283A1 WO 2016045283 A1 WO2016045283 A1 WO 2016045283A1 CN 2015071406 W CN2015071406 W CN 2015071406W WO 2016045283 A1 WO2016045283 A1 WO 2016045283A1
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Prior art keywords
driving
transistor
pole
gate
control
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PCT/CN2015/071406
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English (en)
French (fr)
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杨盛际
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to EP19187202.7A priority Critical patent/EP3576080B1/en
Priority to US14/769,346 priority patent/US9640109B2/en
Priority to EP15748154.0A priority patent/EP3200178B1/en
Publication of WO2016045283A1 publication Critical patent/WO2016045283A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a method, a display panel, and a display device.
  • AMOLED (Active Matrix/Organic Light Emitting Diode) display is one of the hotspots in the field of flat panel display research.
  • Organic light-emitting diodes (OLEDs) have the advantages of low energy consumption, low production cost, self-luminous, wide viewing angle and fast response.
  • Pixel driver circuit design is the core technology content of AMOLED display, which has important research significance.
  • Vth threshold voltage of the driving transistor of each pixel in the AMOLED display
  • the threshold voltage (Vth) of the driving transistor of each pixel in the AMOLED display may drift due to process process and device aging, etc.; thus, the current flowing through each pixel point OLED changes due to the change of the threshold voltage, so that The display brightness is uneven, which affects the display of the entire image.
  • each of the existing basic AMLOED pixel driving circuits includes only one driving transistor DTFT, one switching transistor T1 and one storage capacitor Cs.
  • the scanning voltage Vscan on the scanning line is shown.
  • T1 is turned on, and the data voltage Vdata is written to the storage capacitor Cs.
  • Vscan goes high, T1 turns off, and the gate voltage stored on Cs drives the DTFT, causing the DTFT to generate current to drive the OLED, ensuring that the OLED continues to emit light within one frame.
  • the current flowing through the OLED, I OLED K(V GS - V th ) 2 , where K is a constant, V GS is the gate-to-source voltage of the DTFT, and V th is the threshold voltage of the DTFT.
  • the threshold voltage Vth of the driving transistor DTFT at each pixel shifts due to the process process and device aging, etc., which causes the current flowing through each pixel OLED to change due to the change of Vth . Thereby affecting the display effect of the entire image.
  • the pixel driving circuit with threshold compensation function in the prior art may be a 6T1C pixel driving circuit, using too many Thin Film Transistors (TFTs) and lines, although The compensation threshold is met, but the aperture ratio of the pixel is correspondingly low; and the existing pixel driving circuit is disposed in each pixel unit, so that the OLED device distribution space is too compact.
  • TFTs Thin Film Transistors
  • a main object of the present disclosure is to provide a pixel driving circuit, a method, a pixel circuit, a display panel, and a display device to solve the pixel unit caused by the number of TFTs and data lines used in threshold compensation in the prior art.
  • the aperture ratio is low, so that higher picture quality and PPI (Pixels per inch, the number of pixels per inch) cannot be obtained.
  • the present disclosure provides a pixel driving circuit for driving a first light emitting element and a second light emitting element, a first end of the first light emitting element and a first end of the second light emitting element Accessing a first level;
  • the pixel driving circuit includes a first pixel driving unit and a second pixel driving unit;
  • the first pixel driving unit includes a first driving transistor, a first storage capacitor, and a first driving control unit, where
  • the first storage capacitor has a first end connected to the gate of the first driving transistor, and a second end accessing the data voltage through the first driving control unit;
  • a first driving transistor the gate is connected to the first electrode of the first driving transistor by the first driving control unit, the first pole is connected to the second level by the first driving control unit, and the second pole passes the first a driving control unit is connected to the first level; a second pole of the first driving transistor is further connected to the second end of the first illuminating element;
  • the first driving control unit is configured to charge and discharge the first storage capacitor by the second level, the data voltage, and the first level, thereby applying a transition to the data voltage in the first compensation phase
  • the voltage is controlled to perform trip compensation for the threshold voltage of the first driving transistor, and controls the first light emitting element to emit light;
  • the second pixel driving unit includes a second driving transistor, a second storage capacitor, and a second driving control unit, where
  • the second storage capacitor has a first end connected to a gate of the second driving transistor, and a second end is connected to the data voltage through the first driving control unit;
  • the second driving transistor has a gate through the second driving control unit and the second driving transistor a first pole connection, the first pole is connected to the second level by the second driving control unit, and the second pole is connected to the first level by the second driving control unit; the second pole of the second driving transistor Also connected to the second end of the second light emitting element;
  • the second driving control unit is configured to charge and discharge the second storage capacitor by the second level, the data voltage, and the first level, thereby applying a transition to the data voltage in the second compensation phase
  • the voltage is controlled to perform trip compensation for the threshold voltage of the second driving transistor, and to control the second light emitting element to emit light.
  • the structure of the first drive control unit and the structure of the second drive control unit are the same.
  • the first driving control unit includes:
  • a first control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the first driving transistor, and the second pole is connected to the gate of the first driving transistor;
  • a second control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the first driving transistor, and the second pole is connected to the first level;
  • a third control transistor the gate is connected to the first driving control signal, the first pole is connected to the second end of the first storage capacitor, and the second pole is connected to the data voltage;
  • a fourth control transistor the gate is connected to the second scan signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the first driving transistor;
  • the second drive control unit includes:
  • a fifth control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the second driving transistor, and the second pole is connected to the gate of the second driving transistor;
  • a sixth control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the second driving transistor, and the second pole is connected to the first level;
  • a seventh control transistor the gate is connected to the second driving control signal, the first pole is connected to the second end of the second storage capacitor, and the second pole is connected to the data voltage;
  • an eighth control transistor the gate is connected to the second scan signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the second driving transistor.
  • the first driving transistor, the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are N-type TFT;
  • the second driving transistor, the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are all n-type TFTs.
  • the first driving control unit includes:
  • a first control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the first driving transistor, and the second pole is connected to the gate of the first driving transistor;
  • a second control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the first driving transistor, and the second pole is connected to the first level;
  • a third control transistor the gate is connected to the first driving control signal, the first pole is connected to the second end of the first storage capacitor, and the second pole is connected to the data voltage;
  • a fourth control transistor the gate is connected to the second scan signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the first driving transistor;
  • the second drive control unit includes:
  • a fifth control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the second driving transistor, and the second pole is connected to the gate of the second driving transistor;
  • a sixth control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the second driving transistor, and the second pole is connected to the first level;
  • a seventh control transistor the gate is connected to the second scan signal, the first pole is connected to the second end of the second storage capacitor, and the second pole is connected to the data voltage;
  • an eighth control transistor the gate is connected to the second scan signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the second driving transistor.
  • the first driving transistor, the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are N-type TFT;
  • the second driving transistor, the fifth control transistor, the sixth control transistor, and the eighth control transistor are all n-type TFTs, and the seventh control transistor is P-type TFT.
  • the first driving control unit includes:
  • a first control transistor the gate is connected to the first scan signal, and the first pole and the first driving crystal a first pole of the tube is connected, and a second pole is connected to a gate of the first driving transistor;
  • a second control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the first driving transistor, and the second pole is connected to the first level;
  • a third control transistor the gate is connected to the first driving control signal, the first pole is connected to the second end of the first storage capacitor, and the second pole is connected to the data voltage;
  • a fourth control transistor the gate is connected to the second driving control signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the first driving transistor;
  • the second drive control unit includes:
  • a fifth control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the second driving transistor, and the second pole is connected to the gate of the second driving transistor;
  • a sixth control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the second driving transistor, and the second pole is connected to the first level;
  • a seventh control transistor the gate is connected to the second driving control signal, the first pole is connected to the second end of the second storage capacitor, and the second pole is connected to the data voltage;
  • an eighth control transistor the gate is connected to the second driving control signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the second driving transistor.
  • the first driving transistor, the first control transistor, the second control transistor, and the third control transistor are all n-type TFTs, and the The four control transistors are p-type TFTs;
  • the second driving transistor, the fifth control transistor, the sixth control transistor, and the seventh control transistor are all n-type TFTs, and the eighth control transistor is P-type TFT.
  • the present disclosure also provides a pixel driving circuit for driving a first light emitting element and a second light emitting element, wherein the first end of the first light emitting element and the first end of the second light emitting element are both connected to the first Level
  • the pixel driving circuit includes a first pixel driving unit and a second pixel driving unit;
  • the first pixel driving unit includes a first driving transistor, a first storage capacitor, and a first driving control unit;
  • the first storage capacitor has a first end connected to a gate of the first driving transistor and a second end passing through The first driving control unit accesses a data voltage
  • a first driving transistor the gate is connected to the first electrode of the first driving transistor through the first driving control unit, and the first electrode is connected to the second end of the first light emitting element through the first driving control unit,
  • the second pole is connected to the second level by the first driving control unit;
  • the first driving control unit is configured to perform reset charging on the first storage capacitor by the second level and the data voltage, so as to control a pair by applying a hopping voltage to the data voltage in a first compensation phase
  • the threshold voltage of the first driving transistor is subjected to hopping compensation, and controlling the first driving transistor to drive the first illuminating element to emit light;
  • the second pixel driving unit includes a second driving transistor, a second storage capacitor, and a second driving control unit;
  • a second storage capacitor the first end is connected to the gate of the second driving transistor, and the second end is connected to the data voltage through the second driving control unit;
  • the second driving transistor has a gate connected to the first electrode of the second driving transistor through the second driving control unit, and the first electrode is connected to the second end of the second illuminating element through the second driving control unit, The second pole is connected to the second level by the second driving control unit;
  • the second driving control unit is configured to reset and charge the second storage capacitor by the second level and the data voltage, so as to control a pair by applying a hopping voltage to the data voltage in a second compensation phase
  • the threshold voltage of the second driving transistor is subjected to hopping compensation, and the second driving transistor is controlled to drive the second illuminating element to emit light.
  • the structure of the first driving control unit and the structure of the second driving control unit are the same.
  • the first driving control unit includes:
  • a first control transistor the gate is connected to the first driving control signal, the first pole is connected to the first pole of the first driving transistor, and the second pole is connected to the gate of the first driving transistor;
  • a second control transistor the gate is connected to the first driving control signal, the first pole is connected to the data voltage, and the second pole is connected to the second end of the first storage capacitor;
  • a third control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the first driving transistor, and the second pole is connected to the second level;
  • a fourth control transistor the gate is connected to the second scan signal, and the first pole and the first a second end of the optical element is connected, and a second end is connected to the first pole of the first driving transistor;
  • the second drive control unit includes:
  • a fifth control transistor the gate is connected to the second driving control signal, the first pole is connected to the first pole of the second driving transistor, and the second pole is connected to the gate of the second driving transistor;
  • a sixth control transistor the gate is connected to the second driving control signal, the first pole is connected to the data voltage, and the second pole is connected to the second end of the second storage capacitor;
  • a seventh control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the second driving transistor, and the second pole is connected to the second level;
  • the gate is connected to the second scan signal, the first pole is connected to the second end of the second light emitting element, and the second pole is connected to the first pole of the second driving transistor.
  • the first driving transistor, the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are a p-type TFT
  • the second driving transistor, the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are P-type TFT.
  • the present disclosure also provides a pixel driving method for driving the above pixel driving circuit, including:
  • the first driving control unit controls the potential of the first end of the first storage capacitor to be charged to the second level
  • the second driving control unit controls the potential of the first end of the second storage capacitor to be charged To the second level
  • the first driving control unit controls the potential of the first end of the first storage capacitor to be discharged to the threshold voltage of the first driving transistor, and controls the second end of the first storage capacitor to access the data voltage;
  • the second driving control unit controls the potential of the first end of the second storage capacitor to be discharged to the threshold voltage of the second driving transistor, and controls the second end of the second storage capacitor to access the data voltage; wherein the data is in the discharging phase
  • the voltage is V0;
  • the first driving control unit controls the second end of the first storage capacitor to access the data voltage, and controls the first end of the first storage capacitor to float, thereby controlling the first driving transistor.
  • the gate-source voltage compensates the threshold voltage of the first driving transistor; wherein, in the first compensation phase, the data voltage jumps to V0+ ⁇ V1;
  • the second driving control unit controls the second end of the second storage capacitor to access the data voltage, and controls the first end of the second storage capacitor to float, thereby controlling the second driving transistor.
  • the gate-source voltage compensates the threshold voltage of the second driving transistor; wherein, in the second compensation phase, the data voltage jumps to V0+ ⁇ V2;
  • the first driving control unit controls the first driving transistor to drive the first light emitting element to emit light
  • the second driving control unit controls the second driving transistor to drive the second light emitting element to emit light
  • the driving TFT included in the pixel driving circuit is an n-type TFT
  • V0, ⁇ V1, and ⁇ V2 are greater than 0, and ⁇ V2 is greater than ⁇ V1.
  • the present disclosure provides a pixel driving method for driving the above pixel driving circuit, including:
  • the first driving control unit controls the potential of the first end of the first storage capacitor to be charged to a difference between the second level and the threshold voltage of the first driving transistor, and controls the first The second end of the storage capacitor is connected to the data voltage;
  • the second driving control unit controls the potential of the first end of the second storage capacitor to be charged to a difference between the second level and the threshold voltage of the second driving transistor, and controls the first The second end of the second storage capacitor is connected to the data voltage;
  • the data voltage is ⁇ V1 during the reset charging phase;
  • the first driving control unit controls the first end of the first storage capacitor to float, thereby controlling the gate-source voltage of the first driving transistor to compensate the threshold voltage of the first driving transistor;
  • the data phase jumps to ⁇ V2 in the first compensation phase;
  • the second driving control unit controls the first end of the second storage capacitor to float, thereby controlling the gate-source voltage of the second driving transistor to compensate the threshold voltage of the second driving transistor;
  • the second compensation phase shifts the data voltage to ⁇ V3;
  • the first driving control unit controls the first driving transistor to drive the first light emitting element to emit light
  • the second driving control unit controls the second driving transistor to drive the second light emitting element to emit light
  • the driving TFT included in the pixel driving circuit is a p-type TFT
  • ⁇ V1, ⁇ V2, and ⁇ V3 are both greater than 0, and ⁇ V3 is greater than ⁇ V2, and V2 is greater than ⁇ V1.
  • the present disclosure also provides a display panel including the above-described pixel driving circuit.
  • the present disclosure also provides a display device including the above display panel.
  • the pixel driving circuit of the embodiment of the present disclosure combines two conventional adjacent pixel driving units with threshold compensation functions, so that the two pixel driving units share one data line, thereby using a pixel driving circuit with threshold compensation function.
  • FIG. 1 is a circuit diagram of a conventional basic AMLOED pixel driving circuit
  • FIG. 2 is a block diagram showing the structure of a pixel driving circuit according to a second embodiment of the present disclosure
  • 3A is a circuit diagram of a pixel driving circuit according to a third embodiment of the present disclosure.
  • 3B is a circuit diagram of a pixel driving circuit according to a fourth embodiment of the present disclosure.
  • 3C is a circuit diagram of a pixel driving circuit according to a fifth embodiment of the present disclosure.
  • FIG. 4 is a timing chart showing the operation of the pixel driving circuit according to the third embodiment of the present disclosure.
  • 5A is a view showing an operation state of a pixel driving circuit according to a third embodiment of the present disclosure in a first stage
  • 5B is a view showing an operation state of a pixel driving circuit according to a third embodiment of the present disclosure in a second stage;
  • 5C is a view showing an operation state of the pixel driving circuit in the third stage according to the third embodiment of the present disclosure
  • 5D is a diagram showing an operation state of a pixel driving circuit according to a third embodiment of the present disclosure in a fourth stage;
  • 5E is a diagram showing an operation state of a pixel driving circuit according to a third embodiment of the present disclosure in a fifth stage;
  • FIG. 6 is a block diagram showing the structure of a pixel driving circuit according to a seventh embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram of a pixel driving circuit according to an eighth embodiment of the present disclosure.
  • FIG. 8 is a timing chart showing an operation of a pixel driving circuit according to an eighth embodiment of the present disclosure.
  • 9A is a view showing an operation state of a pixel driving circuit according to an eighth embodiment of the present disclosure in a first stage
  • FIG. 9B is a working state of the pixel driving circuit in the second stage according to the eighth embodiment of the present disclosure.
  • 9C is a view showing an operation state of a pixel driving circuit according to an eighth embodiment of the present disclosure in a third stage;
  • 9D is a view showing an operation state of a pixel driving circuit according to an eighth embodiment of the present disclosure in a fourth stage;
  • FIG. 10 is a schematic diagram of a pixel circuit in which a pixel driving circuit according to an embodiment of the present disclosure is disposed.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the first pole may be a source or a drain
  • the second pole may be a drain or a source.
  • the transistor can be classified into an n-type transistor or a p-type transistor according to the characteristics of the transistor.
  • the driving circuit provided by the embodiment of the present disclosure, it is conceivable that the implementation using an n-type transistor or a p-type transistor is easily conceivable by those skilled in the art without creative work, and thus is also implemented in the present disclosure. Within the scope of protection.
  • the pixel driving circuit of the first embodiment of the present disclosure is configured to drive the first light emitting element and the second light emitting element, wherein the first end of the first light emitting element and the first end of the second light emitting element are both connected a first level; wherein the pixel driving circuit includes a first pixel driving unit and a second pixel driving unit;
  • the first pixel driving unit includes a first driving transistor, a first storage capacitor, and a first driving control unit, where
  • the first storage capacitor has a first end connected to the gate of the first driving transistor, and a second end accessing the data voltage through the first driving control unit;
  • a first driving transistor the gate is connected to the first electrode of the first driving transistor by the first driving control unit, the first pole is connected to the second level by the first driving control unit, and the second pole passes The first driving control unit is connected to the first level; the second pole of the first driving transistor is further connected to the second end of the first illuminating element;
  • the first driving control unit is configured to charge and discharge the first storage capacitor by the second level, the data voltage, and the first level, thereby applying a transition to the data voltage in the first compensation phase
  • the voltage is controlled to perform trip compensation for the threshold voltage of the first driving transistor, and controls the first light emitting element to emit light;
  • the second pixel driving unit includes a second driving transistor, a second storage capacitor, and a second driving control unit, where
  • the second storage capacitor has a first end connected to a gate of the second driving transistor, and a second end is connected to the data voltage through the first driving control unit;
  • a second driving transistor the gate is connected to the first electrode of the second driving transistor by the second driving control unit, the first pole is connected to the second level by the second driving control unit, and the second pole passes the first
  • the second driving control unit is connected to the first level; the second electrode of the second driving transistor is further connected to the second end of the second illuminating element;
  • the second driving control unit is configured to charge and discharge the second storage capacitor by the second level, the data voltage, and the first level, thereby applying a transition to the data voltage in the second compensation phase
  • the voltage is controlled to perform trip compensation for the threshold voltage of the second driving transistor, and to control the second light emitting element to emit light.
  • the pixel driving circuit of the embodiment of the present disclosure combines two conventional adjacent pixel driving units having a threshold compensation function, so that the first pixel driving unit and the second pixel driving unit share one data line; therefore, it can be used.
  • a pixel driving circuit with a threshold compensation function controls the two pixel units to perform the jump compensation of the threshold of the driving transistor in the respective compensation stages; meanwhile, the number of TFTs and the data lines used for compensation can be greatly improved.
  • the cell's aperture ratio and cost reduction result in higher picture quality and PPI (Pixels per inch, number of pixels per inch).
  • the light emitting element may be an OLED.
  • the pixel driving circuit of the second embodiment of the present disclosure is used to drive the first organic light emitting diode O1 and the second organic light emitting diode O2;
  • the cathode of the first organic light emitting diode O1 and the cathode of the second organic light emitting diode O2 are both connected First level V1;
  • the pixel driving circuit includes a first pixel driving unit that controls the first organic light emitting diode O1, and a second pixel driving unit that controls the second organic light emitting diode O2;
  • the first pixel driving unit includes a first driving transistor D1, a first storage capacitor C1, and a first driving control unit 21;
  • the first storage capacitor C1, the first end is connected to the gate of the first driving transistor D1, and the second end is connected to the data voltage on the data line Data through the first driving control unit 21;
  • the first driving transistor D1 has a gate connected to the first electrode of the first driving transistor D1 through the first driving control unit 21, and the first electrode is connected to the second level V2 through the first driving control unit 21,
  • the second pole is connected to the first level V1 through the first driving control unit 21;
  • the second pole of the first driving transistor D1 is also connected to the anode of the first organic light emitting diode O1;
  • the first driving control unit 21 is configured to charge and discharge the first storage capacitor C1 through the second level V2, the data voltage on the data line Data, and the first level V1, thereby being in the first compensation stage. After controlling the threshold voltage of the first driving transistor D1 to compensate the threshold voltage of the first driving transistor D1, controlling the first driving transistor D1 to drive the first organic light emitting diode O1 to emit light;
  • the second pixel driving unit includes a second driving transistor D2, a second storage capacitor C2, and a second driving control unit 22;
  • the second storage capacitor C2 the first end is connected to the gate of the second driving transistor D2, and the second end is connected to the data voltage on the data line Data through the second driving control unit 22;
  • the second driving transistor D2 has a gate connected to the first electrode of the second driving transistor D2 through the second driving control unit 22, and the first electrode is connected to the second level V2 through the second driving control unit 22,
  • the second pole is connected to the first level V1 through the second driving control unit 22;
  • the second pole of the second driving transistor D2 is also connected to the anode of the second organic light emitting diode O2;
  • the second driving control unit 22 is configured to charge and discharge the second storage capacitor C2 through the second level V2, the data voltage on the data line Data, and the first level V1, thereby being in the second compensation stage. After controlling the gate-source voltage of the second driving transistor D2 to compensate the threshold voltage of the second driving transistor D2, the second driving transistor D2 is controlled to drive the second organic light-emitting diode O2 to emit light.
  • both D1 and D2 are n-type TFTs, in which case the first level V1 is at a low level and the second level V2 is at a high level.
  • the structure of the first drive control unit and the structure of the second drive control unit may be the same.
  • the first driving control unit includes:
  • a first control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the first driving transistor, and the second pole is connected to the gate of the first driving transistor;
  • a second control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the first driving transistor, and the second pole is connected to the first level;
  • a third control transistor the gate is connected to the first driving control signal, the first pole is connected to the second end of the first storage capacitor, and the second pole is connected to the data voltage;
  • a fourth control transistor the gate is connected to the second scan signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the first driving transistor;
  • the second drive control unit includes:
  • a fifth control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the second driving transistor, and the second pole is connected to the gate of the second driving transistor;
  • a sixth control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the second driving transistor, and the second pole is connected to the first level;
  • a seventh control transistor the gate is connected to the second driving control signal, the first pole is connected to the second end of the second storage capacitor, and the second pole is connected to the data voltage;
  • an eighth control transistor the gate is connected to the second scan signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the second driving transistor.
  • the first driving transistor, the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are both n a TFT of the second pixel driving unit, wherein the second driving transistor, the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are n Type TFT.
  • the first driving control unit may include:
  • a first control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the first driving transistor, and the second pole is connected to the gate of the first driving transistor;
  • a second control transistor the gate is connected to the first scan signal, the first pole and the first driving crystal a second pole of the tube is connected, and the second pole is connected to the first level;
  • a third control transistor the gate is connected to the first driving control signal, the first pole is connected to the second end of the first storage capacitor, and the second pole is connected to the data voltage;
  • a fourth control transistor the gate is connected to the second scan signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the first driving transistor;
  • the second drive control unit includes:
  • a fifth control transistor the gate is connected to the first scan signal, the first pole is connected to the first pole of the second driving transistor, and the second pole is connected to the gate of the second driving transistor;
  • a sixth control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the second driving transistor, and the second pole is connected to the first level;
  • a seventh control transistor the gate is connected to the second scan signal, the first pole is connected to the second end of the second storage capacitor, and the second pole is connected to the data voltage;
  • an eighth control transistor the gate is connected to the second scan signal, the first pole is connected to the second level, and the second pole is connected to the first pole of the second driving transistor.
  • the first driving transistor, the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are all n-type TFTs;
  • the second driving transistor, the fifth control transistor, the sixth control transistor, and the eighth control transistor are both n-type TFTs, and the seventh control transistor is a p-type TFT.
  • the pixel driving circuit of the third embodiment of the present disclosure is configured to drive the first organic light emitting diode O1 and the second organic light emitting diode O2;
  • the cathode of the first organic light emitting diode O1 and the cathode of the second organic light emitting diode O2 are both grounded GND;
  • the pixel driving circuit includes a first pixel driving unit that controls the first organic light emitting diode O1, and a second pixel driving unit that controls the second organic light emitting diode O2;
  • the first pixel driving unit includes a first driving transistor D1, a first storage capacitor C1, and a first driving control unit;
  • a gate of the first driving transistor D1 is connected to a first end of the first storage capacitor C1;
  • the first drive control unit includes:
  • the first control transistor T1 has a gate connected to the first scan signal Scan1, a first pole connected to the first pole of the first driving transistor D1, and a second pole connected to the gate of the first driving transistor D1;
  • the second control transistor T2 the gate is connected to the first scan signal Scan1, the first pole is connected to the second pole of the first driving transistor D1, and the second pole is connected to the ground GND;
  • a third control transistor T3 the gate is connected to the first driving control signal EM1, the first pole is connected to the second end of the first storage capacitor C1, and the second pole is connected to the data voltage on the data line Data;
  • a fourth control transistor T4 the gate is connected to the second scan signal Scan2, the first pole is connected to the high level Vdd, and the second pole is connected to the first pole of the first driving transistor D1;
  • a second pole of the first driving transistor D1 is connected to an anode of the first organic light emitting diode O1;
  • the second pixel driving unit includes a second driving transistor D2, a second storage capacitor C2, and a second driving control unit;
  • a gate of the second driving transistor D2 is connected to a first end of the second storage capacitor C2;
  • the second drive control unit includes:
  • a fifth control transistor T5 the gate is connected to the first scan signal Scan1, the first pole is connected to the first pole of the second driving transistor D2, and the second pole is connected to the gate of the second driving transistor D2;
  • the sixth control transistor T6, the gate is connected to the first scan signal Scan1, the first pole is connected to the second pole of the second driving transistor D2, and the second pole is grounded at the ground GND;
  • a seventh control transistor T7 the gate is connected to the second driving control signal EM2, the first pole is connected to the second end of the second storage capacitor C2, and the second pole is connected to the data voltage on the data line Data;
  • an eighth control transistor T8 the gate is connected to the second scan signal Scan2, the first pole is connected to the high level Vdd, and the second pole is connected to the first pole of the second driving transistor D2;
  • a second pole of the second driving transistor D2 is connected to an anode of the second organic light emitting diode O2;
  • the node connected to the first end of C1 is identified as a1, and the node connected to the first end of C2 is identified as a2;
  • the node connected to the second end of C1 is identified as b1, and the node connected to the second end of C2 is identified as B2.
  • D1, D2, T1, T2, T3, T4, T5, T6, T7 and T8 are all n-type TFTs, which can unify the process flow and help to improve the product. Yield.
  • the pixel driving circuit according to the fourth embodiment of the present disclosure may replace the transistor type of the T7 of the original access EM2 in FIG. 3A with a p-type, and change the control signal of the gate connected to the T7. It is the second scan signal Scan2; the same can be achieved for the purpose of the invention, and the number of control signals can be reduced.
  • FIG. 3B the pixel driving circuit according to the fourth embodiment of the present disclosure may replace the transistor type of the T7 of the original access EM2 in FIG. 3A with a p-type, and change the control signal of the gate connected to the T7. It is the second scan signal Scan2; the same can be achieved for the purpose of the invention, and the number of control signals can be reduced.
  • the pixel driving circuit according to the fifth embodiment of the present disclosure may change the control signal of the gate of T4 and the gate of T8 of FIG. 3A from Scan2 to EM2, and simultaneously convert the transistor of T4.
  • Types and T8 transistor types are changed to p-type, which also achieves the purpose of the invention while reducing the number of control signals.
  • both Scan1 and Scan2 are high, EM1 and EM2 are both low, and the data voltage Vdata on the data line is V0;
  • Vdd charges C1 through T4 and T1 such that the potential at point a1 is Vdd and T3 is turned off;
  • Vdd charges C2 through T8 and T5 such that the potential at point a2 is Vdd and T7 is off.
  • Scan1, EM1, and EM2 are both high level, Scan2 is low level, and Vdata is V0;
  • T1, T2, and T3 are all turned on, T4 is turned off, and C1 is discharged to the ground through T1, D1, and T2 until the potential at the point a1 is the threshold voltage Vth1 of D1, and the point b1 is connected to Vdata. At this time, the potential at point b1 is V0;
  • T5 T6 and T7 are both on, T8 is off, C2 is discharged to the ground through T5, D2 and T6 until the potential at point a2 is the threshold voltage Vth2 of D2, and the point b2 is connected to Vdata, then the potential at point b2 Is V0.
  • the first compensation phase Scan1 and Scan2 are both low, EM1 and EM2 are both high, and Vdata jumps to V0+ ⁇ V1;
  • Scan1, Scan2, and EM1 are both low level, EM2 is high level, and Vdata jumps to V0+ ⁇ V2;
  • the potential at point b2 is changed from V0+ ⁇ V1 in the third stage to V0+ ⁇ V2 in the fourth stage, and the potential Va2 at point a2 and the potential Vb2 at point b2 are due to floating at the first end of C2.
  • Scan1, EM1, and EM2 are both low level, and Scan2 is high level;
  • the OLED illumination phase is entered, T4 is turned on, the first pole of D1 is connected to the high level Vdd through T4, T2 is disconnected, and D1 drives the first organic light.
  • the current flowing through O2 is K( ⁇ V2-Voled2) 2
  • Voled2 is the anode potential of O2.
  • the pixel driving circuit of the embodiment of the present disclosure performs a hopping threshold compensation by sequentially performing a hopping threshold compensation on a first pixel unit including a first organic light emitting diode and a second pixel including a second organic light emitting diode, by applying a hopping signal to Vdata That is, the pixel compensation is realized by the signal superposition hopping in different time zones, which solves the problem that the threshold voltage is not uniform due to the process process and long-time operation of the dual-pixel point driving TFT, so that two pixel units including the OLED are flowed.
  • the current is not affected by the threshold voltage of the driving transistor, which ultimately ensures uniformity of image display.
  • the discharging phase, the first compensation phase and the second compensation phase no current can be ensured to pass through the OLED, which indirectly improves the service life of the OLED.
  • An embodiment of the present disclosure further provides a pixel driving method for driving a pixel driving circuit according to the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, or the fifth embodiment of the present disclosure, including :
  • the first driving control unit controls the potential of the first end of the first storage capacitor to be charged to the second level
  • the second driving control unit controls the potential of the first end of the second storage capacitor to be charged To the second level
  • the first driving control unit controls the potential of the first end of the first storage capacitor to be discharged to the threshold voltage of the first driving transistor, and controls the second end of the first storage capacitor to access the data voltage;
  • the second driving control unit controls the potential of the first end of the second storage capacitor to be discharged to the threshold voltage of the second driving transistor, and controls the second end of the second storage capacitor to access the data voltage; wherein the data is in the discharging phase
  • the voltage is V0;
  • the first driving control unit controls the second end of the first storage capacitor to access the data voltage, and controls the first end of the first storage capacitor to float, thereby controlling the first driving transistor.
  • the gate-source voltage compensates the threshold voltage of the first driving transistor; wherein, in the first compensation phase, the data voltage jumps to V0+ ⁇ V1;
  • the second driving control unit controls the second end of the second storage capacitor to access the data voltage, and controls the first end of the second storage capacitor to float, thereby controlling the second driving transistor.
  • the gate-source voltage compensates the threshold voltage of the second driving transistor; wherein, in the second compensation phase, the data voltage jumps to V0+ ⁇ V2;
  • the first driving control unit controls the first driving transistor to drive the first light emitting element to emit light
  • the second driving control unit controls the second driving transistor to drive the second light emitting element to emit light
  • the pixel driving circuit according to the above embodiment of the present disclosure includes a driving TFT which is an n-type TFT, V0 is greater than 0, ⁇ V1 and ⁇ V2 are both greater than 0, and ⁇ V2 is greater than ⁇ V1.
  • the pixel driving circuit of the sixth embodiment of the present disclosure is configured to drive the first light emitting element and the second light emitting element, wherein the first end of the first light emitting element and the first end of the second light emitting element are both connected First level
  • the pixel driving circuit includes a first pixel driving unit and a second pixel driving unit;
  • the first pixel driving unit includes a first driving transistor, a first storage capacitor, and a first driving control unit;
  • the first storage capacitor has a first end connected to the gate of the first driving transistor, and a second end accessing the data voltage through the first driving control unit;
  • a first driving transistor the gate is connected to the first electrode of the first driving transistor through the first driving control unit, and the first electrode is connected to the second end of the first light emitting element through the first driving control unit,
  • the second pole is connected to the second level by the first driving control unit;
  • the first driving control unit is configured to perform reset charging on the first storage capacitor by the second level and the data voltage, so as to control a pair by applying a hopping voltage to the data voltage in a first compensation phase
  • the threshold voltage of the first driving transistor is subjected to hopping compensation, and controlling the first driving transistor to drive the first illuminating element to emit light;
  • the second pixel driving unit includes a second driving transistor, a second storage capacitor, and a second driving control unit;
  • a second storage capacitor the first end is connected to the gate of the second driving transistor, and the second end is connected to the data voltage through the second driving control unit;
  • the second driving transistor has a gate connected to the first electrode of the second driving transistor through the second driving control unit, and the first electrode is connected to the second end of the second illuminating element through the second driving control unit, The second pole is connected to the second level by the second driving control unit;
  • the second driving control unit is configured to reset and charge the second storage capacitor by the second level and the data voltage, so as to control a pair by applying a hopping voltage to the data voltage in a second compensation phase
  • the threshold voltage of the second driving transistor is subjected to hopping compensation, and the second driving transistor is controlled to drive the second illuminating element to emit light.
  • the pixel driving circuit of the embodiment of the present disclosure combines two conventional adjacent pixel driving units having a threshold compensation function, so that the first pixel driving unit and the second pixel driving unit share one data line, and thus, Using a pixel driving circuit with threshold compensation function to control the threshold compensation of the two pixel units in the corresponding compensation phase; simultaneously compressing the number of TFTs for compensation and the number of data lines, the aperture ratio of the pixel unit can be greatly improved. And reduce costs, resulting in higher image quality and PPI.
  • the light emitting element may be an OLED.
  • the pixel driving circuit according to the seventh embodiment of the present disclosure is used to drive the first The light emitting diode O1 and the second organic light emitting diode O2;
  • the cathode of the first organic light emitting diode O1 and the cathode of the second organic light emitting diode O2 are both connected to the first level V1;
  • the pixel driving circuit includes a first pixel driving unit that controls the first organic light emitting diode O1, and a second pixel driving unit that controls the second organic light emitting diode O2;
  • the first pixel driving unit includes a first driving transistor D1, a first storage capacitor C1, and a first driving control unit 61;
  • the first storage capacitor C1, the first end is connected to the gate of the first driving transistor D1, and the second end is connected to the data voltage on the data line Data through the first driving control unit 61;
  • the first driving transistor D1 is connected to the first electrode of the first driving transistor D1 through the first driving control unit 61, and the first electrode passes through the first driving control unit 61 and the first organic light emitting diode O1.
  • the anode connection, the second pole is connected to the second level V2 through the first drive control unit 61;
  • the second pixel driving unit includes a second driving transistor D2, a second storage capacitor C2, and a second driving control unit 62;
  • the second storage capacitor C2 the first end is connected to the gate of the second driving transistor D2, and the second end is connected to the data voltage on the data line Data through the second driving control unit 62;
  • the second driving transistor D2 has a gate connected to the first electrode of the second driving transistor D2 through the second driving control unit 62, and the first electrode passes through the second driving control unit 62 and the second organic light emitting diode O2 The anode is connected, and the second pole is connected to the second level V2 through the second drive control unit 62.
  • both D1 and D2 are p-type TFTs, and the first level V1 is at a low level and the second level V2 is at a high level.
  • the structure of the first drive control unit and the structure of the second drive control unit may be the same.
  • the first driving control unit includes:
  • a first control transistor the gate is connected to the first driving control signal, the first pole is connected to the first pole of the first driving transistor, and the second pole is connected to the gate of the first driving transistor;
  • a second control transistor the gate is connected to the first driving control signal, the first pole is connected to the data voltage, and the second pole is connected to the second end of the first storage capacitor;
  • a third control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the first driving transistor, and the second pole is connected to the second level;
  • a fourth control transistor the gate is connected to the second scan signal, the first pole is connected to the second end of the first light emitting element, and the second pole is connected to the first pole of the first driving transistor;
  • the second drive control unit includes:
  • a fifth control transistor the gate is connected to the second driving control signal, the first pole is connected to the first pole of the second driving transistor, and the second pole is connected to the gate of the second driving transistor;
  • a sixth control transistor the gate is connected to the second driving control signal, the first pole is connected to the data voltage, and the second pole is connected to the second end of the second storage capacitor;
  • a seventh control transistor the gate is connected to the first scan signal, the first pole is connected to the second pole of the second driving transistor, and the second pole is connected to the second level;
  • the gate is connected to the second scan signal, the first pole is connected to the second end of the second light emitting element, and the second pole is connected to the first pole of the second driving transistor.
  • the first driving transistor, the first control transistor, the second control transistor, the third control transistor, and the fourth control transistor are both p a TFT of the second pixel driving unit, wherein the second driving transistor, the fifth control transistor, the sixth control transistor, the seventh control transistor, and the eighth control transistor are both p Type TFT.
  • the pixel driving circuit of the eighth embodiment of the present disclosure is used to drive the first organic light emitting diode O1 and the second organic light emitting diode O2;
  • the cathode of the first organic light emitting diode O1 and the cathode of the second organic light emitting diode O2 are both grounded GND;
  • the pixel driving circuit includes a first pixel driving unit that controls the first organic light emitting diode O1, and a second pixel driving unit that controls the second organic light emitting diode O2;
  • the first pixel driving unit includes a first driving transistor D1, a first storage capacitor C1, and a first driving control unit;
  • the first storage capacitor C1 has a first end a1 connected to a gate of the first driving transistor D1;
  • the first drive control unit includes:
  • the first pole is connected to the first pole of the first driving transistor D1
  • the second pole is connected to the gate of the first driving transistor D1;
  • the first pole is connected to the data voltage on the data line Data, and the second pole is connected to the second end b1 of the first storage capacitor C1;
  • the third control transistor T3, the gate is connected to the first scan signal Scan1, the first pole is connected to the second pole of the first driving transistor D1, and the second pole is connected to the high level Vdd;
  • a fourth control transistor T4 the gate is connected to the second scan signal Scan2, the first pole is connected to the anode of the first organic light emitting diode O1, and the second pole is connected to the first pole of the first driving transistor D1;
  • the second pixel driving unit includes a second driving transistor D2, a second storage capacitor C2, and a second driving control unit;
  • the second storage capacitor C2, the first end a2 is connected to the gate of the second driving transistor D2;
  • the second drive control unit includes:
  • a fifth control transistor T5 the first pole is connected to the first pole of the second driving transistor D2, and the second pole is connected to the gate of the second driving transistor D2;
  • the first pole is connected to the data voltage on the data line Data, and the second pole is connected to the second end b2 of the second storage capacitor C2;
  • the seventh control transistor T7 the gate is connected to the first scan signal Scan1, the first pole is connected to the second pole of the second driving transistor D2, and the second pole is connected to the high level Vdd;
  • an eighth control transistor T8 the gate is connected to the second scan signal Scan2, the first pole is connected to the anode of the second organic light emitting diode O2, and the second pole is connected to the first pole of the second driving transistor D2;
  • the gate of T1 and the gate of T2 are both connected to the third scan signal Scan3;
  • the gate of T5 and the gate of T6 are both connected to the fourth scan signal Scan4;
  • T1, T2, T3, T4, T5, T6, T7, T8, D1 and D2 are all p-type TFTs.
  • all TFTs are p-type TFTs, which can unify the process flow and help to improve product yield.
  • the original two pixel drive units with threshold compensation are combined. And is a pixel driving circuit, and is controlled by only one data line Data, wherein T1, T2, T3, T4, T5, T6, T7 and T8 are all switching TFTs, D1 and D2 are pixel driving TFTs, Scan1. Scan2, Scan3, and Scan4 are both scan signals used to control the switching TFTs to be turned on or off.
  • Scan1, Scan3, and Scan4 are both low level, and Scan2 is high level;
  • Vdd starts charging a1 point through T3, D1, and T1, and charges the potential of a1 point to Vdd-Vth1 (the source of D1 is satisfied).
  • the voltage difference between them is Vth1, and Vth1 is the threshold voltage of D1.
  • Vdata since the data voltage Vdata is turned on at point b1, the potential at point b1 is ⁇ V1, so when the charging is completed, the potential difference between C1 ends. Will consistently maintain Vdd-Vth1- ⁇ V1, and because T4 is turned off, the current will not flow through O1, which indirectly reduces the lifetime loss of O1;
  • Vdd-Vth2- ⁇ V1 the potential difference across C2 of another pixel unit will be maintained at Vdd-Vth2- ⁇ V1, and Vth2 is the threshold voltage of D2;
  • both Scan1 and Scan2 are at a high level, and both Scan3 and Scan4 are at a low level;
  • Scan1, Scan2, and Scan3 are both high level, and Scan4 is low level;
  • both Scan1 and Scan2 are low, Scan3 And Scan4 are both high;
  • the OLED enters a formal illumination phase, and the conduction state is as shown in FIG. 9D, and the working voltage is connected to Vdd, and the two pixels emit light through respective paths;
  • the TFT saturation current formula can be obtained:
  • the current of the current I O2 flowing through O2 is K( ⁇ V3- ⁇ V1) 2 .
  • the pixel driving circuit performs hopping compensation on the first pixel unit including the first organic light emitting diode and the second pixel including the second organic light emitting diode in turn, by applying a hopping signal to Vdata, that is,
  • the pixel compensation is realized by the signal superposition hopping in different time zones, which solves the problem that the threshold voltage is not uniform due to the process process and long-time operation of the dual-pixel point driving TFT, so that the current flowing through the two pixel units including the OLED is not affected.
  • the influence of the threshold voltage of the driving transistor finally ensures the uniformity of the image display, and the compensation and transition phases ensure that no current flows through the OLED, which indirectly improves the service life of the OLED.
  • An embodiment of the present disclosure further provides a pixel driving method for driving the pixel driving circuit according to the fifth embodiment, the sixth embodiment, or the seventh embodiment of the present disclosure, including:
  • the first driving control unit controls the potential of the first end of the first storage capacitor to be charged to a difference between the second level and the threshold voltage of the first driving transistor, and controls the first The second end of the storage capacitor is connected to the data voltage;
  • the second driving control unit controls the potential of the first end of the second storage capacitor to be charged to a difference between the second level and the threshold voltage of the second driving transistor, and controls the first The second end of the second storage capacitor is connected to the data voltage;
  • the data voltage is ⁇ V1 during the reset charging phase;
  • the first driving control unit controls the first end of the first storage capacitor to float, thereby controlling the gate-source voltage of the first driving transistor to compensate the threshold voltage of the first driving transistor;
  • the data phase jumps to ⁇ V2 in the first compensation phase;
  • the second driving control unit controls the first end of the second storage capacitor to float, thereby controlling the gate-source voltage of the second driving transistor to compensate the threshold voltage of the second driving transistor;
  • the second compensation phase shifts the data voltage to ⁇ V3;
  • the first driving control unit controls the driving of the first driving transistor during the light emitting phase of the time period
  • the first light emitting element emits light
  • the second driving control unit controls the second driving transistor to drive the second light emitting element to emit light
  • the pixel driving circuit of the embodiment of the present disclosure includes a driving TFT which is a p-type TFT, ⁇ V1, ⁇ V2, and ⁇ V3 are both greater than 0, and ⁇ V3 is greater than ⁇ V2, and V2 is greater than ⁇ V1.
  • the pixel driving circuit according to an embodiment of the present disclosure is disposed in two phases in the pixel circuit as shown in FIG. In the adjacent pixel unit, the two adjacent pixel units share a data line.
  • the pixel driving circuit according to the embodiment of the present disclosure may be disposed in the adjacent red pixel unit R and the green pixel unit G, and the pixel driving circuit according to the embodiment of the present disclosure may be disposed in the phase. Adjacent green pixel unit G and blue pixel unit B.
  • the display panel according to an embodiment of the present disclosure includes the above-described pixel driving circuit.
  • the display device includes the above display panel.
  • the display device may specifically be an AMOLED display device.
  • the pixel circuit, the organic light emitting display panel and the display device described in the present disclosure may adopt an LTPS (Low Temperature Polysilicon Technology) process.
  • LTPS Low Temperature Polysilicon Technology
  • the pixel circuit, the organic light emitting display panel and the display device described in the present disclosure may also adopt an amorphous silicon process.
  • the pixel circuit provided by the embodiment of the present disclosure may adopt a thin film transistor of a process of amorphous silicon, polysilicon, oxide, or the like.
  • the types of transistors used in the pixel circuit described in the embodiments of the present disclosure may be replaced according to actual needs.
  • the present disclosure is not limited to a display device using an active matrix organic light emitting diode, and can also be applied to a display device using other various light emitting diodes.

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Abstract

一种像素驱动电路、驱动方法、显示面板和显示装置。像素驱动电路包括第一像素驱动单元和第二像素驱动单元；第一像素驱动单元包括第一驱动晶体管（D1）、第一存储电容（C1）和第一驱动控制单元（21）；第一驱动控制单元（21）在第一补偿阶段（3）通过对数据电压（Vdata）施加跳变的电压（V0+△V1）以控制对第一驱动晶体管（D1）的阈值电压（Vth1）进行跳变补偿；第二像素驱动单元包括第二驱动晶体管（D2）、第二存储电容（C2）和第二驱动控制单元（22）；第二驱动控制单元在第二补偿阶段（4）通过对数据电压（Vdata）施加跳变的电压（V0+△V2）以控制对第二驱动晶体管（D2）的阈值电压（Vth2）进行跳变补偿，并控制第二发光元件（O2）发光。

Description

像素驱动电路、方法、显示面板和显示装置
相关申请的交叉引用
本申请主张在2014年9月25日在中国提交的中国专利申请号No.201410498525.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路、方法、显示面板和显示装置。
背景技术
AMOLED(Active Matrix/Organic Light Emitting Diode，有源矩阵有机发光二极管)显示器是当今平板显示器研究领域的热点之一。有机发光二极管(OLED)具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。像素驱动电路设计是AMOLED显示器核心技术内容，具有重要的研究意义。
在AMOLED显示器中，需要稳定的电流来控制OLED发光。由于工艺制程和器件老化等原因，AMOLED显示器中的各像素点的驱动晶体管的阈值电压(Vth)会漂移；这样就导致了流过每个像素点OLED的电流因阈值电压的变化而变化，使得显示亮度不均，从而影响整个图像的显示效果。
如图1所示，每个现有的基本的AMLOED像素驱动电路只包括1个驱动晶体管DTFT，一个开关晶体管T1和一个存储电容Cs，当扫描线选择某一行时，扫描线上的扫描电压Vscan为低电平，T1导通，数据电压Vdata写入存储电容Cs。当该行扫描结束后，Vscan变为高电平，T1关断，存储在Cs上的栅极电压驱动DTFT，使DTFT产生电流来驱动OLED，保证OLED在一帧内持续发光。流过OLED的电流IOLED＝K(VGS-Vth)2，其中，K为常数，VGS为DTFT的栅源电压，Vth为DTFT的阈值电压。正如前面所述，由于工艺制程和器件老化等原因，各像素点的驱动晶体管DTFT的阈值电压Vth会漂移；这样就导致了流过每个像素点OLED的电流因Vth的变化而变化，从而影响整个图像的显示效果。
现有技术中的具有阈值补偿功能的像素驱动电路可以为6T1C像素驱动电路，采用了过多的薄膜晶体管(Thin Film Transistor，TFT)和线路，虽然 满足了补偿阈值的要求，但是像素的开口率相应会比较低；并且现有的像素驱动电路是被设置于每一个像素单元内，从而使得OLED器件分布空间过为紧凑。
发明内容
本公开的主要目的在于提供一种像素驱动电路、方法、像素电路、显示面板和显示装置，以解决现有技术中在进行阈值补偿时采用的TFT和数据线的数目多而引起的像素单元的开口率低，从而不能获得更高的画质和PPI(Pixels per inch，每英寸所拥有的像素数目)的问题。
为了达到上述目的，本公开提供了一种像素驱动电路，用于驱动第一发光元件和第二发光元件，所述第一发光元件的第一端和所述第二发光元件的第一端均接入第一电平；所述像素驱动电路包括第一像素驱动单元和第二像素驱动单元；
所述第一像素驱动单元包括第一驱动晶体管、第一存储电容和第一驱动控制单元，其中，
该第一存储电容，第一端与该第一驱动晶体管的栅极连接，第二端通过该第一驱动控制单元接入数据电压；
该第一驱动晶体管，栅极通过该第一驱动控制单元与该第一驱动晶体管的第一极连接，第一极通过该第一驱动控制单元接入第二电平，第二极通过该第一驱动控制单元接入该第一电平；该第一驱动晶体管的第二极还与所述第一发光元件的第二端连接；
所述第一驱动控制单元，用于通过该第二电平、该数据电压和该第一电平对所述第一存储电容进行充放电，从而在第一补偿阶段通过对数据电压施加跳变的电压以控制对所述第一驱动晶体管的阈值电压进行跳变补偿，并控制所述第一发光元件发光；
所述第二像素驱动单元包括第二驱动晶体管、第二存储电容和第二驱动控制单元，其中，
该第二存储电容，第一端与该第二驱动晶体管的栅极连接，第二端通过该第一驱动控制单元接入数据电压；
该第二驱动晶体管，栅极通过该第二驱动控制单元与该第二驱动晶体管 的第一极连接，第一极通过该第二驱动控制单元接入第二电平，第二极通过该第二驱动控制单元接入该第一电平；该第二驱动晶体管的第二极还与所述第二发光元件的第二端连接；
所述第二驱动控制单元，用于通过该第二电平、该数据电压和该第一电平对所述第二存储电容进行充放电，从而在第二补偿阶段通过对数据电压施加跳变的电压以控制对所述第二驱动晶体管的阈值电压进行跳变补偿，并控制所述第二发光元件发光。
可选地，第一驱动控制单元的结构和第二驱动控制单元的结构相同。
可选地，所述第一驱动控制单元包括：
第一控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
第二控制晶体管，栅极接入该第一扫描信号，第一极与该第一驱动晶体管的第二极连接，第二极接入该第一电平；
第三控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一存储电容的第二端连接，第二极接入所述数据电压；
以及，第四控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第一驱动晶体管的第一极连接；
所述第二驱动控制单元包括：
第五控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
第六控制晶体管，栅极接入该第一扫描信号，第一极与该第二驱动晶体管的第二极连接，第二极接入该第一电平；
第七控制晶体管，栅极接入第二驱动控制信号，第一极与所述第二存储电容的第二端连接，第二极接入所述数据电压；
以及，第八控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第二驱动晶体管的第一极连接。
可选地，在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第三控制晶体管和所述第四控制晶体管都为n型TFT；
在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管、所述第七控制晶体管和所述第八控制晶体管都为n型TFT。
可选地，所述第一驱动控制单元包括：
第一控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
第二控制晶体管，栅极接入该第一扫描信号，第一极与该第一驱动晶体管的第二极连接，第二极接入该第一电平；
第三控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一存储电容的第二端连接，第二极接入所述数据电压；
以及，第四控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第一驱动晶体管的第一极连接；
所述第二驱动控制单元包括：
第五控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
第六控制晶体管，栅极接入该第一扫描信号，第一极与该第二驱动晶体管的第二极连接，第二极接入该第一电平；
第七控制晶体管，栅极接入第二扫描信号，第一极与所述第二存储电容的第二端连接，第二极接入所述数据电压；
以及，第八控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第二驱动晶体管的第一极连接。
可选地，在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第三控制晶体管和所述第四控制晶体管都为n型TFT；
在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管和所述第八控制晶体管都为n型TFT，所述第七控制晶体管为p型TFT。
可选地，所述第一驱动控制单元包括：
第一控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体 管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
第二控制晶体管，栅极接入该第一扫描信号，第一极与该第一驱动晶体管的第二极连接，第二极接入该第一电平；
第三控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一存储电容的第二端连接，第二极接入所述数据电压；
以及，第四控制晶体管，栅极接入第二驱动控制信号，第一极接入该第二电平，第二极与该第一驱动晶体管的第一极连接；
所述第二驱动控制单元包括：
第五控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
第六控制晶体管，栅极接入该第一扫描信号，第一极与该第二驱动晶体管的第二极连接，第二极接入该第一电平；
第七控制晶体管，栅极接入所述第二驱动控制信号，第一极与所述第二存储电容的第二端连接，第二极接入所述数据电压；
以及，第八控制晶体管，栅极接入所述第二驱动控制信号，第一极接入该第二电平，第二极与该第二驱动晶体管的第一极连接。
可选地，在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管和所述第三控制晶体管都为n型TFT，所述第四控制晶体管为p型TFT；
在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管和所述第七控制晶体管都为n型TFT，所述第八控制晶体管为p型TFT。
本公开还提供了一种像素驱动电路，用于驱动第一发光元件和第二发光元件，所述第一发光元件的第一端和所述第二发光元件的第一端均接入第一电平；
所述像素驱动电路包括第一像素驱动单元和第二像素驱动单元；
所述第一像素驱动单元包括第一驱动晶体管、第一存储电容和第一驱动控制单元；
该第一存储电容，第一端与该第一驱动晶体管的栅极连接，第二端通过 该第一驱动控制单元接入数据电压；
该第一驱动晶体管，栅极通过该第一驱动控制单元与该第一驱动晶体管的第一极连接，第一极通过该第一驱动控制单元与所述第一发光元件的第二端连接，第二极通过该第一驱动控制单元接入第二电平；
所述第一驱动控制单元，用于通过该第二电平和该数据电压对所述第一存储电容进行重置充电，从而在第一补偿阶段通过对该数据电压施加跳变的电压以控制对所述第一驱动晶体管的阈值电压进行跳变补偿，并控制该第一驱动晶体管驱动所述第一发光元件发光；
所述第二像素驱动单元包括第二驱动晶体管、第二存储电容和第二驱动控制单元；
该第二存储电容，第一端与该第二驱动晶体管的栅极连接，第二端通过该第二驱动控制单元接入数据电压；
该第二驱动晶体管，栅极通过该第二驱动控制单元与该第二驱动晶体管的第一极连接，第一极通过该第二驱动控制单元与所述第二发光元件的第二端连接，第二极通过该第二驱动控制单元接入第二电平；
所述第二驱动控制单元，用于通过该第二电平和该数据电压对所述第二存储电容进行重置充电，从而在第二补偿阶段通过对该数据电压施加跳变的电压以控制对所述第二驱动晶体管的阈值电压进行跳变补偿，并控制该第二驱动晶体管驱动所述第二发光元件发光。
可选地，所述第一驱动控制单元的结构和所述第二驱动控制单元的结构相同。
可选地，所述第一驱动控制单元包括：
第一控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
第二控制晶体管，栅极接入所述第一驱动控制信号，第一极接入数据电压，第二极与所述第一存储电容的第二端连接；
第三控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第二极连接，第二极接入所述第二电平；
以及，第四控制晶体管，栅极接入第二扫描信号，第一极与所述第一发 光元件的第二端连接，第二极与该第一驱动晶体管的第一极连接；
所述第二驱动控制单元包括：
第五控制晶体管，栅极接入第二驱动控制信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
第六控制晶体管，栅极接入所述第二驱动控制信号，第一极接入数据电压，第二极与所述第二存储电容的第二端连接；
第七控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第二极连接，第二极接入所述第二电平；
以及，第八控制晶体管，栅极接入第二扫描信号，第一极与所述第二发光元件的第二端连接，第二极与该第二驱动晶体管的第一极连接。
可选地，在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第三控制晶体管和所述第四控制晶体管都为p型TFT，在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管、所述第七控制晶体管和所述第八控制晶体管都为p型TFT。
本公开还提供了一种像素驱动方法，用于驱动上述的像素驱动电路，包括：
在一时间周期的充电阶段，第一驱动控制单元控制第一存储电容的第一端的电位被充电至第二电平，第二驱动控制单元控制第二存储电容的第一端的电位被充电至第二电平；
在该时间周期的放电阶段，第一驱动控制单元控制第一存储电容的第一端的电位放电至第一驱动晶体管的阈值电压，并控制该第一存储电容的第二端接入数据电压；第二驱动控制单元控制第二存储电容的第一端的电位放电至第二驱动晶体管的阈值电压，并控制该第二存储电容的第二端接入数据电压；其中，在该放电阶段该数据电压为V0；
在该时间周期的第一补偿阶段，第一驱动控制单元控制第一存储电容的第二端接入所述数据电压，控制该第一存储电容的第一端浮接，从而控制第一驱动晶体管的栅源电压补偿该第一驱动晶体管的阈值电压；其中，在该第一补偿阶段该数据电压跳变为V0+ΔV1；
在该时间周期的第二补偿阶段，第二驱动控制单元控制第二存储电容的第二端接入所述数据电压，控制该第二存储电容的第一端浮接，从而控制第二驱动晶体管的栅源电压补偿该第二驱动晶体管的阈值电压；其中，在该第二补偿阶段该数据电压跳变为V0+ΔV2；
在该时间周期的发光阶段，第一驱动控制单元控制第一驱动晶体管驱动第一发光元件发光，第二驱动控制单元控制第二驱动晶体管驱动第二发光元件发光。
可选地，当所述像素驱动电路包括的驱动TFT为n型TFT时，V0、ΔV1和ΔV2大于0，ΔV2大于ΔV1。
本公开提供了一种像素驱动方法，用于驱动上述的像素驱动电路，包括：
在一时间周期的重置充电阶段，第一驱动控制单元控制第一存储电容的第一端的电位被充电至第二电平与第一驱动晶体管的阈值电压的差值，并控制该第一存储电容的第二端接入数据电压；第二驱动控制单元控制第二存储电容的第一端的电位被充电至第二电平与第二驱动晶体管的阈值电压的差值，并控制该第二存储电容的第二端接入数据电压；在重置充电阶段所述数据电压为ΔV1；
在该时间周期的第一补偿阶段，第一驱动控制单元控制第一存储电容的第一端浮接，从而控制第一驱动晶体管的栅源电压补偿该第一驱动晶体管的阈值电压；其中，在该第一补偿阶段该数据电压跳变为ΔV2；
在该时间周期的第二补偿阶段，第二驱动控制单元控制第二存储电容的第一端浮接，从而控制第二驱动晶体管的栅源电压补偿该第二驱动晶体管的阈值电压；其中，在该第二补偿阶段该数据电压跳变为ΔV3；
在该时间周期的发光阶段，第一驱动控制单元控制第一驱动晶体管驱动第一发光元件发光，第二驱动控制单元控制第二驱动晶体管驱动第二发光元件发光。
可选地，当所述像素驱动电路包括的驱动TFT为p型TFT时，ΔV1、ΔV2和ΔV3都大于0，且ΔV3大于ΔV2，V2大于ΔV1。
本公开还提供了一种显示面板，其中，包括上述的像素驱动电路。
本公开还提供了一种显示装置，包括上述的显示面板。
本公开实施例所述的像素驱动电路，将传统的相邻的两具有阈值补偿功能的单像素驱动单元组合，使得两像素驱动单元共用一条数据线，进而使用一个具有阈值补偿功能的像素驱动电路来控制驱动两个像素单元分别在相应的补偿阶段，对驱动晶体管的阈值进行跳变补偿；同时压缩用于补偿的TFT以及数据线的数目，因此，可以大幅提高像素单元的开口率，并降低成本，从而获得更高的画质和PPI(Pixels per inch，每英寸所拥有的像素数目)。
附图说明
图1是现有的基本的AMLOED像素驱动电路的电路图；
图2是本公开第二实施例所述的像素驱动电路的结构框图；
图3A是本公开第三实施例所述的像素驱动电路的电路图；
图3B是本公开第四实施例所述的像素驱动电路的电路图；
图3C是本公开第五实施例所述的像素驱动电路的电路图；
图4是本公开第三实施例所述的像素驱动电路的工作时序图；
图5A是本公开第三实施例所述的像素驱动电路在第一阶段的工作状态图；
图5B是本公开第三实施例所述的像素驱动电路在第二阶段的工作状态图；
图5C是本公开第三实施例所述的像素驱动电路在第三阶段的工作状态图；
图5D是本公开第三实施例所述的像素驱动电路在第四阶段的工作状态图；
图5E是本公开第三实施例所述的像素驱动电路在第五阶段的工作状态图；
图6是本公开第七实施例所述的像素驱动电路的结构框图；
图7是本公开第八实施例所述的像素驱动电路的电路图；
图8是本公开第八实施例所述的像素驱动电路的工作时序图；
图9A是本公开第八实施例所述的像素驱动电路在第一阶段的工作状态图；
图9B是本公开第八实施例所述的像素驱动电路在第二阶段的工作状态 图；
图9C是本公开第八实施例所述的像素驱动电路在第三阶段的工作状态图；
图9D是本公开第八实施例所述的像素驱动电路在第四阶段的工作状态图；
图10是本公开实施例所述的像素驱动电路设置于其中的像素电路的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，其中第一极可以为源极或漏极，第二极可以为漏极或源极。此外，按照晶体管的特性区分可以将晶体管分为n型晶体管或p型晶体管。在本公开实施例提供的驱动电路中，可以想到的是在采用n型晶体管或p型晶体管实现是本领域技术人员可在没有做出创造性劳动前提下轻易想到的，因此也是在本公开的实施例保护范围内的。
本公开第一实施例所述的像素驱动电路，用于驱动第一发光元件和第二发光元件，所述第一发光元件的第一端和所述第二发光元件的第一端均接入第一电平；其中，所述像素驱动电路包括第一像素驱动单元和第二像素驱动单元；
所述第一像素驱动单元包括第一驱动晶体管、第一存储电容和第一驱动控制单元，其中，
该第一存储电容，第一端与该第一驱动晶体管的栅极连接，第二端通过该第一驱动控制单元接入数据电压；
该第一驱动晶体管，栅极通过该第一驱动控制单元与该第一驱动晶体管的第一极连接，第一极通过该第一驱动控制单元接入第二电平，第二极通过 该第一驱动控制单元接入该第一电平；该第一驱动晶体管的第二极还与所述第一发光元件的第二端连接；
所述第一驱动控制单元，用于通过该第二电平、该数据电压和该第一电平对所述第一存储电容进行充放电，从而在第一补偿阶段通过对数据电压施加跳变的电压以控制对所述第一驱动晶体管的阈值电压进行跳变补偿，并控制所述第一发光元件发光；
所述第二像素驱动单元包括第二驱动晶体管、第二存储电容和第二驱动控制单元，其中，
该第二存储电容，第一端与该第二驱动晶体管的栅极连接，第二端通过该第一驱动控制单元接入数据电压；
该第二驱动晶体管，栅极通过该第二驱动控制单元与该第二驱动晶体管的第一极连接，第一极通过该第二驱动控制单元接入第二电平，第二极通过该第二驱动控制单元接入该第一电平；该第二驱动晶体管的第二极还与所述第二发光元件的第二端连接；
所述第二驱动控制单元，用于通过该第二电平、该数据电压和该第一电平对所述第二存储电容进行充放电，从而在第二补偿阶段通过对数据电压施加跳变的电压以控制对所述第二驱动晶体管的阈值电压进行跳变补偿，并控制所述第二发光元件发光。
本公开实施例所述的像素驱动电路，将传统的相邻的两具有阈值补偿功能的单像素驱动单元组合，使得第一像素驱动单元和第二像素驱动单元共用一条数据线；因此，可以使用一个具有阈值补偿功能的像素驱动电路来控制两个像素单元分别在相应的补偿阶段进行对驱动晶体管的阈值的跳变补偿；同时，压缩用于补偿的TFT以及数据线的数目，可以大幅提高像素单元的开口率并降低成本，从而获得更高的画质和PPI(Pixels per inch，每英寸所拥有的像素数目)。
可选地，所述发光元件可以是OLED。
如图2所示，本公开第二实施例所述的像素驱动电路，用于驱动第一有机发光二极管O1和第二有机发光二极管O2；
第一有机发光二极管O1的阴极和第二有机发光二极管O2的阴极均接入 第一电平V1；
所述像素驱动电路包括控制第一有机发光二极管O1的第一像素驱动单元，以及控制第二有机发光二极管O2的第二像素驱动单元；
第一像素驱动单元包括第一驱动晶体管D1、第一存储电容C1和第一驱动控制单元21；
该第一存储电容C1，第一端与该第一驱动晶体管D1的栅极连接，第二端通过该第一驱动控制单元21接入数据线Data上的数据电压；
该第一驱动晶体管D1，栅极通过该第一驱动控制单元21与该第一驱动晶体管D1的第一极连接，第一极通过该第一驱动控制单元21接入第二电平V2，第二极通过该第一驱动控制单元21接入该第一电平V1；该第一驱动晶体管D1的第二极还与所述第一有机发光二极管O1的阳极连接；
所述第一驱动控制单元21，用于通过该第二电平V2、该数据线Data上的数据电压和该第一电平V1对第一存储电容C1进行充放电，从而在第一补偿阶段控制第一驱动晶体管D1的栅源电压补偿该第一驱动晶体管D1的阈值电压之后，控制该第一驱动晶体管D1驱动第一有机发光二极管O1发光；
第二像素驱动单元包括第二驱动晶体管D2、第二存储电容C2和第二驱动控制单元22；
该第二存储电容C2，第一端与该第二驱动晶体管D2的栅极连接，第二端通过该第二驱动控制单元22接入数据线Data上的数据电压；
该第二驱动晶体管D2，栅极通过该第二驱动控制单元22与该第二驱动晶体管D2的第一极连接，第一极通过该第二驱动控制单元22接入第二电平V2，第二极通过该第二驱动控制单元22接入该第一电平V1；该第二驱动晶体管D2的第二极还与所述第二有机发光二极管O2的阳极连接；
所述第二驱动控制单元22，用于通过该第二电平V2、该数据线Data上的数据电压和该第一电平V1对第二存储电容C2进行充放电，从而在第二补偿阶段控制第二驱动晶体管D2的栅源电压补偿该第二驱动晶体管D2的阈值电压之后，控制该第二驱动晶体管D2驱动第二有机发光二极管O2发光。
在如图2所示的像素驱动电路的实施例中，D1和D2都为n型TFT，此时第一电平V1为低电平，第二电平V2为高电平。
根据一种具体实施方式，第一驱动控制单元的结构和第二驱动控制单元的结构可以相同。
具体地，所述第一驱动控制单元包括：
第一控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
第二控制晶体管，栅极接入该第一扫描信号，第一极与该第一驱动晶体管的第二极连接，第二极接入该第一电平；
第三控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一存储电容的第二端连接，第二极接入所述数据电压；
以及，第四控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第一驱动晶体管的第一极连接；
所述第二驱动控制单元包括：
第五控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
第六控制晶体管，栅极接入该第一扫描信号，第一极与该第二驱动晶体管的第二极连接，第二极接入该第一电平；
第七控制晶体管，栅极接入第二驱动控制信号，第一极与所述第二存储电容的第二端连接，第二极接入所述数据电压；
以及，第八控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第二驱动晶体管的第一极连接。
具体地，在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第三控制晶体管和所述第四控制晶体管都为n型TFT；在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管、所述第七控制晶体管和所述第八控制晶体管都为n型TFT。
根据另一种具体实施方式，所述第一驱动控制单元可以包括：
第一控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
第二控制晶体管，栅极接入该第一扫描信号，第一极与该第一驱动晶体 管的第二极连接，第二极接入该第一电平；
第三控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一存储电容的第二端连接，第二极接入所述数据电压；
以及，第四控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第一驱动晶体管的第一极连接；
所述第二驱动控制单元包括：
第五控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
第六控制晶体管，栅极接入该第一扫描信号，第一极与该第二驱动晶体管的第二极连接，第二极接入该第一电平；
第七控制晶体管，栅极接入第二扫描信号，第一极与所述第二存储电容的第二端连接，第二极接入所述数据电压；
以及，第八控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第二驱动晶体管的第一极连接。
具体地，在该第一像素驱动单元中，该第一驱动晶体管、该第一控制晶体管、该第二控制晶体管、该第三控制晶体管和该第四控制晶体管都为n型TFT；在该第二像素驱动单元中，该第二驱动晶体管、该第五控制晶体管、该第六控制晶体管和该第八控制晶体管都为n型TFT，该第七控制晶体管为p型TFT。
如图3A所示，本公开第三实施例所述的像素驱动电路，用于驱动第一有机发光二极管O1和第二有机发光二极管O2；
第一有机发光二极管O1的阴极和第二有机发光二极管O2的阴极均接地端GND；
所述像素驱动电路包括控制第一有机发光二极管O1的第一像素驱动单元，以及控制第二有机发光二极管O2的第二像素驱动单元；
第一像素驱动单元包括第一驱动晶体管D1、第一存储电容C1和第一驱动控制单元；
所述第一驱动晶体管D1的栅极与所述第一存储电容C1的第一端连接；
所述第一驱动控制单元包括：
第一控制晶体管T1，栅极接入第一扫描信号Scan1，第一极与所述第一驱动晶体管D1的第一极连接，第二极与该第一驱动晶体管D1的栅极连接；
第二控制晶体管T2，栅极接入该第一扫描信号Scan1，第一极与该第一驱动晶体管D1的第二极连接，第二极接地端GND；
第三控制晶体管T3，栅极接入第一驱动控制信号EM1，第一极与所述第一存储电容C1的第二端连接，第二极接入数据线Data上的数据电压；
以及，第四控制晶体管T4，栅极接入第二扫描信号Scan2，第一极接入高电平Vdd，第二极与该第一驱动晶体管D1的第一极连接；
所述第一驱动晶体管D1的第二极与所述第一有机发光二极管O1的阳极连接；
所述第一有机发光二极管O1的阴极接地端GND；
第二像素驱动单元包括第二驱动晶体管D2、第二存储电容C2和第二驱动控制单元；
所述第二驱动晶体管D2的栅极与所述第二存储电容C2的第一端连接；
所述第二驱动控制单元包括：
第五控制晶体管T5，栅极接入第一扫描信号Scan1，第一极与所述第二驱动晶体管D2的第一极连接，第二极与该第二驱动晶体管D2的栅极连接；
第六控制晶体管T6，栅极接入该第一扫描信号Scan1，第一极接入该第二驱动晶体管D2的第二极，第二极接地端GND；
第七控制晶体管T7，栅极接入第二驱动控制信号EM2，第一极与所述第二存储电容C2的第二端连接，第二极接入该数据线Data上的数据电压；
以及，第八控制晶体管T8，栅极接入第二扫描信号Scan2，第一极接入高电平Vdd，第二极与该第二驱动晶体管D2的第一极连接；
所述第二驱动晶体管D2的第二极与所述第二有机发光二极管O2的阳极连接；
所述第二有机发光二极管O2的阴极接地端GND；
在图3A中，与C1的第一端连接的节点标识为a1，与C2的第一端连接的节点标识为a2；
与C1的第二端连接的节点标识为b1，与C2的第二端连接的节点标识为 b2。
在如图3A所示的像素驱动电路的实施例中，D1、D2、T1、T2、T3、T4、T5、T6、T7和T8均为n型TFT，可以统一工艺流程，有助于提高产品良率。
并且，如图4所示，由于Scan2的波形图和EM2的波形图是对称翻转的，因此也可以通过改变接入Scan2和EM2的晶体管的类型的方式来减少控制信号线的数目。例如，如图3B所示，本公开第四实施例所述的像素驱动电路可以将图3A中原接入EM2的T7的晶体管类型更换为p型，并将接入T7的栅极的控制信号改为第二扫描信号Scan2；同样可以达到发明目的，同时可减少控制信号的数目。或者，如图3C所示，本公开第五实施例所述的像素驱动电路可以将图3A中接入T4的栅极和T8的栅极的控制信号由Scan2改为EM2，同时将T4的晶体管类型和T8的晶体管类型改为p型，同样可以达到发明目的，同时可减少控制信号的数目。
如图3A所示的像素驱动电路的实施例在工作时，具体工作过程如下：
在第一阶段，即充电阶段，如图4所示，Scan1和Scan2都为高电平，EM1和EM2都为低电平，数据线上的数据电压Vdata为V0；
如图5A所示，Vdd通过T4和T1向C1充电，使得a1点的电位为Vdd，T3断开；
Vdd通过T8和T5向C2充电，使得a2点的电位为Vdd，T7断开。
在第二阶段，即放电阶段，如图4所示，Scan1、EM1和EM2都为高电平，Scan2为低电平，Vdata为V0；
如图5B所示，T1、T2和T3都导通，T4断开，C1通过T1、D1和T2向地端放电，直至a1点的电位为D1的阈值电压Vth1，b1点接入Vdata，则此时b1点的电位为V0；
T5、T6和T7都导通，T8断开，C2通过T5、D2和T6向地端放电，直至a2点的电位为D2的阈值电压Vth2，b2点接入Vdata，则此时b2点的电位为V0。
在第三阶段，即第一补偿阶段，Scan1和Scan2同时为低电平，EM1和EM2都为高电平，Vdata跳变为V0+ΔV1；
如图5C所示，b1点的电位从第二阶段时的V0跳变为第三阶段的V0+ ΔV1，由于此时C1的第一端浮接，所以a1点的电位Va1和b1点的电位Vb1实现电位等量跳变(保持原来的压差，原来的压差为Vth1-V0)，因此此时a1点的电位Va1＝ΔV1+Vth1，并维持住；
b2点的电位从第二阶段时的V0跳变为第三阶段的V0+ΔV1，由于此时C2的第一端浮接，所以a2点的电位Va2和b2点的电位Vb2实现电位等量跳变(保持原来的压差，原来的压差为Vth2-V0)，因此此时a2点的电位Va2＝ΔV1+Vth2，并稳定住。
在第四阶段，即补偿阶段，如图4所示，Scan1、Scan2和EM1均为低电平，EM2为高电平，Vdata跳变为V0+ΔV2；
如图5D所示，b2点的电位从第三阶段时的V0+ΔV1变为第四阶段时的V0+ΔV2，由于C2的第一端浮接，a2点的电位Va2和b2点的电位Vb2实现电压等量跳变(保持原来的压差，原来的压差为Vth2-V0)，所以a2点的电位Va2＝ΔV2+Vth2，并稳定住。
在第五阶段，即发光阶段，如图4所示，Scan1、EM1和EM2都为低电平，Scan2为高电平；
如图5E所示，经过两次电压补偿、跳变过程后，进入OLED发光阶段，T4导通，D1的第一极通过T4接入高电平Vdd，T2断开，D1驱动第一有机发光二极管O1发光，流过O1的电流IOLED1＝K(Vgs1-Vth1)2＝K[ΔV1+Vth1-Voled1-Vth1]2＝K(ΔV1-Voled1)2；其中，Vgs1为D1的栅源电压，Voled1为O1的阳极电势，K为固定参数；
同理，流过O2的电流为K(ΔV2-Voled2)2，Voled2为O2的阳极电势。
本公开实施例所述的像素驱动电路通过依次对包括第一有机发光二极管的第一像素单元以及包括第二有机发光二极管的第二像素进行跳变阈值补偿，通过对Vdata施加跳变信号的方式，即在不同时区通过信号叠加跳变的方式，实现像素补偿，解决了双像素点驱动TFT由于工艺制程及长时间的操作造成阈值电压不均一的问题，使得流过两个像素单元包括OLED的电流不受驱动晶体管的阈值电压的影响，最终保证了图像显示的均匀性。而且在充电阶段、放电阶段、第一补偿阶段和第二补偿阶段阶段，可以保证无电流通过OLED，间接提高了OLED的使用寿命。
本公开一实施例还提供一种像素驱动方法，用于驱动本公开第一实施例、第二实施例、第三实施例、第四实施例或第五实施例所述的像素驱动电路，包括：
在一时间周期的充电阶段，第一驱动控制单元控制第一存储电容的第一端的电位被充电至第二电平，第二驱动控制单元控制第二存储电容的第一端的电位被充电至第二电平；
在该时间周期的放电阶段，第一驱动控制单元控制第一存储电容的第一端的电位放电至第一驱动晶体管的阈值电压，并控制该第一存储电容的第二端接入数据电压；第二驱动控制单元控制第二存储电容的第一端的电位放电至第二驱动晶体管的阈值电压，并控制该第二存储电容的第二端接入数据电压；其中，在该放电阶段该数据电压为V0；
在该时间周期的第一补偿阶段，第一驱动控制单元控制第一存储电容的第二端接入所述数据电压，控制该第一存储电容的第一端浮接，从而控制第一驱动晶体管的栅源电压补偿该第一驱动晶体管的阈值电压；其中，在该第一补偿阶段该数据电压跳变为V0+ΔV1；
在该时间周期的第二补偿阶段，第二驱动控制单元控制第二存储电容的第二端接入所述数据电压，控制该第二存储电容的第一端浮接，从而控制第二驱动晶体管的栅源电压补偿该第二驱动晶体管的阈值电压；其中，在该第二补偿阶段该数据电压跳变为V0+ΔV2；
在该时间周期的发光阶段，第一驱动控制单元控制第一驱动晶体管驱动第一发光元件发光，第二驱动控制单元控制第二驱动晶体管驱动第二发光元件发光。
当本公开上述实施例所述的像素驱动电路包括的驱动TFT为n型TFT时，V0大于0，ΔV1和ΔV2都大于0，ΔV2大于ΔV1。
本公开第六实施例所述的像素驱动电路，用于驱动第一发光元件和第二发光元件，所述第一发光元件的第一端和所述第二发光元件的第一端均接入第一电平；
所述像素驱动电路包括第一像素驱动单元和第二像素驱动单元；
所述第一像素驱动单元包括第一驱动晶体管、第一存储电容和第一驱动 控制单元；
该第一存储电容，第一端与该第一驱动晶体管的栅极连接，第二端通过该第一驱动控制单元接入数据电压；
该第一驱动晶体管，栅极通过该第一驱动控制单元与该第一驱动晶体管的第一极连接，第一极通过该第一驱动控制单元与所述第一发光元件的第二端连接，第二极通过该第一驱动控制单元接入第二电平；
所述第一驱动控制单元，用于通过该第二电平和该数据电压对所述第一存储电容进行重置充电，从而在第一补偿阶段通过对该数据电压施加跳变的电压以控制对所述第一驱动晶体管的阈值电压进行跳变补偿，并控制该第一驱动晶体管驱动所述第一发光元件发光；
所述第二像素驱动单元包括第二驱动晶体管、第二存储电容和第二驱动控制单元；
该第二存储电容，第一端与该第二驱动晶体管的栅极连接，第二端通过该第二驱动控制单元接入数据电压；
该第二驱动晶体管，栅极通过该第二驱动控制单元与该第二驱动晶体管的第一极连接，第一极通过该第二驱动控制单元与所述第二发光元件的第二端连接，第二极通过该第二驱动控制单元接入第二电平；
所述第二驱动控制单元，用于通过该第二电平和该数据电压对所述第二存储电容进行重置充电，从而在第二补偿阶段通过对该数据电压施加跳变的电压以控制对所述第二驱动晶体管的阈值电压进行跳变补偿，并控制该第二驱动晶体管驱动所述第二发光元件发光。
本公开该实施例所述的像素驱动电路，将传统的相邻的两具有阈值补偿功能的单像素驱动单元组合，使得第一像素驱动单元和第二像素驱动单元共用一条数据线，因此，可以使用一个具有阈值补偿功能的像素驱动电路来在控制两个像素单元在相应的补偿阶段进行阈值的跳变补偿；同时压缩用于补偿的TFT以及数据线的数目，可以大幅提高像素单元的开口率并降低成本，从而获得更高的画质和PPI。
可选地，所述发光元件可以是OLED。
如图6所示，本公开第七实施例所述的像素驱动电路，用于驱动第一有 机发光二极管O1和第二有机发光二极管O2；
第一有机发光二极管O1的阴极和第二有机发光二极管O2的阴极均接入第一电平V1；
所述像素驱动电路包括控制第一有机发光二极管O1的第一像素驱动单元，以及控制第二有机发光二极管O2的第二像素驱动单元；
第一像素驱动单元包括第一驱动晶体管D1、第一存储电容C1和第一驱动控制单元61；
该第一存储电容C1，第一端与该第一驱动晶体管D1的栅极连接，第二端通过该第一驱动控制单元61接入数据线Data上的数据电压；
该第一驱动晶体管D1，栅极通过该第一驱动控制单元61与该第一驱动晶体管D1的第一极连接，第一极通过该第一驱动控制单元61与所述第一有机发光二极管O1的阳极连接，第二极通过该第一驱动控制单元61接入第二电平V2；
第二像素驱动单元包括第二驱动晶体管D2、第二存储电容C2和第二驱动控制单元62；
该第二存储电容C2，第一端与该第二驱动晶体管D2的栅极连接，第二端通过该第二驱动控制单元62接入数据线Data上的数据电压；
该第二驱动晶体管D2，栅极通过该第二驱动控制单元62与该第二驱动晶体管D2的第一极连接，第一极通过该第二驱动控制单元62与所述第二有机发光二极管O2的阳极连接，第二极通过该第二驱动控制单元62接入第二电平V2。
在如图6所示的像素驱动电路的实施例中，D1和D2都为p型TFT，此时第一电平V1为低电平，第二电平V2为高电平。
可选地，第一驱动控制单元的结构和第二驱动控制单元的结构可以相同。
可选地，所述第一驱动控制单元包括：
第一控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
第二控制晶体管，栅极接入所述第一驱动控制信号，第一极接入数据电压，第二极与所述第一存储电容的第二端连接；
第三控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第二极连接，第二极接入所述第二电平；
以及，第四控制晶体管，栅极接入第二扫描信号，第一极与所述第一发光元件的第二端连接，第二极与该第一驱动晶体管的第一极连接；
所述第二驱动控制单元包括：
第五控制晶体管，栅极接入第二驱动控制信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
第六控制晶体管，栅极接入所述第二驱动控制信号，第一极接入数据电压，第二极与所述第二存储电容的第二端连接；
第七控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第二极连接，第二极接入所述第二电平；
以及，第八控制晶体管，栅极接入第二扫描信号，第一极与所述第二发光元件的第二端连接，第二极与该第二驱动晶体管的第一极连接。
具体地，在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第三控制晶体管和所述第四控制晶体管都为p型TFT；在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管、所述第七控制晶体管和所述第八控制晶体管都为p型TFT。
如图7所示，本公开第八实施例所述的像素驱动电路，用于驱动第一有机发光二极管O1和第二有机发光二极管O2；
第一有机发光二极管O1的阴极和第二有机发光二极管O2的阴极均接地端GND；
所述像素驱动电路包括控制第一有机发光二极管O1的第一像素驱动单元，以及控制第二有机发光二极管O2的第二像素驱动单元；
所述第一像素驱动单元包括第一驱动晶体管D1、第一存储电容C1和第一驱动控制单元；
该第一存储电容C1，第一端a1与该第一驱动晶体管D1的栅极连接；
所述第一驱动控制单元包括：
第一控制晶体管T1，第一极与所述第一驱动晶体管D1的第一极连接， 第二极与该第一驱动晶体管D1的栅极连接；
第二控制晶体管T2，第一极接入数据线Data上的数据电压，第二极与所述第一存储电容C1的第二端b1连接；
第三控制晶体管T3，栅极接入第一扫描信号Scan1，第一极与所述第一驱动晶体管D1的第二极连接，第二极接入高电平Vdd；
以及，第四控制晶体管T4，栅极接入第二扫描信号Scan2，第一极与所述第一有机发光二极管O1的阳极连接，第二极与该第一驱动晶体管D1的第一极连接；
第二像素驱动单元包括第二驱动晶体管D2、第二存储电容C2和第二驱动控制单元；
该第二存储电容C2，第一端a2与该第二驱动晶体管D2的栅极连接；
所述第二驱动控制单元包括：
第五控制晶体管T5，第一极与所述第二驱动晶体管D2的第一极连接，第二极与该第二驱动晶体管D2的栅极连接；
第六控制晶体管T6，第一极接入数据线Data上的数据电压，第二极与所述第二存储电容C2的第二端b2连接；
第七控制晶体管T7，栅极接入第一扫描信号Scan1，第一极与所述第二驱动晶体管D2的第二极连接，第二极接入所述高电平Vdd；
以及，第八控制晶体管T8，栅极接入第二扫描信号Scan2，第一极与所述第二有机发光二极管O2的阳极连接，第二极与该第二驱动晶体管D2的第一极连接；
在第一驱动控制单元中，T1的栅极和T2的栅极均接入第三扫描信号Scan3；
在第二驱动控制单元中，T5的栅极和T6的栅极均接入第四扫描信号Scan4；
T1、T2、T3、T4、T5、T6、T7、T8、D1和D2都为p型TFT。
在如图7所示的像素驱动电路的实施例中，所有TFT均为p型TFT，可以统一工艺流程，有助于提高产品良率。
从图7中可以看出，原本的两个具有阈值补偿功能的像素驱动单元被合 并为一个像素驱动电路，并且只由一根数据线Data控制，其中，T1、T2、T3、T4、T5、T6、T7和T8都为开关TFT，D1和D2为像素的驱动TFT，Scan1、Scan2、Scan3和Scan4都为扫描信号，用于控制开关TFT导通或断开。
如图7所示的像素驱动电路的工作过程如下：
如图8所示，在第一阶段，即重置充电阶段，Scan1、Scan3和Scan4均为低电平，Scan2为高电平；
如图9A所示，除T4和T8外所有的TFT均导通，Vdd通过T3、D1和T1开始对a1点进行充电，一直将a1点的电位充电至Vdd-Vth1为止(满足D1的栅源之间的压差为Vth1，Vth1为D1的阈值电压)，在该过程中，由于b1点接通数据电压Vdata，此时b1点的电位为ΔV1，所以当充电完毕后，C1两端的电位差会一致维持在Vdd-Vth1-ΔV1，另外由于T4达到关闭使得电流不会流过O1，间接降低了O1的寿命损耗；
同理，另一个像素单元的C2两端的电位差会一直维持在Vdd-Vth2-ΔV1，Vth2为D2的阈值电压；
如图8所示，在第二阶段，即第一补偿阶段，Scan1和Scan2都为高电平，Scan3和Scan4都为低电平；
如图9B所示，由于Vdata由第一阶段时的ΔV1跳变为第二阶段时的ΔV2(V2大于V1)，由于a1点浮接，因此a1点的电位Va1和b1点的电位Vb1实现电位等量跳变(保持原来的电位差，原来的电位差为Vdd-Vth1-V1)，所以此时a1点的电位Va1＝Vdd-Vth1+ΔV2-ΔV1，并稳定住；
同理，a2点的电位Va2＝Vdd-Vth2+ΔV2-ΔV1；
如图8所示，在第三阶段，即第二补偿阶段，Scan1、Scan2和Scan3都为高电平，Scan4为低电平；
如图9C所示，Vdata跳变为V3，V3大于V2，C2的第二端b2的电位Vb2由ΔV2变为ΔV3，由于a2点浮接，Va2和Vb2实现电位等量跳变(保持原来的电位差，原来的电位差为Vdd-Vth2-ΔV1)，所以a2点的电位Va2＝Vdd-Vth2+ΔV3-ΔV1，并稳定住；
如图8所示，在第四阶段，即发光阶段，Scan1和Scan2都为低电平，Scan3 和Scan4都为高电平；
如图9D所示，经过两次电压补偿、跳变过程后，OLED进入正式发光阶段，导通情况如图9D所示，工作电压接Vdd，两像素通过各自路径进行发光；
由TFT饱和电流公式可以得到：
流过O1的电流IO1＝K(VGS1-Vth1)2＝K[Vdd-(Vdd-Vth1+ΔV2-ΔV1)-Vth1]2＝K(ΔV2-ΔV1)2；其中，K为固定参数，VGS1为D1的栅源电压；
同理，流过O2的电流IO2的电流为K(ΔV3-ΔV1)2。
本公开实施例所述的像素驱动电路通过依次对包括第一有机发光二极管的第一像素单元以及包括第二有机发光二极管的第二像素进行跳变补偿，通过对Vdata施加跳变信号，即在不同时区通过信号叠加跳变的方式，实现像素补偿，解决了双像素点驱动TFT由于工艺制程及长时间的操作造成阈值电压不均一的问题，使得流过两个像素单元包括OLED的电流不受驱动晶体管的阈值电压的影响，最终保证了图像显示的均匀性，且补偿、跳变阶段保证无电流通过OLED，间接提高了OLED的使用寿命。
本公开一实施例还提供了一种像素驱动方法，用于驱动本公开第五实施例、第六实施例或第七实施例所述的像素驱动电路，包括：
在一时间周期的重置充电阶段，第一驱动控制单元控制第一存储电容的第一端的电位被充电至第二电平与第一驱动晶体管的阈值电压的差值，并控制该第一存储电容的第二端接入数据电压；第二驱动控制单元控制第二存储电容的第一端的电位被充电至第二电平与第二驱动晶体管的阈值电压的差值，并控制该第二存储电容的第二端接入数据电压；在重置充电阶段所述数据电压为ΔV1；
在该时间周期的第一补偿阶段，第一驱动控制单元控制第一存储电容的第一端浮接，从而控制第一驱动晶体管的栅源电压补偿该第一驱动晶体管的阈值电压；其中，在该第一补偿阶段该数据电压跳变为ΔV2；
在该时间周期的第二补偿阶段，第二驱动控制单元控制第二存储电容的第一端浮接，从而控制第二驱动晶体管的栅源电压补偿该第二驱动晶体管的阈值电压；其中，在该第二补偿阶段该数据电压跳变为ΔV3；
在该时间周期的发光阶段，第一驱动控制单元控制第一驱动晶体管驱动 第一发光元件发光，第二驱动控制单元控制第二驱动晶体管驱动第二发光元件发光。
当本公开实施例所述的像素驱动电路包括的驱动TFT为p型TFT时，ΔV1、ΔV2和ΔV3都大于0，且ΔV3大于ΔV2，V2大于ΔV1。
与现有技术中在每个像素单元中都设置具有阈值补偿功能的像素驱动电路不同的是，本公开一实施例所述的像素驱动电路设置于如图10所示的像素电路中的两相邻像素单元中，该两相邻像素单元共用一数据线。在图10中，例如可以将本公开实施例所述的像素驱动电路设置于相邻的红色像素单元R和绿色像素单元G中，也可以将本公开实施例所述的像素驱动电路设置于相邻的绿色像素单元G和蓝色像素单元B中。
本公开实施例所述的显示面板包括上述的像素驱动电路。
本公开实施例所述的显示装置包括上述的显示面板。
可选地，该显示装置具体可以为AMOLED显示装置。
本公开所述的像素电路、有机发光显示面板与显示装置可以采用LTPS(低温多晶硅技术)制程。
本公开所述的像素电路、有机发光显示面板与显示装置也可采用非晶硅工艺。
需指出的是，本公开实施例所提供的像素电路可采用非晶硅、多晶硅、氧化物等工艺的薄膜晶体管。本公开实施例所述的像素电路采用的晶体管的类型可以根据实际需要更换。而且，尽管上述实施例中以有源矩阵有机发光二极管为例进行了说明，然而本公开不限于使用有源矩阵有机发光二极管的显示装置，也可以应用于使用其他各种发光二极管的显示装置。
以上所述仅是本公开的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (18)

  1. 一种像素驱动电路，用于驱动第一发光元件和第二发光元件，所述第一发光元件的第一端和所述第二发光元件的第一端均接入第一电平；其中，所述像素驱动电路包括第一像素驱动单元和第二像素驱动单元；
    所述第一像素驱动单元包括第一驱动晶体管、第一存储电容和第一驱动控制单元，其中，
    该第一存储电容，第一端与该第一驱动晶体管的栅极连接，第二端通过该第一驱动控制单元接入数据电压；
    该第一驱动晶体管，栅极通过该第一驱动控制单元与该第一驱动晶体管的第一极连接，第一极通过该第一驱动控制单元接入第二电平，第二极通过该第一驱动控制单元接入该第一电平；该第一驱动晶体管的第二极还与所述第一发光元件的第二端连接；
    所述第一驱动控制单元，用于通过该第二电平、该数据电压和该第一电平对所述第一存储电容进行充放电，从而在第一补偿阶段通过对数据电压施加跳变的电压以控制对所述第一驱动晶体管的阈值电压进行跳变补偿，并控制所述第一发光元件发光；
    所述第二像素驱动单元包括第二驱动晶体管、第二存储电容和第二驱动控制单元，其中，
    该第二存储电容，第一端与该第二驱动晶体管的栅极连接，第二端通过该第一驱动控制单元接入数据电压；
    该第二驱动晶体管，栅极通过该第二驱动控制单元与该第二驱动晶体管的第一极连接，第一极通过该第二驱动控制单元接入第二电平，第二极通过该第二驱动控制单元接入该第一电平；该第二驱动晶体管的第二极还与所述第二发光元件的第二端连接；
    所述第二驱动控制单元，用于通过该第二电平、该数据电压和该第一电平对所述第二存储电容进行充放电，从而在第二补偿阶段通过对数据电压施加跳变的电压以控制对所述第二驱动晶体管的阈值电压进行跳变补偿，并控制所述第二发光元件发光。
  2. 如权利要求1所述的像素驱动电路，其中，第一驱动控制单元的结构和第二驱动控制单元的结构相同。
  3. 如权利要求2所述的像素驱动电路，其中，所述第一驱动控制单元包括：
    第一控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
    第二控制晶体管，栅极接入该第一扫描信号，第一极与该第一驱动晶体管的第二极连接，第二极接入该第一电平；
    第三控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一存储电容的第二端连接，第二极接入所述数据电压；
    以及，第四控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第一驱动晶体管的第一极连接；
    所述第二驱动控制单元包括：
    第五控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
    第六控制晶体管，栅极接入该第一扫描信号，第一极与该第二驱动晶体管的第二极连接，第二极接入该第一电平；
    第七控制晶体管，栅极接入第二驱动控制信号，第一极与所述第二存储电容的第二端连接，第二极接入所述数据电压；
    以及，第八控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第二驱动晶体管的第一极连接。
  4. 如权利要求3所述的像素驱动电路，其中，
    在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第三控制晶体管和所述第四控制晶体管都为n型TFT；
    在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管、所述第七控制晶体管和所述第八控制晶体管都为n型TFT。
  5. 如权利要求1所述的像素驱动电路，其中，
    所述第一驱动控制单元包括：
    第一控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
    第二控制晶体管，栅极接入该第一扫描信号，第一极与该第一驱动晶体管的第二极连接，第二极接入该第一电平；
    第三控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一存储电容的第二端连接，第二极接入所述数据电压；
    以及，第四控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第一驱动晶体管的第一极连接；
    所述第二驱动控制单元包括：
    第五控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
    第六控制晶体管，栅极接入该第一扫描信号，第一极与该第二驱动晶体管的第二极连接，第二极接入该第一电平；
    第七控制晶体管，栅极接入第二扫描信号，第一极与所述第二存储电容的第二端连接，第二极接入所述数据电压；
    以及，第八控制晶体管，栅极接入第二扫描信号，第一极接入该第二电平，第二极与该第二驱动晶体管的第一极连接。
  6. 如权利要求5所述的像素驱动电路，其中，
    在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第三控制晶体管和所述第四控制晶体管都为n型TFT；
    在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管和所述第八控制晶体管都为n型TFT，所述第七控制晶体管为p型TFT。
  7. 如权利要求2所述的像素驱动电路，其中，所述第一驱动控制单元包括：
    第一控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
    第二控制晶体管，栅极接入该第一扫描信号，第一极与该第一驱动晶体管的第二极连接，第二极接入该第一电平；
    第三控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一存储电容的第二端连接，第二极接入所述数据电压；
    以及，第四控制晶体管，栅极接入第二驱动控制信号，第一极接入该第二电平，第二极与该第一驱动晶体管的第一极连接；
    所述第二驱动控制单元包括：
    第五控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
    第六控制晶体管，栅极接入该第一扫描信号，第一极与该第二驱动晶体管的第二极连接，第二极接入该第一电平；
    第七控制晶体管，栅极接入所述第二驱动控制信号，第一极与所述第二存储电容的第二端连接，第二极接入所述数据电压；
    以及，第八控制晶体管，栅极接入所述第二驱动控制信号，第一极接入该第二电平，第二极与该第二驱动晶体管的第一极连接。
  8. 如权利要求7所述的像素驱动电路，其中，
    在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管和所述第三控制晶体管都为n型TFT，所述第四控制晶体管为p型TFT；
    在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管和所述第七控制晶体管都为n型TFT，所述第八控制晶体管为p型TFT。
  9. 一种像素驱动电路，用于驱动第一发光元件和第二发光元件，所述第一发光元件的第一端和所述第二发光元件的第一端均接入第一电平；其中，
    所述像素驱动电路包括第一像素驱动单元和第二像素驱动单元；
    所述第一像素驱动单元包括第一驱动晶体管、第一存储电容和第一驱动控制单元；
    该第一存储电容，第一端与该第一驱动晶体管的栅极连接，第二端通过该第一驱动控制单元接入数据电压；
    该第一驱动晶体管，栅极通过该第一驱动控制单元与该第一驱动晶体管的第一极连接，第一极通过该第一驱动控制单元与所述第一发光元件的第二端连接，第二极通过该第一驱动控制单元接入第二电平；
    所述第一驱动控制单元，用于通过该第二电平和该数据电压对所述第一存储电容进行重置充电，从而在第一补偿阶段通过对该数据电压施加跳变的电压以控制对所述第一驱动晶体管的阈值电压进行跳变补偿，并控制该第一驱动晶体管驱动所述第一发光元件发光；
    所述第二像素驱动单元包括第二驱动晶体管、第二存储电容和第二驱动控制单元；
    该第二存储电容，第一端与该第二驱动晶体管的栅极连接，第二端通过该第二驱动控制单元接入数据电压；
    该第二驱动晶体管，栅极通过该第二驱动控制单元与该第二驱动晶体管的第一极连接，第一极通过该第二驱动控制单元与所述第二发光元件的第二端连接，第二极通过该第二驱动控制单元接入第二电平；
    所述第二驱动控制单元，用于通过该第二电平和该数据电压对所述第二存储电容进行重置充电，从而在第二补偿阶段通过对该数据电压施加跳变的电压以控制对所述第二驱动晶体管的阈值电压进行跳变补偿，并控制该第二驱动晶体管驱动所述第二发光元件发光。
  10. 如权利要求9所述的像素驱动电路，其中，所述第一驱动控制单元的结构和所述第二驱动控制单元的结构相同。
  11. 如权利要求10所述的像素驱动电路，其中，所述第一驱动控制单元包括：
    第一控制晶体管，栅极接入第一驱动控制信号，第一极与所述第一驱动晶体管的第一极连接，第二极与该第一驱动晶体管的栅极连接；
    第二控制晶体管，栅极接入所述第一驱动控制信号，第一极接入数据电压，第二极与所述第一存储电容的第二端连接；
    第三控制晶体管，栅极接入第一扫描信号，第一极与所述第一驱动晶体管的第二极连接，第二极接入所述第二电平；
    以及，第四控制晶体管，栅极接入第二扫描信号，第一极与所述第一发 光元件的第二端连接，第二极与该第一驱动晶体管的第一极连接；
    所述第二驱动控制单元包括：
    第五控制晶体管，栅极接入第二驱动控制信号，第一极与所述第二驱动晶体管的第一极连接，第二极与该第二驱动晶体管的栅极连接；
    第六控制晶体管，栅极接入所述第二驱动控制信号，第一极接入数据电压，第二极与所述第二存储电容的第二端连接；
    第七控制晶体管，栅极接入第一扫描信号，第一极与所述第二驱动晶体管的第二极连接，第二极接入所述第二电平；
    以及，第八控制晶体管，栅极接入第二扫描信号，第一极与所述第二发光元件的第二端连接，第二极与该第二驱动晶体管的第一极连接。
  12. 如权利要求11所述的像素驱动电路，其中，
    在所述第一像素驱动单元中，所述第一驱动晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第三控制晶体管和所述第四控制晶体管都为p型TFT，在所述第二像素驱动单元中，所述第二驱动晶体管、所述第五控制晶体管、所述第六控制晶体管、所述第七控制晶体管和所述第八控制晶体管都为p型TFT。
  13. 一种像素驱动方法，用于驱动如权利要求1至8中任一权利要求所述的像素驱动电路，其中，所述方法包括：
    在一时间周期的充电阶段，第一驱动控制单元控制第一存储电容的第一端的电位被充电至第二电平，第二驱动控制单元控制第二存储电容的第一端的电位被充电至第二电平；
    在该时间周期的放电阶段，第一驱动控制单元控制第一存储电容的第一端的电位放电至第一驱动晶体管的阈值电压，并控制该第一存储电容的第二端接入数据电压；第二驱动控制单元控制第二存储电容的第一端的电位放电至第二驱动晶体管的阈值电压，并控制该第二存储电容的第二端接入数据电压；其中，在该放电阶段该数据电压为V0；
    在该时间周期的第一补偿阶段，第一驱动控制单元控制第一存储电容的第二端接入所述数据电压，控制该第一存储电容的第一端浮接，从而控制第一驱动晶体管的栅源电压补偿该第一驱动晶体管的阈值电压；其中，在该第 一补偿阶段该数据电压跳变为V0+△V1；
    在该时间周期的第二补偿阶段，第二驱动控制单元控制第二存储电容的第二端接入所述数据电压，控制该第二存储电容的第一端浮接，从而控制第二驱动晶体管的栅源电压补偿该第二驱动晶体管的阈值电压；其中，在该第二补偿阶段该数据电压跳变为V0+△V2；
    在该时间周期的发光阶段，第一驱动控制单元控制第一驱动晶体管驱动第一发光元件发光，第二驱动控制单元控制第二驱动晶体管驱动第二发光元件发光。
  14. 如权利要求13所述的方法，其中，当所述像素驱动电路包括的驱动TFT为n型TFT时，V0、△V1和△V2大于0，△V2大于△V1。
  15. 一种像素驱动方法，用于驱动如权利要求9至12中任一权利要求所述的像素驱动电路，其中，所述方法包括：
    在一时间周期的重置充电阶段，第一驱动控制单元控制第一存储电容的第一端的电位被充电至第二电平与第一驱动晶体管的阈值电压的差值，并控制该第一存储电容的第二端接入数据电压；第二驱动控制单元控制第二存储电容的第一端的电位被充电至第二电平与第二驱动晶体管的阈值电压的差值，并控制该第二存储电容的第二端接入数据电压；在重置充电阶段所述数据电压为△V1；
    在该时间周期的第一补偿阶段，第一驱动控制单元控制第一存储电容的第一端浮接，从而控制第一驱动晶体管的栅源电压补偿该第一驱动晶体管的阈值电压；其中，在该第一补偿阶段该数据电压跳变为△V2；
    在该时间周期的第二补偿阶段，第二驱动控制单元控制第二存储电容的第一端浮接，从而控制第二驱动晶体管的栅源电压补偿该第二驱动晶体管的阈值电压；其中，在该第二补偿阶段该数据电压跳变为△V3；
    在该时间周期的发光阶段，第一驱动控制单元控制第一驱动晶体管驱动第一发光元件发光，第二驱动控制单元控制第二驱动晶体管驱动第二发光元件发光。
  16. 如权利要求15所述的方法，其中，当所述像素驱动电路包括的驱动TFT为p型TFT时，△V1、△V2和△V3都大于0，且△V3大于△V2，V2 大于△V1。
  17. 一种显示面板，包括如权利要求1至12中任一权利要求所述的像素驱动电路。
  18. 一种显示装置，包括如权利要求17所述的显示面板。
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