WO2016045395A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2016045395A1
WO2016045395A1 PCT/CN2015/079442 CN2015079442W WO2016045395A1 WO 2016045395 A1 WO2016045395 A1 WO 2016045395A1 CN 2015079442 W CN2015079442 W CN 2015079442W WO 2016045395 A1 WO2016045395 A1 WO 2016045395A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoresist
region
area
alignment film
protective layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/079442
Other languages
English (en)
French (fr)
Inventor
董廷泽
王羽佳
莫骏
管培强
张志男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/778,763 priority Critical patent/US9869902B2/en
Priority to EP15763811.5A priority patent/EP3200021B1/en
Publication of WO2016045395A1 publication Critical patent/WO2016045395A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133784—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by rubbing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133792—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by etching
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the ground is used in the field of high performance display.
  • the TFT-LCD is composed of an array substrate and a color filter substrate.
  • a liquid crystal layer is disposed between the array substrate and the color filter substrate, and the control of the intensity of the light is controlled by controlling the deflection of the liquid crystal molecules in the liquid crystal layer, thereby finally achieving the purpose of image display.
  • the manufacturing process of the existing TFT-LCD mainly includes four stages, namely, a color film substrate preparation process, an Array (array substrate manufacturing) process, a Cell (liquid crystal cell preparation) process, and a module (module assembly) process.
  • the alignment film 10 needs to be disposed on the surface of the effective display area (AA area) of the array substrate that has been prepared.
  • the liquid crystal molecules located on the surface of the alignment film 10 can be aligned. Specifically, a transparent resin layer is formed on the surface of the AA region, and then rubbed on the surface of the transparent resin layer by using a printing roller to form a neat texture, thereby completing the preparation of the alignment film 10.
  • the liquid crystal molecules in the disordered arrangement state cannot be effectively controlled in the deflection state. Resulting in the appearance of the AA area
  • the bright pixels of the control ie, the bad white Mura
  • the array substrate is optically detected in the prior art, the detected defect is repaired.
  • the thickness of the pixel electrode layer on the array substrate is thin, the degree of recognition of the optical detection is lowered, thereby causing an increase in the poor detection rate of the white Mura. Thereby seriously reducing the quality and display effect of the product.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device to eliminate the phenomenon of white Mura generated in the Cell process.
  • An aspect of an embodiment of the present invention provides a method for fabricating an array substrate, including the following steps:
  • the surface height of the transparent protective layer is less than or equal to the surface height of the alignment film.
  • the step of forming a transparent protective layer includes:
  • first photoresist full coverage area and a first photoresist complete removal area by a mask exposure process and a development process, the first photoresist complete coverage area corresponding to the transparent protection layer to be formed; a first photoresist completely removed region corresponding to the pattern of the alignment film and the circuit bonding region;
  • the photoresist of the completely covered region of the first photoresist is peeled off to form the transparent protective layer from the remaining first resin layer.
  • the steps of forming the alignment film and the transparent protective layer include:
  • the second photoresist complete removal region corresponds to the circuit bonding region, and the photoresist partial removal region corresponds to the transparent protective layer to be formed;
  • the photoresist of the completely covered region of the second photoresist is peeled off to form the transparent protective layer from the remaining first resin layer.
  • the transparent protective layer has a thickness in a range of 2 ⁇ m to 5 ⁇ m.
  • an area of the circuit bonding region is smaller than a printing area of a printing roller for performing a rubbed imprint process.
  • an array substrate including:
  • a substrate having a display area and a non-display area, wherein the non-display area is provided with a circuit bonding area;
  • An alignment film located in a display region, the surface of the alignment film being provided with a plurality of lines having a uniform alignment direction for orderly aligning liquid crystal molecules;
  • a transparent protective layer at least in a portion other than the circuit bonding region in the non-display area
  • the surface height of the transparent protective layer is less than or equal to the surface height of the alignment film.
  • an array substrate is provided with only the alignment film on a surface of the substrate corresponding to the display region.
  • an array substrate, the transparent protective layer and the alignment film are sequentially disposed on a surface of the substrate corresponding to the display region.
  • the thickness of the transparent protective layer is in the range of 2 ⁇ m to 5 ⁇ m.
  • an area of the circuit bonding region is smaller than a printing area of a printing roller for forming the texture by performing a friction imprint process.
  • a display device comprising the array substrate according to any of the above embodiments.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device. According to the above manufacturing method, in the process of performing the rubbed imprint process on the alignment film, due to the presence of the protective layer, it is possible to prevent the printing roller from rubbing the metal wire for transmitting the control signal under the protective layer, thereby avoiding metal scrap And excessive Cloth debris generation.
  • FIG. 1 is a partial plan view showing an array substrate provided in the prior art
  • FIG. 2 is a flow chart of a method of fabricating an array substrate in accordance with an exemplary embodiment of the present invention
  • FIG. 3 is a partial plan view showing an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of forming a transparent protective layer in a method of fabricating an array substrate according to an exemplary embodiment of the present invention
  • 5a-5e are schematic diagrams showing a process of fabricating a transparent protective layer in a method of fabricating an array substrate according to an exemplary embodiment of the present invention
  • FIG. 6 is a flow chart of forming an alignment layer and a transparent protective layer in a method of fabricating an array substrate according to another exemplary embodiment of the present invention
  • FIG. 7a-7g are schematic views showing a manufacturing process of forming an alignment layer and a transparent protective layer in a method of fabricating an array substrate according to another exemplary embodiment of the present invention.
  • a method of fabricating an array substrate according to an exemplary embodiment of the present invention includes the following steps:
  • the surface height of the transparent protective layer 30 is less than or equal to the surface height of the alignment film 10.
  • the presence of the protective layer prevents the printing roller from rubbing the metal wire for transmitting the control signal under the protective layer. To avoid the generation of metal debris and excessive Cloth debris.
  • the area of the circuit bonding region is generally set to be smaller than The printing area of the printing roll that performs the rubbed imprint process, and the transparent protective layer is located above the circuit bonding area. Therefore, in the process of performing the rubbed imprint process, the printing roller contacts the transparent protective layer around the circuit bonding region without wearing the metal layer of the circuit bonding region, thereby avoiding the generation of metal debris. Therefore, in the subsequent rinsing process, the surface of the already prepared alignment film is destroyed due to the absence of the hard metal scrap, and the residual amount on the surface of the alignment film is lowered due to the reduction of the Cloth debris. Therefore, the liquid crystal molecules can be sorted on the surface of the alignment film in accordance with the preset position, solving the problem of poor white Mura generated in the Cell process.
  • the circuit binding area 21 may be used to bond an integrated circuit (IC), such as a driving IC for driving a gate line or a data line; and a flexible printed circuit board (FPC). ). Since the transparent protective layer 30 exposes the circuit bonding region 21, the binding of the control circuit is not affected in the module assembly process of the display device.
  • IC integrated circuit
  • FPC flexible printed circuit board
  • the surface height of the transparent protective layer 30 is equal to the surface height of the alignment film 10
  • the step difference between the respective film layers on the surface of the array substrate can be reduced, so that the array The surface of the substrate is flat. It avoids the accumulation of dust and impurities in the above-mentioned steps during production or transportation, and improves product quality. Further, in the process of forming the grain on the surface of the alignment film 10, it is possible to prevent the above-mentioned dust or impurities from contaminating the cloth on the printing roller.
  • the surface height may refer to a height of the film-type transparent protective layer 30 away from the one surface of the substrate 01 to the substrate 01. Therefore, the surface height of the transparent protective layer 30 is less than or equal to the surface height of the alignment film 10, specifically, the height of the transparent protective layer 30 away from the one side surface of the substrate 01 to the substrate 01 is less than or equal to the one side of the alignment film 10 away from the substrate 01. The height of the surface to the substrate 01. Thus, it can be ensured that the printing roller can sufficiently contact the surface of the alignment film 10 during the rubbing imprinting process.
  • the patterning process may be referred to as including a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention. The following is formed by a mask exposure process. The same exposure area, and then multiple etching, ashing, etc. removal processes are performed on different exposed areas to finally obtain a desired pattern as an example of a patterning process of the embodiment of the present invention.
  • the method of forming the transparent protective layer 30 may include the following steps.
  • the first resin layer 101 is applied on the surface of the substrate 01 on which the alignment film 10 is formed.
  • the metal line 20 and the circuit bonding region 21 Since the fabrication of the metal line 20 and the circuit bonding region 21 has been completed on the substrate 01 during the process of fabricating the array substrate, the metal line 20 and the circuit are schematically bound in the drawings provided by the embodiments of the present invention.
  • the area 21 is shown in the substrate 01.
  • a photoresist 40 is formed on the surface of the first resin layer 101.
  • the first photoresist completely covering region 401 corresponds to the pattern of the transparent protective layer 30 to be formed; the first photoresist completely removed region 402 corresponds to the pattern of the alignment film 10 and the circuit bonding region 21 .
  • the photoresist 40 of the first photoresist completely covered region 401 is peeled off to form the transparent protective layer 30 from the remaining first resin layer 101.
  • the transparent protective layer 30 covers a portion other than the circuit bonding region 21 in the non-display area.
  • the photoresist layer in the embodiment of the present invention in the case of using a positive photoresist, after the exposure and development through the mask, the photoresist layer in the exposed region may be in the developing process. The photoresist removed in the unexposed areas is retained during development. In the case of using a reverse photoresist, the photoresist layer in the exposed region is retained during development, and the photoresist in the unexposed region is removed during development.
  • the present invention does not limit the type of photoresist. However, in the embodiment of the present invention, the photoresist layer in the exposed region is removed during the development process, and the photoresist in the unexposed region is retained during the development process. The description of the example.
  • the surface height of the transparent protective layer 30 is less than or equal to the surface height of the alignment film 10 located in the display area AA.
  • the printing roller can be brought into full contact with the alignment film 10, and a texture pattern having a uniform alignment direction is formed on the surface thereof.
  • the transparent protective layer 30 covers the metal wire 20, it is possible to prevent the printing roller from rubbing the metal wire 20 under the protective layer, thereby avoiding generation of metal debris and excessive Cloth debris.
  • the surface of the circuit bonding region 21 does not cover the transparent protective layer 30, in the fabrication process of the array substrate, the area of the circuit bonding region 21 is generally smaller than the printing area of the printing roller (ie, between the printing roller and the printing object).
  • the contact area is) and the transparent protective layer 30 is located above the circuit bonding region 21. Therefore, the printing roller contacts the transparent protective layer 30 around the circuit bonding region 21 without being worn to the metal layer of the circuit bonding region, thereby avoiding the generation of metal debris. In this way, during the subsequent rinsing process, the surface of the prepared alignment film is destroyed due to the absence of hard metal scrap, and the amount of residual film on the surface of the alignment film is reduced due to the reduction of Cloth debris. . Therefore, the liquid crystal molecules can be sorted on the surface of the alignment film in accordance with the preset position, solving the problem of poor white Mura generated in the Cell process.
  • the thickness of the transparent protective layer 30 may be in the range of 2 ⁇ m to 5 ⁇ m. When the thickness of the transparent protective layer 30 is less than 2 ⁇ m, film formation on the substrate may be easily performed because the thickness is too thin. When the thickness of the transparent protective layer 30 is more than 5 ⁇ m, the thickness of the transparent protective layer 30 may be larger than the thickness of the alignment film 10, so that the printing roller cannot be in contact with the surface of the alignment film 10 during the rubbed imprint process, and cannot be formed therein. The texture of the surface.
  • the method of forming the alignment film 10 and the transparent protective layer 30 before the above step S103 includes the following steps.
  • the first resin layer 101 is coated on the surface of the substrate 01 on which the display area AA and the non-display area (not shown in FIG. 3) are formed.
  • a second resin layer 201 is coated on the first resin layer 101.
  • a photoresist 40 is formed on the surface of the second resin layer 201.
  • the second photoresist complete coverage area 411 corresponds to the 10 alignment film to be formed
  • the second photoresist complete removal area 412 corresponds to the circuit bonding area 21
  • the photoresist partial removal area 413 corresponds to the transparent protection layer to be formed.
  • the photoresist 40 of the photoresist partial removal region 413 is ashed, and the second resin layer 201 corresponding to the photoresist partial removal region 413 is etched to be retained by The second resin layer forms the alignment layer 10. During this process, the thickness of the photoresist of the second photoresist completely covering the region 411 is thinned.
  • the photoresist 40 of the second photoresist completely covered region 411 is peeled off to form the transparent protective layer 30 from the remaining first resin layer.
  • the alignment layer 10 is located on the surface of the transparent protective layer 30, so that the surface of the alignment layer 10 can be printed, and the transparent protective layer 30 can cover the metal line 20, thereby preventing The printing roller rubs the metal wire 20 under the protective layer, thereby avoiding the generation of metal debris and excessive Cloth debris.
  • the surface of the circuit bonding region 21 does not cover the transparent protective layer 30, in the fabrication process of the array substrate, the area of the circuit bonding region 21 is generally smaller than the printing area of the printing roller (ie, between the printing roller and the printing object). The contact area is) and the transparent protective layer 30 is located above the circuit bonding region 21.
  • the printing roller contacts the transparent protective layer 30 around the circuit bonding region 21 without being worn to the metal layer of the circuit bonding region, thereby avoiding the generation of metal debris.
  • the surface of the prepared alignment film is destroyed due to the absence of hard metal scrap, and the amount of residual film on the surface of the alignment film is reduced due to the reduction of Cloth debris. . Therefore, the liquid crystal molecules can be sorted on the surface of the alignment film in accordance with the preset position, solving the problem of poor white Mura generated in the Cell process.
  • the alignment layer 10 since the alignment layer 10 is located on the transparent protective layer 30 The surface, therefore, does not require an etching process on the surface of the second resin layer forming the alignment layer 10, thereby avoiding damage to the surface of the alignment layer 10 due to etching precision.
  • the transparent protective layer 30 is provided between the alignment layer 10 and the substrate 01, for a TN (Twist Nematic) type display device including a common electrode formed on the substrate, The distance between the above-mentioned common electrode and the pixel electrode on the color filter substrate is increased, so that an electric field applied to both ends of the liquid crystal layer is affected.
  • an array substrate including: a substrate 01 on which a display area AA and a non-display area (except for the display area AA) are provided.
  • the alignment film 10 is disposed in the display area AA, wherein the surface of the alignment film 10 is provided with a plurality of grain patterns having a uniform alignment direction for orderly aligning the liquid crystal molecules;
  • a transparent protective layer 30 located in a portion other than the circuit bonding region 21 in the non-display area.
  • the surface height of the transparent protective layer 30 is less than or equal to the surface height of the alignment film 10.
  • the printing roller in the process of performing the rubbed imprint process on the alignment film, due to the presence of the protective layer, the printing roller can be prevented from rubbing the metal wire for transmitting the control signal under the protective layer, thereby Metal debris and excessive Cloth debris are avoided.
  • the area of the circuit bonding region 21 is smaller than the printing area of the printing roller (not shown) for forming the texture by performing a friction imprint process, that is, the contact between the printing roller and the printing object. area.
  • the area of the circuit bonding region is generally smaller than the printing area of the printing roller, and the transparent protective layer is located above the circuit bonding region. . Therefore, the printing roller will contact the transparent protective layer around the circuit bonding area without wearing the metal layer of the circuit bonding area, thereby avoiding the generation of metal debris.
  • the liquid crystal molecules can be sorted on the surface of the alignment film in accordance with the preset position, solving the problem of poor white Mura generated in the Cell process.
  • the structure of the transparent protective layer 30 or the alignment film 10 will be described in detail below.
  • the alignment film 10 is provided on the surface of the corresponding display area AA of the substrate.
  • the surface height of the transparent protective layer 30 is less than or equal to the surface height of the alignment film 10 located in the display area AA.
  • the printing roller can be brought into contact with the alignment film 10 before the step S104 is performed, and a texture pattern having a uniform alignment direction is formed on the surface of the alignment film 10. Since the transparent protective layer 30 can cover the metal wire 20, it is possible to prevent the printing roller from rubbing the metal wire 20 under the protective layer, thereby avoiding the generation of metal scrap.
  • the surface of the circuit bonding region 21 does not cover the transparent protective layer 30, in the manufacturing process of the array substrate, the area of the circuit bonding region 21 is generally smaller than the printing area of the printing roller, and the transparent protective layer 30 is located in the circuit. Above the fixed area 21. Therefore, the printing roller will come into contact with the transparent protective layer 30 around the circuit bonding region 21 without being worn to the metal layer of the circuit bonding region, thereby avoiding the generation of metal debris and excessive Cloth debris.
  • the thickness of the transparent protective layer 30 may be in the range of 2 ⁇ m to 5 ⁇ m. When the thickness of the transparent protective layer 30 is less than 2 ⁇ m, film formation on the substrate may be easily performed because the thickness is too thin. When the thickness of the transparent protective layer 30 is more than 5 ⁇ m, the thickness of the transparent protective layer 30 may be larger than the thickness of the alignment film 10, so that the printing roller cannot be in contact with the surface of the alignment film 10 during the rubbed imprint process, and cannot be formed therein. The texture of the surface.
  • a transparent protective layer 30 and an alignment film 10 are sequentially disposed on the surface of the corresponding display region AA of the substrate. Since the alignment layer 10 is located on the surface of the transparent protective layer 30. In this way, the surface of the alignment layer 10 can be printed, and the transparent protective layer 30 can cover the metal line 20. Therefore, the printing roller can prevent the metal wire 20 under the protective layer from rubbing, thereby avoiding metal debris. And excessive Cloth debris generation.
  • the surface of the circuit bonding region 21 does not cover the transparent protective layer 30, in the manufacturing process of the array substrate, the area of the circuit bonding region 21 is generally smaller than the printing area of the printing roller, and the transparent protective layer 30 is located in the circuit. Above the fixed area 21. Therefore, the printing roller contacts the transparent protective layer 30 around the circuit bonding region 21 without being worn to the metal layer of the circuit bonding region, thereby avoiding the generation of metal debris.
  • the alignment layer 10 there is no other hierarchical structure between the alignment layer 10 and the array substrate, which does not affect the electric field applied to both ends of the liquid crystal layer during display.
  • the first resin layer 101 covering the surface of the alignment layer 10 is required. The etching is performed, so the etching precision is required to be high to avoid damage to the surface of the alignment layer 10 during the etching.
  • the alignment layer 10 since the alignment layer 10 is located on the surface of the transparent protective layer 30, it is not necessary to perform an etching process on the surface of the second resin layer forming the alignment layer 10, thereby avoiding alignment due to etching precision.
  • the surface of layer 10 causes damage.
  • the transparent protective layer 30 since the transparent protective layer 30 is provided between the alignment layer 10 and the substrate, the TN (Twist Nematic) type display device including the common electrode formed on the substrate is increased. The distance between the common electrode and the pixel electrode on the color filter substrate affects the electric field applied to both ends of the liquid crystal layer.
  • a display device comprising any of the array substrates as described above, having the same advantageous effects as the array substrate of the foregoing embodiment, due to the structure and beneficial effects of the array substrate A detailed description has been made in the embodiments, and details are not described herein again.
  • the display device may specifically include at least a liquid crystal display device and an organic light emitting diode display device.
  • the display device may be any display product such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer. component.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板及其制作方法、显示装置，以消除在Cell工艺中产生的白Mura不良的问题。该制作方法包括如下步骤：在基板（01）上形成显示区域（AA）和非显示区域；所述非显示区域中设有电路绑定区（21）；通过构图工艺，在所述显示区域（AA）形成取向膜（10）；通过构图工艺，至少在非显示区域中除电路绑定区域（21）以外的部分，形成透明保护层（30）；以及通过摩擦压印工艺，在取向膜（10）的表面形成多条具有一致排列方向的纹路，用于对液晶层中的液晶分子进行有序排列；其中，上述透明保护层（30）的表面高度小于等于取向膜（10）的表面高度。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
TFT-LCD由阵列基板和彩膜基板构成。在阵列基板和彩膜基板之间设置有液晶层，通过控制液晶层中液晶分子的偏转，实现对光线强弱的控制，最终达到图像显示的目的。现有TFT-LCD的制造工艺主要包括四个阶段，分别为彩膜基板制备工艺、Array(阵列基板制造)工艺、Cell(液晶盒制备)工艺以及Module(模块组装)工艺。为了有效的对液晶分子的偏转进行控制，在Cell工艺中，如图1所示，需要在已经制备好的阵列基板的有效显示区域(Active Area，简称AA区域)的表面设置取向膜10，以使得位于所述取向膜10表面的液晶分子能够排列一致。具体的，在所述AA区域的表面形成一透明树脂层，然后采用印刷辊(Rubbing Cloth)在所述透明树脂层的表面进行摩擦，以制作出整齐的纹路，从而完成取向膜10的制备。
然而，在上述制备取向膜的过程中，当印刷辊在所述取向膜材料层的表面进行摩擦时，同时会对AA区域以外的区域(非显示区域)进行摩擦。由于非显示区域内设置有用于传输控制信号的金属线20或用于电路绑定区域21的金属层。当印刷辊与金属线20或金属层摩擦时，会产生金属碎屑以及过多的印刷辊上的印刷布料(Cloth)碎屑。在清洗过程中，由于所述金属碎屑的质地较硬，在水流的冲击作用下会对已经制备好的取向膜10的表面进行破坏，并且上述Cloth碎屑会残留于取向膜的表面。从而导致部分液晶分子无法按照预设位置进行排序。这样一来，在显示过程中，上述处于无序排列状态的液晶分子，其偏转状态将无法被有效控制。从而导致AA区域出现不受 控的亮像素点(即白Mura不良)，对画面品质造成不良的影响。虽然现有技术中会对阵列基板进行光学检测，以对检测出的不良进行修复。然而由于所述阵列基板上的像素电极层的厚度较薄，降低了光学检测的识别度，因此导致白Mura不良漏检率升高。从而严重降低了产品的质量和显示效果。
发明内容
本发明的实施例提供一种阵列基板及其制作方法、显示装置，以消除在Cell工艺中产生的白Mura不良的现象。
本发明实施例的一方面，提供一种阵列基板的制作方法，包括如下步骤：
在基板上形成显示区域和非显示区域，所述非显示区域中设有电路绑定区域；
通过构图工艺，在所述显示区域形成取向膜；
通过构图工艺，至少在所述非显示区域中除电路绑定区域以外的部分，形成透明保护层；以及
通过摩擦压印工艺，在所述取向膜的表面形成多条具有一致排列方向的纹路，用于对液晶分子进行有序排列，
其中，所述透明保护层的表面高度小于等于所述取向膜的表面高度。
根据本发明一种实施例的阵列基板的制作方法，形成透明保护层的步骤包括：
在形成有所述取向膜的基板表面涂覆第一树脂层；
在所述第一树脂层的表面形成光刻胶；
通过一次掩膜曝光工艺和显影工艺，形成第一光刻胶完全覆盖区域和第一光刻胶完全去除区域，所述第一光刻胶完全覆盖区域对应待形成的所述透明保护层；所述第一光刻胶完全去除区域对应所述取向膜的图案以及所述电路绑定区域；
刻蚀对应所述第一光刻胶去除区域的所述第一树脂层；以及
对所述第一光刻胶完全覆盖区域的光刻胶进行剥离，以由保留下的第一树脂层形成所述透明保护层。
根据本发明一种实施例的阵列基板的制作方法，形成所述取向膜和所述透明保护层的步骤包括：
在形成有所述显示区域和所述非显示区域的基板的表面涂覆第一树脂层；
在所述第一树脂层上涂覆第二树脂层；
在所述第二树脂层的表面形成光刻胶；
通过一次掩膜曝光工艺和显影工艺，形成第二光刻胶完全覆盖区域、第二光刻胶完全去除区域以及光刻胶部分去除区域；所述第二光刻胶完全覆盖区域对应待形成的所述取向膜；所述第二光刻胶完全去除区域对应所述电路绑定区域，所述光刻胶部分去除区域对应待形成的所述透明保护层；
刻蚀对应所述第二光刻胶完全去除区域的所述第二树脂层和所述第一树脂层；
将所述光刻胶部分去除区域的光刻胶进行灰化，并刻蚀对应所述光刻胶部分去除区域的所述第二树脂层；以及
对所述第二光刻胶完全覆盖区域的光刻胶进行剥离，以由保留下的第一树脂层形成所述透明保护层。
根据本发明一种实施例的阵列基板的制作方法，所述透明保护层的厚度在2μm～5μm的范围内。
根据本发明一种实施例的阵列基板的制作方法，所述电路绑定区域的面积小于用于执行摩擦压印工艺的印刷辊的印刷面积。
根据本发明另一方面的实施例，提供一种阵列基板，包括：
基板，所述基板上设有显示区域和非显示区域，所述非显示区域中设有电路绑定区域；
位于显示区域的取向膜，所述取向膜的表面设置有多条具有一致排列方向的纹路，用于对液晶分子进行有序排列；以及
至少位于非显示区域中除电路绑定区域以外部分的透明保护层；
其中，所述透明保护层的表面高度小于等于所述取向膜的表面高度。
根据本发明一种实施例的阵列基板，所述基板的对应所述显示区域的表面上仅设置有所述取向膜。
根据本发明一种实施例的阵列基板，所述基板的对应所述显示区域的表面上依次设置有所述透明保护层以及所述取向膜。
根据本发明一种实施例的阵列基板，所述透明保护层的厚度在2μm～5μm的范围内。
根据本发明一种实施例的阵列基板，所述电路绑定区域的面积小于用于通过执行摩擦压印工艺而形成所述纹路的印刷辊的印刷面积。
根据本发明进一步方面的实施例，提供一种显示装置，包括如权利要求上述实施例中的任一项所述的阵列基板。
本发明的实施例提供了一种阵列基板及其制作方法、显示装置。根据上述制作方法，在对取向膜进行摩擦压印工艺的过程中，由于保护层的存在，能够防止印刷辊对保护层下方的用于传输控制信号的金属线进行摩擦，从而避免了金属碎屑和过多Cloth碎屑的产生。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中提供的一种阵列基板的局部平面示意图；
图2为根据本发明的一种示例性实施例的阵列基板的制作方法的流程图；
图3为根据本发明的一种实施例的阵列基板的局部平面示意图；
图4为根据本发明的一种示例性实施例在阵列基板的制作方法中形成透明保护层的流程图；
图5a-图5e为根据本发明的一种示例性实施例在阵列基板的制作方法中形成透明保护层的制作过程示意图；
图6为根据本发明的另一种示例性实施例在阵列基板的制作方法中形成取向层和透明保护层的流程图；以及
图7a-图7g为根据本发明的另一种示例性实施例在阵列基板的制作方法中形成取向层和透明保护层的制作过程示意图。
附图说明：
01-基板；10-取向膜；20-金属线；21-电路绑定区域；30-透明保护层；40-光刻胶；101-第一树脂层；201-第二树脂层；401-第一光刻 胶完全覆盖区域；402-第一光刻胶完全去除区域；411-第二光刻胶完全覆盖区域；412-第二光刻胶完全去除区域；413-光刻胶部分去除区域；AA-显示区域。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
参照图1-3，根据本发明的一种示例性实施例的阵列基板的制作方法包括如下步骤：
S101、，在基板01上形成显示区域AA和非显示区域(除了显示区域AA以外的区域，图中未用附图标记示出)，如图1所示；
S102、通过构图工艺，如图3所示，在显示区域AA形成取向膜；
S103、通过构图工艺，至少在非显示区域中除电路绑定区域21以外的部分，形成透明保护层30；以及
S104、通过摩擦压印工艺，在所述取向膜10的表面形成多条具有一致排列方向的纹路，用于对液晶层中的液晶分子进行有序排列，
其中，透明保护层30的表面高度小于等于取向膜10的表面高度。
根据本发明实施例的阵列基板的制作方法，在对取向膜进行摩擦压印工艺的过程中，由于保护层的存在，能够防止印刷辊对保护层下方的用于传输控制信号的金属线进行摩擦，从而避免了金属碎屑和过多Cloth碎屑的产生。
此外，虽然电路绑定区域的表面没有覆盖透明保护层，但是在阵列基板的制作过程中，上述电路绑定区域的面积设置成一般小于用于 执行摩擦压印工艺的印刷辊的印刷面积，且透明保护层位于电路绑定区域的上方。因此，在执行摩擦压印工艺的过程中，印刷辊会与电路绑定区域周边的透明保护层相接触而不会磨损到电路绑定区域的金属层，避免了金属碎屑的产生。因此在后续的冲洗过程中，由于没有质地较硬的金属碎屑对已经制备好的取向膜的表面进行破坏，并且由于Cloth碎屑的减少，降低了其在取向膜表面的残留数量。因此可以使得液晶分子能够按照预设位置在取向膜的表面进行排序，解决在Cell工艺中，产生的白Mura不良的问题。
需要说明的是，上述电路绑定区域21可以用于绑定驱动IC(integrated circuit，集成电路)，例如用于驱动栅线或数据线的驱动IC；以及柔性电路板(Flexible Printed Circuit board，FPC)。由于上述透明保护层30将电路绑定区域21露出，因此在显示装置的Module(模块组装)工艺中，不会对控制电路的绑定造成影响。
当透明保护层30的表面高度等于取向膜10的表面高度时，不仅能够解决在Cell工艺中，产生的白Mura不良的问题，而且能够降低阵列基板表面的各个薄膜层之间的段差，使得阵列基板的表面平整。避免了在生产或运输过程中灰尘、杂质在上述段差处的堆积，提升了产品质量。并且在取向膜10的表面制作纹路的过程中，能够避免上述灰尘或杂质污染印刷辊上的布料。
需要说明的是，参照图5a和5e，上述表面高度可以是指薄膜式的透明保护层30的远离基板01的一个侧表面到所述基板01的高度。因此透明保护层30的表面高度小于等于取向膜10的表面高度，具体是指，透明保护层30远离基板01的一个侧表面到基板01的高度小于等于取向膜10远离基板01的所述一个侧表面到基板01的高度。这样，能够保证在摩擦压印过程中，印刷辊能够与取向膜10的表面充分接触。
在本发明的实施例中，构图工艺可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。下面以通过一次掩膜曝光工艺形成不 同的曝光区域，然后对不同的曝光区域进行多次刻蚀、灰化等去除工艺最终得到预期图案为例说明本发明实施例的一次构图工艺。
以下对在上述步骤S104之前形成透明保护层30或/和取向膜10的过程进行详细的描述。
在如图4和5a-5e所示的一种示例性实施例中，在上述步骤S104之前，形成透明保护层30的方法可以包括如下步骤。
S201、如图5a所示(通过沿图3中的O-O’进行剖切得到)，在形成有取向膜10的基板01的表面，涂覆第一树脂层101。
由于在制作阵列基板的过程中，已经在基板01上完成了金属线20以及电路绑定区域21的制作，因此本发明的实施例提供的附图中示意性地将金属线20以及电路绑定区域21示出在基板01中。
S202、如图5b所示，在第一树脂层101的表面形成光刻胶40。
S203、通过一次掩膜曝光工艺和显影工艺，如图5c所示，形成第一光刻胶完全覆盖区域401和第一光刻胶完全去除区域402。其中，第一光刻胶完全覆盖区域401对应待形成的透明保护层30的图案；第一光刻胶完全去除区域402对应取向膜10的图案以及电路绑定区域21。
S204、如图5d所示，刻蚀对应第一光刻胶完全去除区域402的第一树脂层101。
S205、如图5e所示，对第一光刻胶完全覆盖区域401的光刻胶40进行剥离，以由保留下的第一树脂层101形成透明保护层30。该透明保护层30覆盖非显示区域中除了电路绑定区域21以外的部分。
需要说明的是，对于本发明实施例中的光刻胶层，在使用正性光刻胶的情况下，在经过掩膜版的曝光显影后，可以是曝光区域的光刻胶层在显影过程中被去除，未曝光区域的光刻胶在显影过程中被保留。在使用反性光刻胶的情况下，在曝光区域的光刻胶层在显影过程中被保留，而未曝光区域的光刻胶在显影过程中被去除。本发明对光刻胶的类型不作限制。但是本发明中的实施例，均是以曝光区域的光刻胶层在显影过程中被去除，未曝光区域的光刻胶在显影过程中被保留为 例进行的说明。
从图5e中可以看出，由于透明保护层30的表面高度小于等于位于显示区域AA的取向膜10的表面高度。这样，在进行步骤S 104之前，印刷辊可以与取向膜10充分接触，并在其表面形成具有一致排列方向的纹路图案。由于透明保护层30将金属线20进行覆盖，因此能够防止印刷辊对保护层下方的金属线20进行摩擦，从而避免了金属碎屑和过多Cloth碎屑的产生。此外，虽然电路绑定区域21的表面没有覆盖透明保护层30，但是在阵列基板的制作过程中，上述电路绑定区域21的面积一般小于印刷辊的印刷面积(即印刷辊与印刷对象之间的接触面积)，且透明保护层30位于电路绑定区域21的上方。因此，印刷辊会与电路绑定区域21周边的透明保护层30相接触而不会磨损到电路绑定区域的金属层，避免了金属碎屑的产生。这样一来，在后续的冲洗过程中，由于没有质地较硬的金属碎屑对已经制备好的取向膜的表面进行破坏，并且由于Cloth碎屑的减少，降低了其在取向膜表面的残留数量。因此可以使得液晶分子能够按照预设位置在取向膜的表面进行排序，解决在Cell工艺中，产生的白Mura不良的问题。
在一种实施例中，上述透明保护层30的厚度可以在2μm～5μm的范围内。当透明保护层30的厚度小于2μm时，会因为厚度太薄而不容易在基板上成膜。当透明保护层30的厚度大于5μm时，会因为其厚度可能大于取向膜10的厚度，而导致在摩擦压印工艺的过程中，印刷辊无法与取向膜10的表面接触，而无法形成位于其表面的纹路。
在如图6和7a-5g所示的另一种示例性实施例中，在上述步骤S103之前，形成取向膜10和透明保护层30的方法包括如下步骤。
S301、如图7a所示，在形成有显示区域AA和非显示区域(图3中未用附图标记示出)的基板01的表面，涂覆第一树脂层101。
S302、如图7b所示，在第一树脂层101上涂覆第二树脂层201。
S303、如图7c所示，在第二树脂层201的表面形成光刻胶40。
S304、通过一次掩膜曝光工艺和显影工艺，如图7d所示，形成第二光刻胶完全覆盖区域411、第二光刻胶完全去除区域412以及光 刻胶部分去除区域413。其中，所第二光刻胶完全覆盖区域411对应待形成的10取向膜，第二光刻胶完全去除区域412对应电路绑定区域21，光刻胶部分去除区域413对应待形成的透明保护层30。
S305、如图7e所示，刻蚀对应第二光刻胶完全去除区域412的第二树脂层201和第一树脂层101，使得电路绑定区域21露出。
S306、如图7f所示，将光刻胶部分去除区域413的光刻胶40进行灰化，并刻蚀对应光刻胶部分去除区域413的所述第二树脂层201，以由保留下的第二树脂层形成取向层10。在此过程中，第二光刻胶完全覆盖区域411的光刻胶的厚度减薄。
S307、如图7g所示，对第二光刻胶完全覆盖区域411的光刻胶40进行剥离，以由保留下的第一树脂层形成透明保护层30。
从图7g中可以看出，取向层10位于透明保护层30的表面，这样，既可以实现对取向层10表面进行纹路印刷，又由于透明保护层30可以将金属线20进行覆盖，因此能够防止印刷辊对保护层下方的金属线20进行摩擦，从而避免了金属碎屑和过多Cloth碎屑的产生。此外，虽然电路绑定区域21的表面没有覆盖透明保护层30，但是在阵列基板的制作过程中，上述电路绑定区域21的面积一般小于印刷辊的印刷面积(即印刷辊与印刷对象之间的接触面积)，且透明保护层30位于电路绑定区域21的上方。因此，印刷辊会与电路绑定区域21周边的透明保护层30相接触而不会磨损到电路绑定区域的金属层，避免了金属碎屑的产生。这样一来，在后续的冲洗过程中，由于没有质地较硬的金属碎屑对已经制备好的取向膜的表面进行破坏，并且由于Cloth碎屑的减少，降低了其在取向膜表面的残留数量。因此可以使得液晶分子能够按照预设位置在取向膜的表面进行排序，解决在Cell工艺中，产生的白Mura不良的问题。
在图5e所示的实施例中，取向层10与基板1之间无其他层级结构，这样不会对显示过程中施加于液晶层两端的电场产生影响。但是在制作过程中，由于需要对覆盖于取向层10表面的第一树脂层101进行刻蚀，因此对刻蚀精度要求较高，以避免在刻蚀过程中对取向层10的表面造成损伤。
在图7g所示的实施例中，由于取向层10位于透明保护层30的 表面，因此无需对形成取向层10的第二树脂层的表面进行刻蚀工艺，避免了由于刻蚀精度而对取向层10的表面造成损伤。但是，在该实施例中，由于在取向层10与基板01之间设置了透明保护层30，对于包括形成在基板上的公共电极的TN(Twist Nematic，扭曲向列)型显示装置而言，增加了上述公共电极与位于彩膜基板上的像素电极之间的距离，所以会对施加于液晶层两端的电场产生影响。
可以理解，本领域技术人员可以根据实际需要对上述两种方式进行选择。
根据本发明另一方面的实施例，如图1所示，提供一种阵列基板，包括：基板01，在基板01上设有显示区域AA和非显示区域(除了显示区域AA以外的区域，图中未用附图标记示出)；位于显示区域AA的取向膜10，其中，取向膜10的表面设置有多条具有一致排列方向的纹路图案，用于对液晶分子进行有序排列；以及至少位于非显示区域中除电路绑定区域21以外部分的透明保护层30。其中，透明保护层30的表面高度小于等于取向膜10的表面高度。
根据本发明实施例的阵列基板，，在对取向膜进行摩擦压印工艺的过程中，由于保护层的存在，能够防止印刷辊对保护层下方的用于传输控制信号的金属线进行摩擦，从而避免了金属碎屑和过多Cloth碎屑的产生。
在一种实施例中，电路绑定区域21的面积小于用于通过执行摩擦压印工艺而形成所述纹路的印刷辊(未示出)的印刷面积，即印刷辊与印刷对象之间的接触面积。这样，虽然电路绑定区域的表面没有覆盖透明保护层，但是在阵列基板的制作过程中，上述电路绑定区域的面积一般小于印刷辊的印刷面积，且透明保护层位于电路绑定区域的上方。因此印刷辊会与电路绑定区域周边的透明保护层相接触而不会磨损到电路绑定区域的金属层，避免了金属碎屑的产生。因此在后续的冲洗过程中，由于没有质地较硬的金属碎屑对已经制备好的取向膜的表面进行破坏，并且由于Cloth碎屑的减少，降低了其在取向膜表面的残留数量。因此可以使得液晶分子能够按照预设位置在取向膜的表面进行排序，解决在Cell工艺中，产生的白Mura不良的问题。
以下对透明保护层30或取向膜10的结构进行详细的描述。
如图5e所示，在阵列基板中，基板的对应显示区域AA的表面上仅设置有取向膜10。由于透明保护层30的表面高度小于等于位于显示区域AA的取向膜10的表面高度。这样，在将进行步骤S104之前时，印刷辊可以与取向膜10接触，并在取向膜10的表面形成具有一致排列方向的纹路图案。由于透明保护层30可以将金属线20进行覆盖，因此能够防止印刷辊对保护层下方的金属线20进行摩擦，从而避免了金属碎屑的产生。此外，虽然电路绑定区域21的表面没有覆盖透明保护层30，但是在阵列基板的制作过程中，上述电路绑定区域21的面积一般小于印刷辊的印刷面积，且透明保护层30位于电路绑定区域21的上方。因此印刷辊会与电路绑定区域21周边的透明保护层30相接触而不会磨损到电路绑定区域的金属层，避免了金属碎屑和过多Cloth碎屑的产生。
在一种实施例中，上述透明保护层30的厚度可以在2μm～5μm的范围内。当透明保护层30的厚度小于2μm时，会因为厚度太薄而不容易在基板上成膜。当透明保护层30的厚度大于5μm时，会因为其厚度可能大于取向膜10的厚度，而导致在摩擦压印工艺的过程中，印刷辊无法与取向膜10的表面接触，而无法形成位于其表面的纹路。
如图7g所示，在阵列基板中，基板的对应显示区域AA的表面上依次设置有透明保护层30以及取向膜10。由于取向层10位于透明保护层30的表面。这样，既可以实现对取向层10表面进行纹路印刷，又由于透明保护层30可以将金属线20进行覆盖，因此能够防止印刷辊对保护层下方的金属线20进行摩擦，从而避免了金属碎屑和过多Cloth碎屑的产生。此外，虽然电路绑定区域21的表面没有覆盖透明保护层30，但是在阵列基板的制作过程中，上述电路绑定区域21的面积一般小于印刷辊的印刷面积，且透明保护层30位于电路绑定区域21的上方。因此印刷辊会与电路绑定区域21周边的透明保护层30相接触而不会磨损到电路绑定区域的金属层，避免了金属碎屑的产生。
在图5e所示的实施例中，取向层10与阵列基板之间无其他层级结构，这样不会对显示过程中施加于液晶层两端的电场产生影响。但是在制作过程中，由于需要对覆盖于取向层10表面的第一树脂层101 进行刻蚀，因此对刻蚀精度要求较高，以避免在刻蚀过程中对取向层10的表面造成损伤。
在图7g所示的实施例中，由于取向层10位于透明保护层30的表面，因此无需对形成取向层10的第二树脂层的表面进行刻蚀工艺，避免了由于刻蚀精度而对取向层10的表面造成损伤。但是，在该实施例中，由于在取向层10与基板之间设置了透明保护层30，对于包括形成在基板上的公共电极的TN(Twist Nematic，扭曲向列)型显示装置而言，增加了上述公共电极与位于彩膜基板上的像素电极之间的距离，所以会对施加于液晶层两端的电场产生影响。
可以理解，本领域技术人员可以根据实际需要对上述两种方式进行选择。
根据本发明再进一步方面的实施例，提供一种显示装置，包括如上所述的任意一种阵列基板，具有前述实施例中的阵列基板相同的有益效果，由于阵列基板的结构和有益效果在前述实施例中已经进行了详细的描述，此处不再赘述。
在本发明实施例中，显示装置具体至少可以包括液晶显示装置和有机发光二极管显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种阵列基板的制作方法，包括如下步骤：
    在基板上形成显示区域和非显示区域，所述非显示区域中设有电路绑定区域；
    通过构图工艺，在所述显示区域形成取向膜；
    通过构图工艺，至少在所述非显示区域中除电路绑定区域以外的部分，形成透明保护层；以及
    通过摩擦压印工艺，在所述取向膜的表面形成多条具有一致排列方向的纹路，用于对液晶分子进行有序排列，
    其中，所述透明保护层的表面高度小于等于所述取向膜的表面高度。
  2. 根据权利要求1所述的阵列基板的制作方法，其中，形成透明保护层的步骤包括：
    在形成有所述取向膜的基板表面涂覆第一树脂层；
    在所述第一树脂层的表面形成光刻胶；
    通过一次掩膜曝光工艺和显影工艺，形成第一光刻胶完全覆盖区域和第一光刻胶完全去除区域，所述第一光刻胶完全覆盖区域对应待形成的所述透明保护层；所述第一光刻胶完全去除区域对应所述取向膜的图案以及所述电路绑定区域；
    刻蚀对应所述第一光刻胶去除区域的所述第一树脂层；以及
    对所述第一光刻胶完全覆盖区域的光刻胶进行剥离，以由保留下的第一树脂层形成所述透明保护层。
  3. 根据权利要求1所述的阵列基板的制作方法，其中，形成所述取向膜和所述透明保护层的步骤包括：
    在形成有所述显示区域和所述非显示区域的基板的表面涂覆第一树脂层；
    在所述第一树脂层上涂覆第二树脂层；
    在所述第二树脂层的表面形成光刻胶；
    通过一次掩膜曝光工艺和显影工艺，形成第二光刻胶完全覆盖区域、第二光刻胶完全去除区域以及光刻胶部分去除区域；所述第二光 刻胶完全覆盖区域对应待形成的所述取向膜；所述第二光刻胶完全去除区域对应所述电路绑定区域，所述光刻胶部分去除区域对应待形成的所述透明保护层；
    刻蚀对应所述第二光刻胶完全去除区域的所述第二树脂层和所述第一树脂层；
    将所述光刻胶部分去除区域的光刻胶进行灰化，并刻蚀对应所述光刻胶部分去除区域的所述第二树脂层；以及
    对所述第二光刻胶完全覆盖区域的光刻胶进行剥离，以由保留下的第一树脂层形成所述透明保护层。
  4. 根据权利要求2所述的阵列基板的制作方法，其中，所述透明保护层的厚度在2μm～5μm的范围内。
  5. 根据权利要求1-4中的任一项所述的阵列基板的制作方法，其中，所述电路绑定区域的面积小于用于执行摩擦压印工艺的印刷辊的印刷面积。
  6. 一种阵列基板，包括：
    基板，所述基板上设有显示区域和非显示区域，所述非显示区域中设有电路绑定区域；
    位于显示区域的取向膜，所述取向膜的表面设置有多条具有一致排列方向的纹路，用于对液晶分子进行有序排列；以及
    至少位于非显示区域中除电路绑定区域以外部分的透明保护层；
    其中，所述透明保护层的表面高度小于等于所述取向膜的表面高度。
  7. 根据权利要求6所述的阵列基板，其中，所述基板的对应所述显示区域的表面上仅设置有所述取向膜。
  8. 根据权利要求6所述的阵列基板，其中，所述基板的对应所述显示区域的表面上依次设置有所述透明保护层以及所述取向膜。
  9. 根据权利要求7所述的阵列基板，其中，所述透明保护层的厚度在2μm～5μm的范围内。
  10. 根据权利要求6-9中的任一项所述的阵列基板，其中，所述电路绑定区域的面积小于用于通过执行摩擦压印工艺而形成所述纹路的印刷辊的印刷面积。
  11. 一种显示装置，包括如权利要求6-10任一项所述的阵列基板。
PCT/CN2015/079442 2014-09-26 2015-05-21 阵列基板及其制作方法、显示装置 Ceased WO2016045395A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/778,763 US9869902B2 (en) 2014-09-26 2015-05-21 Array substrate and method of manufacturing the same, and display device
EP15763811.5A EP3200021B1 (en) 2014-09-26 2015-05-21 Array substrate, manufacturing method thereof, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410505653.5A CN104280958B (zh) 2014-09-26 2014-09-26 一种阵列基板及其制作方法、显示装置
CN201410505653.5 2014-09-26

Publications (1)

Publication Number Publication Date
WO2016045395A1 true WO2016045395A1 (zh) 2016-03-31

Family

ID=52255982

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/079442 Ceased WO2016045395A1 (zh) 2014-09-26 2015-05-21 阵列基板及其制作方法、显示装置

Country Status (4)

Country Link
US (1) US9869902B2 (zh)
EP (1) EP3200021B1 (zh)
CN (1) CN104280958B (zh)
WO (1) WO2016045395A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104280958B (zh) * 2014-09-26 2017-03-08 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104950524A (zh) * 2015-07-13 2015-09-30 合肥京东方光电科技有限公司 显示基板及制作方法、液晶面板的制作方法、显示装置
CN105093693A (zh) * 2015-08-07 2015-11-25 京东方科技集团股份有限公司 显示母板及其制作方法、显示面板、显示装置
CN105467686A (zh) * 2016-01-07 2016-04-06 京东方科技集团股份有限公司 一种显示基板及其制作方法、液晶盒、显示器
CN105974676A (zh) * 2016-07-22 2016-09-28 京东方科技集团股份有限公司 配向层的制造方法、液晶显示面板及显示装置
WO2018124728A1 (ko) * 2016-12-27 2018-07-05 주식회사 엘지화학 액정 변색 소자의 배선부 형성 방법 및 액정 변색 소자
CN109390286B (zh) * 2017-08-09 2022-04-15 昆山国显光电有限公司 阵列基板及其制造方法、显示面板及其制造方法
CN107767807B (zh) * 2017-08-23 2022-07-01 武汉精测电子集团股份有限公司 一种适用于cell工序的色斑修复方法及系统
CN108196402B (zh) * 2018-01-02 2020-12-01 京东方科技集团股份有限公司 取向膜涂覆方法
CN109581718A (zh) * 2019-01-30 2019-04-05 京东方科技集团股份有限公司 阵列基板母版、阵列基板、显示面板和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005164733A (ja) * 2003-11-28 2005-06-23 Optrex Corp 液晶表示パネル
CN101191935A (zh) * 2006-12-01 2008-06-04 群康科技(深圳)有限公司 用于液晶面板的基板、液晶面板和液晶显示装置
CN101211068A (zh) * 2006-12-29 2008-07-02 群康科技(深圳)有限公司 液晶面板制造方法
CN102455548A (zh) * 2010-10-18 2012-05-16 乐金显示有限公司 基板及包括该基板的液晶显示器件
CN104166273A (zh) * 2014-06-26 2014-11-26 京东方科技集团股份有限公司 显示基板、显示基板母板和显示装置
CN104280958A (zh) * 2014-09-26 2015-01-14 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3172840B2 (ja) * 1992-01-28 2001-06-04 株式会社日立製作所 アクティブマトリクス基板の製造方法および液晶表示装置
JP4544809B2 (ja) 2001-07-18 2010-09-15 三星電子株式会社 液晶表示装置
JP3976688B2 (ja) 2003-02-05 2007-09-19 Ｎｅｃ液晶テクノロジー株式会社 液晶表示装置及びその製造方法
JP2005338529A (ja) * 2004-05-28 2005-12-08 Nippon Seiki Co Ltd 液晶表示基板の配向処理方法および液晶表示基板のマザー基板
JP4731259B2 (ja) * 2005-09-16 2011-07-20 富士フイルム株式会社 Ｔｆｔ駆動素子を有する液晶セル用基板の製造方法および液晶セル用基板、ならびに液晶表示装置
US20120069509A1 (en) * 2009-06-12 2012-03-22 Sharp Kabushiki Kaisha Method for fabricating display panel
CN102043295B (zh) * 2009-12-25 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制造方法和液晶显示器
EP2525252A4 (en) * 2010-01-12 2014-06-04 Sharp Kk LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
KR20130000938A (ko) * 2011-06-24 2013-01-03 삼성디스플레이 주식회사 액정 표시 장치 및 액정 표시 장치의 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005164733A (ja) * 2003-11-28 2005-06-23 Optrex Corp 液晶表示パネル
CN101191935A (zh) * 2006-12-01 2008-06-04 群康科技(深圳)有限公司 用于液晶面板的基板、液晶面板和液晶显示装置
CN101211068A (zh) * 2006-12-29 2008-07-02 群康科技(深圳)有限公司 液晶面板制造方法
CN102455548A (zh) * 2010-10-18 2012-05-16 乐金显示有限公司 基板及包括该基板的液晶显示器件
CN104166273A (zh) * 2014-06-26 2014-11-26 京东方科技集团股份有限公司 显示基板、显示基板母板和显示装置
CN104280958A (zh) * 2014-09-26 2015-01-14 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Also Published As

Publication number Publication date
US9869902B2 (en) 2018-01-16
EP3200021A1 (en) 2017-08-02
EP3200021A4 (en) 2018-05-23
CN104280958B (zh) 2017-03-08
US20160306235A1 (en) 2016-10-20
EP3200021B1 (en) 2019-09-11
CN104280958A (zh) 2015-01-14

Similar Documents

Publication Publication Date Title
WO2016045395A1 (zh) 阵列基板及其制作方法、显示装置
US11215893B2 (en) Array substrate, method for manufacturing the same, and display apparatus
US8228455B2 (en) Exposing device, methods for forming pattern, channel, and hole by using the same, and liquid crystal display device therewith and method for fabricating the same
US9798192B2 (en) Display substrate and manufacturing method thereof, display panel and display device
CN105932030A (zh) 一种阵列基板及其制作方法、显示装置
WO2017000431A1 (zh) 阵列基板及其制备方法、显示面板及显示装置
KR101354434B1 (ko) 표시 장치 및 이의 제조 방법
KR101183928B1 (ko) 액정표시장치의 제조방법
KR102418375B1 (ko) 표시 장치 및 이의 제조 방법
US20070249074A1 (en) Active device array substrate, color filter substrate and manufacturing methods thereof
KR102049742B1 (ko) 액정 표시 장치 및 액정 표시 장치의 제조 방법
KR20130027207A (ko) 액정표시장치용 어레이 기판의 제조방법
CN204101854U (zh) 一种显示面板及显示装置
US8780315B2 (en) LCD panel, color filter substrate, and method of manufacturing the color filter substrate
KR20150018144A (ko) 액정표시장치 및 이의 제조방법
KR101131608B1 (ko) 반투과형 액정표시장치용 어레이 기판 및 그 제조방법
US10497725B2 (en) Method of producing display panel board
JP4514561B2 (ja) 反射型表示装置の製造方法
US11914244B2 (en) Display panel, manufacturing method thereof, and display device
KR102162884B1 (ko) 영상표시장치의 제조방법
KR20180092850A (ko) 편광판, 편광판의 제작 방법 및 표시 장치
JP2024049705A (ja) アレイ基板の製造方法、アレイ基板、及び表示装置
KR101028662B1 (ko) 액정표시장치용 박막트랜지스터 및 반도체막 패턴 제조방법
JP2007240932A (ja) 表示パネル用の基板および表示パネル
CN109686698A (zh) Tft阵列基板的制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14778763

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2015763811

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2015763811

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15763811

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE