WO2016058351A1 - 显示电路及其驱动方法和显示装置 - Google Patents

显示电路及其驱动方法和显示装置 Download PDF

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Publication number
WO2016058351A1
WO2016058351A1 PCT/CN2015/077376 CN2015077376W WO2016058351A1 WO 2016058351 A1 WO2016058351 A1 WO 2016058351A1 CN 2015077376 W CN2015077376 W CN 2015077376W WO 2016058351 A1 WO2016058351 A1 WO 2016058351A1
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Prior art keywords
unit
signal
transistor
node
terminal
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English (en)
French (fr)
Inventor
曹昆
吴仲远
宋琛
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to EP15775602.4A priority Critical patent/EP3208791B1/en
Priority to US14/787,893 priority patent/US9997136B2/en
Publication of WO2016058351A1 publication Critical patent/WO2016058351A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/10—Intensity circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/10—Dealing with defective pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present disclosure relates to a display circuit, a driving method thereof, and a display device.
  • the threshold voltage (Vth) of the driving transistor of each pixel unit in the entire panel is not uniform, and the Vth generated after long-term operation. Offsets reduce the uniformity of the panel display. Therefore, the Vth compensation pixel design is used to avoid the above problem.
  • the use of integrated gate drive technology English: gate driver on array, referred to as GOA
  • GOA gate driver on array
  • the design of the display circuit is mainly based on the pixel design with Vth compensation function and the single pulse GOA circuit design.
  • a pixel design with a Vth compensation function is generally performed by a threshold compensation module composed of a switching logic device in a pixel unit to perform signal conversion of the data line signal Vdata for several timings to realize pixel Vth compensation.
  • a single-pulse GOA circuit must provide a timing signal that matches the pixel Vth compensation in addition to the gate drive signal.
  • the Vth compensation function and the gate drive function are performed independently. Therefore, the design of the display circuit is complicated, which is disadvantageous for the improvement of the pixel density of the display panel.
  • a display circuit, a driving method thereof, and a display device are provided, which can reduce the design complexity of the display circuit and facilitate the pixel density of the display panel.
  • a display circuit including a pixel unit, a first gate driving unit, and a second gate driving unit is provided.
  • the first gate driving unit is configured to input a first gate driving signal to the pixel unit.
  • the second gate driving unit is configured to input a second gate driving signal to the pixel unit.
  • the pixel unit is configured to perform threshold compensation and gray scale display simultaneously under the control of the first gate driving signal and the second gate driving signal.
  • the first gate driving unit comprises: at least three GOA units, each of the GOA units comprising: a signal input end, an output end, a reset end, and an idle output end.
  • the signal input end of the first stage GOA unit inputs the first frame start signal, and the reset end of the first stage GOA unit is connected to the idle output end of the third stage GOA unit.
  • the signal input terminal of the level 2 GOA unit inputs a second frame start signal.
  • the reset terminal of the 2nth stage GOA unit is connected to the idle output of the 2n-1th GOA unit and the signal input of the 2n+1th GOA unit.
  • the reset terminal of the 2n+1th GOA unit is connected to the idle output of the 2n+3th GOA unit.
  • the signal input terminal of the 2n+2th GOA unit is connected to the idle output terminal of the 2n-2th GOA unit.
  • the output of the 2nth stage GOA unit and the output of the 2n+1th stage GOA unit output the first gate drive signal to the nth row of pixel units through a logic OR unit, where n is a positive integer.
  • the second gate driving unit comprises: at least three GOA units, each of the GOA units comprising: a signal input end, an output end, a reset end, and an idle output end.
  • the signal input terminal of the first stage GOA unit inputs a third frame start signal, and the reset end of the first stage GOA unit is connected to the idle output end of the third stage GOA unit.
  • the signal input terminal of the level 2 GOA unit inputs a fourth frame start signal.
  • the reset terminal of the 2nth stage GOA unit is connected to the idle output of the 2n-1th GOA unit and the signal input of the 2n+1th GOA unit.
  • the reset terminal of the 2n+1th GOA unit is connected to the idle output of the 2n+3th GOA unit.
  • the signal input terminal of the 2n+2th GOA unit is connected to the idle output terminal of the 2n-2th GOA unit.
  • An output of the 2nth stage GOA unit and an output of the 2n+1th GOA unit are connected to an input of a logic or unit, and an output of the logic or unit is connected to a logic reverse An input of the logic, the output of the logic inversion unit outputs the second gate drive signal, where n is a positive integer.
  • the second gate driving unit comprises: at least one pair of GOA units, each of the GOA units comprising: a signal input end, an output end, a reset end, and an idle output end.
  • the signal input end of the mth stage GOA unit unit is connected to the idle output end of the m-2th GOA unit; the reset end of the mth stage GOA unit unit is connected to the m+th The idle output terminal of the level 1 GOA unit; the signal input end of the m+1th GOA unit is connected to the idle output end of the m-1th GOA unit; the signal reset end of the m+1th GOA unit is connected to the m+3 level The idle output of the GOA unit.
  • the reset terminal of the level 1 GOA unit is connected to the idle output of the second stage GOA unit; the reset end of the level 2 GOA unit is connected to the idle output of the level 4 GOA unit.
  • the signal input end of the first stage GOA unit inputs the fifth frame start signal, and the signal input end of the second stage GOA unit inputs the sixth frame start signal.
  • the input terminal of the m-th stage GOA unit outputs the second gate driving signal to the (m+1)/2-th row pixel unit through a logic inversion unit, where m is an odd number.
  • the GOA unit includes: a pull-up unit, a pull-down unit, a reset unit, an idle output unit, and an output unit.
  • the pull-up unit is connected to the signal input end, the first level end, the first clock signal end, the second clock signal end, the first node, the second node, the third node, and the fourth node; wherein the pull-up unit is used And at a signal input end, a first level end, a first clock signal end, and a second clock signal end, the voltage of the first node is aligned with the signal input end, and the second node is The voltage is aligned with the signal input terminal or the voltage of the second node is aligned with the voltage of the fourth node, and the voltage of the third node is aligned with the voltage of the first level terminal. The voltage of the fourth node is aligned with the voltage of the first clock signal terminal.
  • the pull-down unit is connected to the second level end, the third level end, the idle output end, the output end, the first node, the second node, the third node, and the fourth node;
  • the voltage of the third node is aligned with the second level end under the control of the signal, and the voltages of the first node and the second node are compared with the first
  • the two-level terminal is pulled, and the voltage of the reset output terminal is aligned with the second level terminal under the signal control of the third node, and the signal is controlled by the signal of the third node
  • the voltage of the output terminal is aligned with the third level terminal, and the voltage of the fourth node is aligned with the third level terminal under the signal control of the third node.
  • the reset unit is connected to the reset end, the second level end, the first node and the second node; and is configured to, under the signal control of the reset end, the voltages of the first node and the second node and the second level end Lacy.
  • the idle output unit is connected to the first node, the second clock signal end, and the idle output end, and is configured to output a signal of the second clock signal end at the idle output end under the control of the first node.
  • the output unit is connected to the first node, the second clock signal end and the output end, and is configured to output a signal of the second clock signal end at the output end under the control of the first node.
  • the idle output unit includes: a first transistor, a gate of the first transistor is connected to the first node, a source of the first transistor is connected to a second clock signal end, and a drain of the first transistor is The pole is connected to the idle output.
  • the pull-up unit includes: a fourth transistor, a sixth transistor, a seventh transistor, an eleventh transistor, and a fourteenth transistor.
  • the gate and the source of the fourth transistor are connected to the first level terminal, and the drain of the fourth transistor is connected to the second node.
  • the gate and the source of the sixth transistor are connected to the signal input terminal, and the drain of the sixth transistor is a second node.
  • the gate of the seventh transistor is connected to the first node, the source of the seventh transistor is connected to the second clock signal end, and the drain of the seventh transistor is connected to the fourth node.
  • a gate of the eleventh transistor is connected to the gate to be connected to the idle output terminal, a source of the eleventh transistor is connected to the second node, and a drain of the eleventh transistor is connected to the first Four nodes.
  • the gate of the fourteenth transistor is connected to the first clock signal terminal, the source of the fourteenth transistor is connected to the second node, and the drain of the fourteenth transistor is connected to the first node.
  • the pull-down unit includes: a second transistor, a third transistor, a fifth transistor, an eighth transistor, a tenth transistor, and a thirteenth transistor.
  • the gate of the second transistor is connected to the third node, the source of the second transistor is connected to the idle output terminal, and the drain of the second transistor is connected to the second level terminal.
  • a gate of the third transistor is connected to the first node, a source of the third transistor is connected to the third node, and a drain of the third transistor is connected to the second level terminal.
  • a gate of the fifth transistor is connected to the third node, a source of the fifth transistor is connected to the first node, and a drain of the fifth transistor is connected to the second node.
  • the gate of the eighth transistor is connected to the third node, the source of the eighth transistor is connected to the fourth node, and the drain of the eighth transistor is connected to the third level terminal.
  • the gate of the tenth transistor is connected to the third node, the source of the tenth transistor is connected to the output terminal, and the drain of the tenth transistor is connected to the third level terminal.
  • a gate of the thirteenth transistor is connected to the third node, a source of the thirteenth transistor is connected to the second node, and a drain of the thirteenth transistor is connected to the second level terminal.
  • the reset unit includes: a twelfth transistor and a fifteenth transistor.
  • a gate of the twelfth transistor is connected to the reset terminal, a source of the twelfth transistor is connected to the first node, and a drain of the twelfth transistor is connected to the second node.
  • a gate of the fifteenth transistor is connected to the reset terminal, a source of the fifteenth transistor is connected to the second node, and a drain of the fifteenth transistor is connected to the second level terminal.
  • the output unit includes a ninth transistor, a gate of the ninth transistor is connected to the first node, and a source of the ninth transistor is connected to the second clock signal end, the ninth transistor The drain is connected to the output.
  • the first frame start signal is a single pulse signal
  • the second frame start signal is a multi-pulse signal
  • the second frame start signal is a single pulse signal, and the pulse width of the second frame start signal includes at least two clock cycles of the clock signal input to the first gate driving unit.
  • the third frame start signal is a single pulse signal
  • the fourth frame start signal is a multi-pulse signal.
  • the fourth frame start signal is a single pulse signal, and the pulse width of the fourth frame start signal includes at least two clock cycles of the clock signal input to the second gate driving unit.
  • the fifth frame start signal is a multi-pulse signal
  • the sixth frame start message The number is a single pulse signal
  • the fifth frame start signal is a single pulse signal, and the pulse width of the fifth frame start signal includes at least two clock cycles of the clock signal input to the first gate driving unit.
  • a driving method of a display circuit comprising the following steps:
  • the pixel unit is controlled to perform threshold compensation and gray scale display simultaneously by the first gate driving signal and the second gate driving signal.
  • the first gate driving signal and the second gate driving signal are multi-pulse signals.
  • the first gate driving signal is a pulse signal including at least two pulse widths
  • the second gate driving signal is a pulse signal including at least two pulse widths
  • a display device comprising: any of the above display circuits.
  • a first gate driving signal is input to a pixel unit through a first gate driving unit; a second gate driving signal is input to the pixel unit through a second gate driving unit;
  • the gate driving signal and the second gate driving signal control the pixel unit to perform threshold compensation and gray scale display simultaneously. Since the threshold compensation and the gray scale display of the pixel unit can be simultaneously performed under the signal control of the two gate driving units, the design complexity of the display circuit can be reduced, the pixel density of the display panel is improved, and the resolution of the display panel is improved. rate.
  • FIG. 1 is a schematic structural diagram of a display circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a first gate driving unit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a second gate driving unit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a second gate driving unit according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a GOA unit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a GOA unit according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a timing signal according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of another timing signal provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of still another timing signal according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of another timing signal provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic flow chart of a driving method of a display circuit according to an embodiment of the present disclosure.
  • the switching transistor and the driving transistor used in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other devices having the same characteristics. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. According to the form in the drawing, the middle end of the switching transistor is a gate, the signal input end is a drain, and the output end is a source. In addition, the switching transistor used in the embodiment of the present disclosure includes a P-type switching transistor and an N-type switching transistor.
  • the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switch is turned off.
  • the transistor is turned on when the gate is at a high level and turned off when the gate is at a low level;
  • the driving transistor includes a P type and an N type, wherein the P type driving transistor has a low level at the gate voltage (the gate voltage is smaller than the source voltage) And the absolute value of the voltage difference of the gate source is greater than the threshold voltage in an amplified state or a saturated state; wherein the gate voltage of the N-type driving transistor is at a high level (the gate voltage is greater than the source voltage), and the gate source When the absolute value of the pole differential is greater than the threshold voltage, it is in an amplified state or a saturated state.
  • FIG. 1 is a schematic structural diagram of a display circuit provided by an embodiment of the present disclosure.
  • a display circuit provided by an embodiment of the present disclosure includes: a pixel unit 11 , A gate driving unit 12 and a second gate driving unit 13.
  • the first gate driving unit 12 is configured to input a first gate driving signal to the pixel unit 11;
  • the second gate driving unit 13 is configured to input a second gate driving signal 13 to the pixel unit 11;
  • the pixel unit 11 is configured to perform threshold compensation and gray scale display simultaneously under the control of the first gate driving signal and the second gate driving signal.
  • the pixel units 11 are generally arranged in an array form.
  • a source drive circuit that provides a data line signal is also schematically illustrated in FIG.
  • the pixel unit 11 may be any pixel unit having a Vth compensation function, and the embodiment of the present disclosure does not limit the specific circuit structure of the pixel unit 11.
  • the pixel unit 11 controls the operation timing by at least two gate drive signals.
  • a first gate driving signal is input to a pixel unit through a first gate driving unit; and a second gate driving signal is input to the pixel unit through a second gate driving unit;
  • a gate driving signal and the second gate driving signal control the pixel unit to perform threshold compensation and gray scale display simultaneously. Since the threshold compensation and the gray scale display of the pixel unit can be simultaneously performed under the signal control of the two gate driving units, the design complexity of the display circuit can be reduced, the pixel density of the display panel is improved, and the resolution of the display panel is improved. rate.
  • FIG. 2 is a schematic structural diagram of a first gate driving unit provided by an embodiment of the present disclosure.
  • the first gate driving unit 12 includes: at least three GOA units, each of which includes a signal input terminal INPUT, an output terminal OUT, a reset terminal RESET, and an idle output terminal COUT.
  • the signal input terminal INPUT of the first stage GOA unit (S/R2-0 shown in the figure) inputs the first frame start signal STV1, and the reset end of the first stage GOA unit is connected to the third stage GOA unit.
  • a signal input terminal of the second stage GOA unit (S/R1-1 as shown in the figure) inputs a second frame start signal STV2;
  • the reset terminal RESET of the 2nth stage GOA unit is connected to the idle output terminal COUT of the 2n-1th GOA unit and the signal input terminal INPUT of the 2n+1th GOA unit;
  • the reset terminal RESET of the 2n+1th GOA unit is connected to the idle of the 2n+3th GOA unit Set output COUT;
  • the signal input terminal INPUT of the 2n+2th GOA unit is connected to the idle output terminal COUT of the 2n-2th GOA unit;
  • the output terminal OUT of the 2nth stage GOA unit and the output terminal OUT of the 2n+1th stage GOA unit output the first gate driving signal to the nth row of pixel units through a logical OR unit OR, where n is a positive integer .
  • the logical OR unit can superimpose and output the signals of the output terminal OUT of the 2nth-order GOA unit and the output terminal OUT of the 2n+1th-order GOA unit in the time domain.
  • FIG. 3 is a schematic structural diagram of a second gate driving unit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a second gate driving unit according to another embodiment of the present disclosure.
  • the second gate drive unit can be implemented by any of the two modes as provided in FIG. 3 or 4.
  • the second gate driving unit 13 includes: at least three GOA units, each of the GOA units including: a signal input end, an output end, a reset end, and an idle output end;
  • the signal input end of the second stage GOA unit (S/R1-1) inputs a fourth frame start signal
  • the reset end of the 2nth stage GOA unit is connected to the idle output end of the 2n-1th GOA unit and the signal input end of the 2n+1th GOA unit;
  • the reset end of the 2n+1th GOA unit is connected to the idle output end of the 2n+3th GOA unit;
  • the signal input end of the 2n+2th GOA unit is connected to the idle output end of the 2n-2th GOA unit;
  • An output of the 2nth stage GOA unit and an output of the 2n+1th stage GOA unit are coupled to an input of a logic or unit, the output of the logic or unit being coupled to an input of a logic inversion unit, An output of the logic inversion unit outputs the second gate drive signal, where n is a positive integer.
  • the logic inversion unit NG can output the signal of the input end of the logic or unit OR by 180°.
  • the second gate driving unit 13 includes: at least one pair of GOA units, each of the GOA units including: a signal input terminal INPUT, an output terminal OUT, a reset terminal RESET, and an idle output terminal COUT;
  • the signal input terminal INPUT of the mth stage GOA unit unit is connected to the idle output terminal COUT of the m-2th GOA unit; the reset terminal RESET connection of the mth stage GOA unit unit
  • the reset terminal RESET of the first stage GOA unit is connected to the idle output terminal COUT of the second stage GOA unit; the reset terminal RESET of the second stage GOA unit is connected to the idle output terminal COUT of the fourth stage GOA unit;
  • the signal input terminal INPUT of the first-stage GOA unit inputs a fifth frame start signal, and the signal input terminal INPUT of the second-stage GOA unit inputs a sixth frame start signal;
  • the output of the m-th stage GOA unit outputs the second gate drive signal to the (m+1)th-th row of pixel cells through the logic inversion unit NG, where m is an odd number.
  • the logic inversion unit NG can output the signal of the input terminal OUT of the m-th stage GOA unit by 180°.
  • FIG. 5 is a schematic structural diagram of a GOA unit according to an embodiment of the present disclosure.
  • the GOA unit includes a pull-up unit 41, a pull-down unit 42, a reset unit 43, an idle output unit 44, and an output unit 45.
  • the pull-up unit 41 is connected to the signal input terminal INPUT, the first level terminal V1, the first clock signal terminal CLKA, the second clock signal terminal CLKB, the first node a, the second node b, and the third node. c and the fourth node d.
  • the pull-up unit 41 is configured to compare the voltage of the first node a under the signal control of the signal input terminal INPUT, the first level terminal V1, the first clock signal terminal CLKA and the second clock signal terminal CLKB.
  • the signal input terminal INPUT is aligned, the voltage of the second node b is aligned with the signal input terminal INPUT or the voltage of the second node b is aligned with the voltage of the fourth node d.
  • the voltage of the third node c is aligned with the voltage of the first level terminal V1, and the voltage of the fourth node d is aligned with the voltage of the first clock signal terminal CLKA.
  • the pull-down unit 42 is connected to the second level terminal V2, the third level terminal V3, The idle output terminal COUT, the output terminal OUT, the first node a, the second node b, the third node c, and the fourth node d.
  • the pull-down unit 42 is configured to align the voltage of the third node c with the second level terminal V2 under the control of the signal of the first node a, under the signal control of the third node c
  • the voltages of the first node a and the second node b are aligned with the second level terminal V2, and the voltage of the output terminal OUT and the second are controlled under the signal control of the third node c
  • the level terminal V2 is aligned, and the voltage of the output terminal OUT is aligned with the third level terminal V3 under the control of the signal of the third node c, and the signal is controlled by the signal of the third node c.
  • the voltage of the fourth node d is aligned with the third level terminal V3.
  • the reset unit 43 is connected to the reset terminal RESET, the second level terminal V2, and the second node b, and is connected to the first node a through the pull-down unit 42; for signal control at the reset terminal RESET
  • the voltages of the first node a and the second node b are aligned with the second level terminal V2.
  • the idle output unit 44 is connected to the second clock signal terminal CLKB and the idle output terminal COUT, and is connected to the first node a through the pull-down unit 42 for being under the control of the first node a.
  • the idle output terminal COUT outputs a signal of the second clock signal terminal CLKB.
  • the output unit 45 is connected to the first node a, the second clock signal terminal CLKB, and the output terminal OUT.
  • the output unit 45 is configured to output a signal of the second clock signal terminal CLKB at the output terminal OUT under the control of the first node a.
  • FIG. 6 is a schematic structural diagram of a GOA unit according to another embodiment of the present disclosure.
  • the idle output unit includes: a first transistor M1, a gate of the first transistor M1 is connected to the first node a, and a source of the first transistor M1
  • the second clock signal terminal CLKB is connected to the pole, and the drain of the first transistor M1 is connected to the idle output terminal COUT.
  • the pull-up unit includes a fourth transistor M4, a sixth transistor M6, a seventh transistor M7, an eleventh transistor M11, and a fourteenth transistor M14.
  • the gate and the source of the fourth transistor M4 are connected to the first level terminal V1, and the drain of the fourth transistor M4 is connected to the third node c.
  • the gate and the source of the sixth transistor M6 are connected to the signal input terminal INPUT, and the drain of the sixth transistor M6 is the second node b.
  • a gate of the seventh transistor M7 is connected to the first node a, a source of the seventh transistor M7 is connected to the second clock signal terminal CLKB, and a drain of the seventh transistor M7 is connected to a fourth node d .
  • a gate of the eleventh transistor M11 is connected to the idle output terminal COUT, a source of the eleventh transistor M11 is connected to the second node b, and a drain of the eleventh transistor M11 is connected to the first Four nodes d.
  • the gate of the fourteenth transistor M14 is connected to the first clock signal terminal CLKA, the source of the fourteenth transistor M14 is connected to the second node b, and the drain of the fourteenth transistor M14 is connected to the first One node a.
  • the pull-down unit includes: a second transistor M2, a third transistor M3, a fifth transistor M5, an eighth transistor M8, a tenth transistor M10, and a thirteenth transistor M13.
  • the gate of the second transistor M2 is connected to the third node c, the source of the second transistor M2 is connected to the idle output terminal COUT, and the drain of the second transistor M2 is connected to the second level terminal V2.
  • a gate of the third transistor M3 is connected to the first node a, a source of the third transistor M3 is connected to the third node c, and a drain of the third transistor M3 is connected to the second level terminal V2.
  • a gate of the fifth transistor M5 is connected to the third node c, a source of the fifth transistor M5 is connected to the first node a, and a drain of the fifth transistor M5 is connected to the second node b .
  • the gate of the eighth transistor M8 is connected to the third node c, the source of the eighth transistor M8 is connected to the fourth node d, and the drain of the eighth transistor M8 is connected to the third level terminal V3.
  • a gate of the tenth transistor M10 is connected to the third node c, a source of the tenth transistor M10 is connected to the output terminal OUT, and a drain of the tenth transistor M10 is connected to the third level terminal V3 .
  • a gate of the thirteenth transistor M13 is connected to the third node c, a source of the thirteenth transistor M13 is connected to the second node b, and a drain of the thirteenth transistor M13 is connected to the first Two-level terminal V2.
  • the reset unit includes a twelfth transistor M12 and a fifteenth transistor M15.
  • a gate of the twelfth transistor M12 is connected to the reset terminal RESET, a source of the twelfth transistor M12 is connected to the first node a, and a drain of the twelfth transistor M12 is connected to the second node Node b.
  • a gate of the fifteenth transistor M15 is connected to the reset terminal RESET, a source of the fifteenth transistor M15 is connected to the second node b, and a drain of the fifteenth transistor M15 is connected to the second Level terminal V2.
  • the output unit includes a ninth transistor M9, a gate of the ninth transistor M9 is connected to the first node a, and a source of the ninth transistor M9 is connected to the second clock signal end. CLKB, the drain of the ninth transistor M9 is connected to the output terminal OUT.
  • the first frame start signal is a single pulse signal
  • the second frame start signal is a multi-pulse signal.
  • the second frame start signal is a single pulse signal
  • the pulse width of the second frame start signal includes at least two clock cycles of the clock signal input to the first gate driving unit.
  • the third frame start signal is a single pulse signal
  • the fourth frame start signal is a multi-pulse signal.
  • the fourth frame start signal is a single pulse signal
  • the pulse width of the fourth frame start signal includes at least two clock cycles of the clock signal input to the second gate driving unit.
  • the fifth frame start signal is a multi-pulse signal
  • the sixth frame start signal is a single pulse signal.
  • the fifth frame start signal is a single pulse signal
  • the pulse width of the fifth frame start signal includes at least two clock cycles of the clock signal input to the first gate driving unit.
  • a pixel unit 11 to which the embodiment of the present disclosure is applied may be any pixel unit having a Vth compensation function, and the pixel unit 11 controls the operation timing by at least two gate driving signals, where the pixel unit 11 is no longer provided.
  • the specific circuit structure may be any pixel unit having a Vth compensation function, and the pixel unit 11 controls the operation timing by at least two gate driving signals, where the pixel unit 11 is no longer provided.
  • each of the transistors in the GOA unit may be an N-type switching transistor or a P-type switching transistor.
  • an N-type switching transistor will be described as an example.
  • the signal of the first level terminal V1 is the high level VGH
  • the signal of the second level terminal V2 is the first low level VGL1
  • the signal of the third level terminal V3 is the second low level VGL2.
  • the first clock signal terminal CLKA of the odd-numbered GOA unit (such as S/R2-0, S/R2-1 in FIG. 2) is input.
  • the first clock signal CLK1, the second clock signal terminal CLKB inputs the second clock signal CLK2, and the signal input terminal INPUT of the first stage GOA unit inputs the first frame start signal STV1; wherein CLK1 and CLK2 It is a pair of inverted clock signals, that is, the phase difference between CLK1 and CLK2 is 180°.
  • CLK1 and CLK2 have the same duty cycle (exemplary duty cycles are 50%), the same frequency, and a phase difference of 180°.
  • the clock signal input by the first clock signal terminal CLKA of one GOA unit of two adjacent odd-numbered GOA units is opposite to the clock signal input by the first clock signal terminal CLKA of another GOA unit (ie, there is a phase difference of 180°) ).
  • the first clock signal terminal CLKA of the GOA unit S/R1-2x inputs the third clock signal CLK3 and the second clock signal.
  • the terminal CLKB inputs the fourth clock signal CLK4, the first clock signal terminal CLKA of the GOA unit S/R1-(2x-1) is input to the fifth clock signal CLK5, and the second clock signal terminal CLKB is input to the sixth clock signal CLK6;
  • the signal input terminal INPUT of the GOA unit (S/R1-1) inputs the second frame start signal STV2;
  • CLK3 and CLK4 are a pair of inverted clock signals, that is, the phase difference between CLK3 and CLK4 is 180°.
  • CLK3 and CLK4 have the same duty cycle (exemplary duty cycles are 50%), the same frequency, and a phase difference of 180°.
  • CLK5 and CLK6 are a pair of inverted clock signals, that is, the phase difference between CLK5 and CLK6 is 180°.
  • CLK5 and CLK6 have the same duty cycle (exemplary duty cycles are 50%), the same frequency, and a phase difference of 180°.
  • the frequency of CLK3 is different from the frequency of CLK1.
  • the frequency of CLK3 is greater than the frequency of CLK1, that is, the pulse width of CLK3 is smaller than the pulse width of CLK1, and the frequency of CLK5 is greater than the frequency of CLK1, that is, the pulse width of CLK5 is smaller than the pulse width of CLK1.
  • the pulse width of CLK3 is 50% of the pulse width of CLK1; the pulse width of CLK5 is 50% of the pulse width of CLK1.
  • each transistor in the pull-up unit 41 is in an on state, and each transistor in the pull-down unit 42 is in an off state;
  • Each of the transistors in the reset unit 43 is in an off state, and an on state of each of the output unit 45 and the idle output unit 44.
  • the output end of the second-stage GOA unit (S/R1-1) outputs a multi-pulse signal, and as shown in FIG. 8, a specific implementation manner of the multi-pulse signal is provided, and the second frame start signal STV2 is provided. For multi-pulse signals.
  • FIG. 8 For multi-pulse signals.
  • the pulse width of the STV2 includes at least two clock cycles of the clock signal CLK4 input to the first gate driving unit, that is, In the duration of a pulse width of STV2, CLK4 contains four pulse signals.
  • the output unit can use the signal of CLK4 as the second-order GOA unit (S/R1) during the time period of a high-level pulse of STV2 and CLK4 is high.
  • the output signal since CLK4 contains four pulse signals in the duration of one pulse width of STV2, the output of the output of the second-stage GOA unit (S/R1-1) is four pulses. Multi-pulse signal.
  • the signal input terminal INPUT of the 2n-th stage GOA unit is also a multi-pulse signal (that is, the carry signal is also large. Pulse signal). Therefore, the output terminal OUT of the 2nth stage GOA unit also receives the output of the multi-pulse signal.
  • each transistor in the pull-up unit 41 is in an off state, and each transistor in the pull-down unit 42 is in an on state.
  • Each of the transistors in the reset unit 43 is in an on state, an off state of each of the output unit 45 and the idle output unit 44.
  • the OUT terminal of the output unit 45 is not output, and the COUT terminal of the idle output unit 44 is not output.
  • the respective transistors in the pull-up unit 41 are in an on state, and the respective transistors in the pull-down unit 42 are in an off state; in the reset unit 43
  • Each of the transistors is in an off state, and the conduction state of each of the output unit 45 and the idle output unit 44.
  • the output terminal of the third-stage GOA unit (S/R2-1) outputs a single-pulse signal, and thus the odd-level GOA unit sequences in the first gate driving unit 12 each output a single-pulse signal.
  • each transistor in the pull-up unit 41 is in an off state, and each transistor in the pull-down unit 42 is in an on state; each transistor in the reset unit 43 is in an on state, an output unit 45, and an idle output.
  • the off state of each transistor in cell 44 At this time, the OUT terminal of the output unit 45 is not output, and the COUT terminal of the idle output unit 44 is not output.
  • the output signal of the GOA unit of the 2nth stage and the output signal of the GON unit of the 2n+1th stage are superimposed and outputted by the logical OR unit OR to obtain the gate drive signal Gate1(n) of the pixel unit of the nth row.
  • the multi-pulse signal including four pulses outputted from the output terminal of the second-stage GOA unit (S/R1-1) and the output terminal of the third-stage GOA unit (S/R2-1) are outputted.
  • the pulse signal is superimposed and output to get Gate1.
  • Gate1 contains a wide pulse signal and at least one narrow pulse signal with a fixed waveform.
  • Gate1 includes a wide pulse signal and four waveform-fixed narrow pulse signals are only an example, and the embodiment of the present disclosure is not limited thereto, and may have other combinations.
  • the second gate driving unit 13 shown in FIG. 3 since only the logic is added to the second gate driving unit 13 shown in FIG. 3 with respect to the first gate driving unit 12 shown in FIG.
  • the reverse unit therefore, only the first gate driving signal outputted by the first gate driving unit 12 shown in FIG. 2 is inverted by 180° and used as the second gate driving signal, wherein the two frame start signals are
  • the fifth frame start signal STV5 is similar to the third frame start signal STV3
  • the sixth frame start signal STV6 is similar to the fourth frame start signal STV4, and the specific principle is not described herein again.
  • the first clock signal terminal CLKA of the odd-numbered GOA unit inputs the seventh clock signal CLK7
  • the second clock signal terminal CLKB inputs the eighth clock signal CLK8.
  • the signal input terminal INPUT of the level 1 GOA unit inputs the fifth frame start signal STV5.
  • CLK7 and CLK8 are a pair of inverted clock signals, that is, the phase difference between CLK7 and CLK8 is 180°.
  • CLK7 and CLK8 have the same duty cycle (exemplary duty cycles are 50%), the same frequency, and a phase difference of 180°.
  • the clock signal input by the first clock signal terminal CLKA of one GOA unit of two adjacent odd-numbered GOA units is opposite to the clock signal input by the first clock signal terminal CLKA of another GOA unit (ie, there is a phase difference of 180°) ).
  • the first clock signal terminal CLKA of the even-numbered GOA unit inputs the ninth clock signal CLK9
  • the second clock signal terminal CLKB inputs the tenth clock signal CLK10
  • the signal input terminal INPUT of the second-stage GOA unit inputs the sixth frame start signal STV6.
  • CLK9 and CLK10 are a pair of inverted clock signals, that is, the phase difference between CLK9 and CLK10 is 180°.
  • CLK9 and CLK10 have the same duty cycle (exemplary duty cycles are 50%), the same frequency, and a phase difference of 180°.
  • the clock signal input by the first clock signal terminal CLKA of one GOA unit of two adjacent even-numbered GOA units is opposite to the clock signal input by the first clock signal terminal CLKA of another GOA unit (ie, there is a phase difference of 180°) ).
  • the respective transistors in the pull-up unit 41 are in an on state, and the respective transistors in the pull-down unit 42 are turned on. Is an off state; each transistor in the reset unit 43 The off state of each of the output unit 45 and the idle output unit 44 is the off state.
  • the odd-numbered GOA cells in the second gate driving unit 13 output a multi-pulse signal, which is subjected to 180° inversion processing by the logic inverting unit NG.
  • each transistor in the pull-up unit 41 is in an off state, and each transistor in the pull-down unit 42 is in an on state; each transistor in the reset unit 43 is in an on state, an output unit 45, and an idle output.
  • the off state of each transistor in cell 44 At this time, the OUT terminal of the output unit 45 is not output, and the COUT terminal of the idle output unit 44 is not output.
  • the respective transistors in the pull-up unit 41 are in an on state, and the respective transistors in the pull-down unit 42 are in an off state; in the reset unit 43
  • Each of the transistors is in an off state, and the conduction state of each of the output unit 45 and the idle output unit 44.
  • the even-numbered GOA unit in the second gate driving unit 13 provides a reset signal of the reset terminal RESET input to the adjacent upper-order even-numbered GOA unit through the COUT terminal, and the reset signal may be a single pulse signal, the third level
  • the GOA unit (S/R2-1) is similar to the odd-numbered GOA unit in the first gate driving unit 12, and will not be described again here.
  • each transistor in the pull-up unit 41 is in an off state, and each transistor in the pull-down unit 42 is in an on state; each transistor in the reset unit 43 is in an on state, an output unit 45, and an idle output.
  • the off state of each transistor in cell 44 At this time, the OUT terminal of the output unit 45 is not output, and the COUT terminal of the idle output unit 44 is not output.
  • timing states of the first gate driving signal generated by the first gate driving unit 12 and the second gate driving signal generated by the second gate driving unit 13 provided in the above FIGS. 7, 8, 9, and 10 are only one possibility.
  • the implementation manner is that when the clock signal and the frame start signal of the input GOA unit are adjusted, the first gate driving signal and the second gate driving signal output of other timing states can also be generated, which are not specifically limited herein.
  • FIG. 11 is a flow chart showing a driving method of a display circuit according to an embodiment of the present disclosure. Referring to FIG. 11 , an embodiment of the present disclosure provides a driving method of a display circuit, including the following steps:
  • step 101 a first gate driving signal is input to the pixel unit through the first gate driving unit;
  • step 102 a second gate driving signal is input to the pixel unit through a second gate driving unit;
  • the pixel unit is controlled to perform threshold compensation and gray scale display simultaneously by the first gate driving signal and the second gate driving signal in step 103.
  • the first gate driving signal and the second gate driving signal are multi-pulse signals.
  • the first gate driving signal is a pulse signal including at least two pulse widths
  • the second gate driving signal is a pulse signal including at least two pulse widths.
  • the first gate driving signal is input to the pixel unit through the first gate driving unit; the second gate driving signal is input to the pixel unit through the second gate driving unit; and the first gate is passed through the first gate
  • the driving signal and the second gate driving signal control the pixel unit to perform threshold compensation and gray scale display simultaneously. Since the threshold compensation and the gray scale display of the pixel unit can be simultaneously performed under the signal control of the two gate driving units, the design complexity of the display circuit can be reduced, the pixel density of the display panel is improved, and the resolution of the display panel is improved. rate.
  • An embodiment of the present disclosure further provides a display device comprising: any of the above display circuits.
  • the display circuit includes a pixel unit, a first gate driving unit, and a second gate driving unit.
  • the display device can be a display device such as an electronic paper, a mobile phone, a television, a digital photo frame, or the like.

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Abstract

一种显示电路及其驱动方法和显示装置。该显示电路包括像素单元（11）、第一栅极驱动单元（12）和第二栅极驱动单元（13）；其中，所述第一栅极驱动单元（12）用于向所述像素单元（11）输入第一栅极驱动信号；所述第二栅极驱动单元（13）用于向所述像素单元（11）输入第二栅极驱动信号；所述像素单元（11）用于在所述第一栅极驱动信号和所述第二栅极驱动信号的控制下同时进行阈值补偿和灰阶显示。所述装置和方法能够降低显示电路的设计复杂度，有利于提高显示面板的像素密度。所述装置和方法的实施例可应用于显示器制造。

Description

显示电路及其驱动方法和显示装置 技术领域
本公开涉及一种显示电路及其驱动方法和显示装置。
背景技术
由于有机发光二极管(英文：Organic Light-Emitting Diode，简称OLED)像素设计多采用电流控制型，因此整个面板内各像素单元的驱动晶体管的阈值电压(Vth)不均一，并且长期工作后产生的Vth偏移会降低面板显示的均匀性。因此，通过Vth补偿像素设计来避免上述问题的发生。为了提高OLED显示面板的工艺集成度，同时降低成本，采用集成栅极驱动技术(英文：gate driver on array，简称GOA)是未来的发展趋势。但是OLED的Vth补偿像素设计需要外围栅极驱动电路与之相配合提供进行Vth补偿过程中的驱动信号，因此对栅极驱动电路提出了更高的要求。
目前显示电路的设计以单纯具有Vth补偿功能的像素设计配合单脉冲的GOA电路设计为主。具有Vth补偿功能的像素设计，通常是在像素单元中通过开关逻辑器件组成的阈值补偿模块将数据线信号Vdata进行若干时序的信号转换实现像素Vth补偿。此外，单脉冲的GOA电路除需要提供栅极驱动信号外，还必须能够提供与像素Vth补偿匹配的时序信号。Vth补偿功能和栅极驱动功能独立进行。因此，显示电路的设计较为复杂，不利于显示面板的像素密度的提高。
发明内容
在本公开的一些实施例中提供一种显示电路及其驱动方法和显示装置，能够降低显示电路的设计复杂度，有利于提高显示面板的像素密度。
在本公开的一个方面，提供一种显示电路，包括像素单元、第一栅极驱动单元和第二栅极驱动单元。
所述第一栅极驱动单元用于向所述像素单元输入第一栅极驱动信号。
所述第二栅极驱动单元用于向所述像素单元输入第二栅极驱动信号。
所述像素单元用于在所述第一栅极驱动信号和所述第二栅极驱动信号的控制下，同时进行阈值补偿和灰阶显示。
可选地，所述第一栅极驱动单元包括：至少三个GOA单元，每个所述GOA单元包括：信号输入端、输出端、复位端和闲置输出端。
第1级GOA单元的信号输入端输入第一帧起始信号，第1级GOA单元的复位端连接第3级GOA单元的闲置输出端。
第2级GOA单元的信号输入端输入第二帧起始信号。
第2n级GOA单元的复位端连接第2n-1级GOA单元的闲置输出端和第2n+1级GOA单元的信号输入端。
第2n+1级GOA单元的复位端连接第2n+3级GOA单元的闲置输出端。
第2n+2级GOA单元的信号输入端连接第2n-2级GOA单元的闲置输出端。
所述第2n级GOA单元的输出端和第2n+1级GOA单元的输出端通过逻辑或单元向第n行像素单元输出所述第一栅极驱动信号，其中，n为正整数。
可选地，所述第二栅极驱动单元包括：至少三个GOA单元，每个所述GOA单元包括：信号输入端、输出端、复位端和闲置输出端。
第1级GOA单元的信号输入端输入第三帧起始信号，第1级GOA单元的复位端连接第3级GOA单元的闲置输出端。
第2级GOA单元的信号输入端输入第四帧起始信号。
第2n级GOA单元的复位端连接第2n-1级GOA单元的闲置输出端和第2n+1级GOA单元的信号输入端。
第2n+1级GOA单元的复位端连接第2n+3级GOA单元的闲置输出端。
第2n+2级GOA单元的信号输入端连接第2n-2级GOA单元的闲置输出端。
所述第2n级GOA单元的输出端和第2n+1级GOA单元的输出端连接至逻辑或单元的输入端，所述逻辑或单元的输出端连接至逻辑反向单 元的输入端，所述逻辑反向单元的输出端输出所述第二栅极驱动信号，其中，n为正整数。
可选地，所述第二栅极驱动单元包括：至少一对GOA单元，每个所述GOA单元包括：信号输入端、输出端、复位端和闲置输出端。
除第1级GOA单元和第2级GOA单元外，第m级GOA单元单元的信号输入端连接第m-2级GOA单元的闲置输出端；第m级GOA单元单元的复位端连接第m+1级GOA单元的闲置输出端；第m+1级GOA单元的信号输入端连接第m-1级GOA单元的闲置输出端；第m+1级GOA单元的信号复位端连接第m+3级GOA单元的闲置输出端。
第1级GOA单元的复位端连接第2级GOA单元的闲置输出端；第2级GOA单元的复位端连接第4级GOA单元的闲置输出端。
其中第1级GOA单元的信号输入端输入第五帧起始信号，第2级GOA单元的信号输入端输入第六帧起始信号。
第m级GOA单元的输入端通过逻辑反向单元向第(m+1)/2行像素单元输出所述第二栅极驱动信号，m为奇数。
可选地，所述GOA单元包括：上拉单元、下拉单元、复位单元、闲置输出单元和输出单元。
所述上拉单元连接信号输入端、第一电平端、第一时钟信号端、第二时钟信号端、第一节点、第二节点、第三节点和第四节点；其中所述上拉单元用于在所述信号输入端、第一电平端、第一时钟信号端和第二时钟信号端的信号控制下将所述第一节点的电压与所述信号输入端拉齐，将所述第二节点的电压与所述信号输入端拉齐或将所述第二节点的电压与所述第四节点的电压拉齐，将所述第三节点的电压与所述第一电平端的电压拉齐，将所述第四节点的电压与所述第一时钟信号端的电压拉齐。
所述下拉单元连接第二电平端、第三电平端、所述闲置输出端、所述输出端、第一节点、第二节点、第三节点和第四节点；用于在所述第一节点的信号控制下将所述第三节点的电压与所述第二电平端拉齐，在所述第三节点的信号控制下将所述第一节点及所述第二节点的电压与所述第二电平端拉齐，在所述第三节点的信号控制下将所述重置输出端的电压与所述第二电平端拉齐，在所述第三节点的信号控制下将所述 输出端的电压与所述第三电平端拉齐，在所述第三节点的信号控制下将所述第四节点的电压与所述第三电平端拉齐。
所述复位单元连接复位端，第二电平端、第一节点和第二节点；用于在所述复位端的信号控制下将所述第一节点及第二节点的电压与所述第二电平端拉齐。
所述闲置输出单元连接第一节点、第二时钟信号端和闲置输出端，用于在所述第一节点的控制下在所述闲置输出端输出所述第二时钟信号端的信号。
所述输出单元连接第一节点、第二时钟信号端和输出端，用于在所述第一节点的控制下在所述输出端输出所述第二时钟信号端的信号。
可选地，所述闲置输出单元包括：第一晶体管，所述第一晶体管的栅极连接第一节点，所述第一晶体管的源极连接第二时钟信号端，所述第一晶体管的漏极连接所述闲置输出端。
可选地，所述上拉单元包括：第四晶体管、第六晶体管、第七晶体管、第十一晶体管、第十四晶体管。
所述第四晶体管的栅极和源极连接第一电平端，所述第四晶体管的漏极连接第二节点。
所述第六晶体管的栅极和源极连接所述信号输入端，所述第六晶体管的漏极第二节点。
所述第七晶体管的栅极连接所述第一节点，所述第七晶体管的源极连接所述第二时钟信号端，所述第七晶体管的漏极连接第四节点。
所述第十一晶体管的栅极连接所述栅极连接所述闲置输出端，所述第十一晶体管的源极连接所述第二节点，所述第十一晶体管的漏极连接所述第四节点。
所述第十四晶体管的栅极连接第一时钟信号端，所述第十四晶体管的源极连接所述第二节点，所述第十四晶体管的漏极连接所述第一节点。
可选地，所述下拉单元包括：第二晶体管、第三晶体管、第五晶体管、第八晶体管、第十晶体管和第十三晶体管。
所述第二晶体管的栅极连接第三节点，所述第二晶体管的源极连接所述闲置输出端，所述第二晶体管的漏极连接第二电平端。
所述第三晶体管的栅极连接所述第一节点，所述第三晶体管的源极连接所述第三节点，所述第三晶体管的漏极连接所述第二电平端。
所述第五晶体管的栅极连接所述第三节点，所述第五晶体管的源极连接所述第一节点，所述第五晶体管的漏极连接所述第二节点。
所述第八晶体管的栅极连接所述第三节点，所述第八晶体管的源极连接所述第四节点，所述第八晶体管的漏极连接第三电平端。
所述第十晶体管的栅极连接所述第三节点，所述第十晶体管的源极连接所述输出端，所述第十晶体管的漏极连接所述第三电平端。
所述第十三晶体管的栅极连接所述第三节点，所述第十三晶体管的源极连接所述第二节点，所述第十三晶体管的漏极连接所述第二电平端。
可选地，所述复位单元包括：第十二晶体管和第十五晶体管。
所述第十二晶体管的栅极连接所述复位端，所述第十二晶体管的源极连接所述第一节点，所述第十二晶体管的漏极连接所述第二节点。
所述第十五晶体管的栅极连接所述复位端，所述第十五晶体管的源极连接所述第二节点，所述第十五晶体管的漏极连接所述第二电平端。
可选地，所述输出单元包括第九晶体管，所述第九晶体管的栅极连接所述第一节点，所述第九晶体管的源极连接所述第二时钟信号端，所述第九晶体管的漏极连接所述输出端。
可选地，所述第一帧起始信号为单脉冲信号，所述第二帧起始信号为多脉冲信号。
或者，所述第二帧起始信号为单脉冲信号，所述第二帧起始信号的脉冲宽度包含输入所述第一栅极驱动单元的时钟信号的至少两个时钟周期。
可选地，所述第三帧起始信号为单脉冲信号，所述第四帧起始信号为多脉冲信号。
或者，所述第四帧起始信号为单脉冲信号，所述第四帧起始信号的脉冲宽度包含输入所述第二栅极驱动单元的时钟信号的至少两个时钟周期。
可选地，所述第五帧起始信号为多脉冲信号，所述第六帧起始信 号为单脉冲信号。
或者，所述第五帧起始信号为单脉冲信号，所述第五帧起始信号的脉冲宽度包含输入所述第一栅极驱动单元的时钟信号的至少两个时钟周期。
按照本公开的另一方面，提供一种显示电路的驱动方法，该方法包括下列步骤：
通过第一栅极驱动单元向像素单元输入第一栅极驱动信号；
通过第二栅极驱动单元向所述像素单元输入第二栅极驱动信号；
通过所述第一栅极驱动信号和所述第二栅极驱动信号控制所述像素单元同时进行阈值补偿和灰阶显示。
可选地，所述第一栅极驱动信号和所述第二栅极驱动信号为多脉冲信号。
可选地，所述第一栅极驱动信号为包含至少两种脉冲宽度的脉冲信号，和/或所述第二栅极驱动信号为包含至少两种脉冲宽度的脉冲信号。
按照本发明的另一方面，提供一种显示装置，包括：上述任一的显示电路。
按照本公开的实施例，通过第一栅极驱动单元向像素单元输入第一栅极驱动信号；通过第二栅极驱动单元向所述像素单元输入第二栅极驱动信号；通过所述第一栅极驱动信号和所述第二栅极驱动信号控制所述像素单元同时进行阈值补偿和灰阶显示。由于像素单元的阈值补偿和灰阶显示可以同时在两个栅极驱动单元的信号控制下进行，因此能够降低显示电路的设计复杂度，有利于提高显示面板的像素密度，从而提高显示面板的分辨率。
附图说明
图1为本公开的实施例提供的一种显示电路的结构示意图；
图2为本公开的实施例提供的第一栅极驱动单元的结构示意图；
图3为本公开的实施例提供的第二栅极驱动单元的结构示意图；
图4为本公开的另一实施例提供的第二栅极驱动单元的结构示意图；
图5为本公开的实施例提供的一种GOA单元的结构示意图；
图6为本公开的另一实施例提供的一种GOA单元的结构示意图；
图7为本公开的实施例提供的一种时序信号示意图；
图8为本公开的实施例提供的另一种时序信号示意图；
图9为本公开的实施例提供的又一种时序信号示意图；
图10为本公开的实施例提供的另外一种时序信号示意图；
图11为本公开的实施例提供的一种显示电路的驱动方法流程示意图。
具体实施方式
下面结合附图对本公开实施例提供的显示电路及其驱动方法和显示装置进行详细描述，其中用相同的附图标记指示本文中的相同元件。在下面的描述中，为便于解释，给出了大量具体细节，以便提供对一个或多个实施例的全面理解。然而，很明显，也可以不用这些具体细节来实现所述实施例。
本公开所有实施例中采用的开关晶体管和驱动晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为漏极、输出端为源极。此外，本公开实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止；驱动晶体管包括P型和N型，其中P型驱动晶体管在栅极电压为低电平(栅极电压小于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态；其中N型驱动晶体管的栅极电压为高电平(栅极电压大于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态。
图1示出了本公开的实施例提供的一种显示电路的结构示意图。参照图1所示，本公开实施例提供的显示电路包括：像素单元11、第 一栅极驱动单元12和第二栅极驱动单元13。
图1中，所述第一栅极驱动单元12用于向所述像素单元11输入第一栅极驱动信号；
所述第二栅极驱动单元13用于向所述像素单元11输入第二栅极驱动信号13；
所述像素单元11用于在所述第一栅极驱动信号和所述第二栅极驱动信号的控制下同时进行阈值补偿和灰阶显示。
这里，像素单元11通常为按照阵列形式排列。图1中还示意性地示出了提供数据线信号的源极驱动电路。像素单元11可以为任一种具备Vth补偿功能的像素单元，本公开的实施例对像素单元11的具体电路结构不做限制。该像素单元11至少通过两个栅极驱动信号控制工作时序。
在图1所示电路中，通过第一栅极驱动单元向像素单元输入第一栅极驱动信号；通过第二栅极驱动单元向所述像素单元输入第二栅极驱动信号；通过所述第一栅极驱动信号和所述第二栅极驱动信号控制所述像素单元同时进行阈值补偿和灰阶显示。由于像素单元的阈值补偿和灰阶显示可以在两个栅极驱动单元的信号控制下同时进行，因此能够降低显示电路的设计复杂度，有利于提高显示面板的像素密度，从而提高显示面板的分辨率。
进一步地，图2示出了本公开的实施例提供的第一栅极驱动单元的结构示意图。参照图2所示，第一栅极驱动单元12包括：至少三个GOA单元，每个所述GOA单元包括：信号输入端INPUT、输出端OUT、复位端RESET和闲置输出端COUT。
图2中，第1级GOA单元(如图中所示的S/R2-0)的信号输入端INPUT输入第一帧起始信号STV1，第1级GOA单元的复位端连接第3级GOA单元的闲置输出端COUT；
第2级GOA单元(如图中所示的S/R1-1)的信号输入端输入第二帧起始信号STV2；
第2n级GOA单元的复位端RESET连接第2n-1级GOA单元的闲置输出端COUT和第2n+1级GOA单元的信号输入端INPUT；
第2n+1级GOA单元的复位端RESET连接第2n+3级GOA单元的闲 置输出端COUT；
第2n+2级GOA单元的信号输入端INPUT连接第2n-2级GOA单元的闲置输出端COUT；
所述第2n级GOA单元的输出端OUT和第2n+1级GOA单元的输出端OUT通过逻辑或单元OR向第n行像素单元输出所述第一栅极驱动信号，其中，n为正整数。
在此，可以理解的是，逻辑或单元OR能够将所述第2n级GOA单元的输出端OUT和第2n+1级GOA单元的输出端OUT的信号在时域上叠加输出。
进一步地，图3示出了本公开的实施例提供的第二栅极驱动单元的结构示意图。图4示出了本公开的另一实施例提供的第二栅极驱动单元的结构示意图。第二栅极驱动单元可以通过如图3或4提供的两种方式中的任何一种实现。参照图3所示，所述第二栅极驱动单元13包括：至少三个GOA单元，每个所述GOA单元包括：信号输入端、输出端、复位端和闲置输出端；
图3中，第1级GOA单元(S/R2-0)的信号输入端输入第三帧起始信号，第1级GOA单元的复位端连接第3级GOA单元(S/R2-1)的闲置输出端；
第2级GOA单元(S/R1-1)的信号输入端输入第四帧起始信号；
第2n级GOA单元的复位端连接第2n-1级GOA单元的闲置输出端和第2n+1级GOA单元的信号输入端；
第2n+1级GOA单元的复位端连接第2n+3级GOA单元的闲置输出端；
第2n+2级GOA单元的信号输入端连接第2n-2级GOA单元的闲置输出端；
所述第2n级GOA单元的输出端和第2n+1级GOA单元的输出端连接至逻辑或单元的输入端，所述逻辑或单元的输出端连接至逻辑反向单元的输入端，所述逻辑反向单元的输出端输出所述第二栅极驱动信号，其中，n为正整数。
可以理解的是，逻辑反向单元NG能够将逻辑或单元OR的输入端的信号反相180°后输出。
参照图4所示，所述第二栅极驱动单元13包括：至少一对GOA单元，每个所述GOA单元包括：信号输入端INPUT、输出端OUT、复位端RESET和闲置输出端COUT；
除第1级GOA单元和第2级GOA单元外，第m级GOA单元单元的信号输入端INPUT连接第m-2级GOA单元的闲置输出端COUT；第m级GOA单元单元的复位端RESET连接第m+1级GOA单元的闲置输出端COUT；第m+1级GOA单元的信号输入端INPUT连接第m-1级GOA单元的闲置输出端COUT；第m+1级GOA单元的信号复位端RESET连接第m+3级GOA单元的闲置输出端COUT；
第1级GOA单元的复位端RESET连接第2级GOA单元的闲置输出端COUT；第2级GOA单元的复位端RESET连接第4级GOA单元的闲置输出端COUT；
其中第1级GOA单元的信号输入端INPUT输入第五帧起始信号，第2级GOA单元的信号输入端INPUT输入第六帧起始信号；
第m级GOA单元的输出端通过逻辑反向单元NG向第(m+1)/2行像素单元输出所述第二栅极驱动信号，m为奇数。
可以理解的是，逻辑反向单元NG能够将第m级GOA单元的输入端OUT的信号反相180°后输出。
图5示出本公开的实施例提供的一种GOA单元的结构示意图。可选地，参照图5所示，该GOA单元包括：上拉单元41、下拉单元42、复位单元43、闲置输出单元44和输出单元45。
在图5中，所述上拉单元41连接信号输入端INPUT、第一电平端V1、第一时钟信号端CLKA、第二时钟信号端CLKB、第一节点a、第二节点b、第三节点c和第四节点d。所述上拉单元41用于在所述信号输入端INPUT、第一电平端V1、第一时钟信号端CLKA和第二时钟信号端CLKB的信号控制下将所述第一节点a的电压与所述信号输入端INPUT拉齐，将所述第二节点b的电压与所述信号输入端INPUT拉齐或将所述第二节点b的电压与所述第四节点d的电压拉齐，将所述第三节点c的电压与所述第一电平端V1的电压拉齐，将所述第四节点d的电压与所述第一时钟信号端CLKA的电压拉齐。
在图5中，所述下拉单元42连接第二电平端V2、第三电平端V3、 所述闲置输出端COUT、所述输出端OUT、第一节点a、第二节点b、第三节点c和第四节点d。所述下拉单元42用于在所述第一节点a的信号控制下将所述第三节点c的电压与所述第二电平端V2拉齐，在所述第三节点c的信号控制下将所述第一节点a及所述第二节点b的电压与所述第二电平端V2拉齐，在所述第三节点c的信号控制下将所述输出端OUT的电压与所述第二电平端V2拉齐，在所述第三节点c的信号控制下将所述输出端OUT的电压与所述第三电平端V3拉齐，在所述第三节点c的信号控制下将所述第四节点d的电压与所述第三电平端V3拉齐。
如图5所示，所述复位单元43连接复位端RESET，第二电平端V2、和第二节点b，并通过下拉单元42连接第一节点a；用于在所述复位端RESET的信号控制下将所述第一节点a及第二节点b的电压与所述第二电平端V2拉齐。
如图5所示，所述闲置输出单元44连接第二时钟信号端CLKB和闲置输出端COUT，并通过下拉单元42连接第一节点a；用于在所述第一节点a的控制下在所述闲置输出端COUT输出所述第二时钟信号端CLKB的信号。
如所5所示，所述输出单元45连接第一节点a、第二时钟信号端CLKB，和输出端OUT。所述输出单元45用于在所述第一节点a的控制下在所述输出端OUT输出所述第二时钟信号端CLKB的信号。
图6示出本公开的另一实施例提供的一种GOA单元的结构示意图。进一步地，参照图6所示，在该GOA单元中，所述闲置输出单元包括：第一晶体管M1，所述第一晶体管M1的栅极连接第一节点a，所述第一晶体管M1的源极连接第二时钟信号端CLKB，所述第一晶体管M1的漏极连接所述闲置输出端COUT。
如图6所示，所述上拉单元包括：第四晶体管M4、第六晶体管M6、第七晶体管M7、第十一晶体管M11、第十四晶体管M14。
所述第四晶体管M4的栅极和源极连接第一电平端V1，所述第四晶体管M4的漏极连接第三节点c。
所述第六晶体管M6的栅极和源极连接所述信号输入端INPUT，所述第六晶体管M6的漏极第二节点b.
所述第七晶体管M7的栅极连接所述第一节点a，所述第七晶体管M7的源极连接所述第二时钟信号端CLKB，所述第七晶体管M7的漏极连接第四节点d.
所述第十一晶体管M11的栅极连接所述闲置输出端COUT，所述第十一晶体管M11的源极连接所述第二节点b，所述第十一晶体管M11的漏极连接所述第四节点d.
所述第十四晶体管M14的栅极连接第一时钟信号端CLKA，所述第十四晶体管M14的源极连接所述第二节点b，所述第十四晶体管M14的漏极连接所述第一节点a。
如图6所示，所述下拉单元包括：第二晶体管M2、第三晶体管M3、第五晶体管M5、第八晶体管M8、第十晶体管M10和第十三晶体管M13。
所述第二晶体管M2的栅极连接第三节点c，所述第二晶体管M2的源极连接所述闲置输出端COUT，所述第二晶体管M2的漏极连接第二电平端V2。
所述第三晶体管M3的栅极连接所述第一节点a，所述第三晶体管M3的源极连接所述第三节点c，所述第三晶体管M3的漏极连接所述第二电平端V2。
所述第五晶体管M5的栅极连接所述第三节点c，所述第五晶体管M5的源极连接所述第一节点a，所述第五晶体管M5的漏极连接所述第二节点b。
所述第八晶体管M8的栅极连接所述第三节点c，所述第八晶体管M8的源极连接所述第四节点d，所述第八晶体管M8的漏极连接第三电平端V3。
所述第十晶体管M10的栅极连接所述第三节点c，所述第十晶体管M10的源极连接所述输出端OUT，所述第十晶体管M10的漏极连接所述第三电平端V3。
所述第十三晶体管M13的栅极连接所述第三节点c，所述第十三晶体管M13的源极连接所述第二节点b，所述第十三晶体管M13的漏极连接所述第二电平端V2。
如图6所示，所述复位单元包括：第十二晶体管M12和第十五晶体管M15。
所述第十二晶体管M12的栅极连接所述复位端RESET，所述第十二晶体管M12的源极连接所述第一节点a，所述第十二晶体管M12的漏极连接所述第二节点b。
所述第十五晶体管M15的栅极连接所述复位端RESET，所述第十五晶体管M15的源极连接所述第二节点b，所述第十五晶体管M15的漏极连接所述第二电平端V2。
如图6所示，所述输出单元包括第九晶体管M9，所述第九晶体管M9的栅极连接所述第一节点a，所述第九晶体管M9的源极连接所述第二时钟信号端CLKB，所述第九晶体管M9的漏极连接所述输出端OUT。
进一步可选地，所述第一帧起始信号为单脉冲信号，所述第二帧起始信号为多脉冲信号。或者，所述第二帧起始信号为单脉冲信号，所述第二帧起始信号的脉冲宽度包含输入所述第一栅极驱动单元的时钟信号的至少两个时钟周期。所述第三帧起始信号为单脉冲信号，所述第四帧起始信号为多脉冲信号。或者，所述第四帧起始信号为单脉冲信号，所述第四帧起始信号的脉冲宽度包含输入所述第二栅极驱动单元的时钟信号的至少两个时钟周期。所述第五帧起始信号为多脉冲信号，所述第六帧起始信号为单脉冲信号。或者，所述第五帧起始信号为单脉冲信号，所述第五帧起始信号的脉冲宽度包含输入所述第一栅极驱动单元的时钟信号的至少两个时钟周期。
本公开的实施例应用的一种像素单元11，可以为任一种具备Vth补偿功能的像素单元，并且像素单元11至少通过两个栅极驱动信号控制工作时序，这里不再提供像素单元11的具体电路结构。
下面参照如图7、8、9、10所示的时序信号示意图，对上述的显示电路的工作过程进行描述。在此，上述GOA单元中各晶体管可以为N型开关晶体管，或P型开关晶体管，以下以N型开关晶体管为例进行说明。此外，第一电平端V1的信号为高电平VGH，第二电平端V2的信号为第一低电平VGL1，第三电平端V3的信号为第二低电平VGL2。参照图2所示，对于第一栅极驱动单元12中的GOA单元，奇数级的GOA单元(如图2中的S/R2-0、S/R2-1)的第一时钟信号端CLKA输入第一时钟信号CLK1，第二时钟信号端CLKB输入第二时钟信号CLK2，第一级GOA单元的信号输入端INPUT输入第一帧起始信号STV1；其中CLK1和CLK2 为一对反相的时钟信号，即CLK1和CLK2的相位差为180°。例如：CLK1和CLK2占空比相同(示例性的占空比均为50％)、频率相同、相位差为180°。两个相邻的奇数级的GOA单元中一个GOA单元的第一时钟信号端CLKA输入的时钟信号与另一个GOA单元的第一时钟信号端CLKA输入的时钟信号相位相反(即存在180°相位差)。偶数级的GOA单元(如图2中的S/R1-1、S/R1-2)中，GOA单元S/R1-2x的第一时钟信号端CLKA输入第三时钟信号CLK3、第二时钟信号端CLKB输入第四时钟信号CLK4，GOA单元S/R1-(2x-1)的第一时钟信号端CLKA输入第五时钟信号CLK5、第二时钟信号端CLKB输入第六时钟信号CLK6；第2级GOA单元(S/R1-1)的信号输入端INPUT输入第二帧起始信号STV2；CLK3和CLK4为一对反相的时钟信号，即CLK3和CLK4的相位差为180°。例如：CLK3和CLK4占空比相同(示例性的占空比均为50％)、频率相同、相位差为180°。CLK5和CLK6为一对反相的时钟信号，即CLK5和CLK6的相位差为180°。例如：CLK5和CLK6占空比相同(示例性的占空比均为50％)、频率相同、相位差为180°。CLK3与CLK5存在预设的相位差，示例性地，CLK3与CLK5存在90°或180°相位差，或者CLK5的脉冲上升沿比CLK3的脉冲的上升沿延迟四分之一周期或二分之一周期。CLK3的频率与CLK1的频率不同，如：CLK3的频率大于CLK1的频率，即CLK3的脉冲宽度小于CLK1的脉冲宽度，CLK5的频率大于CLK1的频率，即CLK5的脉冲宽度小于CLK1的脉冲宽度。示例性地，CLK3的脉冲宽度为CLK1的脉冲宽度的50％；CLK5的脉冲宽度为CLK1的脉冲宽度的50％。
图2中，第一栅极驱动单元12中对于偶数级的GOA单元，在本级输出过程中，上拉单元41中的各个晶体管为导通状态，下拉单元42中的各个晶体管为截止状态；复位单元43中的各个晶体管为截止状态，输出单元45和闲置输出单元44中的各个晶体管的导通状态。参照图7所示，第2级GOA单元(S/R1-1)的输出端输出多脉冲信号，参照图8所示，提供一种多脉冲信号的具体实现方式，第二帧起始信号STV2为多脉冲信号。可替换地，如图9所示，通过调整第二帧起始信号STV2脉冲宽度，使得STV2的脉冲宽度包含输入所述第一栅极驱动单元的时钟信号CLK4的至少两个时钟周期，即在STV2的一个脉冲宽度的时长中， CLK4包含四个脉冲信号。针对图9，如果各晶体管为高电平导通，在STV2的一个高电平脉冲的时间周期内，CLK4为高电平时，输出单元能够将CLK4的信号作为第2级GOA单元(S/R1-1)的输出信号，由于在STV2的一个脉冲宽度的时长中，CLK4包含四个脉冲信号，因此第2级GOA单元(S/R1-1)的输出端输出的信号为包含4个脉冲的多脉冲信号。对于之后的第2n级GOA单元，因为2n-2级的GOA单元的COUT端输出的为多脉冲信号，因此第2n级GOA单元的信号输入端INPUT也为多脉冲信号(即进位信号也为多脉冲信号)。因此，第2n级GOA单元的输出端OUT也得到多脉冲信号的输出。
在本级非输出过程中，上拉单元41中的各个晶体管为截止状态，下拉单元42中的各个晶体管为导通状态。复位单元43中的各个晶体管为导通状态，输出单元45和闲置输出单元44中的各个晶体管的截止状态。此时，输出单元45的OUT端不输出，闲置输出单元44的COUT端也不输出。
第一栅极驱动单元12中对于奇数级的GOA单元，在本级输出过程中，上拉单元41中的各个晶体管为导通状态，下拉单元42中的各个晶体管为截止状态；复位单元43中的各个晶体管为截止状态，输出单元45和闲置输出单元44中的各个晶体管的导通状态。示例性地，参照图7所示，第3级GOA单元(S/R2-1)的输出端输出单脉冲信号，因此第一栅极驱动单元12中奇数级的GOA单元序列均输出单脉冲信号，其为常规方式，本公开的实施例不再结合STV1及CLK1和CLK2的时序图进行详述。在本级非输出过程中，上拉单元41中的各个晶体管为截止状态，下拉单元42中的各个晶体管为导通状态；复位单元43中的各个晶体管为导通状态，输出单元45和闲置输出单元44中的各个晶体管的截止状态。此时，输出单元45的OUT端不输出，闲置输出单元44的COUT端也不输出。
第2n级的GOA单元的输出信号和第2n+1级的GOA单元的输出信号通过逻辑或单元OR进行叠加输出，得到第n行像素单元的栅极驱动信号Gate1(n)。如图7所示，将第2级GOA单元(S/R1-1)的输出端输出的包含四个脉冲的多脉冲信号与第3级GOA单元(S/R2-1)的输出端输出单脉冲信号叠加输出得到Gate1。由于CLK3的脉冲宽度小于 CLK1的脉冲宽度，CLK5的脉冲宽度小于CLK1的脉冲宽度，因此Gate1包含一个宽脉冲信号和至少一个波形固定的窄脉冲信号。其中图6-10中Gate1包含一个宽脉冲信号和四个波形固定的窄脉冲信号只是一种示例，本公开的实施例中不局限于此，可以具有其他形式的组合。
对于图3所示的第二栅极驱动单元13的工作原理，由于相对于图2所示的第一栅极驱动单元12，图3所示的第二栅极驱动单元13中仅增加了逻辑反向单元，因此仅是将图2所示的第一栅极驱动单元12输出的第一栅极驱动信号反相180°后用作第二栅极驱动信号，其中两个帧起始信号中，第五帧起始信号STV5类似于第三帧起始信号STV3，第六帧起始信号STV6类似于第四帧起始信号STV4，具体原理这里不再赘述。
对于图4所示的第二栅极驱动单元13中的GOA单元，奇数级的GOA单元的第一时钟信号端CLKA输入第七时钟信号CLK7，第二时钟信号端CLKB输入第八时钟信号CLK8，第1级GOA单元的信号输入端INPUT输入第五帧起始信号STV5。这里CLK7和CLK8为一对反相的时钟信号，即CLK7和CLK8的相位差为180°。例如：CLK7和CLK8占空比相同(示例性的占空比均为50％)、频率相同、相位差为180°。两个相邻的奇数级的GOA单元中一个GOA单元的第一时钟信号端CLKA输入的时钟信号与另一个GOA单元的第一时钟信号端CLKA输入的时钟信号相位相反(即存在180°相位差)。偶数级的GOA单元的第一时钟信号端CLKA输入第九时钟信号CLK9、第二时钟信号端CLKB输入第十时钟信号CLK10，第2级GOA单元的信号输入端INPUT输入第六帧起始信号STV6。此处，CLK9和CLK10为一对反相的时钟信号，即CLK9和CLK10的相位差为180°。例如：CLK9和CLK10占空比相同(示例性的占空比均为50％)、频率相同、相位差为180°。两个相邻的偶数级的GOA单元中一个GOA单元的第一时钟信号端CLKA输入的时钟信号与另一个GOA单元的第一时钟信号端CLKA输入的时钟信号相位相反(即存在180°相位差)。
此外，参照图10所示，第二栅极驱动单元13中对于奇数级的GOA单元，在本级输出过程中，上拉单元41中的各个晶体管为导通状态，下拉单元42中的各个晶体管为截止状态；复位单元43中的各个晶体管 为截止状态，输出单元45和闲置输出单元44中的各个晶体管的导通状态。类似于第一栅极驱动单元12中的偶数级的GOA单元，第二栅极驱动单元13中的奇数级GOA单元输出多脉冲信号，通过逻辑反相单元NG进行180°反相处理后作为第(m+1)/2行像素单元的栅极驱动信号Gate2，其中m为奇数。在本级非输出过程中，上拉单元41中的各个晶体管为截止状态，下拉单元42中的各个晶体管为导通状态；复位单元43中的各个晶体管为导通状态，输出单元45和闲置输出单元44中的各个晶体管的截止状态。此时，输出单元45的OUT端不输出，闲置输出单元44的COUT端也不输出。
第二栅极驱动单元13中对于偶数级的GOA单元，在本级输出过程中，上拉单元41中的各个晶体管为导通状态，下拉单元42中的各个晶体管为截止状态；复位单元43中的各个晶体管为截止状态，输出单元45和闲置输出单元44中的各个晶体管的导通状态。第二栅极驱动单元13中的偶数级的GOA单元通过COUT端为相邻的上一级偶数级的GOA单元提供复位端RESET输入的复位信号，该复位信号可以为单脉冲信号，第3级GOA单元(S/R2-1)，类似于第一栅极驱动单元12中的奇数级的GOA单元，这里不再赘述。在本级非输出过程中，上拉单元41中的各个晶体管为截止状态，下拉单元42中的各个晶体管为导通状态；复位单元43中的各个晶体管为导通状态，输出单元45和闲置输出单元44中的各个晶体管的截止状态。此时，输出单元45的OUT端不输出，闲置输出单元44的COUT端也不输出。
当然上述图7、8、9、10提供的第一栅极驱动单元12生成的第一栅极驱动信号和第二栅极驱动单元13生成的第二栅极驱动信号的时序状态只是一种可能的实现形式，在调整输入GOA单元的时钟信号和帧起始信号时还能产生其他时序状态的第一栅极驱动信号和第二栅极驱动信号输出，这里不做具体限定。
图11示出本公开的实施例提供的一种显示电路的驱动方法流程示意图。参照图11所示，本公开的实施例提供一种显示电路的驱动方法，包括如下步骤：
在步骤101中，通过第一栅极驱动单元向像素单元输入第一栅极驱动信号；
在步骤102中，通过第二栅极驱动单元向所述像素单元输入第二栅极驱动信号；
在步骤103中通过所述第一栅极驱动信号和所述第二栅极驱动信号控制所述像素单元同时进行阈值补偿和灰阶显示。
可选地，所述第一栅极驱动信号和所述第二栅极驱动信号为多脉冲信号。可选地，所述第一栅极驱动信号为包含至少两种脉冲宽度的脉冲信号，和/或所述第二栅极驱动信号为包含至少两种脉冲宽度的脉冲信号。
上述实施例中，通过第一栅极驱动单元向像素单元输入第一栅极驱动信号；通过第二栅极驱动单元向所述像素单元输入第二栅极驱动信号；通过所述第一栅极驱动信号和所述第二栅极驱动信号控制所述像素单元同时进行阈值补偿和灰阶显示。由于像素单元的阈值补偿和灰阶显示可以在两个栅极驱动单元的信号控制下同时进行，因此能够降低显示电路的设计复杂度，有利于提高显示面板的像素密度，从而提高显示面板的分辨率。
本公开的实施例还提供一种显示装置，包括：上述的任一显示电路。其中，显示电路，包括像素单元、第一栅极驱动单元和第二栅极驱动单元。该显示装置可以为电子纸、手机、电视、数码相框等等显示设备。
以上所述，仅为本公开的具体实施方式，本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。
本申请要求于2014年10月17日递交的中国专利申请第201410554799.9号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (17)

  1. 一种显示电路，包括像素单元、第一栅极驱动单元和第二栅极驱动单元；
    其中，所述第一栅极驱动单元用于向所述像素单元输入第一栅极驱动信号；
    所述第二栅极驱动单元用于向所述像素单元输入第二栅极驱动信号；
    所述像素单元用于在所述第一栅极驱动信号和所述第二栅极驱动信号的控制下同时进行阈值补偿和灰阶显示。
  2. 根据权利要求1所述的显示电路，其中，所述第一栅极驱动单元包括：至少三个GOA单元，每个所述GOA单元包括：信号输入端、输出端、复位端和闲置输出端；
    第1级GOA单元的信号输入端输入第一帧起始信号，第1级GOA单元的复位端连接第3级GOA单元的闲置输出端；
    第2级GOA单元的信号输入端输入第二帧起始信号；
    第2n级GOA单元的复位端连接第2n-1级GOA单元的闲置输出端和第2n+1级GOA单元的信号输入端；
    第2n+1级GOA单元的复位端连接第2n+3级GOA单元的闲置输出端；
    第2n+2级GOA单元的信号输入端连接第2n-2级GOA单元的闲置输出端；
    所述第2n级GOA单元的输出端和第2n+1级GOA单元的输出端通过逻辑或单元向第n行像素单元输出所述第一栅极驱动信号，其中，n为正整数。
  3. 根据权利要求1所述的显示电路，其中，所述第二栅极驱动单元包括：至少三个GOA单元，每个所述GOA单元包括：信号输入端、输出端、复位端和闲置输出端；
    第1级GOA单元的信号输入端输入第三帧起始信号，第1级GOA单元的复位端连接第3级GOA单元的闲置输出端；
    第2级GOA单元的信号输入端输入第四帧起始信号；
    第2n级GOA单元的复位端连接第2n-1级GOA单元的闲置输出端和第2n+1级GOA单元的信号输入端；
    第2n+1级GOA单元的复位端连接第2n+3级GOA单元的闲置输出端；
    第2n+2级GOA单元的信号输入端连接第2n-2级GOA单元的闲置输出端；
    所述第2n级GOA单元的输出端和第2n+1级GOA单元的输出端连接至逻辑或单元的输入端，所述逻辑或单元的输出端连接至逻辑反向单元的输入端，所述逻辑反向单元的输出端输出所述第二栅极驱动信号，其中，n为正整数。
  4. 根据权利要求1所述的显示电路，其中，所述第二栅极驱动单元包括：至少两个GOA单元，每个所述GOA单元包括：信号输入端、输出端、复位端和闲置输出端；
    除第1级GOA单元和第2级GOA单元外，第m级GOA单元单元的信号输入端连接第m-2级GOA单元的闲置输出端；第m级GOA单元单元的复位端连接第m+1级GOA单元的闲置输出端；第m+1级GOA单元的信号输入端连接第m-1级GOA单元的闲置输出端；第m+1级GOA单元的信号复位端连接第m+3级GOA单元的闲置输出端；
    第1级GOA单元的复位端连接第2级GOA单元的闲置输出端；第2级GOA单元的复位端连接第4级GOA单元的闲置输出端；
    第1级GOA单元的信号输入端输入第五帧起始信号，第2级GOA单元的信号输入端输入第六帧起始信号；
    第m级GOA单元的输出端通过逻辑反向单元向第(m+1)/2行像素单元输出所述第二栅极驱动信号，m为奇数。
  5. 根据权利要求2-4任一项所述的显示电路，其中，所述GOA单元包括：上拉单元、下拉单元、复位单元、闲置输出单元和输出单元；
    所述上拉单元连接信号输入端、第一电平端、第一时钟信号端、第二时钟信号端、第一节点、第二节点、第三节点和第四节点，用于在所述信号输入端、第一电平端、第一时钟信号端和第二时钟信号端的信号控制下将所述第一节点的电压与所述信号输入端拉齐，将所述第二节点的电压与所述信号输入端拉齐或将所述第二节点的电压与所述第四节点 的电压拉齐，将所述第三节点的电压与所述第一电平端的电压拉齐，将所述第四节点的电压与所述第一时钟信号端的电压拉齐；
    所述下拉单元连接第二电平端、第三电平端、所述闲置输出端、所述输出端、第一节点、第二节点、第三节点和第四节点，用于在所述第一节点的信号控制下将所述第三节点的电压与所述第二电平端拉齐，在所述第三节点的信号控制下将所述第一节点及所述第二节点的电压与所述第二电平端拉齐，在所述第三节点的信号控制下将所述重置输出端的电压与所述第二电平端拉齐，在所述第三节点的信号控制下将所述输出端的电压与所述第三电平端拉齐，在所述第三节点的信号控制下将所述第四节点的电压与所述第三电平端拉齐；
    所述复位单元连接复位端，第二电平端、第一节点和第二节点，用于在所述复位端的信号控制下将所述第一节点及第二节点的电压与所述第二电平端拉齐；
    所述闲置输出单元连接第一节点、第二时钟信号端和闲置输出端，用于在所述第一节点的控制下在所述闲置输出端输出所述第二时钟信号端的信号；
    所述输出单元连接第一节点、第二时钟信号端和输出端，用于在所述第一节点的控制下在所述输出端输出所述第二时钟信号端的信号。
  6. 根据权利要求5所述的显示电路，其中，所述闲置输出单元包括：第一晶体管，所述第一晶体管的栅极连接第一节点，所述第一晶体管的源极连接第二时钟信号端，所述第一晶体管的漏极连接所述闲置输出端。
  7. 根据权利要求5所述的显示电路，其中，所述上拉单元包括：第四晶体管、第六晶体管、第七晶体管、第十一晶体管、第十四晶体管；
    所述第四晶体管的栅极和源极连接第一电平端，所述第四晶体管的漏极连接第二节点；
    所述第六晶体管的栅极和源极连接所述信号输入端，所述第六晶体管的漏极第二节点；
    所述第七晶体管的栅极连接所述第一节点，所述第七晶体管的源极连接所述第二时钟信号端，所述第七晶体管的漏极连接第四节点；
    所述第十一晶体管的栅极连接所述栅极连接所述闲置输出端，所述第十一晶体管的源极连接所述第二节点，所述第十一晶体管的漏极连接所述第四节点；
    所述第十四晶体管的栅极连接第一时钟信号端，所述第十四晶体管的源极连接所述第二节点，所述第十四晶体管的漏极连接所述第一节点。
  8. 根据权利要求5所述的显示电路，其中，所述下拉单元包括：第二晶体管、第三晶体管、第五晶体管、第八晶体管、第十晶体管和第十三晶体管；
    所述第二晶体管的栅极连接第三节点，所述第二晶体管的源极连接所述闲置输出端，所述第二晶体管的漏极连接第二电平端；
    所述第三晶体管的栅极连接所述第一节点，所述第三晶体管的源极连接所述第三节点，所述第三晶体管的漏极连接所述第二电平端；
    所述第五晶体管的栅极连接所述第三节点，所述第五晶体管的源极连接所述第一节点，所述第五晶体管的漏极连接所述第二节点；
    所述第八晶体管的栅极连接所述第三节点，所述第八晶体管的源极连接所述第四节点，所述第八晶体管的漏极连接第三电平端；
    所述第十晶体管的栅极连接所述第三节点，所述第十晶体管的源极连接所述输出端，所述第十晶体管的漏极连接所述第三电平端；
    所述第十三晶体管的栅极连接所述第三节点，所述第十三晶体管的源极连接所述第二节点，所述第十三晶体管的漏极连接所述第二电平端。
  9. 根据权利要求5所述的显示电路，其中，所述复位单元包括：第十二晶体管和第十五晶体管，其中：
    所述第十二晶体管的栅极连接所述复位端，所述第十二晶体管的源极连接所述第一节点，所述第十二晶体管的漏极连接所述第二节点；
    所述第十五晶体管的栅极连接所述复位端，所述第十五晶体管的源极连接所述第二节点，所述第十五晶体管的漏极连接所述第二电平端。
  10. 根据权利要求5所述的显示电路，其中，所述输出单元包括第九晶体管，所述第九晶体管的栅极连接所述第一节点，所述第九晶体管的源极连接所述第二时钟信号端，所述第九晶体管的漏极连接所述输出端。
  11. 根据权利要求2所述的显示电路，其中，所述第一帧起始信号为单脉冲信号，所述第二帧起始信号为多脉冲信号；
    或者，所述第二帧起始信号为单脉冲信号，所述第二帧起始信号的脉冲宽度包含输入所述第一栅极驱动单元的时钟信号的至少两个时钟周期。
  12. 根据权利要求3所述的显示电路，其中，所述第三帧起始信号为单脉冲信号，所述第四帧起始信号为多脉冲信号；
    或者，所述第四帧起始信号为单脉冲信号，所述第四帧起始信号的脉冲宽度包含输入所述第二栅极驱动单元的时钟信号的至少两个时钟周期。
  13. 根据权利要求4所述的显示电路，其中，所述第五帧起始信号为多脉冲信号，所述第六帧起始信号为单脉冲信号；
    或者，所述第五帧起始信号为单脉冲信号，所述第五帧起始信号的脉冲宽度包含输入所述第一栅极驱动单元的时钟信号的至少两个时钟周期。
  14. 一种显示电路的驱动方法，包括下列步骤：
    通过第一栅极驱动单元向像素单元输入第一栅极驱动信号；
    通过第二栅极驱动单元向所述像素单元输入第二栅极驱动信号；
    通过所述第一栅极驱动信号和所述第二栅极驱动信号控制所述像素单元同时进行阈值补偿和灰阶显示。
  15. 根据权利要求14所述的方法，其中，所述第一栅极驱动信号和所述第二栅极驱动信号为多脉冲信号。
  16. 根据权利要求14所述的方法，其中，所述第一栅极驱动信号为包含至少两种脉冲宽度的脉冲信号，和/或所述第二栅极驱动信号为包含至少两种脉冲宽度的脉冲信号。
  17. 一种显示装置，包括：如权利要求1-13任一项所述的显示电路。
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