WO2016065817A1 - 移位寄存器单元电路、移位寄存器、驱动方法及显示装置 - Google Patents

移位寄存器单元电路、移位寄存器、驱动方法及显示装置 Download PDF

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Publication number
WO2016065817A1
WO2016065817A1 PCT/CN2015/074852 CN2015074852W WO2016065817A1 WO 2016065817 A1 WO2016065817 A1 WO 2016065817A1 CN 2015074852 W CN2015074852 W CN 2015074852W WO 2016065817 A1 WO2016065817 A1 WO 2016065817A1
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Prior art keywords
terminal
transistor
storage capacitor
clock
low level
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PCT/CN2015/074852
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English (en)
French (fr)
Inventor
王峥
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to EP15763474.2A priority Critical patent/EP3040981A4/en
Priority to US14/778,072 priority patent/US20160293091A1/en
Publication of WO2016065817A1 publication Critical patent/WO2016065817A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register unit circuit, a shift register, a driving method, and a display device.
  • GOA Gate IC on Array
  • LCD liquid crystal display
  • GOA Gate IC on Array
  • the advantage of using GOA technology is that it saves costs, simplifies the back-end process of the product, and facilitates the design of the flat panel and the mechanical structure of the whole machine.
  • the biggest difficulty of GOA technology is the problem of service life, size and power consumption.
  • the present invention provides a mobile register unit circuit having low power consumption.
  • a shift register unit circuit includes: a trigger signal terminal, a first clock terminal, a second clock terminal, a reset terminal, a gate output terminal, a low-level terminal, a storage capacitor, and a reset module. a first pull-down module, a second pull-down module, a charging module, and an output control module;
  • the first input end and the first control end of the charging module are connected to the trigger signal end, and the first output end is connected to the first end of the storage capacitor for storing when the trigger signal end is high level
  • the second input end is connected to the first end of the storage capacitor, the second control end is connected to the first clock end, and the second output end is connected to the trigger signal end for being high level at the first clock end and Pulling the first end of the storage capacitor to a low level when the trigger signal terminal is low;
  • the input end of the output control module is connected to the second clock end, the control end is connected to the first end of the storage capacitor, and the output end is connected to the gate output end for being high at the first end of the storage capacitor Level-level outputting a high-level signal of the second clock terminal to the gate output terminal, causing the gate output terminal to be a high level; and connecting a second end of the storage capacitor to the gate output terminal;
  • the first control end of the first pull-down module is connected to the first clock end, the first input end is connected to the gate output end, the first output end is connected to the low-level end, and the second control end is connected to the first of the storage capacitor
  • the second input end is connected to the first clock end, the second output end is connected to the low level end
  • the input end of the second pull-down module is connected to the gate output end, and the control end is connected to the intermediate control node in the first pull-down module, and the output end is Connecting a first end of the storage capacitor
  • the first pull-down module is configured to pull the gate output to a low level, and pass the middle when the first end of the storage capacitor is low
  • the control node triggers the second pull-down module to pull both ends of the storage capacitor to a low level
  • the input end of the reset module is connected to the first end of the storage capacitor, the control end is connected to the reset end, and the output end is connected to the gate output end for pulling the two ends of the storage capacitor to a low level under the control of the reset end Level.
  • the charging module includes: a fourth transistor and a fifth transistor, wherein a gate and a source of the fourth transistor are connected to a trigger signal end, and a drain is connected to the first end of the storage capacitor, Transmitting a high level signal of the trigger signal end to a first end of the storage capacitor; a gate of the fifth transistor is connected to the first clock end, and a source is connected to a first end of the storage capacitor, The drain is connected to the trigger signal end for pulling the first end of the storage capacitor to a low level when the first clock terminal is at a high level and the trigger signal terminal is at a low level.
  • the output control module includes: a first transistor, a gate of the first transistor is connected to a first end of the storage capacitor, a source is connected to the second clock end, and a drain is connected
  • the gate output terminal is configured to output a high level signal of the second clock terminal to the gate output terminal when the first end of the storage capacitor is at a high level.
  • the first pull-down module includes: an eighth transistor, a ninth transistor, and a tenth transistor;
  • the second pull-down module includes: a third transistor and a seventh transistor;
  • a gate of the ninth transistor is connected to the first clock terminal, a drain is connected to a source of the eighth transistor, and a gate of the eighth transistor is connected to a first end of the storage capacitor.
  • a gate connected to the low-level terminal a gate of the tenth transistor connected to the first clock terminal, a source connected to the gate output terminal, and a drain connected to the low-level terminal;
  • a gate of the third transistor a pole is connected to the source of the eighth transistor, a source is connected to the gate output terminal, a drain is connected to the low voltage terminal, a gate of the seventh transistor is connected to a source of the eighth transistor, and a source is connected Low electricity a flat end, a drain connected to the first end of the storage capacitor;
  • the eighth transistor and the ninth transistor are configured to form a path from the first clock terminal to the low level end when the first end of the storage capacitor is at a high level, or be low at a first end of the storage capacitor Leveling the source of the eighth transistor to a high level to turn the third transistor and the seventh transistor on, thereby pulling both ends of the storage capacitor to a low level;
  • the tenth transistor is configured to pull the gate output to a low level when the first clock terminal is at a high level.
  • the reset module includes: a second transistor and a sixth transistor, a gate of the second transistor is connected to the reset terminal, a source is connected to the low-level end, and a drain is connected to the gate a pole output terminal, configured to pull the gate output terminal to a low level when the reset terminal is at a high level; a gate of the sixth transistor is connected to the reset terminal, and a source is connected to the first of the storage capacitor And a drain connected to the low-level terminal for pulling the first end of the storage capacitor to a low level when the reset terminal is at a high level.
  • a driving method for the above-described shift register unit circuit comprising:
  • the first clock terminal applies a high level
  • the first pull-down module pulls the gate output terminal to a low level
  • the second pull-down module Pull both ends of the storage capacitor to a low level.
  • a high level is applied to the trigger signal end and the first clock end
  • the second clock terminal and the reset terminal apply a low level, so that the charging module charges the storage capacitor
  • the step of the first pull-down module pulling the gate output terminal to a low level specifically includes:
  • a low level is applied to the trigger signal end, the first clock end and the reset end, and a high level is applied to the second clock end to keep the first end of the storage capacitor high
  • the output The step of the control module controlling the output of the second clock terminal by the gate output terminal specifically includes:
  • a high level is applied to the first clock terminal and the reset terminal
  • a low level is applied to the second clock terminal and the trigger signal terminal
  • the reset module connects the two ends of the storage capacitor and the gate
  • a low level is applied to the trigger signal terminal, the first clock terminal and the reset terminal, a high level is applied to the second clock terminal, and the second pull-down module connects the two ends of the storage capacitor
  • the step of pulling the gate output to the low level specifically includes:
  • a low level is applied to the trigger signal terminal, the second clock terminal and the reset terminal, a high level is applied to the first clock terminal, and the first pull-down module pulls the gate output terminal to a low level.
  • Level, the step of the second pull-down module pulling the two ends of the storage capacitor to a low level specifically includes:
  • a shift register comprising a cascade of the shift register unit circuits of any of the above.
  • a display device comprising the above shift register.
  • the shift register unit circuit structure according to the embodiment of the present invention includes only ten thin film transistors (TFTs), and does not repeatedly switch with the input pulse signal, thereby avoiding power loss and reducing power consumption of the entire circuit.
  • TFTs thin film transistors
  • FIG. 1 is a schematic structural diagram of a shift register unit circuit according to an embodiment of the present invention.
  • FIG. 2 is a timing chart showing the operation of a shift register unit circuit according to an embodiment of the present invention
  • FIG. 3 is a block diagram showing the structure of a shift register according to an embodiment of the present invention.
  • the shift register unit circuit 100 of the embodiment of the present invention includes: a trigger signal terminal INPUT, a first clock terminal CLKB, a second clock terminal CLK, a reset terminal REST, a gate output terminal OUT, and a low level terminal VSS. .
  • the shift register unit circuit 100 shown in FIG. 1 further includes a storage capacitor C1, a reset module 110, a first pull-down module 120, a second pull-down module 130, a charging module 140, and an output control module 150.
  • the gate line voltage is composed of a high level voltage for one line time and a low level voltage for several lines of time.
  • the high level voltage Vgh is obtained by outputting a high level signal of the clock signal in the GOA circuit
  • the low level voltage Vgl is generally obtained by outputting a VSS voltage from the GOA circuit. Therefore, in the embodiment of the present invention, the low-level terminal VSS provides a reference voltage serving as a low level, and a clock signal (a first clock signal supplied from the first clock terminal CLKB and a second clock provided from the second clock terminal CLK) The low level of the signal) is the same, that is, the gate line signal Vgl voltage.
  • the high level of the clock signal provides the gate line voltage Vgh.
  • the first input end and the first control end of the charging module 140 are connected to the trigger signal end INPUT, and the first output end is connected to the first end of the storage capacitor C1 for the trigger signal.
  • the INPUT is high, the storage capacitor C1 is charged, the second input is connected to the first end of the storage capacitor, the second control is connected to the first clock terminal CLKB, and the second output is connected to the trigger signal terminal INPUT,
  • the first end of the storage capacitor is pulled to a low level when the first clock terminal CLKB is at a high level and the trigger signal terminal INPUT is at a low level.
  • the input end of the output control module 150 is connected to the second clock end CLK, the control end is connected to the first end of the storage capacitor, and the output end is connected to the gate output end OUT for high power at the first end of the storage capacitor C1.
  • a high level signal of the second clock terminal CLK is output to the gate output terminal OUT, so that the gate output terminal OUT is at a high level; and a second end of the storage capacitor C1 is connected to the gate output End OUT.
  • the first control terminal of the first pull-down module 120 is connected to the first clock terminal CLKB, the first input terminal is connected to the gate output terminal OUT, the first output terminal is connected to the low-level terminal VSS, and the second control terminal is connected to the storage terminal.
  • the first end of the capacitor is connected to the first clock terminal CLKB, and the second output terminal is connected to the low level terminal VSS.
  • the input end of the second pull-down module 130 is connected to the gate output terminal OUT, and the control end is connected to the intermediate control node Q in the first pull-down module 120, and the output end is connected to the first end of the storage capacitor.
  • the first pull-down module 120 is configured to pull the gate output terminal OUT to a low level, and trigger the second pull-down through the intermediate control node Q when the first end of the storage capacitor C1 is at a low level.
  • the module pulls both ends of the storage capacitor C1 to a low level.
  • the input end of the reset module 110 is connected to the first end of the storage capacitor, the control end is connected to the reset end REST, the output end is connected to the gate output end OUT, and the second end of the storage capacitor C1 is connected to the gate output.
  • the terminal OUT is used to pull both ends of the storage capacitor C1 to a low level under the control of the reset terminal REST.
  • Figure 1 also shows a specific example of each module.
  • the charging module 140 includes: a fourth transistor M4 and a fifth transistor M5.
  • the gate and the source of the fourth transistor M4 are connected to the trigger signal terminal INPUT, and the drain is connected to the storage capacitor C1.
  • One end U for transmitting a high level signal of the trigger signal terminal INPUT to the first end of the storage capacitor C1;
  • the gate of the fifth transistor M5 is connected to the first clock terminal CLKB, and the source is connected to the storage
  • the first end of the capacitor C1 is connected to the trigger signal terminal INPUT for pulling the first end of the storage capacitor C1 low when the first clock terminal CLKB is at a high level and the trigger signal terminal INPUT is at a low level. Level.
  • the fourth The source, the gate and the drain of the transistor M4 respectively correspond to the first input end, the first control end and the first output end of the charging module 140
  • the source, the gate and the drain of the fifth transistor M5 respectively correspond to the charging A second input, a second control, and a second output of the module 140.
  • the output control module 150 includes: a first transistor M1, a gate of the first transistor M1 is connected to a first end of the storage capacitor C1, a source is connected to the second clock terminal CLK, and a drain connection is The gate output terminal OUT is configured to output a high level signal of the second clock terminal CLK to the gate output terminal OUT when the first end of the storage capacitor C1 is at a high level.
  • the source, the gate and the drain of the first transistor M1 correspond to the input terminal, the control terminal and the output terminal of the output control module 150, respectively.
  • the first pull-down module 120 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
  • the second pull-down module 130 includes a third transistor M3 and a seventh transistor M7.
  • a gate and a source of the ninth transistor M9 are connected to the first clock terminal CLKB, a drain is connected to a source of the eighth transistor M8, and a gate of the eighth transistor M8 is connected to the storage capacitor C1.
  • a first terminal U a drain connected to the low-level terminal VSS, a gate of the tenth transistor M10 connected to the first clock terminal CLKB, a source connected to the gate output terminal OUT, and a drain connected to the low terminal a level terminal VSS;
  • a gate of the third transistor M3 is connected to a source of the eighth transistor M8, a source is connected to the gate output terminal OUT, and a drain is connected to the low voltage terminal VSS, and the seventh transistor M7 is The gate is connected to the source of the eighth transistor M8, the source is connected to the low level terminal VSS, and the drain is connected to the first end of the storage capacitor C1.
  • the eighth transistor M8 and the ninth transistor M9 are configured to form a path from the first clock terminal CLKB to the low level terminal VSS when the first terminal of the storage capacitor C1 is at a high level, or at the storage capacitor C1
  • the source of the eighth transistor M8 ie, the intermediate control node Q
  • the third transistor M3 and the seventh transistor M7 are turned on, thereby storing the capacitor C1.
  • the two ends are pulled to a low level; and the tenth transistor M10 is for pulling the gate output terminal OUT to a low level when the first clock terminal CLKB is at a high level.
  • the source, the gate and the drain of the tenth transistor M10 respectively correspond to the first input end, the first control end and the first output end of the first pull-down module 120; the ninth transistor The source, the gate of the eighth transistor, and the drain of the eighth transistor respectively correspond to the second input terminal, the second control terminal, and the second output terminal of the first pull-down module 120.
  • the source of the third transistor M3, the gate of the third transistor M3, and the drain of the seventh transistor M7 correspond to the input terminal, the control terminal, and the output terminal of the second pull-down module 130, respectively.
  • the reset module 110 includes: a second transistor M2 and a sixth transistor M6.
  • the gate of the second transistor M2 is connected to the reset terminal REST, and the source is connected to the low-level terminal VSS and the drain. Connecting the gate output terminal OUT for pulling the gate output terminal OUT to a low level when the reset terminal REST is at a high level; the gate of the sixth transistor M6 is connected to the reset terminal REST, the source The first terminal of the storage capacitor C1 is connected to the drain, and the drain is connected to the low-level terminal VSS for pulling the first end of the storage capacitor C1 to a low level when the reset terminal REST is at a high level.
  • the source of the sixth transistor, the gate of the sixth transistor, and the drain of the second transistor respectively correspond to the input terminal, the control terminal, and the output terminal of the reset module 110.
  • each transistor is illustrated by taking an N-type transistor as an example.
  • the various modules of the present invention are not limited to the specific structure illustrated in FIG. 1, and that other types of transistors may be used.
  • FIG. 2 The working timing diagram of the gate driving circuit of this embodiment is shown in FIG. 2, and the specific working principle is as follows:
  • Stage a The INPUT signal is high, the REST and CLK are low, the CLKB is high, M4 is on, and the first end of C1 (U) is charged high, M1, M5, M8, M10 and M9 are turned on.
  • the potentials of Q and OUT are pulled low by VSS, the output of OUT is low, and M2, M3, M6 and M7 are off. This is the charging phase.
  • Phase b The CLK terminal is high, the INPUT terminal, the REST terminal, and the CLKB terminal are both low. Since the first end (U point) of C1 maintains the high level of phase a, M1 and M8 are still on, Q The point is still low, the U point is raised due to the coupling of the CLK terminal, and the OUT terminal outputs the high level of the CLK terminal. M2, M3, M4, M5, M6, M7, M9, and M10 are all off. This is the output stage.
  • Phase c INPUT terminal and CLK terminal are low level, CLKB terminal and REST terminal are high level. At this time, M6, M2, M5, M9 and M10 are turned on, and since M2 and M10 are turned on, OUT is pulled to a low level. That is, the OUT output is low. Since the INPUT terminal is low, the U point is pulled Low, causing Q to be charged high, so M7 and M3 are turned on, and both U and OUT are connected to VSS. Since the voltage at VSS is the same as the gate voltage Vgl of GOA, the OUT and VSS are connected. Connected to stabilize the gate line voltage Vgl, M1, M4, M7 and M8 are off. This is the reset phase.
  • Phase d The INPUT, CLKB, and REST signals are low, and the CLK terminal is high. At this stage, the Q voltage remains in a high state due to the non-discharged path, except for M3 and M7. When turned on, M1, M2, M4, M5, M6, M8, M9, and M10 are all off. The opening of M7 and M3 respectively makes the U point and the OUT end continuously connected with the VSS line to stabilize the gate line voltage Vgl, and the OUT output is low level. This is the first stable phase.
  • Stage e INPUT, CLK and REST signals are low, CLKB is high, M5, M9 and M10 are on, Q is still high, and Q3 control M3 and M7 remain The on state, where M10 and M3 connect the OUT terminal to VSS, and M5 and M7 connect the U point to VSS to keep the gate line voltage stable. M1, M2, M4, M6, and M8 are off. This is the second stable phase.
  • the INPUT terminal and the REST terminal signal are always low in the subsequent timing, and the CLK terminal and the CLKB terminal are alternately high and low, that is, the repetition of the d phase and the e phase, which will not be described herein.
  • the shift register unit circuit structure of the present invention only includes 10 thin film transistors (TFTs), and does not repeatedly switch with the input pulse signal, thereby avoiding power loss and reducing power consumption of the entire circuit.
  • the ninth transistor that is, the M9 diode of FIG. 1 (the M9 gate and source are connected together) structure, uses a diode characteristic to form a DC-like waveform at the Q point (the waveform of the Q point in FIG. 2), and does not become The wave shape further reduces the power consumption of the circuit, and the shift register unit circuit of the present invention has only 10 transistors, and the product size can be made smaller.
  • the present invention also provides a driving method for the above shift register unit circuit, comprising:
  • Phase 1 applying a high level to the trigger signal end and the first clock end, applying a low level to the second clock end and the reset end, so that the charging module charges the storage capacitor, and the first pull-down module will apply the gate
  • the pole output is pulled low.
  • the fourth transistor when a high level is applied to the trigger signal terminal and the first clock terminal, and a low level is applied to the second clock terminal and the reset terminal, the fourth transistor is turned on, and the storage capacitor is turned on.
  • the first end (U point) is charged to a high level, the first crystal
  • the transistor and the tenth transistor are turned on to pull the gate output to a low level.
  • Phase 2 applying a low level to the trigger signal end, the first clock end and the reset end, and applying a high level to the second clock end to keep the first end of the storage capacitor high, the output control module controlling the The gate output terminal outputs a high level of the second clock terminal.
  • the first end of the storage capacitor remains at a high level.
  • the first transistor is turned on, so that the gate output terminal outputs a high level of the second clock terminal.
  • Phase 3 applying a high level to the first clock terminal and the reset terminal, and applying a low level to the second clock terminal and the trigger signal terminal, the reset module pulling the two ends of the storage capacitor and the gate output terminal to Low level.
  • the reset module pulling the two ends of the storage capacitor and the gate output terminal to Low level.
  • the second transistor and the sixth transistor are turned on. Pulling both ends of the storage capacitor and the gate output to a low level.
  • Phase 4 applying a low level to the trigger signal terminal, the first clock terminal and the reset terminal, and applying a high level to the second clock terminal, the second pull-down module connecting the two ends of the storage capacitor and the gate output terminal Pull down to low level.
  • the third transistor and the seventh transistor are turned on. Pulling both ends of the storage capacitor and the gate output to a low level.
  • Phase 5 applying a low level to the trigger signal terminal, the second clock terminal, and the reset terminal, and applying a high level to the first clock terminal, and the first pull-down module pulls the gate output terminal to a low level
  • the two pull-down modules pull both ends of the storage capacitor to a low level.
  • the tenth transistor is turned on, and the The gate output is pulled down to a low level, and the third transistor and the seventh transistor are turned on to pull both ends of the storage capacitor to a low level.
  • the present invention also provides a shift register comprising a plurality of the above-described shift register unit circuits cascaded.
  • FIG. 3 shows a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • a shift register according to an embodiment of the present invention includes a plurality of cascaded shift register unit circuits, wherein a trigger signal end of the first stage shift register unit circuit is connected to the input signal terminal, and receives a trigger signal STV, wherein In any two adjacent shift register unit circuits other than the stage and last stage shift register unit circuits, the gate output terminal of the shift register unit circuit of the previous stage is connected to the next The trigger signal terminal of the stage shift register unit circuit; the first clock terminal of each stage shift register unit circuit receives the first clock signal, the second clock terminal receives the second clock signal, the low voltage terminal receives the low voltage signal, and the reset terminal receives Reset signal.
  • a gate line is connected to the gate output of each stage of the shift register unit circuit to provide a switching signal for the switch in the pixel unit connected to the gate line.
  • the shift register shown in FIG. 3 includes a plurality of cascaded shift register unit circuits SR1, SR2, SR3, SR4, ..., wherein the gate output terminal OUTPUT of the first stage shift register unit circuit SR1
  • the trigger signal terminal INPUT of the second stage shift register unit circuit SR2 is connected and connected to the gate line G1; the gate output terminal OUTPUT of the second stage shift register unit circuit SR2 is connected to the trigger signal end of the third stage shift register unit circuit SR3.
  • each shift register unit circuit has two clock terminals and a low voltage terminal.
  • the first clock terminal of each shift register unit circuit is connected to the first clock signal input terminal CLK1, and the second clock.
  • the terminal is connected to the second clock signal input terminal CLK2, and the low voltage terminal is connected to the low voltage input terminal VSS.
  • the reset terminal of each stage of the shift register unit circuit receives a reset signal. For example, as shown in FIG.
  • the reset signal can be obtained by delaying the output signal of the gate output terminal of the shift register unit circuit of the stage by a falling edge triggered one-shot by one cycle.
  • other methods of providing a reset signal are also possible. The invention is not limited to this.
  • the present invention also provides a display device including the above shift register, which may be: a liquid crystal panel, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Functional product or part.
  • a display device including the above shift register, which may be: a liquid crystal panel, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Functional product or part.

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Abstract

一种移位寄存器单元电路（100），包括：触发信号端（INPUT）、第一时钟端（CLKB）、第二时钟端（CLK）、复位端（REST）、栅极输出端（OUT）、低电平端（VSS）、存储电容（C1）、复位模块（110）、第一下拉模块（120）、第二下拉模块（130）、充电模块（140）、输出控制模块（150）。还公开了一种移位寄存器、驱动方法及显示装置。该移位寄存器单元电路（100）避免了功耗损失，降低了整个电路的功耗。

Description

移位寄存器单元电路、移位寄存器、驱动方法及显示装置 技术领域
本发明涉及显示技术领域，特别涉及一种移位寄存器单元电路、移位寄存器、驱动方法及显示装置。
背景技术
随着液晶显示器(LCD)技术的发展，周边电路小型化、集成化逐渐成为了市场的主流技术。其中GOA(Gate IC on Array，即将Gate IC的移位寄存器电路做在阵列面板上)技术已比较成熟，且各厂商所采用的结构均不相同。使用GOA技术的好处就是节省了成本，简化了产品后端工艺流程，方便了面板纯平再在整机端机械结构上的设计。而GOA技术最大的难点在于使用寿命、尺寸以及功耗等问题。
发明内容
为解决现有技术存在的技术问题，本发明提供了一种具有低功耗的移动寄存器单元电路。
根据本发明的一个方面，提供了一种移位寄存器单元电路，包括：触发信号端、第一时钟端、第二时钟端、复位端、栅极输出端、低电平端、存储电容、复位模块、第一下拉模块、第二下拉模块、充电模块和输出控制模块；
所述充电模块的第一输入端和第一控制端均连接所述触发信号端，第一输出端连接所述存储电容的第一端，用于在所述触发信号端为高电平时为存储电容充电；第二输入端连接所述存储电容的第一端，第二控制端连接第一时钟端，第二输出端连接触发信号端，用于在所述第一时钟端为高电平且触发信号端为低电平时将所述存储电容的第一端拉至低电平；
所述输出控制模块的输入端连接第二时钟端，控制端连接所述存储电容的第一端，输出端连接栅极输出端，用于在所述存储电容的第一端为高 电平时将第二时钟端的高电平信号输出至所述栅极输出端，使所述栅极输出端为高电平；所述存储电容的第二端连接所述栅极输出端；
所述第一下拉模块的第一控制端连接于第一时钟端，第一输入端连接栅极输出端，第一输出端连接低电平端；第二控制端连接所述存储电容的第一端，第二输入端连接第一时钟端，第二输出端连接低电平端；第二下拉模块的输入端连接栅极输出端，控制端连接第一下拉模块中的中间控制节点，输出端连接所述存储电容的第一端；所述第一下拉模块用于将所述栅极输出端拉至低电平，并在所述存储电容的第一端为低电平时通过所述中间控制节点触发所述第二下拉模块将所述存储电容两端均拉至低电平；
所述复位模块的输入端连接所述存储电容的第一端，控制端连接所述复位端，输出端连接栅极输出端，用于在复位端的控制下将所述存储电容两端拉至低电平。
根据本发明的实施例，所述充电模块包括：第四晶体管和第五晶体管，所述第四晶体管的栅极和源极连接触发信号端，漏极连接所述存储电容的第一端，用于将所述触发信号端的高电平信号传输至所述存储电容的第一端；所述第五晶体管的栅极连接所述第一时钟端，源极连接所述存储电容的第一端，漏极连接所述触发信号端，用于在第一时钟端为高电平且触发信号端为低电平时，将所述存储电容的第一端拉至低电平。
根据本发明的实施例，所述输出控制模块包括：第一晶体管，所述第一晶体管的栅极连接所述存储电容的第一端，源极连接所述第二时钟端，漏极连接所述栅极输出端，用于在所述存储电容的第一端为高电平时，将所述第二时钟端的高电平信号输出至所述栅极输出端。
根据本发明的实施例，所述第一下拉模块包括：第八晶体管、第九晶体管和第十晶体管；所述第二下拉模块包括：第三晶体管和第七晶体管；
所述第九晶体管的栅极和源极连接所述第一时钟端，漏极连接所述第八晶体管的源极，所述第八晶体管的栅极连接所述存储电容的第一端，漏极连接所述低电平端，所述第十晶体管的栅极连接所述第一时钟端，源极连接所述栅极输出端，漏极连接所述低电平端；所述第三晶体管的栅极连接所述第八晶体管的源极，源极连接所述栅极输出端，漏极连接所述低电压端，第七晶体管的栅极连接所述第八晶体管的源极，源极连接所述低电 平端，漏极连接所述存储电容的第一端；
所述第八晶体管和第九晶体管用于在所述存储电容的第一端为高电平时，形成从第一时钟端到低电平端的通路，或者在所述存储电容的第一端为低电平时使第八晶体管的源极变为高电平，以使所述第三晶体管和第七晶体管打开，从而将存储电容的两端拉至低电平；
并且第十晶体管用于在所述第一时钟端为高电平时将所述栅极输出端拉至低电平。
根据本发明的实施例，所述复位模块包括：第二晶体管和第六晶体管，所述第二晶体管的栅极连接所述复位端，源极连接所述低电平端，漏极连接所述栅极输出端，用于在复位端为高电平时将所述栅极输出端拉至低电平；所述第六晶体管的栅极连接所述复位端，源极连接所述存储电容的第一端，漏极连接所述低电平端，用于在复位端为高电平时将所述存储电容的第一端拉至低电平。
根据本发明的另一方面，还提供了一种用于上述的移位寄存器单元电路的驱动方法，包括：
对所述触发信号端和第一时钟端施加高电平，第二时钟端和复位端施加低电平，使所述充电模块为存储电容充电，第一下拉模块将所述栅极输出端下拉至低电平；
对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，使存储电容的第一端保持高电平，所述输出控制模块控制所述栅极输出端输出第二时钟端的高电平；
对所述第一时钟端和复位端施加高电平，第二时钟端和触发信号端施加低电平，所述复位模块将所述存储电容的两端和栅极输出端拉至低电平；
对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，所述第二下拉模块将所述存储电容的两端和栅极输出端下拉至低电平；
对所述触发信号端、第二时钟端和复位端施加低电平，第一时钟端施加高电平，第一下拉模块将所述栅极输出端下拉至低电平，第二下拉模块将所述存储电容的两端下拉至低电平。
根据本发明的实施例，对所述触发信号端和第一时钟端施加高电平， 第二时钟端和复位端施加低电平，使所述充电模块为存储电容充电，所述第一下拉模块将所述栅极输出端下拉至低电平的步骤具体包括：
对所述触发信号端和第一时钟端施加高电平，第二时钟端和复位端施加低电平，第四晶体管导通，将存储电容的第一端充电为高电平，第一晶体管和第十晶体管导通，将所述栅极输出端下拉至低电平。
根据本发明的实施例，对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，使存储电容的第一端保持高电平，所述输出控制模块控制所述栅极输出端输出第二时钟端的高电平的步骤具体包括：
对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，存储电容第一端保持高电平，第一晶体管导通，使栅极输出端输出第二时钟端的高电平。
根据本发明的实施例，对所述第一时钟端和复位端施加高电平，第二时钟端和触发信号端施加低电平，所述复位模块将所述存储电容的两端和栅极输出端拉至低电平的步骤具体包括：
对所述第一时钟端和复位端施加高电平，第二时钟端和触发信号端施加低电平，第二晶体管和第六晶体管导通，将所述存储电容的两端和栅极输出端拉至低电平。
根据本发明的实施例，对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，所述第二下拉模块将所述存储电容的两端和栅极输出端下拉至低电平的步骤具体包括：
对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，第三晶体管和第七晶体管导通，将所述存储电容的两端和栅极输出端下拉至低电平。
根据本发明的实施例，对所述触发信号端、第二时钟端和复位端施加低电平，第一时钟端施加高电平，第一下拉模块将所述栅极输出端下拉至低电平，第二下拉模块将所述存储电容的两端下拉至低电平的步骤具体包括：
对所述触发信号端、第二时钟端和复位端施加低电平，第一时钟端施加高电平，第十晶体管导通，将所述栅极输出端下拉至低电平，第三晶体 管和第七晶体管导通，将存储电容的两端下拉至低电平。
根据本发明的又一方面，还提供了一种移位寄存器，包括级联的若干上述任一项所述的移位寄存器单元电路。
根据本发明的另一方面，还提供了一种显示装置，包括上述的移位寄存器。
根据本发明实施例的移位寄存器单元电路结构只包含10个薄膜晶体管(TFT)，且不会随输入的脉冲信号反复的开关，从而避免了功耗损失，降低了整个电路的功耗。
附图说明
图1是本发明实施例的移位寄存器单元电路的结构示意图；
图2是根据本发明实施例的移位寄存器单元电路的工作时序图；以及
图3是根据本发明实施例的移位寄存器的结构示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
本发明实施例的移位寄存器单元电路100如图1所示，包括：触发信号端INPUT、第一时钟端CLKB、第二时钟端CLK、复位端REST、栅极输出端OUT、低电平端VSS。如图1所示的移位寄存器单元电路100还包括：存储电容C1、复位模块110、第一下拉模块120、第二下拉模块130、充电模块140和输出控制模块150。
在GOA中，栅线电压是由一行时间的高电平电压和若干行时间的低电平电压组成。高电平电压Vgh是将GOA电路中的时钟信号的高电平信号输出得到，而低电平电压Vgl一般是从GOA电路中输出VSS电压得到。因此，在本发明的实施例中，低电平端VSS提供用作低电平的基准电压，与时钟信号(第一时钟端CLKB提供的第一时钟信号和第二时钟端CLK提供的第二时钟信号)的低电平相同，也就是栅线信号Vgl电压。时钟信号的高电平提供栅线电压Vgh。
所述充电模块140的第一输入端和第一控制端均连接所述触发信号端INPUT，第一输出端连接所述存储电容C1的第一端，用于在所述触发信 号端INPUT为高电平时为存储电容C1充电，第二输入端连接所述存储电容的第一端，第二控制端连接第一时钟端CLKB，第二输出端连接触发信号端INPUT，用于在所述第一时钟端CLKB为高电平且触发信号端INPUT为低电平时将所述存储电容的第一端拉至低电平。
所述输出控制模块150的输入端连接第二时钟端CLK，控制端连接所述存储电容的第一端，输出端连接栅极输出端OUT，用于在存储电容C1的第一端为高电平时将第二时钟端CLK的高电平信号输出至所述栅极输出端OUT，使所述栅极输出端OUT为高电平；所述存储电容C1的第二端连接所述栅极输出端OUT。
所述第一下拉模块120的第一控制端连接于第一时钟端CLKB，第一输入端连接栅极输出端OUT，第一输出端连接低电平端VSS；第二控制端连接所述存储电容的第一端，第二输入端连接第一时钟端CLKB，第二输出端连接低电平端VSS。
所述第二下拉模块130的输入端连接栅极输出端OUT，控制端连接第一下拉模块120中的中间控制节点Q，输出端连接所述存储电容的第一端。
所述第一下拉模块120用于将所述栅极输出端OUT拉至低电平，并在所述存储电容C1的第一端为低电平时通过中间控制节点Q触发所述第二下拉模块将所述存储电容C1两端均拉至低电平。
所述复位模块110的输入端连接所述存储电容的第一端，控制端连接所述复位端REST，输出端连接栅极输出端OUT，由于存储电容C1的第二端连接所述栅极输出端OUT，所述复位模块110用于在复位端REST的控制下将所述存储电容C1两端拉至低电平。
图1还示出了各个模块的一个具体示例。
本实施例中，所述充电模块140包括：第四晶体管M4和第五晶体管M5，所述第四晶体管M4的栅极和源极连接触发信号端INPUT，漏极连接所述存储电容C1的第一端U，用于将所述触发信号端INPUT的高电平信号传输至所述存储电容C1的第一端；第五晶体管M5的栅极连接第一时钟端CLKB，源极连接所述存储电容C1的第一端，漏极连接触发信号端INPUT，用于在第一时钟端CLKB为高电平且触发信号端INPUT为低电平时，将所述存储电容C1的第一端拉至低电平。在本实施例中，第四 晶体管M4的源极、栅极和漏极分别对应于充电模块140的第一输入端、第一控制端和第一输出端，第五晶体管M5的源极、栅极和漏极分别对应于充电模块140的第二输入端、第二控制端和第二输出端。
本实施例中，所述输出控制模块150包括：第一晶体管M1，所述第一晶体管M1的栅极连接存储电容C1的第一端，源极连接所述第二时钟端CLK，漏极连接所述栅极输出端OUT，用于在所述存储电容C1的第一端为高电平时，将所述第二时钟端CLK的高电平信号输出至所述栅极输出端OUT。在本实施例中，第一晶体管M1的源极、栅极和漏极分别对应于输出控制模块150的输入端、控制端和输出端。
本实施例中，所述第一下拉模块120包括：第八晶体管M8、第九晶体管M9和第十晶体管M10。
本实施例中，所述第二下拉模块130包括：第三晶体管M3和第七晶体管M7。
所述第九晶体管M9的栅极和源极连接所述第一时钟端CLKB，漏极连接所述第八晶体管M8的源极，所述第八晶体管M8的栅极连接所述存储电容C1的第一端U，漏极连接所述低电平端VSS，所述第十晶体管M10的栅极连接所述第一时钟端CLKB，源极连接所述栅极输出端OUT，漏极连接所述低电平端VSS；所述第三晶体管M3的栅极连接所述第八晶体管M8的源极，源极连接所述栅极输出端OUT，漏极连接所述低电压端VSS，第七晶体管M7的栅极连接所述第八晶体管M8的源极，源极连接所述低电平端VSS，漏极连接所述存储电容C1的第一端。
所述第八晶体管M8和第九晶体管M9用于在所述存储电容C1的第一端为高电平时，形成从第一时钟端CLKB到低电平端VSS的通路，或者在所述存储电容C1的第一端为低电平时使第八晶体管M8的源极(即中间控制节点Q)变为高电平，以使所述第三晶体管M3和第七晶体管M7打开，从而将存储电容C1的两端拉至低电平；并且第十晶体管M10用于在所述第一时钟端CLKB为高电平时将所述栅极输出端OUT拉至低电平。
在本实施例中，第十晶体管M10的源极、栅极、漏极分别对应于第一下拉模块120的第一输入端、第一控制端和第一输出端；第九晶体管的 源极、第八晶体管的栅极和第八晶体管的漏极分别对应于第一下拉模块120的第二输入端、第二控制端和第二输出端。在本实施例中，第三晶体管M3的源极、第三晶体管M3的栅极和第七晶体管M7的漏极分别对应于第二下拉模块130的输入端、控制端和输出端。
本实施例中，所述复位模块110包括：第二晶体管M2和第六晶体管M6，所述第二晶体管M2的栅极连接所述复位端REST，源极连接所述低电平端VSS，漏极连接所述栅极输出端OUT，用于在复位端REST为高电平时将所述栅极输出端OUT拉至低电平；所述第六晶体管M6的栅极连接所述复位端REST，源极连接所述存储电容C1的第一端，漏极连接所述低电平端VSS，用于在复位端REST为高电平时将所述存储电容C1的第一端拉至低电平。在本实施例中，第六晶体管的源极、第六晶体管的栅极和第二晶体管的漏极分别对应于所述复位模块110的输入端、控制端和输出端。
在图1所示的实施例中，以N型晶体管为例示出了各个晶体管。但是，本领域技术人员可以认识到，本发明的各个模块不局限于图1所示的具体结构，而且也可以使用其他类型的晶体管。
本实施例的栅极驱动电路的工作时序图如图2所示，具体工作原理如下：
阶段a：INPUT端信号为高电平，REST端和CLK端为低电平，CLKB端为高电平，M4开启，C1的第一端(U点)充电为高电平，M1、M5、M8、M10和M9开启，Q点和OUT端电位被VSS拉为低电平，OUT端输出为低电平，M2、M3、M6、M7为关闭状态。此为充电阶段。
阶段b：CLK端为高电平，INPUT端、REST端和CLKB端均为低电平，由于C1的第一端(U点)保持阶段a的高电平，因此M1和M8依然开启，Q点依然为低电平，U点因为CLK端的耦合被抬高，OUT端输出CLK端的高电平。M2、M3、M4、M5、M6、M7、M9和M10均为关闭状态。此为输出阶段。
阶段c：INPUT端、CLK端为低电平，CLKB端和REST端为高电平，此时M6、M2、M5、M9和M10开启，由于M2和M10开启，将OUT拉至低电平，即OUT端输出为低电平。由于INPUT端为低电平，U点被拉 低，导致Q点被充电为高电平，因此M7和M3开启，且U点和OUT端均与VSS端连接，由于VSS端的电压与GOA的栅线电压Vgl相同，所以将OUT端与VSS端相连起到稳定栅线电压Vgl的功能，M1、M4、M7和M8为关闭状态。此为复位阶段。
阶段d：INPUT端、CLKB端和REST端信号为低电平，CLK端为高电平，在本阶段Q点电压由于没有放电的通路，依然保持为高电平的状态，除M3和M7为开启外，M1、M2、M4、M5、M6、M8、M9和M10均为关闭状态。而M7和M3的开启分别使U点和OUT端持续与VSS线连接，以稳定栅线电压Vgl，此时OUT输出低电平。此为第一稳定阶段。
阶段e：INPUT端、CLK端和REST端信号为低电平，CLKB端为高电平，M5、M9和M10开启，Q点依然保持为高电平，Q点控制的M3和M7也依然保持开启的状态，其中M10和M3使OUT端连接VSS，M5和M7使U点连接VSS，以保持栅线的电压稳定。M1、M2、M4、M6和M8为关闭状态。此为第二稳定阶段。
对于该单元电路，在之后的时序中INPUT端和REST端信号一直为低电平，CLK端和CLKB端高低电平交替，即为d阶段和e阶段的重复，此处不再赘述。
本发明的移位寄存器单元电路结构只包含10个薄膜晶体管(TFT)，且不会随输入的脉冲信号反复的开关，从而避免了功耗损失，降低了整个电路的功耗。其中第九晶体管，即图1中的M9的二极管(M9栅源极连接在一起)结构，利用二极管特性在Q点形成了一个类似直流的波形(图2中Q点的波形)，不会成为波浪状，进一步减小了电路功耗，而且本发明的移位寄存器单元电路只有10个晶体管，产品尺寸可以更小。
本发明还提供了一种用于上述的移位寄存器单元电路的驱动方法，包括：
阶段一：对所述触发信号端和第一时钟端施加高电平，第二时钟端和复位端施加低电平，使所述充电模块为存储电容充电，第一下拉模块将所述栅极输出端下拉至低电平。具体地，结合图1所示的实施例，在对所述触发信号端和第一时钟端施加高电平，第二时钟端和复位端施加低电平时，第四晶体管导通，将存储电容的第一端(U点)充电为高电平，第一晶体 管和第十晶体管导通，将所述栅极输出端下拉至低电平。
阶段二：对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，使存储电容的第一端保持高电平，所述输出控制模块控制所述栅极输出端输出第二时钟端的高电平。具体地，结合图1所示的实施例，在对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平时，存储电容第一端保持高电平，第一晶体管导通，使栅极输出端输出第二时钟端的高电平。
阶段三：对所述第一时钟端和复位端施加高电平，第二时钟端和触发信号端施加低电平，所述复位模块将所述存储电容的两端和栅极输出端拉至低电平。具体地，结合图1所示的实施例，在对所述第一时钟端和复位端施加高电平，第二时钟端和触发信号端施加低电平时，第二晶体管和第六晶体管导通，将所述存储电容的两端和栅极输出端拉至低电平。
阶段四：对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，所述第二下拉模块将所述存储电容的两端和栅极输出端下拉至低电平。具体地，结合图1所示的实施例，在对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平时，第三晶体管和第七晶体管导通，将所述存储电容的两端和栅极输出端下拉至低电平。
阶段五：对所述触发信号端、第二时钟端和复位端施加低电平，第一时钟端施加高电平，第一下拉模块将所述栅极输出端下拉至低电平，第二下拉模块将所述存储电容的两端下拉至低电平。具体地，结合图1所示的实施例，在对所述触发信号端、第二时钟端和复位端施加低电平，第一时钟端施加高电平时，第十晶体管导通，将所述栅极输出端下拉至低电平，第三晶体管和第七晶体管导通，将存储电容的两端下拉至低电平。
本发明还提供了一种移位寄存器，包括级联的若干上述的移位寄存器单元电路。
图3示出了根据本发明实施例的移位寄存器的结构示意图。根据本发明实施例的移位寄存器包括多个级联的移位寄存器单元电路，其中，第一级移位寄存器单元电路的触发信号端连接输入信号端，接收触发信号STV，其中，除第一级和最后一级移位寄存器单元电路以外的任意相邻的两个移位寄存器单元电路中，上一级移位寄存器单元电路的栅极输出端连接下一 级移位寄存器单元电路的触发信号端；每级移位寄存器单元电路的第一时钟端接收第一时钟信号，第二时钟端接收第二时钟信号，低电压端接收低电压信号，复位端接收复位信号。
每级移位寄存器单元电路的栅极输出端连接一条栅线，为与栅线连接的像素单元中的开关提供开关信号。
具体的，如图3所示的移位寄存器，包括多个级联的移位寄存器单元电路SR1、SR2、SR3、SR4……，其中第一级移位寄存器单元电路SR1的栅极输出端OUTPUT连接第二级移位寄存器单元电路SR2的触发信号端INPUT并连接栅线G1；第二级移位寄存器单元电路SR2的栅极输出端OUTPUT连接第三级移位寄存器单元电路SR3的触发信号端INPUT并连接栅线G2；第三级移位寄存器单元电路SR3的栅极输出端OUTPUT连接第四级移位寄存器单元电路SR4的触发信号端INPUT并连接栅线G3；其他级的移位寄存器单元电路依照此方法连接，此外每个移位寄存器单元电路都有两个时钟端和低电压端，每级移位寄存器单元电路的第一时钟端与第一时钟信号输入端CLK1连接，第二时钟端与第二时钟信号输入端CLK2连接，低电压端与低电压输入端VSS连接。每级移位寄存器单元电路的复位端接收复位信号。例如，如图3所示，复位信号可以通过本级移位寄存器单元电路的栅极输出端的输出信号经过下降沿触发的单稳态触发器延迟一个周期之后得到。当然，其他提供复位信号的方法也是可行的。本发明并不局限于此。
本发明还提供了一种包括上述移位寄存器的显示装置，该显示装置可以为：液晶面板、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (13)

  1. 一种移位寄存器单元电路，其特征在于，包括：触发信号端、第一时钟端、第二时钟端、复位端、栅极输出端、低电平端、存储电容、复位模块、第一下拉模块、第二下拉模块、充电模块和输出控制模块；
    所述充电模块的第一输入端和第一控制端均连接所述触发信号端，第一输出端连接所述存储电容的第一端，用于在所述触发信号端为高电平时为存储电容充电；第二输入端连接所述存储电容的第一端，第二控制端连接第一时钟端，第二输出端连接触发信号端，用于在所述第一时钟端为高电平且触发信号端为低电平时将所述存储电容的第一端拉至低电平；
    所述输出控制模块的输入端连接第二时钟端，控制端连接所述存储电容的第一端，输出端连接栅极输出端，用于在所述存储电容的第一端为高电平时将第二时钟端的高电平信号输出至所述栅极输出端，使所述栅极输出端为高电平；所述存储电容的第二端连接所述栅极输出端；
    所述第一下拉模块的第一控制端连接于第一时钟端，第一输入端连接栅极输出端，第一输出端连接低电平端；第二控制端连接所述存储电容的第一端，第二输入端连接第一时钟端，第二输出端连接低电平端；第二下拉模块的输入端连接栅极输出端，控制端连接第一下拉模块中的中间控制节点，输出端连接所述存储电容的第一端；所述第一下拉模块用于将所述栅极输出端拉至低电平，并在所述存储电容的第一端为低电平时通过所述中间控制节点触发所述第二下拉模块将所述存储电容两端均拉至低电平；
    所述复位模块的输入端连接所述存储电容的第一端，控制端连接所述复位端，输出端连接栅极输出端，用于在复位端的控制下将所述存储电容两端拉至低电平。
  2. 如权利要求1所述的移位寄存器单元电路，其特征在于，所述充电模块包括：第四晶体管和第五晶体管，所述第四晶体管的栅极和源极连接触发信号端，漏极连接所述存储电容的第一端，用于将所述触发信号端的高电平信号传输至所述存储电容的第一端；所述第五晶体管的栅极连接所述第一时钟端，源极连接所述存储电容的第一端，漏极连接所述触发信号端，用于在第一时钟端为高电平且触发信号端为低电平时，将所述存储 电容的第一端拉至低电平。
  3. 如权利要求2所述的移位寄存器单元电路，其特征在于，所述输出控制模块包括：第一晶体管，所述第一晶体管的栅极连接所述存储电容的第一端，源极连接所述第二时钟端，漏极连接所述栅极输出端，用于在所述存储电容的第一端为高电平时，将所述第二时钟端的高电平信号输出至所述栅极输出端。
  4. 如权利要求3所述的移位寄存器单元电路，其特征在于，所述第一下拉模块包括：第八晶体管、第九晶体管和第十晶体管；所述第二下拉模块包括：第三晶体管和第七晶体管；
    所述第九晶体管的栅极和源极连接所述第一时钟端，漏极连接所述第八晶体管的源极，所述第八晶体管的栅极连接所述存储电容的第一端，漏极连接所述低电平端，所述第十晶体管的栅极连接所述第一时钟端，源极连接所述栅极输出端，漏极连接所述低电平端；所述第三晶体管的栅极连接所述第八晶体管的源极，源极连接所述栅极输出端，漏极连接所述低电压端，第七晶体管的栅极连接所述第八晶体管的源极，源极连接所述低电平端，漏极连接所述存储电容的第一端；
    所述第八晶体管和第九晶体管用于在所述存储电容的第一端为高电平时，形成从第一时钟端到低电平端的通路，或者在所述存储电容的第一端为低电平时使第八晶体管的源极变为高电平，以使所述第三晶体管和第七晶体管打开，从而将存储电容的两端拉至低电平；
    并且第十晶体管用于在所述第一时钟端为高电平时将所述栅极输出端拉至低电平。
  5. 如权利要求4所述的移位寄存器单元电路，其特征在于，所述复位模块包括：第二晶体管和第六晶体管，所述第二晶体管的栅极连接所述复位端，源极连接所述低电平端，漏极连接所述栅极输出端，用于在复位端为高电平时将所述栅极输出端拉至低电平；所述第六晶体管的栅极连接所述复位端，源极连接所述存储电容的第一端，漏极连接所述低电平端，用于在复位端为高电平时将所述存储电容的第一端拉至低电平。
  6. 一种用于权利要求5所述的移位寄存器单元电路的驱动方法，其特征在于，包括：
    对所述触发信号端和第一时钟端施加高电平，第二时钟端和复位端施加低电平，使所述充电模块为存储电容充电，第一下拉模块将所述栅极输出端下拉至低电平；
    对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，使存储电容的第一端保持高电平，所述输出控制模块控制所述栅极输出端输出第二时钟端的高电平；
    对所述第一时钟端和复位端施加高电平，第二时钟端和触发信号端施加低电平，所述复位模块将所述存储电容的两端和栅极输出端拉至低电平；
    对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，所述第二下拉模块将所述存储电容的两端和栅极输出端下拉至低电平；
    对所述触发信号端、第二时钟端和复位端施加低电平，第一时钟端施加高电平，第一下拉模块将所述栅极输出端下拉至低电平，第二下拉模块将所述存储电容的两端下拉至低电平。
  7. 如权利要求6所述的驱动方法，其特征在于，对所述触发信号端和第一时钟端施加高电平，第二时钟端和复位端施加低电平，使所述充电模块为存储电容充电，所述第一下拉模块将所述栅极输出端下拉至低电平的步骤具体包括：
    对所述触发信号端和第一时钟端施加高电平，第二时钟端和复位端施加低电平，第四晶体管导通，将存储电容的第一端充电为高电平，第一晶体管和第十晶体管导通，将所述栅极输出端下拉至低电平。
  8. 如权利要求6所述的驱动方法，其特征在于，对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，使存储电容的第一端保持高电平，所述输出控制模块控制所述栅极输出端输出第二时钟端的高电平的步骤具体包括：
    对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，存储电容第一端保持高电平，第一晶体管导通，使栅极输出端输出第二时钟端的高电平。
  9. 如权利要求6所述的驱动方法，其特征在于，对所述第一时钟端和复位端施加高电平，第二时钟端和触发信号端施加低电平，所述复位模 块将所述存储电容的两端和栅极输出端拉至低电平的步骤具体包括：
    对所述第一时钟端和复位端施加高电平，第二时钟端和触发信号端施加低电平，第二晶体管和第六晶体管导通，将所述存储电容的两端和栅极输出端拉至低电平。
  10. 如权利要求6所述的驱动方法，其特征在于，对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，所述第二下拉模块将所述存储电容的两端和栅极输出端下拉至低电平的步骤具体包括：
    对所述触发信号端、第一时钟端和复位端施加低电平，第二时钟端施加高电平，第三晶体管和第七晶体管导通，将所述存储电容的两端和栅极输出端下拉至低电平。
  11. 如权利要求6所述的驱动方法，其特征在于，对所述触发信号端、第二时钟端和复位端施加低电平，第一时钟端施加高电平，第一下拉模块将所述栅极输出端下拉至低电平，第二下拉模块将所述存储电容的两端下拉至低电平的步骤具体包括：
    对所述触发信号端、第二时钟端和复位端施加低电平，第一时钟端施加高电平，第十晶体管导通，将所述栅极输出端下拉至低电平，第三晶体管和第七晶体管导通，将存储电容的两端下拉至低电平。
  12. 一种移位寄存器，其特征在于，包括级联的若干如权利要求1～5中任一项所述的移位寄存器单元电路，其中，第一级移位寄存器单元电路的触发信号端连接输入信号端，其中，除第一级和最后一级移位寄存器单元电路以外的任意相邻的两个移位寄存器单元电路中，上一级移位寄存器单元电路的栅极输出端连接下一级移位寄存器单元电路的触发信号端；每级移位寄存器单元电路的第一时钟端接收第一时钟信号，第二时钟端接收第二时钟信号，低电压端接收低电压信号，复位端接收复位信号。
  13. 一种显示装置，其特征在于，包括如权利要求12所述的移位寄存器。
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