WO2016070592A1 - 一种互补隧穿场效应晶体管及其制作方法 - Google Patents

一种互补隧穿场效应晶体管及其制作方法 Download PDF

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WO2016070592A1
WO2016070592A1 PCT/CN2015/077523 CN2015077523W WO2016070592A1 WO 2016070592 A1 WO2016070592 A1 WO 2016070592A1 CN 2015077523 W CN2015077523 W CN 2015077523W WO 2016070592 A1 WO2016070592 A1 WO 2016070592A1
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layer
source region
drain region
channel
gate
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French (fr)
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杨喜超
赵静
张臣雄
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to US15/587,781 priority patent/US10141434B2/en
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Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a complementary tunneling field effect transistor and a method of fabricating the same.
  • transistors As the transistor fabrication process evolves, the size of transistors continues to shrink. However, in the process of shrinking the transistor size to near the physical limit, transistors also face many problems, such as severe short channel effect, large leakage current, and high power density. . In response to these problems, the industry has proposed various solutions. Among them, the TFET (Tunnel Field Effect Transistor) has a weak short channel effect, a small off-state current, and is not affected by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The advantages of threshold swing limits and other advantages have received wide attention.
  • the existing tunneling field effect transistor for the tunneling field effect transistor of this structure, different types of ion implantation are performed on the source region and the drain region, respectively, in the fabrication process.
  • the gate region and the source region are partially overlapped during the fabrication process (as shown by A in FIG. 1).
  • the gate electric field carriers are tunneled between the layers to generate a channel current.
  • the carrier tunneling direction is parallel to the gate electric field direction, the gate control capability is relatively strong, and the tunneling current can be overlapped by the gate region and the source region. Area to regulate.
  • the impurity concentration distribution formed by the ion implantation process in the source region and the drain region is generally Gaussian, and thus the ion implantation process is employed.
  • the ion distribution is uneven, it is difficult
  • the tunneling efficiency of the carrier is relatively low under the action of a certain gate electric field.
  • Embodiments of the present invention provide a complementary tunneling field effect transistor and a method of fabricating the same, which can increase the tunneling efficiency of carriers, thereby improving the performance of the tunneling field effect transistor.
  • a complementary tunneling field effect transistor includes:
  • first drain region and a first source region disposed on the substrate the first drain region and the first source region including a first dopant
  • a second gate stack layer disposed on the second epitaxial layer wherein the first drain region
  • the first channel, the second source region, the first epitaxial layer and the first gate stack layer form a first tunneling field effect transistor
  • the first dopant is a P-type dopant
  • the second dopant is an N-type dopant, or the first dopant is an N-type dopant, and the second dopant a P-type dopant
  • the first channel and The second channel is a lightly doped layer or a first insulating layer, and the concentration of impurities in the lightly doped layer is less than or equal to 10 15 per cubic centimeter.
  • the first gate stack layer includes a first gate dielectric layer and a first gate conductive layer; the second gate stacked layer includes a second gate dielectric layer and a second gate conductive layer; the complementary tunneling field effect transistor further includes a first spacer disposed on the second source region and the first drain region, and a second spacer disposed on the first source region and the second drain region, the first a spacer is in contact with the first epitaxial layer and the first gate stack layer, the second spacer is in contact with the second epitaxial layer and the second gate stack layer; a source region, the first gate stack layer, the first drain region, the first source region, the second gate stack layer, and a second insulating layer on the second drain region; a first drain on the first drain region, a first source disposed on the second source region, and a first gate disposed on the first gate conductive layer; disposed on the second drain a second drain on the region, a second source disposed on the first source region, and a second gate disposed on the second gate conductive layer.
  • the tunneling field effect transistor further includes: an isolated shallow trench disposed between the first drain region and the first source region.
  • the material of one channel and the second channel is silicon, germanium, germanium silicon or a tri-five compound; the materials of the first gate dielectric layer and the second gate dielectric layer are silicon dioxide and nitrided
  • the silicon or high dielectric material, the material of the first gate conductive layer and the second gate conductive layer is polysilicon, titanium nitride or a metal material.
  • an embodiment of the present invention provides a method for fabricating a complementary tunneling field effect transistor, the method comprising:
  • a substrate a first doped layer, a channel layer and a second doping are sequentially deposited on the substrate a layer, the first doped layer includes a first dopant, the second doped layer includes a second dopant; and the second doped layer, the channel layer, and the first doped layer Etching the impurity layer to form a second source region, a second drain region, a first channel, a second channel, a first drain region, and a first source region, wherein the first channel is located in the first drain region Upper, the second source region is located on the first channel, the second channel is located on the first source region, the second drain region is located on the second channel, and in the second An epitaxial layer and a gate stack layer are sequentially deposited on the source region, the first drain region, the first source region, and the second drain region; and the gate stack layer and the epitaxial layer are etched and sequentially formed a first gate stack layer, a second gate stack layer, a first epitaxial layer and a second epitaxial layer
  • the first dopant is a P-type dopant
  • the second dopant is an N-type dopant, or the first dopant is an N-type dopant, and the second dopant a P-type dopant
  • the first channel and The second channel is a lightly doped layer or a first insulating layer, and the concentration of impurities in the lightly doped layer is less than or equal to 10 15 per cubic centimeter.
  • the first gate stack layer includes a first gate dielectric layer and a first gate conductive layer; the second gate stack layer includes a second gate dielectric layer and a second gate conductive layer; After the epitaxial layer is etched to form the first gate stack layer, the second gate stack layer, the first epitaxial layer and the second epitaxial layer, the fabrication method further includes: a first spacer is disposed on the source region and the first drain region, and a second spacer is disposed on the first source region and the second drain region, the first spacer and the first epitaxial a layer is in contact with the first gate stack layer, the second spacer is in contact with the second epitaxial layer and the second gate stack layer; in the second source region, the first gate stack Providing a second insulating layer on the layer, the first drain region, the first source region, the second gate stack layer, and the second drain region; etching the second insulating layer, and Forming a first drain on the first drain region, forming a first source on the second source region, forming a first
  • the fabricating method further comprises: providing an isolated shallow trench on the first doped layer, the isolating A shallow trench is located between the first drain region and the first source region.
  • the material of one channel and the second channel is silicon, germanium, germanium silicon or a tri-five compound; the materials of the first gate dielectric layer and the second gate dielectric layer are silicon dioxide and nitrided
  • the silicon or high dielectric material, the material of the first gate conductive layer and the second gate conductive layer is polysilicon, titanium nitride or a metal material.
  • Embodiments of the present invention provide a complementary tunneling field effect transistor and a method of fabricating the same, the complementary tunneling field effect transistor comprising: a first drain region and a first source region disposed on a substrate, a first drain region and a first The source region includes a first dopant; a first channel disposed on the first drain region and a second channel disposed on the first source region; and a second surface disposed on the first channel a source region and a second drain region disposed on the second channel, the second source region and the second drain region including a second dopant; a first epitaxial layer disposed on the first drain region and the second source region, and a second epitaxial layer disposed on the second drain region and the first source region, the first epitaxial layer covering the sidewalls of the first channel and the second source region, and the second epitaxial layer covering the second channel and the second drain region a first gate stack layer disposed on the first epitaxial layer, and a second gate stack layer disposed on the second epitaxial layer
  • the complementary tunneling field effect transistor provided by the embodiment of the present invention includes a first tunneling field effect transistor and a second tunneling field effect transistor, wherein the first tunneling field effect transistor includes a first drain region. a first channel, a second source region, a first epitaxial layer, and a first gate stack layer, the second tunneling field effect transistor including a second drain region, a second channel, a first source region, a second epitaxial layer, and The second gate stacks the layer, and the first drain region and the first source region include a first dopant, and the second source region and the second drain region include a second dopant.
  • the means is doped in the semiconductor material, so that the first dopant and the second dopant are uniformly distributed, instead of the Gaussian distribution of the dopant by ion implantation as in the prior art, thus enabling the second
  • the impurity concentration between the source region and the first epitaxial layer and between the first source region and the second epitaxial layer is abruptly changed within a short distance, thereby increasing the tunneling efficiency of the carrier and improving the performance of the tunneling field effect transistor .
  • FIG. 1 is a schematic structural view of a tunneling field effect transistor in the prior art
  • FIG. 2 is a schematic structural diagram 1 of a complementary tunneling field effect transistor according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram 2 of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram 3 of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram 4 of a complementary tunneling field effect transistor according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram 5 of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 7 is a schematic flowchart diagram of a method for fabricating a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram 1 of a process for fabricating a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 9 is a second schematic diagram of a fabrication process of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 10 is a third schematic diagram of a fabrication process of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram 4 of a manufacturing process of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram 5 of a manufacturing process of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram 6 of a manufacturing process of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram 7 of a process for fabricating a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • 15 is a schematic diagram 8 of a manufacturing process of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 16 is a schematic diagram of a complementary tunneling field effect transistor according to an embodiment of the present invention.
  • the flow chart of the method is nine.
  • FIG. 2 is a schematic structural diagram of the tunneling field effect transistor.
  • the tunneling field effect transistor includes: a substrate 10; a first drain region 20a and a first source region 20b disposed on the substrate 10, the first drain region 20a and the first source region 20b including a first dopant; a first channel 30a on the first drain region 20a and a second channel 30b disposed on the first source region 20b; a second source region 40a disposed on the first channel 30a and disposed on the second channel a second drain region 40b on 30b, the second source region 40a and the second drain region 40b include a second dopant; a first epitaxial layer 50a disposed on the first drain region 20a and the second source region 40a, and a setting In the second drain region 40b and the second epitaxial layer 50b on the first source region 20b, the first epitaxial layer 50a covers the sidewalls of the first trench 30a and the second source region 40a, and the second epitaxial layer 50b covers the second trench a sidewall of the track 30b and the second drain region 40b; a first gate
  • the first drain region 20a, the first drain region 30a, the second source region 40a, the first epitaxial layer 50a, and the first gate stack layer 60a form a first tunneling field effect transistor, a second drain region 40b, and a second trench.
  • the track 30b, the first source region 20b, the second epitaxial layer 50b, and the second gate stack layer 60b form a second tunneling field effect transistor.
  • the first dopant is a P-type dopant
  • the second dopant is an N-type dopant
  • the first dopant is an N-type dopant
  • the second dopant is a P-type dopant. Dopant.
  • the first tunneling field effect transistor is an N-type tunneling field effect transistor
  • the second tunneling field The effect transistor is a P-type tunneling field effect transistor
  • the first dopant is a P-type dopant and the second dopant is an N-type dopant
  • the first tunneling field effect transistor is a P-type The tunneling field effect transistor
  • the second tunneling field effect transistor is an N-type tunneling field effect transistor.
  • first drain region 20a, the first source region 20b, the second source region 40a, and the second drain region 40b are heavily doped, which can be understood as included in the first drain region 20a and the first source region 20b.
  • the first dopant and the second dopant included in the second source region 40a and the second drain region 40b have an impurity concentration ranging from 10 19 per cubic centimeter to 10 21 per cubic centimeter; the first channel The 30a and the second channel 30b are lightly doped layers or first insulating layers.
  • the lightly doped layer can be understood as uniformly adding impurities in the semiconductor film, and the concentration of the impurities is less than or equal to 10 15 per cubic centimeter.
  • the material of the semiconductor film is germanium, silicon, germanium silicon or a tri-five compound.
  • the first channel 30a and the second channel 30b may also be a first insulating layer, and the first channel 30a and the second channel 30b have a thickness of several tens of nanometers to several hundreds of nanometers. It is also necessary to add that the impurities in the lightly doped layer may be donor impurities or acceptor impurities, which is not limited in the present invention.
  • the substrate 10 is a semiconductor substrate, and the specific material of the substrate 10 may be germanium, silicon, germanium silicon or a tri-five compound.
  • the first epitaxial layer 50a and the second epitaxial layer 50b are lightly doped semiconductor thin films, and the material of the semiconductor thin film is germanium, silicon, germanium silicon or a tri-five compound. Light doping means that the concentration of impurities added is less than or equal to 10 15 per cubic centimeter.
  • the thickness of the first epitaxial layer 50a and the second epitaxial layer 50b is between 1 nm and 10 nm.
  • the first gate stack layer 60a includes a first gate dielectric layer and a first gate conductive layer
  • the second gate stack layer 60b includes a second gate dielectric layer and a second gate conductive layer, wherein the first gate conductive layer Located above the first gate dielectric layer, the second gate conductive layer is above the second gate dielectric layer.
  • the material of the first gate dielectric layer and the second gate dielectric layer may be an insulating material such as silicon dioxide, silicon nitride, or a high dielectric material.
  • the material of the first gate conductive layer and the second gate conductive layer may be a conductive material such as polysilicon, titanium nitride or metal, and the first gate conductive layer and the second gate conductive layer have a thickness of several tens of nanometers.
  • the complementary tunneling field effect transistor further includes: a first spacer 70a disposed on the second source region 40a and the first drain region 20a, and disposed on the first source region 20b and the second drain region 40b.
  • Second spacer 70b, first spacer 70a and first epitaxial layer 50a is in contact with the first gate stack layer 60a
  • the second spacer 70b is in contact with the second epitaxial layer 50b and the second gate stack layer 60b.
  • the materials of the first spacer 70a and the second spacer 70b may be insulating materials such as silicon dioxide, silicon nitride, and high dielectric materials.
  • the tunneling field effect transistor further includes: a second source region 40a, a first gate stack layer 60a, a first drain region 20a, a first source region 20b, and a second gate stack layer.
  • the second insulating layer 80 on the 60b and the second drain region 40b, and the second insulating layer 80 is an insulating material such as a low dielectric material.
  • the complementary tunneling field effect transistor further includes: a first drain ad disposed on the first drain region 20a, a first source as disposed on the second source region 40a, and a first gate conductive a first gate ag on the layer; a second drain bd disposed on the second drain region 40b, a second source bs disposed on the first source region 20b, and a second electrode disposed on the second gate conductive layer Two gates bg.
  • the first drain ad, the second source bs, the first gate ag, the first source as, the second drain bd, and the second gate bg are not in contact with each other, and may be metal electrodes.
  • the complementary tunneling field effect transistor combined with the N-type tunneling field effect transistor and the P-type tunneling field effect transistor provided by the embodiment of the present invention, as shown in FIG. 3, further includes: disposed on the substrate 10. Isolating the shallow trench I, the isolation shallow trench I is located between the first drain region 20a and the first source region 20b. Since the first drain region 20a and the first source region 20b both include the first dopant, the isolation shallow trench I is used. The adjacent first drain region 20a and the first source region 20b are isolated.
  • the complementary tunneling field effect transistor provided in the embodiment of the present invention adopts a working mechanism of line tunneling.
  • the working mechanism of the line tunneling means that the tunneling direction of the carriers is parallel to the direction of the gate electric field, and the gate control capability is relatively strong, and the tunneling current can be regulated by the overlapping area of the gate region and the source region.
  • the on-state current of the transistor is provided by a tunnel junction of a source region and an epitaxial layer.
  • the on-state current of the N-type tunneling field effect transistor is formed by tunneling electrons in the source region to the epitaxial layer in contact with the source region, and the on-state current of the P-type tunneling field effect transistor is empty in the source region thereof.
  • the holes are formed by tunneling of an epitaxial layer in contact with the source region. Due to the line tunneling mechanism The tunneling probability of high carriers and the linearly adjustable on-state current are within a certain range.
  • the complementary tunneling field effect transistor provided by the invention has higher on-state current, smaller subthreshold swing and larger Current regulation freedom.
  • the current drive capability of P-type tunneling field effect transistors is weaker than that of N-type tunneling field effect transistors.
  • the complementary tunneling field effect transistor provided by the embodiment of the invention can increase the on-state current of the P-type tunneling field effect transistor by increasing the tunneling junction area of the P-type tunneling field effect transistor, thereby realizing the N-type The on-state current of the tunneling field effect transistor is matched.
  • FIG. 3 A schematic diagram of the structure of the complementary tunneling field effect transistor obtained by matching the on-state current of the tunneling field effect transistor is shown in FIG.
  • a portion of the first source region is over-etched to form an L-shaped surface, as shown by E in FIG. 4, thereby increasing the P-type tunneling field effect transistor.
  • the tunneling junction area increases the on-state current of the P-type tunneling field effect transistor to match the on-state current of the N-type tunneling field effect transistor.
  • the positions of the N-type tunneling field effect transistor and the P-type tunneling field effect transistor in the complementary tunneling field effect transistor can be interchanged, when the N-type tunneling field effect transistor and the P-type tunneling field effect transistor When the positions are interchanged, the corresponding electrodes are also changed accordingly.
  • the tunneling junction area of the P-type tunneling field effect transistor can be increased by increasing the thickness of the second source region. Thereby increasing the on-state current of the P-type tunneling field effect transistor.
  • the tunneling field effect transistor provided by the embodiment of the present invention can be fabricated to include only an N-type tunneling field effect transistor, including a substrate 10, and disposed on the substrate 10.
  • An epitaxial layer 50a, the first epitaxial layer 50a covers the second source region 40a and a sidewall of the first trench 30a, a first gate stack layer 60a disposed on the first epitaxial layer 50a, and a first spacer 70a disposed on the first drain region 20a and the second source region 40a
  • first The spacer 70a is in contact with the first epitaxial layer 50a and the first gate stack layer 60a
  • the second insulating layer is disposed on the first drain region 20a, the second source region 40a, the first spacer 70a, and the first gate stack layer 60a.
  • the tunneling field effect transistor provided by the embodiment of the present invention may be configured to include only a P-type tunneling field effect transistor, including a substrate 10, and a first source disposed on the substrate 10.
  • the second trench 30b disposed on the first source region 20b, the second drain region 40b disposed on the second trench 30b, and the second drain region 40b disposed on the first source region 20b and the second drain region 40b
  • the epitaxial layer 50b, the second epitaxial layer 50b covers the sidewalls of the second drain region 40b and the second trench 30b, and the second gate stack layer 60b disposed on the second epitaxial layer 50b is disposed in the first source region 20b and
  • the second spacer 70b on the second drain region 40b is in contact with the second epitaxial layer 50b and the second gate stack layer 60b, and is disposed on the first source region 20b, the second drain region 40b, and the second spacer.
  • Embodiments of the present invention provide a complementary tunneling field effect transistor including a first tunneling field effect transistor and a second tunneling field effect transistor, wherein the first tunneling field effect transistor includes a drain region, a first channel, a second source region, a first epitaxial layer and a first gate stack layer, the second tunneling field effect transistor comprising a second drain region, a second channel, a first source region, and a second
  • the epitaxial layer and the second gate stack layer, and the first drain region and the first source region include a first dopant, and the second source region and the second drain region include a second dopant.
  • the dopants in the first drain region and the second source region in the first tunneling field effect transistor and in the first source region and the second drain region in the second tunneling field effect transistor are uniformly distributed, Rather than the prior art ion implanted dopants are Gaussian distributed, thus enabling the second source region and the first epitaxial layer and between the first source region and the second The impurity concentration between the epitaxial layers is abruptly changed within a short distance, thereby increasing the tunneling efficiency of the carriers and improving the performance of the tunneling field effect transistor.
  • the embodiment of the invention provides a method for fabricating a complementary tunneling field effect transistor, as shown in FIG. 7 , which is a schematic flowchart of the manufacturing method.
  • the substrate 10 is shown in FIG. It should be added that the substrate 10 may be a semiconductor substrate, and the specific material of the substrate 10 may be germanium, silicon, germanium silicon or a tri-five compound.
  • a first doped layer 20 is deposited on the substrate 10.
  • the first doping layer 20 includes a first dopant, and the first dopant is doped in the semiconductor film, and the concentration of the first dopant is higher than 10 19 per cubic centimeter. 10 19 per cubic centimeter to 10 21 per cubic centimeter.
  • the material of the semiconductor thin film is germanium, silicon, germanium silicon or a tri-five compound, which is not limited in the present invention.
  • the thickness of the first doped layer is several tens of nanometers to several hundreds of nanometers.
  • the manufacturing method further includes: An isolated shallow trench I is provided on the doped layer 20.
  • the isolation shallow trench I is located between the first drain region 20a and the first source region 20b.
  • the bottom of the isolation shallow trench I is equal to or lower than the bottom of the first doping layer 20.
  • the isolation shallow trench I is optional, that is, when the isolation shallow trench I is not provided, the first doped layer can be etched by an etching process, and the second insulating layer is filled with the first drain region 20a. Isolating from the first source region 20b.
  • a channel layer 30 is formed on the first doped layer.
  • the channel layer 30 is a lightly doped layer or a first insulating layer.
  • Light doping can be understood as uniformly adding impurities in the semiconductor film, and the concentration of the impurities is less than or equal to 10 15 per cubic centimeter.
  • the material of the semiconductor film is germanium, silicon, germanium silicon or a tri-five compound.
  • the channel layer 30 may also be a first insulating layer, which is not limited in the present invention.
  • the channel layer 30 has a thickness of several tens of nanometers to several hundreds of nanometers.
  • a second doped layer 40 is deposited on the channel layer 30.
  • the second doping layer 40 includes a second dopant, and the second dopant is doped in the semiconductor film, and the concentration of the second dopant is higher than 10 19 per cubic centimeter. 10 19 per cubic centimeter to 10 21 per cubic centimeter.
  • the material of the semiconductor film is germanium, silicon, germanium silicon or a tri-five compound.
  • the thickness of the second doping layer 40 is several tens of nanometers to several hundreds of nanometers.
  • the channel layer 30 and the second doping layer 40 of the intermediate portion are removed to form the second source region 40a, the second drain region 40b, the first channel 30a, and the first
  • the second channel 30b has a first channel 30a on the first drain region 20a, a second source region 40a on the first channel 30a, a second channel 30b on the first source region 20b, and a second drain region 40b. On the second channel 30b.
  • S105 Depositing an epitaxial layer on the second source region, the first drain region, the first source region, and the second drain region.
  • an epitaxial layer 50 is deposited on the second source region 40a, the first drain region 20a, the first source region 20b, and the second drain region 40b.
  • the epitaxial layer 50 is a lightly doped semiconductor film, and the material of the semiconductor film is germanium, silicon, germanium silicon or a tri-five compound.
  • Light doping means that the concentration of impurities added is less than or equal to 10 15 per cubic centimeter.
  • the thickness of the epitaxial layer 50 is between 1 nm and 10 nm.
  • a gate dielectric layer is deposited on the epitaxial layer 50.
  • the material of the gate dielectric layer may be an insulating material such as silicon dioxide, silicon nitride, or a high dielectric material.
  • a gate conductive layer is deposited on the gate dielectric layer, and the gate dielectric layer and the gate conductive layer constitute a gate stack layer 60.
  • the material of the gate conductive layer may be a conductive material such as polysilicon, titanium nitride or metal.
  • the thickness of the gate conductive layer is several tens of nanometers. It should be noted that, as shown in FIG. 14, after the gate conductive layer is formed on the gate dielectric layer, the first epitaxial layer 50a and the first gate stack layer 60a and the second of the first tunneling field effect transistor are formed by an etching process.
  • the first gate stack layer 60a is located above the first epitaxial layer 50a
  • the second gate stack layer 60b is located above the second epitaxial layer 50b
  • An epitaxial layer 50a covers the sidewalls of the first trench 30a and the second source region 40a
  • the second epitaxial layer 50b covers the sidewalls of the second trench 30b and the second drain region 40b.
  • the epitaxial layer 50 in the embodiment of the present invention includes a first epitaxial layer 50a and a second epitaxial layer 50b, that is, the epitaxial layer 50 is partially etched to form a first epitaxial layer 50a and a second epitaxial layer. 50b.
  • the relationship between the gate dielectric layer and the first gate dielectric layer and the second gate dielectric layer, and the relationship between the gate conductive layer and the first gate conductive layer and the second gate conductive layer are examples of the first epitaxial layer 50a and a second epitaxial layer.
  • the first drain region 20a, the first drain region 30a, the second source region 40a, the first epitaxial layer 50a, and the first gate stack layer 60a form a first tunneling field effect transistor, a second drain region 40b, and a second trench.
  • the track 30b, the first source region 20b, the second epitaxial layer 50b, and the second gate stack layer 60 form a second tunneling field effect transistor.
  • the first dopant is a P-type dopant
  • the second dopant is an N-type dopant
  • the first dopant is an N-type dopant
  • the second dopant is a P-type dopant. Dopant.
  • the first tunneling field effect transistor is an N-type tunneling field effect transistor
  • the second tunneling field The effect transistor is a P-type tunneling field effect transistor
  • the first dopant is a P-type dopant and the second dopant is an N-type dopant
  • the first tunneling field effect transistor is a P-type tunneling field
  • the effect transistor, the second tunneling field effect transistor is an N-type tunneling field effect transistor.
  • the first spacer is disposed on the second source region and the first drain region, and the second spacer is disposed on the first source region and the second drain region.
  • a first spacer 70a is disposed on the second source region 40a and the first drain region 20a
  • a second spacer 70b is disposed on the first source region 20b and the second drain region 40b.
  • first spacer 70a and the first epitaxial layer 50a and the first gate stack layer 60a In contact with each other, the second spacer 70b is in contact with the second epitaxial layer 50b and the second gate stack layer 60b; in addition, the materials of the first spacer 70a and the second spacer 70b are both silicon dioxide and nitrided. Insulating materials such as silicon and high dielectric materials.
  • a second insulating layer is disposed on the second source region, the first gate stack layer, the first drain region, the first source region, the second gate stack layer, and the second drain region.
  • a second insulating layer is disposed on the second source region 40a, the first gate stack layer 60a, the first drain region 20a, the first source region 20b, the second gate stack layer 60b, and the second drain region 40b. 80.
  • the process of forming the second insulating layer 80 is to fill an insulating material such as a low dielectric material.
  • a metal electrode contact window is formed by photolithography and etching processes, a metal is deposited on the metal electrode contact window, and a source, a drain, and a gate of the transistor are fabricated by a lift-off technique. Extreme metal electrode.
  • a first drain ad is formed on the first drain region 20a, a first source as is formed on the second source region 40a, and a first gate is formed on the first gate conductive layer. Ag; forming a second drain bd on the second drain region 40b, forming a second source bs on the first source region 20b, and forming a second gate bg on the second gate conductive layer.
  • the first drain ad, the second source bs, the first gate ag, the second source bs, the second drain bd, and the second gate bg are not in contact with each other, and may be metal electrodes.
  • the tunneling field effect transistor fabricated according to the fabrication method provided by the embodiment of the present invention may be an N-type tunneling field effect transistor (NTFET), a P-type tunneling field effect transistor (PTFET), or an N-type tunneling field effect transistor and a P
  • NFET N-type tunneling field effect transistor
  • PFET P-type tunneling field effect transistor
  • PFET N-type tunneling field effect transistor
  • PFET N-type tunneling field effect transistor and a P
  • the type of tunneling field effect transistor combined with a complementary tunneling field effect transistor is not limited in the present invention.
  • the tunneling field effect transistor provided in the embodiment of the present invention operates by using a line tunneling working mechanism.
  • the so-called line tunneling mechanism refers to the tunneling direction and gate of carriers.
  • the direction of the electric field is parallel, the gate control capability is relatively strong, and the tunneling current can be regulated by the overlapping area of the gate region and the source region.
  • the on-state current of the transistor is provided by a tunnel junction of a source region and an epitaxial layer.
  • the on-state current of the N-type tunneling field effect transistor is formed by tunneling electrons in the source region to the epitaxial layer in contact with the source region, and the on-state current of the P-type tunneling field effect transistor is empty in the source region thereof.
  • the holes are formed by tunneling of an epitaxial layer in contact with the source region.
  • the tunneling field effect transistor provided by the invention has a higher on-state current and a smaller sub-threshold. Swing and greater current regulation freedom.
  • the current drive capability of P-type tunneling field effect transistors is weaker than that of N-type tunneling field effect transistors.
  • the complementary tunneling field effect transistor provided by the embodiment of the invention can also increase the on-state current of the P-type tunneling field effect transistor by increasing the tunnel junction area of the P-type tunneling field effect transistor, and realize the N-type tunnel Matching of the on-state current of the field effect transistor.
  • a part of the P-type tunneling field effect transistor is over-etched to form an L-shaped surface of the first source region, thereby increasing a tunneling junction area of the P-type tunneling field effect transistor and increasing
  • the on-state current of the P-type tunneling field effect transistor is matched with the on-state current of the N-type tunneling field effect transistor.
  • Embodiments of the present invention provide a method for fabricating a tunneling field effect transistor, the method comprising: sequentially depositing a first doped layer, a channel layer and a second doped layer on a substrate, the first doped layer comprising a dopant, the second doped layer includes a second dopant; etching the second doped layer, the channel layer and the first doped layer to form a second source region, a second drain region, and a first a channel, a second channel, a first drain region and a first source region, the first channel is located on the first drain region, the second source region is located on the first channel, and the second channel is located on the first source region a second drain region is disposed on the second channel; an epitaxial layer and a gate stack layer are sequentially deposited on the second source region, the first drain region, the first source region, and the second drain region; etching the gate stack layer and the epitaxial layer Forming a first gate stack layer, a second gate stack layer, a first
  • the complementary tunneling field effect transistor obtained by the fabrication method provided by the embodiment of the present invention includes a first tunneling field effect transistor and a second tunneling field effect transistor, wherein the first tunneling field effect is based on the description of the above embodiments.
  • the transistor includes a first drain region, a first channel, a second source region, a first epitaxial layer and a first gate stack layer
  • the second tunneling field effect transistor includes a second drain region, a second channel, and a first source region a second epitaxial layer and a second gate stack layer, and the first drain region and the first source region comprise a first dopant, and the second source region and the second drain region comprise a second dopant.
  • the dopants in the first drain region and the second source region in the first tunneling field effect transistor and in the first source region and the second drain region in the second tunneling field effect transistor are uniformly distributed, Rather than the dopant implanted in the prior art, the dopant is Gaussian, so that the impurity concentration between the second source region and the first epitaxial layer and between the first source region and the second epitaxial layer can be made shorter. Mutations occur within the distance, thereby increasing the tunneling efficiency of the carriers and improving the performance of the tunneling field effect transistor.

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Abstract

一种互补隧穿场效应晶体管及其制作方法，涉及半导体技术领域，该互补隧穿场效应晶体管能够增加载流子的隧穿效率，从而提高互补隧穿场效应晶体管的性能。该晶体管包括：设置于衬底（10）上的第一漏区（20a）和第一源区（20b），第一漏区和第一源区包括第一掺杂物；设置于第一漏区上的第一沟道（30a）和设置于第一源区上的第二沟道（30b）；设置于第一沟道上的第二源区（40a）和设置于第二沟道上的第二漏区（40b），第二源区和第二漏区包括第二掺杂物；设置于第一漏区和第二源区上的第一外延层（50a），设置于第二漏区和第一源区上的第二外延层（50b）；设置于第一外延层上的第一栅堆叠层（60a），设置于第二外延层上的第二栅堆叠层（60b）。

Description

一种互补隧穿场效应晶体管及其制作方法
本申请要求于2014年11月07日提交中国专利局、申请号为201410623588.6、发明名称为“一种互补隧穿场效应晶体管及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种互补隧穿场效应晶体管及其制作方法。
背景技术
随着晶体管制作工艺的演进，晶体管的尺寸不断缩小，但是，在晶体管的尺寸缩小至接近物理极限的过程中，晶体管也面临诸多问题，如短沟道效应严重、泄漏电流大、功率密度大等。针对这些问题，业界提出了各种解决方案。其中，TFET(Tunnel Field Effect Transistor，隧穿场效应晶体管)由于具有较弱的短沟道效应、关态电流小、不受MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)亚阈值摆幅的限制等优势，得到了广泛关注。
现有的隧穿场效应晶体管，如图1所示，对于这种结构的隧穿场效应晶体管，在制作的过程中，要分别对源区和漏区进行不同类型的离子注入。为了增加隧穿电流，在制作过程中使栅区与源区部分重叠(如图1中A所示)，在栅电场的作用下，载流子发生带间隧穿，从而产生沟道电流。在这种采用线隧穿工作机制的隧穿场效应晶体管中，载流子隧穿方向与栅电场方向平行，栅控能力比较强，并且隧穿电流的大小可以通过栅区和源区的重叠面积来进行调控。由于现有技术采用离子注入的方式对隧穿场效应晶体管的源区和漏区掺杂杂质，但是离子注入工艺在源区和漏区形成的杂质浓度分布一般为高斯分布，因此采用离子注入工艺时，离子分布不均匀，难 以形成掺杂突变的隧穿结，所以在一定栅电场的作用下，载流子的隧穿效率比较低。
发明内容
本发明的实施例提供一种互补隧穿场效应晶体管及其制作方法，能够增加载流子的隧穿效率，从而提高隧穿场效应晶体管的性能。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，一种互补隧穿场效应晶体管，包括：
设置于衬底上的第一漏区和第一源区，所述第一漏区和所述第一源区包括第一掺杂物；设置于所述第一漏区上的第一沟道和设置于所述第一源区上的第二沟道；设置于所述第一沟道上的第二源区和设置于所述第二沟道上的第二漏区，所述第二源区和所述第二漏区包括第二掺杂物；设置于所述第一漏区和所述第二源区上的第一外延层，以及设置于所述第二漏区和所述第一源区上的第二外延层，所述第一外延层覆盖所述第一沟道和所述第二源区的侧墙，所述第二外延层覆盖所述第二沟道和所述第二漏区的侧墙；设置于所述第一外延层上的第一栅堆叠层，以及设置于所述第二外延层上的第二栅堆叠层；其中，所述第一漏区、所述第一沟道、所述第二源区、所述第一外延层和所述第一栅堆叠层形成第一隧穿场效应晶体管，所述第二漏区、所述第二沟道、所述第一源区、所述第二外延层和所述第二栅堆叠层形成第二隧穿场效应晶体管。
结合第一方面，在第一方面的第一种可能的实现方式中，
所述第一掺杂物为P型掺杂物，所述第二掺杂物为N型掺杂物，或者所述第一掺杂物为N型掺杂物，所述第二掺杂物为P型掺杂物；所述第一掺杂物和所述第二掺杂物的杂质浓度在每立方厘米1019个到每立方厘米1021个的范围内；所述第一沟道和所述第二沟道为轻掺杂层或者第一绝缘层，所述轻掺杂层中杂质的浓度小于等于每立方厘米1015个。
结合第一方面，在第一方面的第三种可能的实现方式中，
所述第一栅堆叠层包括第一栅介质层和第一栅导电层；所述第二栅堆叠层包括第二栅介质层和第二栅导电层；所述互补隧穿场效应晶体管还包括：设置于所述第二源区和所述第一漏区上的第一隔离物，以及设置于所述第一源区和所述第二漏区上的第二隔离物，所述第一隔离物与所述第一外延层和所述第一栅堆叠层相接触，所述第二隔离物与所述第二外延层和所述第二栅堆叠层相接触；设置于所述第二源区、所述第一栅堆叠层、所述第一漏区、所述第一源区、所述第二栅堆叠层和所述第二漏区上的第二绝缘层；设置于所述第一漏区上的第一漏极，设置于所述第二源区上的第一源极，以及设置于所述第一栅导电层上的第一栅极；设置于所述第二漏区上的第二漏极，设置于所述第一源区上的第二源极，以及设置于所述第二栅导电层上的第二栅极。
结合第一方面或者第一方面的第一种可能的实现方式或者第一方面的第二种可能的实现方式，在第一方面的第三种可能的实现方式中，
所述隧穿场效应晶体管还包括：设置于所述第一漏区和所述第一源区之间的隔离浅槽。
结合第一方面或者第一方面的第一种可能的实现方式或者第一方面的第二种可能的实现方式，在第一方面的第四种可能的实现方式中，
所述衬底、所述第一漏区、所述第一源区、所述第二漏区、所述第二源区、所述第一外延层、所述第二外延层、所述第一沟道和所述第二沟道的材料均为硅、锗、锗硅或者三五族化合物；所述第一栅介质层和所述第二栅介质层的材料为二氧化硅、氮化硅或者高介电材料，所述第一栅导电层和所述第二栅导电层的材料为多晶硅、氮化钛或者金属材料。
第二方面，本发明实施例提供一种互补隧穿场效应晶体管的制作方法，该制作方法包括：
衬底；在所述衬底上依次沉积第一掺杂层，沟道层和第二掺杂 层，所述第一掺杂层包括第一掺杂物，所述第二掺杂层包括第二掺杂物；对所述第二掺杂层、所述沟道层和所述第一掺杂层进行刻蚀，形成第二源区、第二漏区、第一沟道、第二沟道、第一漏区和第一源区，所述第一沟道位于所述第一漏区上，所述第二源区位于所述第一沟道上，所述第二沟道位于所述第一源区上，所述第二漏区位于所述第二沟道上；在所述第二源区、所述第一漏区、所述第一源区和所述第二漏区上依次沉积外延层和栅堆叠层；对所述栅堆叠层和所述外延层进行刻蚀，依次形成第一栅堆叠层、第二栅堆叠层、第一外延层和第二外延层，所述第一栅堆叠层位于所述第一外延层的上方，所述第二栅堆叠层位于所述第二外延层的上方，所述第一外延层覆盖所述第一沟道和所述第二源区的侧墙，所述第二外延层覆盖所述第二沟道和所述第二漏区的侧墙；其中，所述第一漏区、所述第一沟道、所述第二源区、所述第一外延层和所述第一栅堆叠层形成第一隧穿场效应晶体管，所述第二漏区、所述第二沟道、所述第一源区、所述第二外延层和所述第二栅堆叠层形成第二隧穿场效应晶体管。
结合第二方面，在第二方面的第一种可能的实现方式中，
所述第一掺杂物为P型掺杂物，所述第二掺杂物为N型掺杂物，或者所述第一掺杂物为N型掺杂物，所述第二掺杂物为P型掺杂物；所述第一掺杂物和所述第二掺杂物的杂质浓度在每立方厘米1019个到每立方厘米1021个的范围内；所述第一沟道和所述第二沟道为轻掺杂层或者第一绝缘层，所述轻掺杂层中杂质的浓度小于等于每立方厘米1015个。
结合第二方面或者第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，
所述第一栅堆叠层包括第一栅介质层和第一栅导电层；所述第二栅堆叠层包括第二栅介质层和第二栅导电层；在对所述栅堆叠层和所述外延层进行刻蚀，依次形成第一栅堆叠层、第二栅堆叠层、第一外延层和第二外延层之后，所述制作方法还包括：在所述第二 源区和所述第一漏区上设置第一隔离物，以及在所述第一源区和所述第二漏区上设置第二隔离物，所述第一隔离物与所述第一外延层和所述第一栅堆叠层相接触，所述第二隔离物与所述第二外延层和所述第二栅堆叠层相接触；在所述第二源区、所述第一栅堆叠层、所述第一漏区、所述第一源区、所述第二栅堆叠层和所述第二漏区上设置第二绝缘层；对所述第二绝缘层进行刻蚀，并在所述第一漏区上形成第一漏极，在所述第二源区上形成第一源极，在所述第一栅导电层上形成第一栅极，在所述第二漏区上形成第二漏极，在所述第一源区上形成第二源极，以及在所述第二栅导电层上形成第二栅极。
结合第二方面或者第二方面的第一种可能的实现方式或者第二方面的第二种可能的实现方式，在第二方面的第三种可能的实现方式中，
在所述衬底上沉积所述第一掺杂层之后，且在沉积所述沟道层之前，所述制作方法还包括：在所述第一掺杂层上设置隔离浅槽，所述隔离浅槽位于所述第一漏区和所述第一源区之间。
结合第二方面或者第二方面的第一种可能的实现方式或者第二方面的第二种可能的实现方式，在第二方面的第四种可能的实现方式中，
所述衬底、所述第一漏区、所述第一源区、所述第二漏区、所述第二源区、所述第一外延层、所述第二外延层、所述第一沟道和所述第二沟道的材料均为硅、锗、锗硅或者三五族化合物；所述第一栅介质层和所述第二栅介质层的材料为二氧化硅、氮化硅或高介电材料，所述第一栅导电层和所述第二栅导电层的材料为多晶硅、氮化钛或者金属材料。
本发明实施例提供一种互补隧穿场效应晶体管及其制作方法，该互补隧穿场效应晶体管包括：设置于衬底上的第一漏区和第一源区，第一漏区和第一源区包括第一掺杂物；设置于第一漏区上的第一沟道和设置于第一源区上的第二沟道；设置于第一沟道上的第二 源区和设置于第二沟道上的第二漏区，第二源区和第二漏区包括第二掺杂物；设置于第一漏区和第二源区上的第一外延层，以及设置于第二漏区和第一源区上的第二外延层，第一外延层覆盖第一沟道和第二源区的侧墙，第二外延层覆盖第二沟道和第二漏区的侧墙；设置于第一外延层上的第一栅堆叠层，以及设置于第二外延层上的第二栅堆叠层；其中，第一漏区、第一沟道、第二源区、第一外延层和第一栅堆叠层形成第一隧穿场效应晶体管，第二漏区、第二沟道、第一源区、第二外延层和第二栅堆叠层形成第二隧穿场效应晶体管。
基于上述实施例的描述，本发明实施例提供的互补隧穿场效应晶体管包括第一隧穿场效应晶体管和第二隧穿场效应晶体管，其中，第一隧穿场效应晶体管包括第一漏区、第一沟道、第二源区、第一外延层和第一栅堆叠层，第二隧穿场效应晶体管包括第二漏区、第二沟道、第一源区、第二外延层和第二栅堆叠层，并且第一漏区和第一源区包括第一掺杂物，第二源区和第二漏区包括第二掺杂物。由于第一源区和第一漏区、第二源区和第二漏区分别是通过对半导体材料的一次沉积刻蚀形成的，且第一掺杂物和第二掺杂物是通过搅拌等手段掺杂在半导体材料中的，因此第一掺杂物和第二掺杂物是均匀分布的，而不是像现有技术中通过离子注入的掺杂物是高斯分布的，因而可以使得第二源区和第一外延层之间以及第一源区和第二外延层之间的杂质浓度在较短距离内发生突变，从而增加载流子的隧穿效率，提高隧穿场效应晶体管的性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中隧穿场效应晶体管的结构示意图；
图2为本发明实施例提供的一种互补隧穿场效应晶体管的结构示意图一；
图3为本发明实施例提供的一种互补隧穿场效应晶体管的结构示意图二；
图4为本发明实施例提供的一种互补隧穿场效应晶体管的结构示意图三；
图5为本发明实施例提供的一种互补隧穿场效应晶体管的结构示意图四；
图6为本发明实施例提供的一种互补隧穿场效应晶体管的结构示意图五；
图7为本发明实施例提供的一种互补隧穿场效应晶体管的制作方法的流程示意图；
图8为本发明实施例提供的一种互补隧穿场效应晶体管的制作流程示意图一；
图9为本发明实施例提供的一种互补隧穿场效应晶体管的制作流程示意图二；
图10为本发明实施例提供的一种互补隧穿场效应晶体管的制作流程示意图三；
图11为本发明实施例提供的一种互补隧穿场效应晶体管的制作流程示意图四；
图12为本发明实施例提供的一种互补隧穿场效应晶体管的制作流程示意图五；
图13为本发明实施例提供的一种互补隧穿场效应晶体管的制作流程示意图六；
图14为本发明实施例提供的一种互补隧穿场效应晶体管的制作流程示意图七；
图15为本发明实施例提供的一种互补隧穿场效应晶体管的制作流程示意图八；
图16为本发明实施例提供的一种互补隧穿场效应晶体管的制 作方法的流程示意图九。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
实施例一
本发明实施例提供一种互补隧穿场效应晶体管，如图2所示为该隧穿场效应晶体管的结构示意图。
该隧穿场效应晶体管包括：衬底10；设置于衬底10上的第一漏区20a和第一源区20b，第一漏区20a和第一源区20b包括第一掺杂物；设置于第一漏区20a上的第一沟道30a和设置于第一源区20b上的第二沟道30b；设置于第一沟道30a上的第二源区40a和设置于第二沟道30b上的第二漏区40b，第二源区40a和第二漏区40b包括第二掺杂物；设置于第一漏区20a和第二源区40a上的第一外延层50a，以及设置于第二漏区40b和第一源区20b上的第二外延层50b，第一外延层50a覆盖第一沟道30a和第二源区40a的侧墙，第二外延层50b覆盖第二沟道30b和第二漏区40b的侧墙；设置于第一外延层50a上的第一栅堆叠层60a，以及设置于第二外延层50b上的第二栅堆叠层60b。
其中，第一漏区20a、第一沟道30a、第二源区40a、第一外延层50a和第一栅堆叠层60a形成第一隧穿场效应晶体管，第二漏区40b、第二沟道30b、第一源区20b、第二外延层50b和第二栅堆叠层60b形成第二隧穿场效应晶体管。
需要说明的是，第一掺杂物为P型掺杂物，第二掺杂物为N型掺杂物，或者第一掺杂物为N型掺杂物，第二掺杂物为P型掺杂物。
进一步的，若第一掺杂物为N型掺杂物，第二掺杂物为P型掺杂物，则第一隧穿场效应晶体管为N型隧穿场效应晶体管，第二隧穿场效应晶体管为P型隧穿场效应晶体管；若第一掺杂物为P型掺杂物，第二掺杂物为N型掺杂物，则第一隧穿场效应晶体管为P型 隧穿场效应晶体管，第二隧穿场效应晶体管为N型隧穿场效应晶体管。
需要说明的是，第一漏区20a、第一源区20b、第二源区40a和第二漏区40b为重掺杂，可以理解为第一漏区20a和第一源区20b中包括的第一掺杂物以及第二源区40a和第二漏区40b中包括的第二掺杂物的杂质浓度在每立方厘米1019个到每立方厘米1021个的范围内；第一沟道30a和第二沟道30b为轻掺杂层或者第一绝缘层。
需要说明的是，轻掺杂层可以理解为在半导体薄膜中均匀加入杂质，且杂质的浓度小于等于每立方厘米1015个。其中，半导体薄膜的材料为锗、硅、锗硅或者三五族化合物。第一沟道30a和第二沟道30b也可以为第一绝缘层，第一沟道30a和第二沟道30b的厚度为几十纳米至几百纳米。还需要补充的是，轻掺杂层中的杂质可以为施主杂质或者受主杂质，本发明对此不做限制。
还需要补充的是，衬底10为半导体衬底，衬底10的具体材料可以为锗、硅、锗硅或者三五族化合物。第一外延层50a和第二外延层50b为轻掺杂的半导体薄膜，半导体薄膜的材料为锗、硅、锗硅或者三五族化合物。轻掺杂是指加入的杂质浓度小于等于每立方厘米1015个。第一外延层50a和第二外延层50b的厚度在1纳米到10纳米之间。
需要说明的是，第一栅堆叠层60a包括第一栅介质层和第一栅导电层；第二栅堆叠层60b包括第二栅介质层和第二栅导电层，其中，第一栅导电层位于第一栅介质层的上方，第二栅导电层位于第二栅介质层的上方。第一栅介质层和第二栅介质层的材料可以为二氧化硅、氮化硅、高介电材料等绝缘材料。第一栅导电层和第二栅导电层的材料可以为多晶硅、氮化钛或者金属等导电材料，第一栅导电层和第二栅导电层的厚度为几十纳米。
进一步的，该互补隧穿场效应晶体管还包括：设置于第二源区40a和第一漏区20a上的第一隔离物70a，以及设置于第一源区20b和第二漏区40b上的第二隔离物70b，第一隔离物70a与第一外延层 50a和第一栅堆叠层60a相接触，第二隔离物70b与第二外延层50b和第二栅堆叠层60b相接触。
需要补充的是，第一隔离物70a和第二隔离物70b的材料可以为二氧化硅、氮化硅、高介电材料等绝缘材料。
进一步的，如图3所示，该隧穿场效应晶体管还包括：设置于第二源区40a、第一栅堆叠层60a、第一漏区20a、第一源区20b、第二栅堆叠层60b和第二漏区40b上的第二绝缘层80，第二绝缘层80为低介电材料等绝缘材料。
进一步的，该互补隧穿场效应晶体管还包括：设置于第一漏区20a上的第一漏极ad，设置于第二源区40a上的第一源极as，以及设置于第一栅导电层上的第一栅极ag；设置于第二漏区40b上的第二漏极bd，设置于第一源区20b上的第二源极bs，以及设置于第二栅导电层上的第二栅极bg。其中，第一漏极ad、第二源极bs、第一栅极ag、第一源极as、第二漏极bd和第二栅极bg互不接触，且可以都为金属电极。
优选的，本发明实施例提供的N型隧穿场效应晶体管和P型隧穿场效应晶体管结合的互补型隧穿场效应晶体管，如图3所示，还包括：设置于衬底10上的隔离浅槽I，隔离浅槽I位于第一漏区20a和第一源区20b之间，因为第一漏区20a和第一源区20b都包括第一掺杂物，所以隔离浅槽I用于隔离相邻的第一漏区20a和第一源区20b。
进一步的，本发明实施例中提供的互补隧穿场效应晶体管采用线隧穿的工作机制。所谓线隧穿的工作机制是指载流子的隧穿方向和栅电场的方向平行，栅控能力比较强，并且隧穿电流的大小可以通过栅区和源区的重叠面积进行调控。
晶体管的开态电流由源区和外延层构成的隧穿结来提供。具体的，N型隧穿场效应晶体管的开态电流由其源区的电子向与源区接触的外延层隧穿形成，而P型隧穿场效应晶体管的开态电流由其源区的空穴向与源区接触的外延层隧穿形成。由于线隧穿机制能够提 高载流子的隧穿几率以及开态电流在一定范围内线性可调等优势，本发明提供的互补隧穿场效应晶体管具有更高的开态电流、更小的亚阈值摆幅以及更大的电流调节自由度。
还需要补充的是，通常情况下，与MOSFET相似，P型隧穿场效应晶体管的电流驱动能力要弱于N型隧穿场效应晶体管的电流驱动能力。本发明实施例提供的互补型隧穿场效应晶体管可以通过增加P型隧穿场效应晶体管的隧穿结的面积，来增大P型隧穿场效应晶体管的开态电流，从而实现与N型隧穿场效应晶体管的开态电流匹配。
以图3所示的互补型隧穿场效应晶体管为例，通过增加P型隧穿场效应晶体管的隧穿结的面积，来增大P型隧穿场效应晶体管的开态电流，实现与N型隧穿场效应晶体管开态电流的匹配，得到的互补隧穿场效应晶体管的结构示意图如图4所示。
具体的在P型隧穿场效应晶体管的部分对其第一源区，进行一定程度的过刻蚀形成L型的表面，如图4中E所示，从而增加P型隧穿场效应晶体管的隧穿结面积，增大P型隧穿场效应晶体管的开态电流，实现与N型隧穿场效应晶体管开态电流的匹配。
需要补充的是，互补型隧穿场效应晶体管中N型隧穿场效应晶体管和P型隧穿场效应晶体管的位置可以互换，当N型隧穿场效应晶体管和P型隧穿场效应晶体管的位置互换时，其对应的电极也进行相应的改变。
当P型隧穿场效应晶体管位于如图3所示的N型隧穿场效应晶体管的位置时，可以通过增加第二源区的厚度来增加P型隧穿场效应管的隧穿结面积，从而增加P型隧穿场效应晶体管的开态电流。
示例性的，如图5所示，可以将本发明实施例提供的隧穿场效应晶体管的结构制作成只含有N型隧穿场效应晶体管，包括衬底10，设置于衬底10上的第一漏区20a，设置于第一漏区上的第一沟道30a，设置于第一沟道30a上的第二源区40a，设置于第一漏区20a和第二源区40a上的第一外延层50a，第一外延层50a覆盖第二源区 40a和第一沟道30a的侧墙，设置于第一外延层50a上的第一栅堆叠层60a，设置于第一漏区20a和第二源区40a上的第一隔离物70a，第一隔离物70a与第一外延层50a和第一栅堆叠层60a接触，设置于第一漏区20a、第二源区40a、第一隔离物70a和第一栅堆叠层60a上的第二绝缘层80，以及设置于第一漏区20a上的第一漏极ad，设置于第一栅导电层上的第一栅极ag，设置于第二源区40a上的第一源极as。
或者，如图6所示，可以将本发明实施例提供的隧穿场效应晶体管的结构制作成只含有P型隧穿场效应晶体管，包括衬底10，设置于衬底10上的第一源区20b，设置于第一源区20b上的第二沟道30b，设置于第二沟道30b上的第二漏区40b，设置于第一源区20b和第二漏区40b上的第二外延层50b，第二外延层50b覆盖第二漏区40b和第二沟道30b的侧墙，设置于第二外延层50b上的第二栅堆叠层60b，设置于第一源区20b和第二漏区40b上的第二隔离物70b，第二隔离物70b与第二外延层50b和第二栅堆叠层60b接触，设置于第一源区20b、第二漏区40b、第二隔离物70b和第二栅堆叠层60b上的第二绝缘层80，以及设置于第一源区20b上的第二源极bs，设置于第二栅导电层上的第二栅极bg，设置于第二漏区40b上的第二漏极bd。
本发明实施例提供了一种互补隧穿场效应晶体管，该互补隧穿场效应晶体管包括第一隧穿场效应晶体管和第二隧穿场效应晶体管，其中，第一隧穿场效应晶体管包括第一漏区、第一沟道、第二源区、第一外延层和第一栅堆叠层，第二隧穿场效应晶体管包括第二漏区、第二沟道、第一源区、第二外延层和第二栅堆叠层，并且第一漏区和第一源区包括第一掺杂物，第二源区和第二漏区包括第二掺杂物。由于在第一隧穿场效应晶体管中的第一漏区和第二源区以及在第二隧穿场效应晶体管中的第一源区和第二漏区中的掺杂物是均匀分布的，而不是像现有技术中离子注入的掺杂物是高斯分布的，因而可以使得第二源区和第一外延层之间以及第一源区和第二 外延层之间的杂质浓度在较短距离内发生突变，从而增加载流子的隧穿效率，提高隧穿场效应晶体管的性能。
实施例二
本发明实施例提供一种互补隧穿场效应晶体管的制作方法，如图7所示，为该制作方法的流程示意图。
S101、在衬底上沉积第一掺杂层。
如图8所示为衬底10。需要补充的是，衬底10可以为半导体衬底，衬底10的具体材料可以为锗、硅、锗硅或者三五族化合物。
如图9所示，在衬底10上沉积第一掺杂层20。
需要说明的是，第一掺杂层20包括第一掺杂物，第一掺杂物是掺杂在半导体薄膜中的，第一掺杂物的浓度高于每立方厘米1019个，介于每立方厘米1019个到每立方厘米1021个之间。其中，半导体薄膜的材料为锗、硅、锗硅或者三五族化合物，本发明对此不做限制。
需要补充的是，第一掺杂层的厚度为几十纳米至几百纳米。
S102、在第一掺杂层上设置隔离浅槽。
需要说明的是，本发明实施例提供的互补隧穿场效应晶体管的制作方法，如图10所示，在衬底10上形成第一掺杂层20之后，该制作方法还包括：在第一掺杂层20上设置隔离浅槽I。其中，隔离浅槽I位于第一漏区20a和第一源区20b之间。隔离浅槽I的底部等于或低于第一掺杂层20的底部。
需要补充的是，隔离浅槽I是可选的，即不设置隔离浅槽I时，可以通过刻蚀工艺将第一掺杂层进行刻断，并填充第二绝缘层对第一漏区20a和第一源区20b进行隔离。
S103、在第一掺杂层上沉积沟道层。
如图11所示，在第一掺杂层上形成沟道层30。
需要说明的是，沟道层30为轻掺杂层或者第一绝缘层，轻掺杂可以理解为在半导体薄膜中均匀加入杂质，且杂质的浓度小于等于每立方厘米1015个。其中，半导体薄膜的材料为锗、硅、锗硅或者三五族化合物。沟道层30也可以为第一绝缘层，本发明对此不做限制。
需要补充的是，沟道层30的厚度为几十纳米至几百纳米。
S104、在沟道层上沉积第二掺杂层。
如图11所示，在沟道层30上沉积第二掺杂层40。
需要说明的是，第二掺杂层40包括第二掺杂物，第二掺杂物是掺杂在半导体薄膜中的，第二掺杂物的浓度高于每立方厘米1019个，介于每立方厘米1019个到每立方厘米1021个之间。其中，半导体薄膜的材料为锗、硅、锗硅或者三五族化合物。
需要补充的是，第二掺杂层40的厚度为几十纳米至几百纳米。
结合光刻和刻蚀工艺，如图12所示，去除中间部分的沟道层30和第二掺杂层40，形成第二源区40a、第二漏区40b、第一沟道30a、第二沟道30b，第一沟道30a位于第一漏区上20a，第二源区40a位于第一沟道30a上，第二沟道30b位于第一源区20b上，第二漏区40b位于第二沟道30b上。
S105、在第二源区、第一漏区、第一源区和第二漏区上沉积外延层。
如图13所示，在第二源区40a、第一漏区20a、第一源区20b和第二漏区40b上沉积外延层50。
需要说明的是，外延层50为轻掺杂的半导体薄膜，半导体薄膜的材料为锗、硅、锗硅或者三五族化合物。轻掺杂是指加入的杂质浓度小于等于每立方厘米1015个。
需要补充的是，外延层50的厚度在1纳米到10纳米之间。
S106、在外延层上沉积栅介质层。
如图13所示，在外延层50上沉积栅介质层。
需要说明的是，栅介质层的材料可以为二氧化硅、氮化硅、高介电材料等绝缘材料。
S107、在栅介质层上沉积栅导电层。
如图13所示，在栅介质层上沉积栅导电层，栅介质层和栅导电层组成栅堆叠层60。
栅导电层的材料可以为多晶硅、氮化钛或者金属等导电材料， 栅导电层的厚度为几十纳米。需要说明的是，如图14所示，在栅介质层上形成栅导电层后，通过刻蚀工艺形成第一隧穿场效应晶体管的第一外延层50a和第一栅堆叠层60a以及第二隧穿场效应晶体管的第二外延层50b和第二栅堆叠层60b，第一栅堆叠层60a位于第一外延层50a的上方，第二栅堆叠层60b位于第二外延层50b的上方，第一外延层50a覆盖第一沟道30a和第二源区40a的侧墙，第二外延层50b覆盖第二沟道30b和第二漏区40b的侧墙。
需要说明的是，本发明实施例中所说的外延层50包括第一外延层50a和第二外延层50b，即对外延层50进行部分刻蚀从而形成第一外延层50a和第二外延层50b。同理，栅介质层与第一栅介质层和第二栅介质层，栅导电层与第一栅导电层和第二栅导电层的关系也是如此。
其中，第一漏区20a、第一沟道30a、第二源区40a、第一外延层50a和第一栅堆叠层60a形成第一隧穿场效应晶体管，第二漏区40b、第二沟道30b、第一源区20b、第二外延层50b和第二栅堆叠层60形成第二隧穿场效应晶体管。
需要说明的是，第一掺杂物为P型掺杂物，第二掺杂物为N型掺杂物，或者第一掺杂物为N型掺杂物，第二掺杂物为P型掺杂物。
进一步的，若第一掺杂物为N型掺杂物，第二掺杂物为P型掺杂物，则第一隧穿场效应晶体管为N型隧穿场效应晶体管，第二隧穿场效应晶体管为P型隧穿场效应晶体管；若第一掺杂物为P型掺杂物，第二掺杂物为N型掺杂物，则第一隧穿场效应晶体管为P型隧穿场效应晶体管，第二隧穿场效应晶体管为N型隧穿场效应晶体管。
S108、在第二源区和第一漏区上设置第一隔离物，在第一源区和第二漏区上设置第二隔离物。
如图14所示，在第二源区40a和第一漏区20a上设置第一隔离物70a，在第一源区20b和第二漏区40b上设置第二隔离物70b。
其中，第一隔离物70a与第一外延层50a和第一栅堆叠层60a 相接触，第二隔离物70b与第二外延层50b和第二栅堆叠层60b相接触；需要补充的是，第一隔离物70a和第二隔离物70b的材料均为二氧化硅、氮化硅、高介电材料等绝缘材料。
S109、在第二源区、第一栅堆叠层、第一漏区、第一源区、第二栅堆叠层和第二漏区上设置第二绝缘层。
如图15所示，在第二源区40a、第一栅堆叠层60a、第一漏区20a、第一源区20b、第二栅堆叠层60b和第二漏区40b上设置第二绝缘层80。
具体的，形成第二绝缘层80的过程为填充低介电材料等绝缘材料。
S110、对第二绝缘层进行刻蚀，并在第一漏区上形成第一漏极，在第二源区上形成第一源极，在第一栅导电层上形成第一栅极，在第二漏区上形成第二漏极，在第一源区上形成第二源极，以及在第二栅导电层上形成第二栅极。
需要说明的是，在设置了第二绝缘层80之后，通过光刻和刻蚀工艺制作金属电极接触窗口，对金属电极接触窗口沉积金属，并通过剥离技术制作晶体管的源极、漏极和栅极的金属电极。
具体的，如图16所示，在第一漏区20a上形成第一漏极ad，在第二源区40a上形成第一源极as，以及在第一栅导电层上形成第一栅极ag；在第二漏区40b上形成第二漏极bd，在第一源区20b上形成第二源极bs，以及在第二栅导电层上形成第二栅极bg。其中，第一漏极ad、第二源极bs、第一栅极ag、第二源极bs、第二漏极bd和第二栅极bg互不接触，且可以都为金属电极。
根据本发明实施例提供的制作方法制作的隧穿场效应晶体管，可以为N型隧穿场效应晶体管(NTFET)、P型隧穿场效应晶体管(PTFET)或者N型隧穿场效应晶体管和P型隧穿场效应晶体管相结合的互补型隧穿场效应晶体管，本发明对此不做限制。
进一步的，本发明实施例中提供的隧穿场效应晶体管采用线隧穿的工作机制来工作。所谓线隧穿机制是指载流子的隧穿方向和栅 电场的方向平行，栅控能力比较强，并且隧穿电流的大小可以通过栅区和源区的重叠面积进行调控。
无论是N型隧穿场效应晶体管还是P型隧穿场效应晶体管，晶体管的开态电流由源区和外延层构成的隧穿结来提供。具体的，N型隧穿场效应晶体管的开态电流由其源区的电子向与源区接触的外延层隧穿形成，而P型隧穿场效应晶体管的开态电流由其源区的空穴向与源区接触的外延层隧穿形成。由于线隧穿机制能够提高载流子的隧穿几率以及开态电流在一定范围内线性可调等优势，本发明提供的隧穿场效应晶体管具有更高的开态电流、更小的亚阈值摆幅以及更大的电流调节自由度。
还需要补充的是，通常情况下，与MOSFET相似，P型隧穿场效应晶体管的电流驱动能力要弱于N型隧穿场效应晶体管的电流驱动能力。本发明实施例提供的互补型隧穿场效应晶体管还可以通过增加P型隧穿场效应晶体管的隧穿结的面积，增大P型隧穿场效应晶体管的开态电流，实现与N型隧穿场效应晶体管开态电流的匹配。
具体的，在P型隧穿场效应晶体管的部分对其第一源区，进行一定程度的过刻蚀形成L型的表面，从而增加P型隧穿场效应晶体管的隧穿结面积，增大P型隧穿场效应晶体管的开态电流，实现与N型隧穿场效应晶体管开态电流的匹配。
本发明实施例提供一种隧穿场效应晶体管的制作方法，该制作方法包括：在衬底上依次沉积第一掺杂层，沟道层和第二掺杂层，第一掺杂层包括第一掺杂物，第二掺杂层包括第二掺杂物；对第二掺杂层、沟道层和第一掺杂层进行刻蚀，形成第二源区、第二漏区、第一沟道、第二沟道、第一漏区和第一源区，第一沟道位于第一漏区上，第二源区位于第一沟道上，第二沟道位于第一源区上，第二漏区位于第二沟道上；在第二源区、第一漏区、第一源区和第二漏区上依次沉积外延层和栅堆叠层；对栅堆叠层和外延层进行刻蚀，依次形成第一栅堆叠层、第二栅堆叠层、第一外延层和第二外延层，第一栅堆叠层位于第一外延层的上方，第二栅堆叠层位于第二外延 层的上方，第一外延层覆盖第一沟道和第二源区的侧墙，第二外延层覆盖第二沟道和第二漏区的侧墙；其中，第一漏区、第一沟道、第二源区、第一外延层和第一栅堆叠层形成第一隧穿场效应晶体管，第二漏区、第二沟道、第一源区、第二外延层和第二栅堆叠层形成第二隧穿场效应晶体管。
基于上述实施例的描述，采用本发明实施例提供的制作方法得到的互补隧穿场效应晶体管，包括第一隧穿场效应晶体管和第二隧穿场效应晶体管，其中，第一隧穿场效应晶体管包括第一漏区、第一沟道、第二源区、第一外延层和第一栅堆叠层，第二隧穿场效应晶体管包括第二漏区、第二沟道、第一源区、第二外延层和第二栅堆叠层，并且第一漏区和第一源区包括第一掺杂物，第二源区和第二漏区包括第二掺杂物。由于在第一隧穿场效应晶体管中的第一漏区和第二源区以及在第二隧穿场效应晶体管中的第一源区和第二漏区中的掺杂物是均匀分布的，而不是像现有技术中离子注入的掺杂物是高斯分布的，因而可以使得第二源区和第一外延层之间以及第一源区和第二外延层之间的杂质浓度在较短距离内发生突变，从而增加载流子的隧穿效率，提高隧穿场效应晶体管的性能。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (10)

  1. 一种互补隧穿场效应晶体管，其特征在于，包括：
    设置于衬底上的第一漏区和第一源区，所述第一漏区和所述第一源区包括第一掺杂物；
    设置于所述第一漏区上的第一沟道和设置于所述第一源区上的第二沟道；
    设置于所述第一沟道上的第二源区和设置于所述第二沟道上的第二漏区，所述第二源区和所述第二漏区包括第二掺杂物；
    设置于所述第一漏区和所述第二源区上的第一外延层，以及设置于所述第二漏区和所述第一源区上的第二外延层，所述第一外延层覆盖所述第一沟道和所述第二源区的侧墙，所述第二外延层覆盖所述第二沟道和所述第二漏区的侧墙；
    设置于所述第一外延层上的第一栅堆叠层，以及设置于所述第二外延层上的第二栅堆叠层；
    其中，所述第一漏区、所述第一沟道、所述第二源区、所述第一外延层和所述第一栅堆叠层形成第一隧穿场效应晶体管，所述第二漏区、所述第二沟道、所述第一源区、所述第二外延层和所述第二栅堆叠层形成第二隧穿场效应晶体管。
  2. 根据权利要求1所述的互补隧穿场效应晶体管，其特征在于，
    所述第一掺杂物为P型掺杂物，所述第二掺杂物为N型掺杂物，或者所述第一掺杂物为N型掺杂物，所述第二掺杂物为P型掺杂物；
    所述第一掺杂物和所述第二掺杂物的杂质浓度在每立方厘米1019个到每立方厘米1021个的范围内；所述第一沟道和所述第二沟道为轻掺杂层或者第一绝缘层，所述轻掺杂层中杂质的浓度小于等于每立方厘米1015个。
  3. 根据权利要求1所述的互补隧穿场效应晶体管，其特征在于，
    所述第一栅堆叠层包括第一栅介质层和第一栅导电层；所述第二栅堆叠层包括第二栅介质层和第二栅导电层；
    所述互补隧穿场效应晶体管还包括：
    设置于所述第二源区和所述第一漏区上的第一隔离物，以及设置于所述第一源区和所述第二漏区上的第二隔离物，所述第一隔离物与所述第一外延层和所述第一栅堆叠层相接触，所述第二隔离物与所述第二外延层和所述第二栅堆叠层相接触；
    设置于所述第二源区、所述第一栅堆叠层、所述第一漏区、所述第一源区、所述第二栅堆叠层和所述第二漏区上的第二绝缘层；
    设置于所述第一漏区上的第一漏极，设置于所述第二源区上的第一源极，以及设置于所述第一栅导电层上的第一栅极；
    设置于所述第二漏区上的第二漏极，设置于所述第一源区上的第二源极，以及设置于所述第二栅导电层上的第二栅极。
  4. 根据权利要求1-3中任意一项所述的互补隧穿场效应晶体管，其特征在于，所述互补隧穿场效应晶体管还包括：
    设置于所述第一漏区和所述第一源区之间的隔离浅槽。
  5. 根据权利要求1-3中任意一项所述的互补隧穿场效应晶体管，其特征在于，
    所述衬底、所述第一漏区、所述第一源区、所述第二漏区、所述第二源区、所述第一外延层、所述第二外延层、所述第一沟道和所述第二沟道的材料均为硅、锗、锗硅或者三五族化合物；
    所述第一栅介质层和所述第二栅介质层的材料为二氧化硅、氮化硅或者高介电材料，所述第一栅导电层和所述第二栅导电层的材料为多晶硅、氮化钛或者金属材料。
  6. 一种互补隧穿场效应晶体管的制作方法，其特征在于，包括：
    衬底；
    在所述衬底上依次沉积第一掺杂层，沟道层和第二掺杂层，所述第一掺杂层包括第一掺杂物，所述第二掺杂层包括第二掺杂物；
    对所述第二掺杂层、所述沟道层和所述第一掺杂层进行刻蚀，形成第二源区、第二漏区、第一沟道、第二沟道、第一漏区和第一源区，所述第一沟道位于所述第一漏区上，所述第二源区位于所述第一沟道上，所述第二沟道位于所述第一源区上，所述第二漏区位于所述第二 沟道上；
    在所述第二源区、所述第一漏区、所述第一源区和所述第二漏区上依次沉积外延层和栅堆叠层；
    对所述栅堆叠层和所述外延层进行刻蚀，依次形成第一栅堆叠层、第二栅堆叠层、第一外延层和第二外延层，所述第一栅堆叠层位于所述第一外延层的上方，所述第二栅堆叠层位于所述第二外延层的上方，所述第一外延层覆盖所述第一沟道和所述第二源区的侧墙，所述第二外延层覆盖所述第二沟道和所述第二漏区的侧墙；
    其中，所述第一漏区、所述第一沟道、所述第二源区、所述第一外延层和所述第一栅堆叠层形成第一隧穿场效应晶体管，所述第二漏区、所述第二沟道、所述第一源区、所述第二外延层和所述第二栅堆叠层形成第二隧穿场效应晶体管。
  7. 根据权利要求6所述的制作方法，其特征在于，
    所述第一掺杂物为P型掺杂物，所述第二掺杂物为N型掺杂物，或者所述第一掺杂物为N型掺杂物，所述第二掺杂物为P型掺杂物；
    所述第一掺杂物和所述第二掺杂物的杂质浓度在每立方厘米1019个到每立方厘米1021个的范围内；所述第一沟道和所述第二沟道为轻掺杂层或者第一绝缘层，所述轻掺杂层中杂质的浓度小于等于每立方厘米1015个。
  8. 根据权利要求6所述的制作方法，其特征在于，
    所述第一栅堆叠层包括第一栅介质层和第一栅导电层；所述第二栅堆叠层包括第二栅介质层和第二栅导电层；
    在对所述栅堆叠层和所述外延层进行刻蚀，依次形成第一栅堆叠层、第二栅堆叠层、第一外延层和第二外延层之后，所述制作方法还包括：
    在所述第二源区和所述第一漏区上设置第一隔离物，以及在所述第一源区和所述第二漏区上设置第二隔离物，所述第一隔离物与所述第一外延层和所述第一栅堆叠层相接触，所述第二隔离物与所述第二外延层和所述第二栅堆叠层相接触；
    在所述第二源区、所述第一栅堆叠层、所述第一漏区、所述第一源区、所述第二栅堆叠层和所述第二漏区上设置第二绝缘层；
    对所述第二绝缘层进行刻蚀，并在所述第一漏区上形成第一漏极，在所述第二源区上形成第一源极，在所述第一栅导电层上形成第一栅极，在所述第二漏区上形成第二漏极，在所述第一源区上形成第二源极，以及在所述第二栅导电层上形成第二栅极。
  9. 根据权利要求6-8中任意一项所述的制作方法，其特征在于，
    在所述衬底上沉积所述第一掺杂层之后，且在沉积所述沟道层之前，所述制作方法还包括：
    在所述第一掺杂层上设置隔离浅槽，所述隔离浅槽位于所述第一漏区和所述第一源区之间。
  10. 根据权利要求6-8中任意一项所述的制作方法，其特征在于，
    所述衬底、所述第一漏区、所述第一源区、所述第二漏区、所述第二源区、所述第一外延层、所述第二外延层、所述第一沟道和所述第二沟道的材料均为硅、锗、锗硅或者三五族化合物；
    所述第一栅介质层和所述第二栅介质层的材料为二氧化硅、氮化硅或高介电材料，所述第一栅导电层和所述第二栅导电层的材料为多晶硅、氮化钛或者金属材料。
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