WO2016074373A1 - 薄膜晶体管组件、阵列基板及其制作方法、和显示装置 - Google Patents

薄膜晶体管组件、阵列基板及其制作方法、和显示装置 Download PDF

Info

Publication number
WO2016074373A1
WO2016074373A1 PCT/CN2015/073341 CN2015073341W WO2016074373A1 WO 2016074373 A1 WO2016074373 A1 WO 2016074373A1 CN 2015073341 W CN2015073341 W CN 2015073341W WO 2016074373 A1 WO2016074373 A1 WO 2016074373A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
drain
source
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/073341
Other languages
English (en)
French (fr)
Inventor
孙双
张方振
牛菁
吕志军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/777,666 priority Critical patent/US9543443B2/en
Priority to EP15763182.1A priority patent/EP3200230B1/en
Publication of WO2016074373A1 publication Critical patent/WO2016074373A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Definitions

  • Embodiments of the present invention relate to a display device, and more particularly to a thin film transistor device, an array substrate, a method of fabricating the same, and a display device including the array substrate.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light
  • TFTs Thin film transistors
  • LTPS low temperature poly-Silicon
  • the electron mobility is increased by 100 times or more.
  • an electron mobility of 200 cm 2 /V-sec or more can effectively reduce the area of the thin film transistor, thereby increasing the aperture ratio of the display, and improving the brightness of the display while reducing the overall power consumption.
  • display devices using LTPS technology have faster response times, higher resolution, and better picture display quality.
  • a source, a drain, and a data line connected to a source of a thin film transistor are formed on a glass substrate, and a gate is formed at a source and Above the drain, the active layer is between the gate and the source and drain.
  • a light shielding layer is further provided between the active layer and the glass substrate for blocking the light introduced from the glass substrate from being irradiated onto the active layer to affect the electrical characteristics of the low temperature polysilicon film used to form the active layer.
  • a plurality of patterning processes are generally required to form a source drain, a light shielding layer, and a gate, respectively, and the mask used in each patterning process has a different pattern. Due to the high cost of the mask, the array substrate is prepared by multiple patterning processes, the process is complicated, and the development cost is high.
  • Embodiments of the present invention provide a thin film transistor device, an array substrate, a method of fabricating the same, and a display device including the same, which can reduce the number of patterning processes and reduce the number of masks used.
  • a thin film transistor assembly comprising: a thin film transistor; and a light shielding layer disposed between a source and a drain of the thin film transistor and configured to block light
  • the active layer of the thin film transistor is irradiated from the outside, wherein the light shielding layer is formed in the same layer as the source and the drain of the thin film transistor.
  • the light shielding layer and the source and drain of the thin film transistor are formed by the same material layer by one patterning process.
  • the thin film transistor is a top gate thin film transistor.
  • the active layer is formed of a polysilicon film.
  • an ohmic doping region is respectively provided at a portion of the active layer electrically connected to the source and the drain.
  • the thin film transistor is an N-type transistor.
  • a lightly doped drain region is further provided in the vicinity of the ohmic doping region.
  • an array substrate comprising: a substrate; and the thin film transistor assembly of any of the above embodiments, wherein the plurality of thin film transistors are formed on the substrate.
  • the light shielding layer and the source and the drain of the thin film transistor are formed in the same layer on the substrate.
  • the light shielding layer and the source and drain of the thin film transistor are formed by the same material layer on the substrate by one patterning process.
  • a source of each of the thin film transistors is connected to a corresponding data line, and a data line, a light shielding layer, a source, and a drain are formed on the same substrate In the layer.
  • a method of fabricating an array substrate comprising: a substrate; a plurality of top-gate thin film transistors formed on the substrate; and a plurality of light shielding layers, each A light shielding layer is disposed on the substrate between a source and a drain of the thin film transistor and configured to block light from illuminating an active layer of the corresponding thin film transistor from the substrate.
  • the method includes the steps of forming a source, a light shielding layer, and a drain which are sequentially spaced apart by a patterning process using a single mask on a substrate.
  • the following steps are further included:
  • the thin film transistor is a top gate thin film transistor, and the active layer is made of a low temperature polysilicon film.
  • the step of forming the sequentially spaced source, light shielding layer and drain by one patterning process using a single mask on the substrate comprises: using a single mask on the substrate once The patterning process forms a source, a light shielding layer, a drain, and a data line electrically connected to the source.
  • the step of forming a source, a light shielding layer, a drain, and a data line electrically connected to the source by a patterning process using a single mask on a substrate includes: Forming a metal thin film on the substrate; coating a photoresist layer on the metal thin film; using the first reticle having a pattern corresponding to the source, the light shielding layer, the drain, and the data line respectively The glue is exposed and developed; the metal film of the photoresist removal region is removed by an etching process; and the unremoved photoresist is stripped.
  • the active layer is formed by an ion implantation process. A portion electrically connected to the source and drain electrodes respectively forms an ohmic doping region.
  • the thin film transistor has a gate of an N-type structure, and after forming an ohmic doped region, a lightly doped drain region is formed in the vicinity of the ohmic doped region.
  • the step of electrically connecting the active layer to the source and the drain, respectively, by via holes formed in the first, second, and third insulating layers includes forming a pixel electrode electrically connected to the drain on the third insulating layer.
  • a display device comprising the array substrate of any of the above embodiments is provided.
  • the display device including the array substrate, the light shielding layer, the source and drain of the thin film transistor, and the data lines are formed in the same layer on the substrate
  • the same material can be formed by one patterning process, which reduces the number of patterning processes and reduces the number of masks used, thereby simplifying the fabrication process of the array substrate and reducing the manufacturing cost.
  • FIG. 1 is a partial cross-sectional view of an array substrate in accordance with an exemplary embodiment of the present invention
  • FIGS. 2a-2g are schematic diagrams of operational processes of a method of fabricating an array substrate in accordance with an exemplary embodiment of the present invention.
  • an array substrate includes: a substrate; a plurality of thin film transistors formed on the substrate; and a plurality of shading a layer, each light shielding layer being disposed on the substrate between a source and a drain of the thin film transistor and configured to block light from illuminating an active layer of a corresponding thin film transistor from a substrate; wherein the light shielding layer is The source and drain of the thin film transistor are formed in the same layer on the substrate.
  • the light shielding layer and the source and drain of the thin film transistor may be formed by the same material layer using a patterning process.
  • the source and the drain of the light shielding layer and the thin film transistor can be formed by one patterning process by using the same material, which reduces the number of patterning processes and reduces the number of masks used, thereby simplifying the fabrication process of the array substrate and saving.
  • the time and cost of transporting the glass substrate back and forth between various film devices reduces manufacturing costs.
  • an array substrate in accordance with an exemplary embodiment of the present invention includes a substrate 1, a plurality of thin film transistors, and a light shielding layer 2 made of, for example, glass or a transparent resin material.
  • the source 31 of each thin film transistor is electrically connected to a corresponding data line (not shown), the drain 32 is electrically connected to the pixel electrode 7, and the gate 33 is electrically connected to a gate line (not shown).
  • the thin film transistor may be a top gate thin film transistor, the gate 33 is located above the active layer 5, and a gate insulating layer is also disposed between the active layer 5 and the gate 33.
  • the second insulating layer 42 of the layer, that is, the gate electrode 33 is located upstream of the active layer 5 in a direction away from the substrate 1.
  • a thin film transistor is formed on the substrate 1.
  • Each of the light shielding layers 2 is formed on the substrate 1 and configured to block light, for example, generated by an external light source, from illuminating the active layer 5 of the corresponding thin film transistor from the substrate 1.
  • the light shielding layer 2 and the source 31 and the drain 32 of the thin film transistor are formed in the same layer on the substrate 1. This arrangement of the light shielding layer 2 can prevent the active layer 5 from undergoing a property change under the action of illumination, thereby improving the reliability of the device.
  • the light shielding layer 2 and the source 31 and the drain 32 of the thin film transistor are formed in the same layer on the substrate 1, so that the light shielding layer 2, the source 31 and the drain 32 can be
  • the same metal film is formed by one patterning process, thereby reducing the number of patterning processes and reducing the number of masks used.
  • the metal thin film may be made of molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or a copper metal, or may be made of a combination of the above materials.
  • the specific thickness and material of the metal film can be set as the case may be.
  • the light shielding layer 2 is disposed between the source 31 and the drain 32 and corresponds to the position of the active layer 5, and since the light introduced from the substrate 1 is blocked from being irradiated onto the active layer 5, the electricity of the active layer 5 can be maintained. Characteristics, which in turn improve the characteristics of thin film transistors.
  • the light shielding layer 2 is made of a chromium or molybdenum metal film.
  • the chrome or molybdenum metal film has good light blocking properties and etching properties, and can improve the performance of the array substrate.
  • Such an arrangement of the light shielding layer 2 can prevent the active layer 5 from undergoing a property change under the action of illumination, thereby improving the reliability of the device; and, since the light shielding layer 2, the source 31, and the drain 32 can be formed by one patterning process , reducing the number of patterning processes, reducing the number of masks used, simplifying process complexity and saving process time.
  • the active layer 5 of the thin film transistor is formed of a polysilicon film (for example, a low temperature poly-Silicon (LTPS) film), and thus the thin film transistor of the embodiment of the present invention is low temperature.
  • Polysilicon thin film transistor (LTPS-TFT) For example, the electron mobility in the active layer formed of the polysilicon film is 200 cm 2 /V-sec or more, thereby effectively reducing the area of the thin film transistor, thereby increasing the aperture ratio of the display, and improving the brightness of the display while Reduce overall power consumption.
  • the arrangement of the light shielding layer 2 can block the light introduced from the substrate 1 from being irradiated onto the active layer 5, so that the active layer 5 can be maintained. Electrical characteristics, which in turn improve the characteristics of thin film transistors.
  • the source 31 of each thin film transistor is connected to a corresponding data line (not shown), and the data line, the light shielding layer 2, the source 31, and the drain 32 are on the substrate 1.
  • the upper layer is formed in the same layer.
  • an ohmic doping region 61 is provided at a portion of the active layer 5 that is electrically connected to the source 31 and the drain 32, respectively.
  • the ohmic doping region 61 may be doped with, for example, a phosphorus or boron element, whereby the contact resistance between the source 31 and the drain 32 and the active layer 5 and the pixel electrode 7 can be reduced.
  • the thin film transistor may be a P-type transistor or an N-type transistor.
  • a Lightly Doped Drain (LDD) 62 is provided in the vicinity of the ohmic doping region 61 to prevent the hot electron degradation effect and improve the hot carrier lifetime of the thin film transistor.
  • LDD Lightly Doped Drain
  • a thin film transistor assembly including a thin film transistor and a light shielding layer 2 is provided.
  • the light shielding layer 2 is disposed between the source 31 and the drain 32 of the thin film transistor, and is configured to block light from externally illuminating the active layer 5 of the thin film transistor; wherein the light shielding layer 2 and the source 31 of the thin film transistor
  • the drain electrodes 32 are formed in the same layer.
  • FIG. 1 shows an embodiment in which the thin film transistor is a top gate thin film transistor, the present invention is not limited thereto.
  • the thin film transistor may be a bottom gate thin film transistor, and the light shielding layer 2 is disposed between the source 31 and the drain 32 of the thin film transistor.
  • the light shielding layer 2 and the source 31 and the drain 32 of the thin film transistor can be formed by one patterning process using the same material, reducing the number of patterning processes and reducing the number of masks used.
  • the light shielding layer is disposed between the source and the drain and corresponds to the position of the active layer, and the light introduced from the substrate is irradiated onto the active layer, thereby maintaining the electrical characteristics of the active layer, thereby improving the thin film transistor. characteristic.
  • a method of fabricating an array substrate may include: a substrate; a plurality of thin film transistors formed on the substrate; and a plurality of light shielding layers each disposed on the substrate between a source and a drain of the thin film transistor and An active layer configured to block light from illuminating the respective thin film transistor from the substrate.
  • the method of fabricating an array substrate includes the following steps: A source, a light shielding layer, and a drain which are sequentially spaced apart are formed by a patterning process on a substrate using a single mask. Thereafter, a first insulating layer covering the source, the light shielding layer, and the drain is formed on the substrate.
  • An active layer is formed on the first insulating layer.
  • a second insulating layer covering the active layer is formed on the first insulating layer.
  • An electrical connection of the active layer to the source and drain is achieved.
  • the source and the drain of the light shielding layer and the thin film transistor can be formed by one patterning process using the same material, for example, forming the light shielding layer and the source and the drain of the thin film transistor through the same material layer by one patterning process, thereby reducing the patterning.
  • the number of processes reduces the number of reticle used, which simplifies the fabrication process of the array substrate and reduces the manufacturing cost.
  • the array substrate includes: a substrate 1; a plurality of thin film transistors formed on the substrate 1, the thin film transistor may be, for example, a thin film transistor having a top gate structure; and a plurality of light shielding layers 2, each of which is disposed on the substrate 1
  • the source 31 and the drain 32 of the thin film transistor are configured to block light from the substrate 1 to illuminate the active layer 5 of the corresponding thin film transistor.
  • the method for fabricating an array substrate includes the step S100 of forming a source 31 sequentially spaced by a single patterning process on a substrate 1 made of, for example, glass or a transparent resin material, using a single mask (not shown).
  • Layer 2 and drain 32 see Figure 2a.
  • the source 31, the light shielding layer 2, the drain 32, and the data line electrically connected to the source 31 are formed by a patterning process on the substrate 1 using a single mask (not shown) ).
  • the patterning process mainly includes processes of substrate cleaning, film formation, photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the step of forming the source 31, the light shielding layer 2, the drain 32, and the data line electrically connected to the source 31 by one patterning process using a single mask on the substrate includes, for example, magnetron sputtering or thermal evaporation.
  • a metal thin film on the substrate 1 Forming a metal thin film on the substrate 1; coating a photoresist layer on the metal thin film; exposing the photoresist by using a first mask having a pattern corresponding to the source, the light shielding layer, the drain, and the data line, respectively, to Forming a photoresist retention region and a photoresist removal region; completely removing the photoresist in the photoresist removal region by development, completely retaining the photoresist in the photoresist retention region; and removing the photoresist by an etching process
  • the metal film of the region is removed; and the unremoved photoresist is stripped.
  • the residual photoresist can also be removed using an ashing process.
  • a source 31, a light shielding layer 2, a drain 32, and a data line may be formed on the substrate 1.
  • the metal thin film used in the step S100 may be made of molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or a copper metal, or may be made of a combination of the above materials.
  • the light shielding layer 2 is disposed between the source 31 and the drain 32 and corresponds to the position of the active layer 5, whereby the light shielding layer can block light introduced from the substrate 1 from being irradiated onto the active layer 5, thereby being able to remain used for The electrical characteristics of the polysilicon film of the active layer 5 are formed.
  • the light shielding layer 2 may be made of a chromium or molybdenum metal film.
  • the method for fabricating an array substrate according to an embodiment of the present invention further includes:
  • Step S200 forming a first insulation covering the source electrode 31, the light shielding layer 2 and the drain electrode 32 on the substrate 1 by, for example, a chemical vapor deposition (CVD) process.
  • Layer 41 and amorphous silicon film 51 are made of, for example, SiN (silicon nitride) or SiOx (silicon oxide).
  • the amorphous silicon film 51 is transformed into a low-temperature polysilicon film by forming an active layer 5 of a thin film transistor by performing an excimer laser annealing process on the amorphous silicon film 51.
  • the method for fabricating an array substrate according to an embodiment of the present invention may further include:
  • Step S300 forming a second insulating layer 42 covering the active layer 5 on the first insulating layer 41, for example, by a chemical vapor deposition process;
  • Step S400 forming a gate electrode 33 on the second insulating layer 42 by, for example, a patterning process
  • Step S500 forming a third insulating layer 43 covering the gate electrode 33 on the second insulating layer 42.
  • the method for fabricating an array substrate according to an embodiment of the present invention may further include S600: realizing the active layer 5 and the source 31 and the drain 32 through the via holes 9 formed in the first, second, and third insulating layers, respectively. Electrical connection.
  • the electron gun bombardment forms an ohmic doping region 61 at a portion of the active layer 5 to be electrically connected to the source 31 and the drain 32, respectively.
  • the ohmic doping region 61 is doped with, for example, phosphorus or boron, and the contact resistance between the source 31 and the drain 32 and the active layer 5 and the pixel electrode 7 can be reduced.
  • the thin film transistor may be a P-type transistor or an N-type transistor.
  • the thin film transistor is an N-type transistor, as shown in FIG. 2d, after the ohmic doping region 61 is formed, the active layer is lightly doped by ashing the photoresist to be doped in ohmic A lightly doped drain region 62 is formed near the region 61.
  • the lightly doped drain region 62 prevents thermal electron degradation effects and increases the hot carrier lifetime of the thin film transistor.
  • the electrical connection of the active layer 5 to the source 31 and the drain 32 is achieved by vias 9 formed in the first, second and third insulating layers, respectively.
  • the step may include forming a pixel electrode 7 electrically connected to the drain 32 on the third insulating layer 43.
  • a via hole 9 is formed in the first insulating layer 41, the second insulating layer 42, and the third insulating layer 43 by a patterning process; as shown in FIG. 2f, a sputtering process (Sputter) is employed.
  • the third insulating layer 43 and the via 9 are coated with a thin film of ITO film or other conductive material to realize electrical connection between the active layer 5 and the source 31 and the drain 32, and the image is formed by a patterning process using a mask.
  • the data line may be formed on the third insulating layer 43 and electrically connected to the source 31 by the one-time patterning process with the pixel electrode 7.
  • a fourth insulating layer 44 covering the pixel electrode 7 is formed on the third insulating layer 43 by, for example, a chemical vapor deposition process, and an ITO film is coated on the fourth insulating layer 44 by a sputtering process.
  • Other conductive material films are used and at least one common electrode 8 is formed by a patterning process.
  • the second insulating layer 42, the third insulating layer 43, and the fourth insulating layer 44 may each be made of, for example, SiN (silicon nitride) or SiOx (silicon oxide).
  • a buffer layer may be formed on the substrate 1 to help improve the surface flatness and adhesion of the substrate 1 before performing step S100, and also contribute to improvement of water vapor permeability resistance.
  • the buffer layer may be made of, for example, SiN (silicon nitride) or SiOx (silicon oxide).
  • a display device comprising the array substrate of any of the above embodiments.
  • the display device may be a liquid crystal display device. These liquid crystal display devices can realize a display function under the driving of a thin film transistor of an array substrate.
  • the array substrate of the embodiment of the present invention can be applied to an OLED (Organic Light Emitting Diode) display device and an AMOLED (Active Matrix Organic Light Emitting Diode). ) display device.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device including the array substrate, the light shielding layer, the source and drain of the thin film transistor, and the data lines are formed in the same layer on the substrate
  • the same material can be formed by one patterning process, which reduces the number of patterning processes and reduces the number of masks used, thereby simplifying the fabrication process of the array substrate and reducing the manufacturing cost.

Landscapes

  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种薄膜晶体管组件、阵列基板及其制作方法、和包括这种阵列基板的显示装置。阵列基板包括：基板(1)；多个薄膜晶体管，形成在基板(1)上；以及多个遮光层(2)，每个遮光层(2)在基板(1)上设置在薄膜晶体管的源极(31)和漏极(32)之间并被构造成用于阻挡光线从外部照射相应薄膜晶体管的有源层(5)。其中，遮光层(2)与薄膜晶体管的源极(31)和漏极(32)在基板(1)上形成在同一层中。可以利用相同的材料通过一次构图工艺形成遮光层、薄膜晶体管的源极和漏极、以及数据线，减少了构图工艺的次数和掩模板的使用数量，从而简化了阵列基板的制作工艺，降低了制作成本。

Description

薄膜晶体管组件、阵列基板及其制作方法、和显示装置 技术领域
本发明的实施例涉及一种显示装置，尤其涉及一种薄膜晶体管组件、阵列基板及其制作方法、和包括这种阵列基板的显示装置。
背景技术
目前在薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display(TFT-LCD))、有机发光二极体(Organic Light Emitting Diode(OLED))显示装置以及有源矩阵有机发光二极体(Active Matrix Organic Light Emitting Diode(AMOLED))显示装置中广泛采用的薄膜晶体管(TFT)主要包括非晶硅薄膜晶体管和多晶硅薄膜晶体管。其中，低温多晶硅(Low Temperature Poly-Silicon；LTPS)技术也已应用到薄膜晶体管显示器制造工艺中，其主要是通过准分子激光退火工艺(Excimer Laser Anneal)将非晶硅(a-Si)薄膜转变为多晶硅(Poly-Si)薄膜。相比非晶硅(a-Si)，在这样制成的多晶硅中，电子迁移率有100倍以上的增加。例如，电子迁移率达到200cm2/V-sec以上，可有效减小薄膜晶体管的面积，从而提高显示器的开口率，并且在增进显示器亮度的同时还可以降低整体的功耗。此外，采用LTPS技术的显示装置具有更快的响应时间，更高的分辨率，更佳的画面显示品质。
一般地，在利用这种多晶硅薄膜形成有源层的顶栅薄膜晶体管中，薄膜晶体管的源极、漏极、以及与源极连接的数据线形成在玻璃基板上，栅极形成在源极和漏极的上方，而有源层位于栅极和源漏极之间。另外，在有源层与玻璃基板之间还设有遮光层，用于阻挡从玻璃基板引入的光照射到有源层上从而影响用于形成有源层的低温多晶硅薄膜的电特性。在制作这种阵列基板的过程中，一般需要多个构图工艺分别形成源漏极、遮光层和栅极，每个构图工艺所采用的掩模板具有不同的图形。由于掩膜板造价昂贵，采用多次构图工艺制备阵列基板，工艺复杂，开发费用较高。
发明内容
本发明的实施例提供一种薄膜晶体管组件、阵列基板及其制作方法、和包括这种阵列基板的显示装置，可以减少了构图工艺的次数，减少了掩模板的使用数量。
根据本发明一个发明的实施例，提供一种薄膜晶体管组件，包括：薄膜晶体管；以及遮光层，所述遮光层布置在所述薄膜晶体管的源极和漏极之间并且被构造成能够阻挡光线从外部照射薄膜晶体管的有源层，其中，所述遮光层与薄膜晶体管的源极和漏极形成在同一层中。
在根据本发明的一种实施例的薄膜晶体管组件，通过一次构图工艺通过相同的材料层形成所述遮光层与薄膜晶体管的源极和漏极。
在根据本发明的一种实施例的薄膜晶体管组件，所述薄膜晶体管为顶栅式薄膜晶体管。
在根据本发明的一种实施例的薄膜晶体管组件，所述有源层由多晶硅薄膜形成。
在根据本发明的一种实施例的薄膜晶体管组件，在所述有源层的与所述源极和漏极电连接的部位分别设有欧姆掺杂区。
在根据本发明的一种实施例的薄膜晶体管组件，所述薄膜晶体管为N型晶体管。
在根据本发明的一种实施例的薄膜晶体管组件，在所述欧姆掺杂区附近还设有轻掺杂漏区。
根据本发明进一步方面的实施例，提供一种阵列基板，包括：基板；以及多个上述实施例中的任一项所述的薄膜晶体管组件，多个所述薄膜晶体管形成在所述基板上。其中，所述遮光层与薄膜晶体管的源极和漏极在所述基板上形成在同一层中。
在根据本发明的一种实施例的阵列基板中，在所述基板上通过一次构图工艺通过相同的材料层形成所述遮光层与薄膜晶体管的源极和漏极。
在根据本发明的一种实施例的阵列基板中，每个所述薄膜晶体管的源极与相应的数据线连接，并且数据线、遮光层、源极和漏极在所述基板上形成在同一层中。
根据本发明再一方面的实施例，提供一种制作阵列基板的方法，所述阵列基板包括：基板；多个顶栅式薄膜晶体管，形成在所述基板上；以及多个遮光层，每个遮光层在所述基板上设置在所述薄膜晶体管的源极和漏极之间并被构造成能够阻挡光线从基板照射相应薄膜晶体管的有源层。所述方法包括如下步骤：在基板上利用单个掩模板通过一次构图工艺形成依次间隔布置的源极、遮光层和漏极。
在根据本发明的一种实施例的方法中，在执行在基板上利用单个掩模板通过一次构图工艺形成依次间隔布置的源极、遮光层和漏极的步骤之后，还包括如下步骤：
在基板上形成覆盖所述源极、遮光层和漏极的第一绝缘层；
在所述第一绝缘层上形成有源层；
在所述第一绝缘层上形成覆盖所述有源层的第二绝缘层；
在所述第二绝缘层上形成栅极；
在第二绝缘层上形成覆盖所述栅极的第三绝缘层；以及
通过形成在所述第一、第二和第三绝缘层中的过孔分别实现所述有源层与源极和漏极的电连接。
在根据本发明的一种实施例的方法中，所述薄膜晶体管为顶栅式薄膜晶体管，所述有源层由低温多晶硅薄膜制成
在根据本发明的一种实施例的方法中，在基板上利用单个掩模板通过一次构图工艺形成依次间隔布置的源极、遮光层和漏极的步骤包括：在基板上利用单个掩模板通过一次构图工艺形成源极、遮光层、漏极以及与所述源极电连接的数据线。
在根据本发明的一种实施例的方法中，在基板上利用单个掩模板通过一次构图工艺形成源极、遮光层、漏极以及与所述源极电连接的数据线的步骤包括：在所述基板上形成金属薄膜；在所述金属薄膜上涂覆光刻胶层；利用具有与所述源极、遮光层、漏极以及数据线分别对应的图形的第一掩模板对所述光刻胶进行曝光和显影；采用刻蚀工艺，将光刻胶去除区的金属薄膜去除；以及将未去除的光刻胶剥离。
在根据本发明的一种实施例的方法中，在所述第一绝缘层上形成覆盖所述有源层的第二绝缘层和栅极之后，通过离子植入工艺在所述有源层的将与所述源极和漏极电连接的部位分别形成欧姆掺杂区。
在根据本发明的一种实施例的方法中，所述薄膜晶体管具有N型结构的栅极，在形成欧姆掺杂区之后，在所述欧姆掺杂区附近形成轻掺杂漏区。
在根据本发明的一种实施例的方法中，通过形成在所述第一、第二和第三绝缘层中的过孔分别实现所述有源层与源极和漏极的电连接的步骤包括：在所述第三绝缘层上形成与所述漏极电连接的像素电极。
根据本发明更进一步方面的实施例，提供一种显示装置，包括上述任一实施例所述的阵列基板。
根据本发明上述实施例的薄膜晶体管组件、阵列基板及其制作方法、包括这种阵列基板的显示装置，遮光层、薄膜晶体管的源极和漏极、以及数据线在基板上形成在同一层中，可以利用相同的材料通过一次构图工艺形成，减少了构图工艺的次数，减少了掩模板的使用数量，从而简化了阵列基板的制作工艺，降低了制作成本。
附图说明
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明，其中：
图1是根据本发明的一种示例性实施例的阵列基板的局部剖视示意图；以及
图2a-2g是根据本发明的一种示例性实施例的阵列基板的制作方法的操作过程示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。
根据本发明的各种示例性实施例的总体上的发明构思，提供一种阵列基板，包括：基板；多个薄膜晶体管，形成在所述基板上；以及多个遮光 层，每个遮光层在所述基板上设置在所述薄膜晶体管的源极和漏极之间并被构造成能够阻挡光线从基板照射相应薄膜晶体管的有源层；其中，所述遮光层与薄膜晶体管的源极和漏极在所述基板上形成在同一层中。可以利用一次构图工艺通过相同的材料层形成遮光层与薄膜晶体管的源极和漏极。这样，遮光层与薄膜晶体管的源极和漏极可以利用相同的材料通过一次构图工艺形成，减少了构图工艺的次数，减少了掩模板的使用数量，从而简化了阵列基板的制作工艺，节省了将玻璃基板在各种薄膜设备之间来回输送的时间和成本，降低了制作成本。
在下面的详细描述中,为便于解释,阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下,公知的结构和装置以图示的方式体现以简化附图。
图1是根据本发明的一种示例性实施例的阵列基板的局部剖视示意图。参见图1，根据本发明实施例的阵列基板，包括：由例如玻璃或者透明树脂材料制成的基板1、多个薄膜晶体管和遮光层2。每个薄膜晶体管的源极31与相应的数据线(未示出)电连接，漏极32与像素电极7电连接，栅极33与栅线(未示出)电连接。在本发明的一种实施例中，薄膜晶体管可以是顶栅式薄膜晶体管，栅极33位于有源层5的上方，且在有源层5和栅极33之间还设置有用做栅极绝缘层的第二绝缘层42，即栅极33在远离基板1的方向上位于有源层5的上游。
根据本发明的一个实施例，薄膜晶体管形成在基板1上。每个遮光层2形成在基板1上并被构造成用于阻挡例如由外部光源产生的光线从基板1照射相应薄膜晶体管的有源层5。遮光层2与薄膜晶体管的源极31和漏极32在基板1上形成在同一层中。遮光层2的这种布置可以防止有源层5在光照的作用下发生性质改变，从而提高了器件的可靠性。
在本发明的一个实施例的阵列基板中，遮光层2与薄膜晶体管的源极31和漏极32在基板1上形成在同一层中，这样，遮光层2、源极31和漏极32可以由同一金属薄膜通过一次构图工艺制成，从而减少了构图工艺的次数，减少了掩模板的使用数量。该金属薄膜可以利用由钼、铝、铝镍合金、钼钨合金、铬、或铜金属制成，也可以由上述几种材料的组合制成。 金属薄膜的具体厚度和材料可以根据具体情况设定。遮光层2设置在源极31和漏极32之间并与有源层5的位置相对应，由于阻挡从基板1引入的光照射到有源层5上，从而可以保持有源层5的电特性，进而提高薄膜晶体管的特性。例如，遮光层2由铬或者钼金属薄膜制成。铬或者钼金属薄膜的遮光性和刻蚀性能均较好，可以提高阵列基板的性能。遮光层2的这种布置可以防止有源层5在光照的作用下发生性质改变，从而提高了器件的可靠性；并且，由于可以通过一次构图工艺形成遮光层2、源极31和漏极32，减少了构图工艺的次数，减少了掩模板的使用数量，简化了工艺复杂度，节省工艺时间。
在本发明的一种示例性实施例中，薄膜晶体管的有源层5由多晶硅薄膜(例如低温多晶硅(Low Temperature Poly-Silicon；LTPS)薄膜)形成，因此本发明的实施例的薄膜晶体管为低温多晶硅薄膜晶体管(LTPS-TFT)。例如，由多晶硅薄膜形成的有源层中的电子迁移率达到200cm2/V-sec以上，因而可有效减小薄膜晶体管的面积，从而提高显示器的开口率，并且在增进显示器亮度的同时还可以降低整体的功耗。另外，由于多晶硅薄膜形成的有源层的电特性更容易受到光照的影响，而遮光层2的布置可以阻挡从基板1引入的光照射到有源层5上，从而可以保持有源层5的电特性，进而提高薄膜晶体管的特性。
在本发明的一种示例性实施例中，每个薄膜晶体管的源极31与相应的数据线(未示出)连接，并且数据线、遮光层2、源极31和漏极32在基板1上形成在同一层中。这样，可以进一步减少构图工艺的次数，降低掩模板的使用量，节省玻璃基板在多个工艺步骤的设备来回之间输送的时间。
在本发明的一种示例性实施例中，在有源层5的与源极31和漏极32电连接的部位分别设有欧姆掺杂区61。欧姆掺杂区61可以掺杂有例如磷或者硼元素，由此可以减小源极31和漏极32与有源层5和像素电极7之间的接触阻抗。薄膜晶体管可以为P型晶体管，也可以是N型晶体管。在N型晶体管的情况下，在欧姆掺杂区61附近还设有轻掺杂漏区(Lightly Doped Drain(LDD))62，以防止热电子退化效应，提高薄膜晶体管的热载流子寿命。
如图1所示，根据本发明的另一方面的实施例，提供一种薄膜晶体管组件，包括：薄膜晶体管以及遮光层2。遮光层2设置在薄膜晶体管的源极31和漏极32之间，并被构造成用于阻挡光线从外部照射薄膜晶体管的有源层5；其中，遮光层2与薄膜晶体管的源极31和漏极32形成在同一层中。
虽然图1示出了薄膜晶体管为顶栅式薄膜晶体管的实施例，但本发明并不局限于此。在本发明的一种可替换的实施例中，薄膜晶体管可以是底栅式薄膜晶体管，并且遮光层2设置在薄膜晶体管的源极31和漏极32之间。
根据本发明实施例的薄膜晶体管组件，遮光层2与薄膜晶体管的源极31和漏极32可以利用相同的材料通过一次构图工艺形成，减少了构图工艺的次数，减少了掩模板的使用数量，从而简化了薄膜晶体管组件的制作工艺，降低了制作成本。遮光层设置在源极和漏极之间并与有源层的位置相对应，由于阻挡从基板引入的光照射到有源层上，从而可以保持有源层的电特性，进而提高薄膜晶体管的特性。
根据本发明进一步方面的发明构思，提供一种制作阵列基板的方法。阵列基板可以包括：基板；多个薄膜晶体管，形成在所述基板上；以及多个遮光层，每个遮光层在所述基板上设置在所述薄膜晶体管的源极和漏极之间并被构造成用于阻挡光线从基板照射相应薄膜晶体管的有源层。制作阵列基板的方法包括如下步骤：。在基板上利用单个掩模板通过一次构图工艺形成依次间隔布置的源极、遮光层和漏极。之后，在基板上形成覆盖所述源极、遮光层和漏极的第一绝缘层。在所述第一绝缘层上形成有源层。在所述第一绝缘层上形成覆盖所述有源层的第二绝缘层。在所述第二绝缘层上形成栅极；在第二绝缘层上形成覆盖所述栅极的第三绝缘层；通过形成在所述第一、第二和第三绝缘层中的过孔分别实现所述有源层与源极和漏极的电连接。这样，遮光层与薄膜晶体管的源极和漏极可以利用相同的材料通过一次构图工艺形成，例如利用一次构图工艺通过相同的材料层形成遮光层与薄膜晶体管的源极和漏极，减少了构图工艺的次数，减少了掩模板的使用数量，从而简化了阵列基板的制作工艺，降低了制作成本。
图2a-2g是根据本发明的一种示例性实施例的阵列基板的制作方法的操作过程示意图。阵列基板包括：基板1；形成在基板1上的多个薄膜晶体管，薄膜晶体管可以是例如具有顶栅式结构的薄膜晶体管；以及多个遮光层2，每个遮光层2在基板1上设置在薄膜晶体管的源极31和漏极32之间并被构造成用于阻挡光线从基板1照射相应薄膜晶体管的有源层5。本发明实施例的制作阵列基板的方法包括步骤S100：在例如玻璃或者透明树脂材料制成的基板1上利用单个掩模板(未示出)通过一次构图工艺形成依次间隔布置的源极31、遮光层2和漏极32，参见图2a。在本发明的一种示例性实施例中，在基板1上利用单个掩模板通过一次构图工艺形成源极31、遮光层2、漏极32以及与源极31电连接的数据线(未示出)。
在本发明的实施例中，构图工艺主要包括基板清洗、成膜、光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。例如，在基板上利用单个掩模板通过一次构图工艺形成源极31、遮光层2、漏极32以及与源极31电连接的数据线的步骤包括：例如采用磁控溅射或热蒸发的方法在基板1上形成金属薄膜；在金属薄膜上涂覆光刻胶层；利用具有与源极、遮光层、漏极以及数据线分别对应的图形的第一掩模板对光刻胶进行曝光，以形成光刻胶保留区和光刻胶去除区；通过显影将光刻胶去除区的光刻胶完全去除，光刻胶保留区的光刻胶完全保留；采用刻蚀工艺，将光刻胶去除区的金属薄膜去除；以及将未去除的光刻胶剥离。另外，还可以利用灰化工艺切除残余的光刻胶。这样，如图2a所示，可以在基板1形成源极31、遮光层2、漏极32以及数据线(未示出)。
在步骤S100中所使用的金属薄膜可以利用由钼、铝、铝镍合金、钼钨合金、铬、或铜金属制成，也可以由上述几种材料的组合制成。遮光层2设置在源极31和漏极32之间并与有源层5的位置相对应，由此遮光层可以阻挡从基板1引入的光照射到有源层5上，从而可以保持用于形成有源层5的多晶硅薄膜的电特性。例如，遮光层2可以由铬或者钼金属薄膜制成。
如图2b所示，本发明实施例的制作阵列基板的方法还包括：
步骤S200：在基板1上例如采用化学气相沉积(Chemical Vapor Deposition，CVD)工艺形成覆盖源极31、遮光层2和漏极32的第一绝缘 层41和非晶硅薄膜51。第一绝缘层41例如可以由SiN(氮化硅)、SiOx(氧化硅)制成。通过对非晶硅薄膜51进行准分子激光退火工艺，使非晶硅薄膜51转变成为低温多晶硅薄膜，所述低温多晶硅薄膜用于形成薄膜晶体管的有源层5。
如图2c所示，本发明实施例的制作阵列基板的方法还可以包括：
步骤S300：例如采用化学气相沉积工艺在第一绝缘层41上形成覆盖有源层5的第二绝缘层42；
步骤S400：例如采用构图工艺在第二绝缘层42上形成栅极33；以及
步骤S500：在第二绝缘层42上形成覆盖栅极33的第三绝缘层43。
本发明实施例的制作阵列基板的方法还可以包括S600：通过形成在所述第一、第二和第三绝缘层中的过孔9分别实现有源层5与源极31和漏极32的电连接。
根据本发明的一种示例性实施例，如图2c所示，在第一绝缘层41上形成覆盖所述有源层的第二绝缘层42和栅极之后，通过离子植入工艺，例如采用电子枪轰击，在有源层5的将与源极31和漏极32电连接的部位分别形成欧姆掺杂区61。欧姆掺杂区61例如掺杂有磷或者硼元素，可以减小源极31和漏极32与有源层5和像素电极7之间的接触阻抗。
薄膜晶体管可以为P型晶体管，也可以是N型晶体管。在薄膜晶体管为N型晶体管的情况下，如图2d所示，在形成欧姆掺杂区61之后，通过对光刻胶进行灰化处理，对有源层进行轻掺杂，以在欧姆掺杂区61附近形成轻掺杂漏区62。轻掺杂漏区62可以防止热电子退化效应，提高薄膜晶体管的热载流子寿命。
在本发明的一种示例性实施例中，通过形成在所述第一、第二和第三绝缘层中的过孔9分别实现有源层5与源极31和漏极32的电连接的步骤可以包括：在第三绝缘层43上形成与漏极32电连接的像素电极7。具体地，如图2e所示，采用构图工艺在第一绝缘层41、第二绝缘层42和第三绝缘层43中形成过孔9；如图2f所示，采用溅射工艺(Sputter)在第三绝缘层43和过孔9中涂覆ITO薄膜或其他导电材料薄膜，实现有源层5与源极31和漏极32间的电连接，并使用一张掩膜版通过构图工艺形成像 素电极7。在一种示例性实施例中，数据线可以与像素电极7通过一次构图工艺形成在第三绝缘层43上并与源极31电连接。
进一步地，如图2g所示，例如采用化学气相沉积工艺在第三绝缘层43上形成覆盖像素电极7的第四绝缘层44，采用溅射工艺在第四绝缘层44上涂覆ITO薄膜或其他导电材料薄膜，并使用通过构图工艺形成至少一个公共电极8。这样，形成本发明实施例的阵列基板。
可以理解，第二绝缘层42、第三绝缘层43和第四绝缘层44都可以例如由SiN(氮化硅)、SiOx(氧化硅)制成。另外，在执行步骤S100之前，可以在基板1上形成缓冲层，以有助于改善基板1的表面平整度和附着力，而且还有助于改善抗水氧渗透性。缓冲层可以例如由SiN(氮化硅)、SiOx(氧化硅)制成。
根据本发明一方面的实施例，提供一种显示装置，包括上述任一实施例所述的阵列基板。显示装置可以是液晶显示装置。这些液晶显示装置在阵列基板的薄膜晶体管的驱动下，可以实现显示功能。在替换的实施例中，本发明实施例的阵列基板可以应用于OLED(Organic Light Emitting Diode，有机发光二极体)显示装置以及AMOLED(Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极体)显示装置。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
根据本发明上述实施例的薄膜晶体管组件、阵列基板及其制作方法、包括这种阵列基板的显示装置，遮光层、薄膜晶体管的源极和漏极、以及数据线在基板上形成在同一层中，可以利用相同的材料通过一次构图工艺形成，减少了构图工艺的次数，减少了掩模板的使用数量，从而简化了阵列基板的制作工艺，降低了制作成本。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (19)

  1. 一种薄膜晶体管组件，包括：
    薄膜晶体管；以及
    遮光层，所述遮光层布置在所述薄膜晶体管的源极和漏极之间并且被构造成能够阻挡光线从外部照射薄膜晶体管的有源层，
    其中，所述遮光层与薄膜晶体管的源极和漏极形成在同一层中。
  2. 如权利要求1所述的薄膜晶体管组件，其中，通过一次构图工艺通过相同的材料层形成所述遮光层与薄膜晶体管的源极和漏极。
  3. 如权利要求1或2所述的薄膜晶体管组件，其中，所述薄膜晶体管为顶栅式薄膜晶体管。
  4. 如权利要求1-3中任一项所述的薄膜晶体管组件，其中，所述有源层由多晶硅薄膜形成。
  5. 如权利要求4所述的薄膜晶体管组件，其中，在所述有源层的与所述源极和漏极电连接的部位分别设有欧姆掺杂区。
  6. 如权利要求5所述的薄膜晶体管组件，其中，所述薄膜晶体管为N型晶体管。
  7. 如权利要求6所述的薄膜晶体管组件，其中，在所述欧姆掺杂区附近还设有轻掺杂漏区。
  8. 一种阵列基板，包括：
    基板；以及
    多个如权利要求1-7中的任一项所述的薄膜晶体管组件，多个所述薄膜晶体管形成在所述基板上；
    其中，所述遮光层与薄膜晶体管的源极和漏极在所述基板上形成在同一层中。
  9. 如权利要求8所述的阵列基板，其中，在所述基板上通过一次构图工艺通过相同的材料层形成所述遮光层与薄膜晶体管的源极和漏极。
  10. 如权利要求8或9所述的阵列基板，其中，每个所述薄膜晶体管的源极与相应的数据线连接，并且数据线、遮光层、源极和漏极在所述基板上形成在同一层中。
  11. 一种制作阵列基板的方法，所述阵列基板包括：
    基板；
    多个薄膜晶体管，形成在所述基板上；以及
    多个遮光层，每个遮光层在所述基板上设置在所述薄膜晶体管的源极和漏极之间并被构造成能够阻挡光线从基板照射相应薄膜晶体管的有源层，
    所述方法包括如下步骤：在基板上利用单个掩模板通过一次构图工艺形成依次间隔布置的源极、遮光层和漏极。
  12. 如权利要求11所述的方法，其中，在执行在基板上利用单个掩模板通过一次构图工艺形成依次间隔布置的源极、遮光层和漏极的步骤之后，还包括如下步骤：
    在基板上形成覆盖所述源极、遮光层和漏极的第一绝缘层；
    在所述第一绝缘层上形成有源层；
    在所述第一绝缘层上形成覆盖所述有源层的第二绝缘层；
    在所述第二绝缘层上形成栅极；
    在第二绝缘层上形成覆盖所述栅极的第三绝缘层；以及
    通过形成在所述第一、第二和第三绝缘层中的过孔分别实现所述有源层与源极和漏极的电连接。
  13. 如权利要求12所述的方法，其中，所述薄膜晶体管为顶栅式薄膜晶体管，所述有源层由低温多晶硅薄膜制成
  14. 如权利要求11-13中的任一项所述的方法，其中，
    在基板上利用单个掩模板通过一次构图工艺形成依次间隔布置的源极、遮光层和漏极的步骤包括：
    在基板上利用单个掩模板通过一次构图工艺形成源极、遮光层、漏极以及与所述源极电连接的数据线。
  15. 如权利要求14所述的方法，其中，在基板上利用单个掩模板通过一次构图工艺形成源极、遮光层、漏极以及与所述源极电连接的数据线的步骤包括：
    在所述基板上形成金属薄膜；
    在所述金属薄膜上涂覆光刻胶层；
    利用具有与所述源极、遮光层、漏极以及数据线分别对应的图形的第一掩模板对所述光刻胶进行曝光和显影；
    采用刻蚀工艺，将光刻胶去除区的金属薄膜去除；以及
    将未去除的光刻胶剥离。
  16. 如权利要求12或13所述的方法，其中，在所述第一绝缘层上形成覆盖所述有源层的第二绝缘层和栅极后，通过离子植入工艺在所述有源层的将与所述源极和漏极电连接的部位分别形成欧姆掺杂区。
  17. 如权利要求16所述的方法，其中，所述薄膜晶体管为N型晶体管，并且在形成欧姆掺杂区之后，在所述欧姆掺杂区附近形成轻掺杂漏区。
  18. 如权利要求12或13所述的方法，其中，通过形成在所述第一、第二和第三绝缘层中的过孔分别实现所述有源层与源极和漏极的电连接的步骤包括：
    在所述第三绝缘层上形成与所述漏极电连接的像素电极。
  19. 一种显示装置，包括如权利要求8-10中的任一项所述的阵列基板。
PCT/CN2015/073341 2014-11-14 2015-02-27 薄膜晶体管组件、阵列基板及其制作方法、和显示装置 Ceased WO2016074373A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/777,666 US9543443B2 (en) 2014-11-14 2015-02-27 Thin film transistor assembly, array substrate method of manufacturing the same, and display device
EP15763182.1A EP3200230B1 (en) 2014-11-14 2015-02-27 Thin film transistor component, array substrate and manufacturing method therefor, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410645972.6A CN104332477B (zh) 2014-11-14 2014-11-14 薄膜晶体管组件、阵列基板及其制作方法、和显示装置
CN201410645972.6 2014-11-14

Publications (1)

Publication Number Publication Date
WO2016074373A1 true WO2016074373A1 (zh) 2016-05-19

Family

ID=52407175

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/073341 Ceased WO2016074373A1 (zh) 2014-11-14 2015-02-27 薄膜晶体管组件、阵列基板及其制作方法、和显示装置

Country Status (4)

Country Link
US (1) US9543443B2 (zh)
EP (1) EP3200230B1 (zh)
CN (1) CN104332477B (zh)
WO (1) WO2016074373A1 (zh)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101679252B1 (ko) * 2014-09-30 2016-12-07 엘지디스플레이 주식회사 박막 트랜지스터 기판과 그 제조방법 및 그를 이용한 디스플레이 장치
CN104332477B (zh) * 2014-11-14 2017-05-17 京东方科技集团股份有限公司 薄膜晶体管组件、阵列基板及其制作方法、和显示装置
US9520421B1 (en) * 2015-06-29 2016-12-13 Shenzhen China Star Optoelectronics Technology Co., Ltd. Method for manufacturing LTPS TFT substrate and LTPS TFT substrate
KR102402605B1 (ko) * 2015-07-28 2022-05-27 삼성디스플레이 주식회사 유기 발광 표시 장치
CN105047675B (zh) * 2015-08-06 2018-06-22 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN105336745B (zh) * 2015-09-30 2019-01-22 深圳市华星光电技术有限公司 低温多晶硅tft基板
CN105336626A (zh) * 2015-12-08 2016-02-17 深圳市华星光电技术有限公司 与数据线导通的薄膜晶体管的制备方法及薄膜晶体管
CN105428313A (zh) * 2016-01-05 2016-03-23 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
US10656483B2 (en) * 2016-03-14 2020-05-19 Sharp Kabushiki Kaisha Semiconductor apparatus and method for manufacturing semiconductor apparatus
CN105932067A (zh) * 2016-06-07 2016-09-07 京东方科技集团股份有限公司 一种顶栅型薄膜晶体管、制备方法、阵列基板及显示面板
CN106168865B (zh) 2016-06-28 2019-11-26 京东方科技集团股份有限公司 内嵌式触摸屏及其制作方法、显示装置
CN106371253A (zh) * 2016-08-26 2017-02-01 武汉华星光电技术有限公司 阵列基板、液晶显示面板以及制造方法
KR102584959B1 (ko) * 2016-08-31 2023-10-06 엘지디스플레이 주식회사 표시장치
CN106324931B (zh) * 2016-09-06 2019-07-26 武汉华星光电技术有限公司 一种高分辨率的低温多晶硅像素的制作方法
CN107093583A (zh) * 2017-05-03 2017-08-25 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN107068772B (zh) * 2017-05-11 2019-10-18 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法
CN109273404B (zh) * 2017-07-12 2021-01-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板、显示装置
CN107611084B (zh) 2017-09-04 2020-02-28 京东方科技集团股份有限公司 一种阵列基板接触孔制备方法、阵列基板及显示器件
CN107910378B (zh) 2017-11-14 2021-01-26 京东方科技集团股份有限公司 Ltps薄膜晶体管、阵列基板及其制作方法、显示装置
CN108110010B (zh) 2017-12-15 2021-10-01 京东方科技集团股份有限公司 阵列基板及其制备方法、触控显示面板
CN108598172B (zh) * 2018-04-28 2019-08-13 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制作方法
CN108873527A (zh) * 2018-07-25 2018-11-23 Oppo（重庆）智能科技有限公司 阵列基板、液晶显示面板、装置及制备阵列基板的方法
CN109103231B (zh) * 2018-08-27 2021-08-24 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
KR102517126B1 (ko) * 2018-09-28 2023-04-03 삼성디스플레이 주식회사 표시 장치
CN109638079A (zh) * 2018-11-30 2019-04-16 武汉华星光电技术有限公司 一种阵列基板及显示面板
KR102704437B1 (ko) * 2019-06-13 2024-09-09 삼성디스플레이 주식회사 박막트랜지스터 기판 및 이를 구비한 디스플레이 장치
KR102652197B1 (ko) * 2019-12-12 2024-03-27 엘지디스플레이 주식회사 박막 트랜지스터를 포함하는 표시장치
CN111128874A (zh) * 2019-12-18 2020-05-08 武汉华星光电半导体显示技术有限公司 Tft阵列基板及其制备方法、oled触控显示装置
JP7372832B2 (ja) * 2019-12-26 2023-11-01 シャープ株式会社 液晶表示装置およびその製造方法
CN111312731B (zh) * 2020-02-28 2022-08-23 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN111969008A (zh) * 2020-06-03 2020-11-20 京东方科技集团股份有限公司 有机发光显示基板及其制备方法、显示装置
JP7484632B2 (ja) 2020-09-30 2024-05-16 セイコーエプソン株式会社 電気光学装置、および電子機器
CN112530978B (zh) * 2020-12-01 2024-02-13 京东方科技集团股份有限公司 开关器件结构及其制备方法、薄膜晶体管膜层、显示面板
CN113437090A (zh) * 2021-06-11 2021-09-24 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示面板
CN113540131B (zh) * 2021-09-15 2022-01-18 惠科股份有限公司 阵列基板、显示面板以及阵列基板的制备方法
CN115425031A (zh) * 2022-08-30 2022-12-02 深圳市华星光电半导体显示技术有限公司 阵列基板及其制造方法、显示面板
CN115696978A (zh) * 2022-11-08 2023-02-03 广州华星光电半导体显示技术有限公司 一种显示装置及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050258488A1 (en) * 2004-04-27 2005-11-24 Toppoly Optoelectronics Corp. Serially connected thin film transistors and fabrication methods thereof
CN103367165A (zh) * 2013-07-01 2013-10-23 北京京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板及显示器
CN203312302U (zh) * 2013-07-01 2013-11-27 北京京东方光电科技有限公司 薄膜晶体管、阵列基板及显示器
CN104332477A (zh) * 2014-11-14 2015-02-04 京东方科技集团股份有限公司 薄膜晶体管组件、阵列基板及其制作方法、和显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3240258B2 (ja) * 1996-03-21 2001-12-17 シャープ株式会社 半導体装置、薄膜トランジスタ及びその製造方法、ならびに液晶表示装置及びその製造方法
KR101084278B1 (ko) * 2009-11-05 2011-11-16 삼성모바일디스플레이주식회사 표시장치 및 표시장치의 제조방법
KR101137391B1 (ko) * 2010-03-24 2012-04-20 삼성모바일디스플레이주식회사 박막 트랜지스터를 갖는 기판, 이를 제조하는 방법, 및 상기 박막 트랜지스터를 갖는 기판을 구비하는 유기 발광 표시 장치
KR101877448B1 (ko) * 2011-06-30 2018-07-12 엘지디스플레이 주식회사 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판 및 이의 제조 방법
CN202473925U (zh) * 2012-03-30 2012-10-03 京东方科技集团股份有限公司 一种顶栅型tft阵列基板及显示装置
CN103018989A (zh) * 2012-12-07 2013-04-03 京东方科技集团股份有限公司 一种阵列基板及其制造方法和液晶显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050258488A1 (en) * 2004-04-27 2005-11-24 Toppoly Optoelectronics Corp. Serially connected thin film transistors and fabrication methods thereof
CN103367165A (zh) * 2013-07-01 2013-10-23 北京京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板及显示器
CN203312302U (zh) * 2013-07-01 2013-11-27 北京京东方光电科技有限公司 薄膜晶体管、阵列基板及显示器
CN104332477A (zh) * 2014-11-14 2015-02-04 京东方科技集团股份有限公司 薄膜晶体管组件、阵列基板及其制作方法、和显示装置

Also Published As

Publication number Publication date
US9543443B2 (en) 2017-01-10
CN104332477B (zh) 2017-05-17
EP3200230B1 (en) 2025-04-02
US20160141425A1 (en) 2016-05-19
EP3200230A4 (en) 2018-06-06
CN104332477A (zh) 2015-02-04
EP3200230A1 (en) 2017-08-02

Similar Documents

Publication Publication Date Title
CN104332477B (zh) 薄膜晶体管组件、阵列基板及其制作方法、和显示装置
CN103383945B (zh) 一种阵列基板、显示装置及阵列基板的制造方法
KR102049685B1 (ko) 저온 폴리실리콘 어레이 기판의 제조방법
CN108538860B (zh) 顶栅型非晶硅tft基板的制作方法
JP6956008B2 (ja) 薄膜トランジスタ、表示基板及び表示基板を有する表示パネル、並びにそれらの製造方法
US10120256B2 (en) Preparation method for thin film transistor, preparation method for array substrate, array substrate, and display apparatus
WO2018227750A1 (zh) 柔性tft基板的制作方法
US10192993B2 (en) Thin film transfer, manufacturing method thereof, array substrate and manufacturing method thereof
US10224416B2 (en) Method for manufacturing low-temperature poly-silicon thin film transistor, low-temperature poly-silicon thin film transistor and display device
WO2016112663A1 (zh) 制作阵列基板的方法和阵列基板
CN105304500B (zh) N型tft的制作方法
US9006059B2 (en) CMOS transistor and method for fabricating the same
CN105390451A (zh) 低温多晶硅tft基板的制作方法
CN105390443B (zh) Tft基板的制作方法
TW201622158A (zh) 薄膜電晶體以及其製作方法
CN107204345B (zh) 一种阵列基板及其制备方法、显示装置
WO2017173712A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN105702623A (zh) Tft阵列基板的制作方法
WO2015188594A1 (zh) 多晶硅层及显示基板的制备方法、显示基板
WO2019218566A1 (zh) Ltps tft基板的制作方法
CN108565247A (zh) Ltps tft基板的制作方法及ltps tft基板
CN105679705A (zh) 阵列基板的制作方法
US10957606B2 (en) Manufacturing method of complementary metal oxide semiconductor transistor and manufacturing method of array substrate
CN107195689B (zh) 一种薄膜晶体管及其制作方法、oled显示面板
US9461066B2 (en) Thin film transistor and method of manufacturing the same, array substrate and display device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14777666

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2015763182

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2015763182

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15763182

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWG Wipo information: grant in national office

Ref document number: 2015763182

Country of ref document: EP