WO2016086566A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2016086566A1
WO2016086566A1 PCT/CN2015/076401 CN2015076401W WO2016086566A1 WO 2016086566 A1 WO2016086566 A1 WO 2016086566A1 CN 2015076401 W CN2015076401 W CN 2015076401W WO 2016086566 A1 WO2016086566 A1 WO 2016086566A1
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Prior art keywords
input
latch
module
output
signal
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English (en)
French (fr)
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青海刚
祁小敬
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to EP15777600.6A priority Critical patent/EP3229226B1/en
Priority to US14/785,251 priority patent/US9799287B2/en
Publication of WO2016086566A1 publication Critical patent/WO2016086566A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) is composed of a matrix of pixels defined by intersections of gate lines and data lines in both horizontal and vertical directions.
  • the TFT controlled by the row gate line is turned on by supplying a gate signal to the gate line of each row, so that the pixel electrode located in the same pixel as the TFT is in communication with the data line.
  • the voltage of the display signal is input to the pixel electrode by inputting a display signal to the data line.
  • the design of the existing display often uses a GOA (Gate Driver on Array) circuit design in which a TFT (Thin Film Transistor) gate switch circuit is integrated in the display panel.
  • the scan driving of the display panel is formed on the array substrate, so that the Bonding area of the gate driving circuit and the peripheral wiring space can be omitted, thereby realizing the aesthetic design of the two sides of the display panel and the narrow border.
  • the GOA circuit includes a plurality of shift register units.
  • a shift register unit in a conventional LTPS (Low Temperature Poly-Silicon) GOA circuit can be composed of two latches (a first latch 01 and a second latch 02).
  • Each of the latches 01 may include an inverter, two transfer gates, and a NAND gate capable of transmitting and shifting the input control signal D using the clock signal Clk (or Clk_).
  • Clk clock signal
  • the first latch 01 When the next clock signal arrives, the first latch 01 is turned off, and the control signal D is latched, at which time the second latch 02 is turned on, so that the control signal D enters the second latch 02 and is output, thereby realizing The shift operation of the control signal D.
  • the shift register unit During one frame scan time, the shift register unit will be in a non-operational state after completing the shift output. Therefore, for the entire display panel, when the first stage shift register unit is in the active state, the remaining shift register units are in a non-operational state.
  • the transmission gate controlled by the clock signal in each shift register unit is frequently turned on and off by the clock signal during the signal flipping even if it is in an inoperative state. Since the transmission gate is formed by parallelizing complementary transistors, the gate capacitance formed by the gate and the substrate in the transistor is charged and discharged multiple times during the opening and closing of the transmission gate. In this way, the clock signal loaded on the transmission gate generates a large useless power consumption, thereby greatly reducing the utilization of the display driving capability.
  • Embodiments of the present invention provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device, which can solve the problem of a large amount of useless power consumption due to clock signal inversion in a non-operating state.
  • a shift register unit includes a latch module and a latch output module, wherein the latch module is respectively connected to a first voltage terminal, a second voltage terminal, and a first a clock signal end, an input end, and a control end of the latch output module, wherein the latch module is configured to control the device according to a signal input by an input end of the latch module and a signal input by the first clock signal end a latching function of the latch module and an opening and closing of the input end of the latch output module; and wherein the latch output module is respectively connected to the first voltage terminal, the second clock signal terminal, and the signal output terminal of the current stage And an output end of the latch module, the latch output module is configured to output a signal input by the second clock signal end to the local level signal when an input end of the latch output module is turned on The output end isolates the signal input by the second clock signal end in an off state of the input end of the latch output module.
  • the latch output module is respectively connected to the first voltage terminal, the second clock signal terminal, the local signal output terminal and the latch module; and is configured to be in an open state of the input end of the latch output module, And outputting the signal input by the second clock signal terminal to the signal output end of the current stage, and isolating the signal input by the second clock signal end when the input end thereof is in a closed state.
  • a gate driving circuit comprising at least two stages of shift register units according to the first aspect of the invention.
  • a display device comprising the gate drive circuit according to the second aspect of the present invention.
  • a driving method for a shift register unit according to the first aspect of the present invention, wherein the second voltage terminal inputs a high level and the first voltage terminal input is low.
  • Level the method includes: in a latch-on phase, an input end of the latch module, the first clock signal terminal inputs a high level, and the second clock signal terminal inputs a low level,
  • the latch module turns on the latch function of the latch module according to the input terminal of the latch module and the high level input by the first clock signal terminal, and performs the high level input by the first signal input terminal.
  • Lapping and turning on the input end of the latch output module, outputting the low level input by the second clock signal terminal to the signal output end of the current stage, so that the signal output end of the current stage outputs a low level; a data output stage, an input end of the latch module, the first clock signal end inputs a low level, and the second clock signal end inputs a high level, the latch module is according to the latch module Input and the first clock The low level of the input terminal continues to maintain the input end of the latch output module, and the latch output module outputs the high level input by the second clock signal terminal to the signal output of the local stage.
  • the output signal output terminal of the current stage outputs a high level; and in the signal isolation phase, the first clock signal terminal inputs a high level, and the input end of the latch module and the second clock signal end
  • the latch module Inputting a low level, the latch module, according to a low level input by an input end of the latch module and a high level input by the first clock signal end, a latch function of the latch module and the lock
  • the input end of the memory output module is turned off, the latch module isolates a signal input by the first clock signal end, and the latch output module isolates a signal input by the second clock signal end, and
  • a low level input from a voltage input terminal is output to the signal output end of the current stage, so that the signal output end of the current stage outputs a low level.
  • the basic idea of the present invention is to replace the clock signal, using an intermediate signal generated based on the clock signal and the input signal to control the opening and closing of the transmission gate, so that the shift register unit is not frequently flipped by the clock signal in the non-operating state. The impact of this, thus avoiding a lot of useless power consumption.
  • 1 is a schematic structural diagram of a shift register unit provided by the prior art
  • FIG. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 5 is a circuit diagram of the shift register unit shown in Figure 3;
  • Fig. 6 is a control timing chart for the shift register unit shown in Fig. 5.
  • the shift register unit can include a latch module 10 and a latch output module 20.
  • the latch module 10 can be respectively connected to the first voltage terminal VSS, the second voltage terminal VDD, the first clock signal terminal CLKB, the input terminal Input_S, and the control terminal of the latch output module 20.
  • the latch module 10 controls the latch function of the latch module 10 and the opening and closing of the input terminal of the latch output module 20 according to the signal input from the input terminal Input_S and the signal input from the first clock signal terminal CLKB.
  • the latch function of the latch module 10 when the latch function of the latch module 10 is turned on, the high level input to the input terminal Input_S of the latch module 10 is latched.
  • the latch function of the latch module 10 is turned off, until the next frame of the high level input latch module 10 (ie, in the non-operating state of the shift register), the first clock signal terminal CLKB is input. The signal is isolated so that it cannot enter the shift register unit.
  • the latch output module 20 can be connected to the first voltage terminal VSS, the second clock signal terminal CLK, the local signal output terminal Output, and the output terminal of the latch module 10, respectively. Specifically, when the input end of the latch output module 20 is turned on, the signal input by the second clock signal terminal CLK is output to the signal output terminal Output of the current stage, thereby being opposite to the signal output end of the current stage. The connected gate lines are scanned. When the input terminal of the latch output module 20 is turned off, the signal input from the second clock signal terminal CLK is isolated so that it cannot enter the shift register unit.
  • the shift register unit generates a large amount of useless power consumption due to frequent flipping of the input signals of the first clock signal terminal CLKB and the second clock signal terminal CLK.
  • the first voltage terminal VSS is input with a low level or grounded, and the second voltage terminal VDD is input with a high level as an example.
  • FIG. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. As shown, the shift register unit may further include a scan direction control module 30 in order to implement a bidirectional scan function.
  • the scan direction control module 30 can be respectively connected to the first signal input terminal OUT(n-1), the second signal input terminal OUT(n+1), the first voltage control terminal CN, the second voltage control terminal CNB, and the latch module 10. Input Input_S.
  • the scan direction control module 30 is configured to input the first signal input terminal OUT(n-1) or the second signal input terminal OUT(n+1) according to the voltage input by the first voltage control terminal CN and the second voltage control terminal CNB.
  • the signal is transmitted to the input of the latch module 10.
  • the latch module 10 can receive the signal input by the first signal input terminal OUT(n-1) during the forward scan, and the latch module 10 receives the second signal input terminal during the inverse scan.
  • a logic amplifying module 40 may be disposed at the output end of the latch output module 20 to amplify the output signal of the latch output module 20.
  • the logic amplification module 40 can be respectively connected to the output end of the latch output module 20, the third signal output terminal OUT(n), the enable signal terminal EN, and the local signal output terminal Output.
  • the logic amplification module 40 is configured to perform amplification processing on the signal output from the latch output module 20 under the control of the input signal of the enable signal terminal EN, and output the signal to the signal output terminal Output of the current stage.
  • the third signal output terminal OUT(n) is coupled to the output of the latch output module 20.
  • the output signal of the third signal output terminal OUT(n) may be the same as the output signal of the signal output terminal Output of the present stage (discussed later).
  • FIG. 4 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention, wherein at least two stages of the shift register units SR0, SR1, . Into a gate drive circuit.
  • the first signal input terminal OUT(n-1) of each of the shift register units and the third signal output end of the adjacent upper stage shift register unit OUT(n) is connected.
  • each stage shift register unit In addition to the last stage shift register unit SRn, the second signal input terminal OUT(n+1) of each stage shift register unit is in phase with its third signal output terminal of the next stage shift register. )connection.
  • the number of shift register units is equal to the number of gate lines of the display area. That is, the signal output terminal Output of each stage of each stage shift register unit is connected to a row of gate lines of the display area. Thereby, the input scan signal is shifted by the multi-stage shift register to realize progressive scan of each row of gate lines.
  • each stage When the second signal input terminal OUT(n+1) of the last stage shift register unit SRn of the shift register units SR0, SR1...SRn of the gate drive circuit is input to the inverted scan signal STV_D, each stage The signal output terminal of the present stage sequentially outputs the scan signals to the corresponding gate lines Gn, Gn-1, ... G1 in an inverted manner (from bottom to top). Thereby, two-way scanning is realized.
  • the above-mentioned gate driving circuit has the same advantageous effects as the shift register unit in the foregoing embodiment, and details are not described herein again.
  • FIG. 5 is a circuit diagram of the shift register unit shown in FIG.
  • the scan direction control module 30 can include a first transfer gate TG1 and a second transfer gate TG2.
  • the input end of the first transmission gate TG1 is connected to the first signal input terminal OUT(n-1), the first control terminal is connected to the first voltage control terminal CN, the second control terminal is connected to the second voltage control terminal CNB, and the output terminal and the latch are connected.
  • the input terminal Input_S of the module 10 is connected.
  • the input end of the second transmission gate TG2 is connected to the second signal input terminal OUT(n+1), the first control terminal is connected to the second voltage control terminal CNB, and the second control terminal is connected to the first voltage
  • the control terminal CN has an output connected to the input terminal Input_S of the latch module 10.
  • the shift register unit implements a forward scan function.
  • the shift register unit implements an inversion scan function.
  • the present invention does not limit the scanning direction. However, the following embodiments are described by taking forward scanning as an example.
  • the latch module 10 may include a first transistor M1, a second transistor M2, a first inverter NIV1, a second inverter NIV2, a third transfer gate TG3, and a third transistor M3.
  • the gate of the first transistor M1 is connected to the output ends of the first transfer gate TG1 and the second transfer gate TG2.
  • the gate of the second transistor M2 is connected to the output ends of the first transfer gate TG1 and the second transfer gate TG2, the first pole is connected to the first voltage terminal VSS, and the second pole is connected to the second pole of the first transistor M1.
  • the input terminal of the first inverter NIV1 is connected to the second electrode of the first transistor M1 and the second electrode of the second transistor M2, and the output terminal is connected to the input terminal of the second inverter NIV2.
  • the input terminal of the second inverter NIV2 is connected to the output terminal of the first inverter NIV1, and the output terminal is connected to the control terminal of the latch output module 20.
  • the first transistor M1 is a P-type transistor, and its gate is turned on when a low level is input, and the second transistor M2 is an N-type transistor, and is turned on when a gate is input to a high level.
  • the input end of the third transmission gate TG3 is connected to the first clock signal terminal CLKB, the output terminal is connected to the first pole of the first transistor M1, the first control terminal is connected to the output end of the first inverter NIV1, and the second control terminal is connected to The outputs of the second inverter NIV2 are connected.
  • the gate of the third transistor M3 is connected to the output end of the first inverter NIV1, the first pole is connected to the second voltage terminal VDD, and the second pole is connected to the first pole of the first transistor M1.
  • the third transistor M3 is a P-type transistor, and is turned on when the gate is input with a low level.
  • the latch output module 20 may include a fourth transfer gate TG4 and a fourth transistor M4.
  • the input end of the fourth transmission gate TG4 is connected to the second clock signal terminal CLK, the first control The terminal is connected to the output end of the first inverter NIV1, and the second control terminal is connected to the output terminal of the second inverter NIV2.
  • the gate of the fourth transistor M4 is connected to the output end of the second inverter NIV2, the first pole is connected to the first voltage terminal VSS, and the second pole is connected to the output terminal of the fourth transmission gate TG4.
  • the fourth transistor M4 is an N-type transistor, and is turned on when a gate is input to a high level.
  • the logic amplification module 40 may include a NAND gate Nand and a third inverter NIV3.
  • the first input end of the NAND gate Nand is connected to the third signal output terminal OUT(n) and the output end of the fourth transmission gate TG4, and the second input terminal is connected to the enable signal terminal EN.
  • the input end of the third inverter NIV3 is connected to the output end of the NAND gate Nand, and the output end is connected to the signal output terminal Output of the current stage.
  • first poles of all the transistors in the embodiment of the present invention may be the source, and the second pole may be the drain.
  • Fig. 6 is a control timing chart for the shift register unit shown in Fig. 5. The operation of the above shift register unit in the forward scan will be described in detail below in conjunction with the timing chart.
  • the high level input from the first signal input terminal OUT(n-1) enters the latch module 10 such that the node m is at a high level. Since the first transistor M1 is a P-type transistor, the first transistor M1 is in an off state. Since the second transistor M2 is an N-type transistor, the second transistor M2 is turned on, so that the first voltage terminal VSS pulls the potential of the node n to a low level. After the inversion of the first inverter NIV1, the potential of the node p is at a high level, so that the third transfer gate TG3 in the latch module 10 and the fourth transfer gate TG4 in the latch output module 20 can be turned on. .
  • the high level input from the first clock signal terminal CLKB is input to the latch module 10, and since the first transistor M1 is in an off state, the above high level cannot affect the potential of the node n.
  • the latch module 10 is in a latch function on state, wherein a high level input by the first signal input terminal OUT(n-1) is latched to the The latch unit 10.
  • the fourth transistor M4 Since the potential of the node q is at a low level, the fourth transistor M4 is in an off state, and the fourth transfer gate TG4 is turned on, so that the input terminal of the latch output module 20 is in an on state, and the latch output module 20 is to be in a second state.
  • the low level of the clock signal terminal CLK input is transmitted to the logic amplification module 40.
  • the input low level is output from the latch output module 20 and the high level is input from the enable signal terminal EN
  • the high level is output after passing the NAND gate Nand, and the third inverter NIV3 is passed at the high level again. Inverted, so that the output of the signal output of this stage is low.
  • the shift register unit latches the input high level signal OUT(n-1), so the first phase T1 is the latch open phase of the shift register unit.
  • the first transistor M1 After the low level input to the first signal input terminal OUT(n-1) is transmitted to the latch module 10, the first transistor M1 is turned on, and the second transistor M2 is turned off. Since the third transfer gate TG3 in the latch module 10 maintains the on state of the previous stage, the low level of the input of the first clock signal input to the CLKB is transmitted to the node n, so that the node n remains at the low level, and the latch module The state of 10 does not change (the latch function remains on).
  • the potential of the node p is made high, and the potential of the node q is low, so that the fourth transmission gate TG4 In the on state, the input terminal of the latch output module 20 continues to be in an on state, the fourth transmission gate TG4 is in an on state, and the third transistor M3 is turned off.
  • the potential of the node q is at a low level, and the fourth transistor M4 is in an off state.
  • the fourth transfer gate TG4 since the fourth transfer gate TG4 is turned on, the high level input by the second clock signal terminal CLK can be transferred to the logic amplification module 40.
  • the NAND gate Nand Since the high level is input from the latch output module 20, and the high level is input from the enable signal terminal EN, the NAND gate Nand outputs a low level, and the low level is further inverted by the third inverter NIV3. The output of the signal output terminal of this stage is outputted to a high level, and the corresponding gate line is scanned.
  • the second phase T2 is the data output phase of the shift register unit.
  • the low level input by the first signal input terminal OUT(n-1) is transmitted to the latch module 10 such that the first transistor M1 is turned on and the second transistor M2 is turned off.
  • the third transfer gate TG3 in the latch module 10 maintains the on state of the previous stage.
  • the first clock signal terminal CLKB inputs a high level to the third transfer gate TG3, the potential of the node n is at a high level.
  • the potential of the node p is low, and the potential of the node q is high.
  • the third transfer gate TG3 and the fourth transfer gate TG4 are in an off state, and the third transistor M3 is turned on, so that the high level input by the second voltage terminal VDD is transmitted to the node n, thereby keeping the node n at the high level. status.
  • the fourth transistor M4 is turned on, and the potential of the node r is pulled down to the low level input by the first voltage terminal VSS, thereby causing the latch output module 20 to input to the logic.
  • the signal of the amplification module 40 is low.
  • the NAND gate Nand Since the low level is input from the latch output module 20, and the high level is input from the enable signal terminal EN, the NAND gate Nand outputs a high level, and the high level is further inverted by the third inverter NIV3. This makes the output of the signal output of this stage output low level.
  • the third stage T3 is the signal isolation stage.
  • T1 to T3 stages may be referred to as the operating time of the shift register unit.
  • the output of the signal of this stage only outputs the high level in the T2 phase, that is, the data output stage of the shift register, and the other non-output time outputs the low level.
  • the shift register unit is in a non-operational state until the next time the first signal input terminal OUT(n-1) is at a high level.
  • the third transfer gate TG3 and the fourth transfer gate TG4 are in an off state, even if the input signals of the first clock signal CLKB and the second clock signal terminal CLK are inverted, they are not input to the shift register unit. So, it does not cause a lot of useless power.
  • the scan direction control module 30 and the logic amplification module 40 are not necessary, and thus in the above description, the corresponding circuit elements and corresponding signals may be omitted (example)
  • a description of the first voltage control terminal CN signal, the second voltage control terminal CNB signal, and the signal of the enable signal terminal EN For example, a description of the first voltage control terminal CN signal, the second voltage control terminal CNB signal, and the signal of the enable signal terminal EN).
  • the signal input from the first signal input terminal OUT(n-1) is directly input to the input terminal Input_S of the latch module 10, and the output signal of the latch output module 20 is directly output to the signal output terminal Output of the present stage.
  • the embodiment of the invention further provides a display device comprising any of the gate drive circuits as described above.
  • the display device has the same advantageous effects as the gate driving circuit provided by the foregoing embodiments of the present invention, and details are not described herein again.
  • the display device may specifically be any liquid crystal display product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the embodiment of the invention further provides a driving method of the shift register unit, wherein the first voltage control terminal CN, the enable signal terminal EN, the second voltage terminal VDD input a high level, and the first voltage terminal VSS is input with a low level.
  • the method can comprise:
  • the first signal input terminal OUT(n-1), the first clock signal terminal CLKB inputs a high level, and the second clock signal terminal CLK inputs a low level.
  • the scan direction control module 30 transmits the high level input from the first signal input terminal OUT(n-1) to the latch module 10.
  • the latch module 10 turns on the latch function of the latch module 10 according to the high level input by the first signal input terminal OUT(n-1) and the high level input by the first clock signal terminal CLKB, and sets the first signal input terminal OUT ( N-1) The input high level is latched.
  • the latch module 10 simultaneously turns on the input terminal of the latch output module 20, and outputs the low level input by the second clock signal terminal CLK to the logic amplification module 40.
  • the logic amplification module 40 amplifies the low level outputted by the latch output module 20 under the control of the high level input by the enable signal terminal EN, and outputs it to the signal output terminal Output of the current stage, so that the signal output of the current stage is output.
  • the terminal output outputs a low level.
  • the first signal input terminal OUT(n-1), the first clock signal terminal CLKB inputs a low level, and the second clock signal terminal CLK inputs a high level.
  • the scan direction control module 30 transmits the low level input by the first signal input terminal OUT(n-1) to the latch module 10.
  • the latch module 10 continues to maintain the input state of the latch output module 20 according to the low level input by the first signal input terminal OUT(n-1) and the low level input by the first clock signal terminal CLKB.
  • the latch output module 20 outputs the high level input to the second clock signal terminal CLK to the logic amplification module 40.
  • the logic amplification module 40 under the control of the high level input by the enable signal terminal EN, amplifies the high level outputted by the latch output module 20 and outputs it to the signal output terminal Output of the current stage, so that the signal output terminal of the current stage is output.
  • the output is high.
  • the first clock signal terminal CLKB inputs a high level, and the first signal input terminal OUT(n-1) and the second clock signal terminal CLK are input to a low level.
  • the scan direction control module 30 transmits the low level input by the first signal input terminal OUT(n-1) to the latch module 10.
  • the latch module 10 switches the latch function of the latch module 10 and the latch output module 20 according to the low level input by the first signal input terminal OUT(n-1) and the high level input by the first clock signal terminal CLKB. The input is closed.
  • the latch module 10 isolates the signal input from the first clock signal terminal CLKB.
  • the latch output module 20 isolates the signal input from the second clock signal terminal CLK, and outputs the low level input from the first voltage input terminal VSS to the logic amplification module 40.
  • the logic amplification module 40 under the control of the high level of the input of the signal terminal EN, amplifies the low level outputted by the latch output module 20 and outputs it to the signal output terminal Output of the current stage, so that the signal output end of the current stage is output. Output output is low.
  • the shift register unit is in a non-operational state until the next time the first signal input terminal OUT(n-1) is at the high level.
  • the latch function of the latch module 10 and the input terminal of the latch output module 20 are turned off, even if the input signals of the first clock signal CLKB and the second clock signal terminal CLK are inverted, they are not input.
  • the shift register unit So as not to cause a lot of useless power.
  • the scan direction control module 30 and the logic amplification module 40 are not necessary, so in the above description, the corresponding modules and corresponding signals may be omitted (for example, the first voltage control terminal CN signal, the second voltage control terminal) Description of the CNB signal and the signal of the enable signal terminal EN).
  • the signal input from the first signal input terminal OUT(n-1) is directly input to the input terminal Input_S of the latch module 10, and the output signal of the latch output module 20 is directly output to the signal output terminal Output of the present stage.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the steps of the foregoing method embodiments are included; and the foregoing storage medium includes various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。移位寄存器单元包括锁存模块（10）以及锁存输出模块（20）。代替时钟信号，使用基于时钟信号和输入信号而生成的中间信号来控制传输门的打开和关闭，使得在非工作状态下，移位寄存器单元不会受到时钟信号频繁翻转的影响，从而避免造成大量无用功耗。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由水平和垂直两个方向的栅线和数据线交叉定义的像素矩阵构成。当TFT-LCD进行显示时，通过向每一行的栅线提供选通信号来打开被该行栅线控制的TFT，使得与所述TFT位于同一个像素中的像素电极与数据线连通。然后，通过向数据线输入显示信号来将该显示信号的电压输入至像素电极中。通过控制所述像素电极对应位置处的液晶分子进行偏转，可以得到不同的透光度，进而可以实现对显示画面灰度或颜色的控制。然而，当分辨率较高时，显示器的栅极驱动和源极驱动的输出均较多，驱动电路的长度也将增大，这将不利于模组驱动电路的绑定(Bonding)工艺。
为了解决上述问题，现有显示器的制造常采用GOA(Gate Driver on Array，阵列基板行驱动)电路的设计，其中将TFT(Thin Film Transistor，薄膜场效应晶体管)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省掉栅极驱动电路的Bonding区域以及外围布线空间，从而实现显示面板的两边对称和窄边框的美观设计。
现有技术中，为了实现逐行扫描，GOA电路包括多个移位寄存器单元。如图1所示，传统的LTPS(Low Temperature Poly-Silicon，低温多晶硅)GOA电路中的移位寄存器单元可以由两个锁存器(第一锁存器01和第二锁存器02)构成。每一个锁存器01可以包括一个反相器、两个传输门以及一个与非门，能够利用时钟信号Clk(或Clk_)对输入的控制信号D进行传输和移位。具体地，当第一锁存器01开启后，上一级移位寄存器单元输入的控制信号D进入锁存器01，此时第二锁存器02关闭，使得信号无法输入。当下一时钟信号到来时，第一锁存器01关闭，并将控制信号D锁存，此时第二锁存器02开启，使得控制信号D进入第二锁存器02并输出，由此实现 控制信号D的移位操作。
在一帧扫描时间内，当移位寄存器单元完成移位输出后会处于非工作状态。因此，对于整个显示面板而言，当一级移位寄存器单元处于工作状态时，其余的移位寄存器单元均处于非工作状态。然而，每个移位寄存器单元中通过时钟信号控制的传输门即使在非工作状态，仍然会被时钟信号在信号翻转的过程中频繁地打开和关闭。由于传输门是由互补的晶体管并联而成，在传输门打开和关闭的过程中，会对晶体管中由栅极和衬底构成的栅电容进行多次充、放电。这样一来，加载于传输门上的时钟信号会产生较大的无用功耗，从而大大降低显示驱动能力的利用率。
发明内容
本发明的实施例提供一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置，能够解决在非工作状态下由于时钟信号翻转造成大量无用功耗的问题。
为达到上述目的，本发明的实施例采用如下技术方案：
根据本发明实施例的第一方面，提供了一种移位寄存器单元，包括锁存模块和锁存输出模块，其中，所述锁存模块分别连接第一电压端、第二电压端、第一时钟信号端、输入端以及所述锁存输出模块的控制端，所述锁存模块用于根据所述锁存模块的输入端输入的信号和所述第一时钟信号端输入的信号，控制所述锁存模块的锁存功能和所述锁存输出模块的输入端的启闭；并且其中，所述锁存输出模块分别连接所述第一电压端、第二时钟信号端、本级信号输出端以及所述锁存模块的输出端，所述锁存输出模块用于在所述锁存输出模块的输入端开启状态下，将所述第二时钟信号端输入的信号输出至所述本级信号输出端，在所述锁存输出模块的输入端关闭状态下，将所述第二时钟信号端输入的信号进行隔离。所述锁存输出模块，分别连接所述第一电压端、第二时钟信号端、本级信号输出端以及所述锁存模块；用于在所述锁存输出模块的输入端开启状态下，将所述第二时钟信号端输入的信号输出至所述本级信号输出端，在其输入端关闭状态下，将所述第二时钟信号端输入的信号进行隔离。
根据本发明实施例的第二方面，提供了一种栅极驱动电路，包括至少两级如本发明的第一方面所述的移位寄存器单元。
根据本发明实施例的第三方面，提供了一种显示装置，包括如本发明的第二方面所述的栅极驱动电路。
本发明实施例的第四方面，提供了一种用于如本发明的第一方面所述的移位寄存器单元的驱动方法，所述第二电压端输入高电平并且第一电压端输入低电平，所述方法包括：在锁存开启阶段，所述锁存模块的输入端、所述第一时钟信号端输入高电平，并且所述第二时钟信号端输入低电平，所述锁存模块根据所述锁存模块的输入端和所述第一时钟信号端输入的高电平开启所述锁存模块的锁存功能，将所述第一信号输入端输入的高电平进行锁存，并且开启锁存输出模块的输入端，将所述第二时钟信号端输入的低电平输出至所述本级信号输出端，使得所述本级信号输出端输出低电平；在数据输出阶段，所述锁存模块的输入端、所述第一时钟信号端输入低电平，并且所述第二时钟信号端输入高电平，所述锁存模块根据所述锁存模块的输入端和所述第一时钟信号端输入的低电平，将所述锁存输出模块的输入端继续维持开启状态，所述锁存输出模块将所述第二时钟信号端输入的高电平输出至所述本级信号输出端，使得所述本级信号输出端输出高电平；以及在信号隔离阶段，所述第一时钟信号端输入高电平，并且所述锁存模块的输入端、所述第二时钟信号端输入低电平，所述锁存模块根据所述锁存模块的输入端输入的低电平和所述第一时钟信号端输入的高电平将所述锁存模块的锁存功能和所述锁存输出模块的输入端关闭，所述锁存模块将所述第一时钟信号端输入的信号进行隔离，所述锁存输出模块将所述第二时钟信号端输入的信号进行隔离，并将第一电压输入端输入的低电平输出至所述本级信号输出端，使得所述本级信号输出端输出低电平。
本发明的基本思想在于：代替时钟信号，使用基于时钟信号和输入信号而生成的中间信号来控制传输门的打开和关闭，使得在非工作状态下，移位寄存器单元不会受到时钟信号频繁翻转的影响，从而避免造成大量无用功耗。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员 来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种移位寄存器单元的结构示意图；
图2为本发明实施例提供的一种移位寄存器单元的结构示意图；
图3为本发明实施例提供的另一种移位寄存器单元的结构示意图；
图4为本发明实施例提供的一种栅极驱动电路的结构示意图；
图5为如图3所示的移位寄存器单元的电路示意图；以及
图6为用于如图5所示的移位寄存器单元的控制时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图2为本发明实施例提供的一种移位寄存器单元的结构示意图。如图所示，该移位寄存器单元可以包括锁存模块10和锁存输出模块20。
锁存模块10可以分别连接第一电压端VSS、第二电压端VDD、第一时钟信号端CLKB、输入端Input_S以及锁存输出模块20的控制端。锁存模块10根据输入端Input_S输入的信号和第一时钟信号端CLKB输入的信号，控制所述锁存模块10的锁存功能以及锁存输出模块20的输入端的启闭。
具体地，当锁存模块10的锁存功能开启时，将锁存模块10的输入端Input_S输入的高电平进行锁存。当锁存模块10的锁存功能关闭后，直至下一帧高电平输入锁存模块10的这段时间内(即移位寄存器的非工作状态下)，将第一时钟信号端CLKB输入的信号进行隔离，使其无法进入移位寄存器单元中。
锁存输出模块20可以分别连接第一电压端VSS、第二时钟信号端CLK、本级信号输出端Output以及锁存模块10的输出端。具体地，在锁存输出模块20的输入端开启状态下，将第二时钟信号端CLK输入的信号输出至本级信号输出端Output，从而对与本级信号输出端相 连接的栅线进行扫描。在锁存输出模块20的输入端关闭状态下，将第二时钟信号端CLK输入的信号进行隔离，使其无法进入移位寄存器单元中。
由此，避免由于第一时钟信号端CLKB和第二时钟信号端CLK输入信号频繁翻转的原因，使得移位寄存器单元产生大量的无用功耗。
需要说明的是，本发明实施例中，是以第一电压端VSS输入低电平或接地而第二电压端VDD输入高电平为例进行说明的。
图3为本发明实施例提供的另一种移位寄存器单元的结构示意图。如图所示，为了实现双向扫描功能，该移位寄存器单元还可以包括扫描方向控制模块30。
扫描方向控制模块30可以分别连接第一信号输入端OUT(n-1)、第二信号输入端OUT(n+1)、第一电压控制端CN、第二电压控制端CNB以及锁存模块10的输入端Input_S。扫描方向控制模块30用于根据第一电压控制端CN和第二电压控制端CNB输入的电压，将第一信号输入端OUT(n-1)或第二信号输入端OUT(n+1)输入的信号传输至锁存模块10的输入端。这样一来，可以在正向扫描时，使得锁存模块10接收第一信号输入端OUT(n-1)输入的信号，而在反相扫描时，使得锁存模块10接收第二信号输入端OUT(n+1)输入的信号，反之亦可。
进一步地，为了增强电路的驱动能力，提高电路的负载能力，可以在锁存输出模块20的输出端设置逻辑放大模块40，以对锁存输出模块20的输出信号进行放大处理。
逻辑放大模块40可以分别连接锁存输出模块20的输出端、第三信号输出端OUT(n)、使能信号端EN以及本级信号输出端Output。逻辑放大模块40用于在所述使能信号端EN输入信号的控制下，将锁存输出模块20输出的信号进行放大处理后输出至本级信号输出端Output。第三信号输出端OUT(n)与锁存输出模块20的输出端相连接。第三信号输出端OUT(n)的输出信号可以与本级信号输出端Output的输出信号相同(后面讨论)。
图4为本发明实施例提供的一种栅极驱动电路的结构示意图，其中，至少两级如上所述的移位寄存器单元SR0、SR1…SRn能够构 成一种栅极驱动电路。
具体地，除第一级移位寄存器单元SR0外，其余每个移位寄存器单元的第一信号输入端OUT(n-1)与其相邻的上一级移位寄存器单元的第三信号输出端OUT(n)相连接。
除最后一级移位寄存器单元SRn外，每一级移位寄存器单元的第二信号输入端OUT(n+1)与其相邻的下一级移位寄存器的第三信号输出端相OUT(n)连接。
需要说明的是，移位寄存器单元的数量与显示区域的栅线的数量相等。即每一级移位寄存器单元的本级信号输出端Output与显示区域的一行栅线相连接。由此，通过多级移位寄存器对输入的扫描信号进行移位，来实现对各行栅线的逐行扫描。
当上述栅极驱动电路的各级移位寄存器单元SR0、SR1…SRn中的第一极移位寄存器单元SR0的第一信号输入端OUT(n-1)输入正向扫描信号STV-U时，各级移位寄存器SR0、SR1…SRn的本级信号输出端Output按正向(从上至下)顺序地将扫描信号输出到与其相对应的栅线G1、G2…Gn上。在该示例中，移位寄存器单元的结构如图3所示。
当上述栅极驱动电路的各级移位寄存器单元SR0、SR1…SRn中的最后一级移位寄存器单元SRn的第二信号输入端OUT(n+1)输入反相扫描信号STV_D，各级的本级信号输出端Output按反相(从下至上)顺序地将扫描信号输出到与其相对应的栅线Gn、Gn-1…G1上。由此，实现双向扫描。
上述栅极驱动电路具有前述实施例中的移位寄存器单元相同的有益效果，在此不再赘述。
以下，对移位寄存器单元的具体电路进行详细的举例说明。图5为如图3所示的移位寄存器单元的电路示意图。如图所示，扫描方向控制模块30可以包括第一传输门TG1和第二传输门TG2。
第一传输门TG1的输入端连接第一信号输入端OUT(n-1)，第一控制端连接第一电压控制端CN，第二控制端连接第二电压控制端CNB，输出端与锁存模块10的输入端Input_S相连接。
第二传输门TG2的输入端连接第二信号输入端OUT(n+1)，第一控制端连接所述第二电压控制端CNB，第二控制端连接第一电压 控制端CN，输出端与锁存模块10的输入端Input_S相连接。
当第一电压控制端CN连接高电平VDD，第二电压控制端CNB连接低电平VSS时，第一传输门TG1导通，使得锁存模块10接收第一信号输入端OUT(n-1)输入的信号，同时禁止第二信号输入端OUT(n+1)输入的信号。此时移位寄存器单元实现正向扫描功能。当第一电压控制端CN连接低电平VSS，第二电压控制端CNB连接高电平VDD时，第二传输门TG2导通，使得锁存模块10接收第二信号输入端OUT(n+1)输入的信号，同时禁止第一信号输入端OUT(n-1)输入的信号。此时移位寄存器单元实现反相扫描功能。本发明对扫描方向不做限定，然而以下实施例均是以正向扫描为例进行说明的。
锁存模块10可以包括第一晶体管M1、第二晶体管M2、第一反相器NIV1、第二反相器NIV2、第三传输门TG3和第三晶体管M3。
第一晶体管M1的栅极连接第一传输门TG1以及第二传输门TG2的输出端。
第二晶体管M2的栅极连接第一传输门TG1以及第二传输门TG2的输出端，第一极连接第一电压端VSS，第二极与第一晶体管M1的第二极相连接。
第一反相器NIV1的输入端与第一晶体管M1的第二极和第二晶体管M2的第二极相连接，输出端连接第二反相器NIV2的输入端。
第二反相器NIV2的输入端与第一反相器NIV1的输出端相连接，输出端连接锁存输出模块20的控制端。
第一晶体管M1为P型晶体管，其栅极输入低电平时导通，并且第二晶体管M2为N型晶体管，其栅极输入高电平时导通。
第三传输门TG3的输入端连接第一时钟信号端CLKB，输出端连接第一晶体管M1的第一极，第一控制端连接所述第一反相器NIV1的输出端，第二控制端与所述第二反相器NIV2的输出端相连接。
第三晶体管M3的栅极连接第一反相器NIV1的输出端，第一极连接第二电压端VDD，第二极与所述第一晶体管M1的第一极相连接。
第三晶体管M3为P型晶体管，其栅极输入低电平时导通。
锁存输出模块20可以包括第四传输门TG4和第四晶体管M4。
第四传输门TG4的输入端连接第二时钟信号端CLK，第一控制 端连接所述第一反相器NIV1的输出端，第二控制端连接第二反相器NIV2的输出端。
第四晶体管M4的栅极连接第二反相器NIV2的输出端，第一极连接第一电压端VSS，第二极连接第四传输门TG4的输出端。
所述第四晶体管M4为N型晶体管，其栅极输入高电平时导通。
逻辑放大模块40可以包括与非门Nand和第三反相器NIV3。
与非门Nand的第一输入端连接第三信号输出端OUT(n)以及第四传输门TG4的输出端，第二输入端连接所述使能信号端EN。
第三反相器NIV3的输入端与与非门Nand的输出端相连接，输出端连接本级信号输出端Output。
需要说明的是，本发明实施例中的所有晶体管的第一极可以为源极、第二极可以为漏极。
图6为用于如图5所示的移位寄存器单元的控制时序图。以下结合该时序图对上述移位寄存器单元在正向扫描时的工作过程进行详细描述。
使能信号端EN、第一电压控制端CN一直输入高电平VDD，并且第二电压控制端CNB一直输入低电平，因此，第一传输门TG1导通，而第二传输门TG2关闭。
第一阶段T1，OUT(n-1)＝1；CLKB＝1；CLK＝0；Node_p＝1；OUT(n)＝0；Output＝0。需要说明的是，以下实施例中，“0”表示低电平，而“1”表示高电平。
第一信号输入端OUT(n-1)输入的高电平进入锁存模块10，使得节点m为高电平。由于第一晶体管M1为P型晶体管，因此第一晶体管M1处于截止状态。由于第二晶体管M2为N型晶体管，因此第二晶体管M2导通，使得第一电压端VSS将节点n的电位拉至低电平。经过第一反相器NIV1的反相作用，节点p的电位为高电平，使得可以将锁存模块10中的第三传输门TG3以及锁存输出模块20中的第四传输门TG4导通。
在此情况下，第一时钟信号端CLKB输入的高电平输入至锁存模块10，并且由于第一晶体管M1处于截止状态，因此上述高电平不能够对节点n的电位产生影响。此时，锁存模块10处于锁存功能开启状态，其中第一信号输入端OUT(n-1)输入的高电平被锁存至所述 锁存单元10。
由于节点q的电位为低电平，因此第四晶体管M4处于截至状态，并且第四传输门TG4导通，使得锁存输出模块20的输入端处于开启状态，该锁存输出模块20将第二时钟信号端CLK输入的低电平传输至逻辑放大模块40。
由于从锁存输出模块20输出输入低电平和并且从使能信号端EN输入高电平，所以通过与非门Nand后输出高电平，在该高电平再经过第三反相器NIV3的反相作用，使得本级信号输出端Output输出低电平。
综上所述，第一阶段T1中，移位寄存器单元将输入的高电平信号OUT(n-1)进行锁存，因此所述第一阶段T1为移位寄存器单元的锁存开启阶段。
第二阶段T2，OUT(n-1)＝0；CLKB＝0；CLK＝1；Node_p＝1；OUT(n)＝1；Output＝1。
第一信号输入端OUT(n-1)输入的低电平传输至锁存模块10后，将使得第一晶体管M1导通，而第二晶体管M2处于截止状态。由于锁存模块10中的第三传输门TG3保持上一阶段的开启状态，因此第一时钟信号端输入CLKB输入的低电平传输至节点n，使得节点n仍然保持低电平，锁存模块10的状态不发生变化(锁存功能保持开启)。通过第一反相器NIV1的反相作用和第二反相器NIV2的反相作用后，使得节点p的电位为高电平，并且节点q的电位为低电平，使得第四传输门TG4处于导通状态，锁存输出模块20的输入端继续维持开启状态，第四传输门TG4处于导通状态，第三晶体管M3截止。，并且通过第二反相器NIV2的反相作用，节点q的电位为低电平，第四晶体管M4处于截止状态。
对于锁存输出模块20而言，由于第四传输门TG4导通，因此可以将第二时钟信号端CLK输入的高电平传输至逻辑放大模块40中。
由于从锁存输出模块20输入高电平，从使能信号端EN输入高电平，所以与非门Nand输出低电平，该低电平再经过第三反相器NIV3的反相作用，使得本级信号输出端Output输出高电平，并对与其相对应的栅线进行扫描。
综上所述，第二阶段T2为该移位寄存器单元的数据输出阶段。
第三阶段T3，OUT(n-1)＝0；CLKB＝1；CLK＝0；Node_p＝0；OUT(n)＝0；Output＝0。
第一信号输入端OUT(n-1)输入的低电平传输至锁存模块10，使得第一晶体管M1导通，第二晶体管M2处于截止状态。锁存模块10中的第三传输门TG3保持上一阶段的开启状态，这时，由于第一时钟信号端CLKB向第三传输门TG3输入高电平，使得节点n的电位为高电平。通过反相器的反相作用后，节点p的电位为低电平，节点q的电位为高电平。这样一来，第三传输门TG3和第四传输门TG4处于截止状态，第三晶体管M3导通，使得第二电压端VDD输入的高电平传输至节点n，从而保持节点n处于高电平的状态。
与此同时，由于节点q的电位为高电平，使得第四晶体管M4导通，将节点r的电位下拉至第一电压端VSS输入的低电平，进而使得锁存输出模块20输入至逻辑放大模块40的信号为低电平。
由于从锁存输出模块20输入低电平，从使能信号端EN输入高电平，所以与非门Nand输出高电平，该高电平再经过第三反相器NIV3的反相作用，使得本级信号输出端Output输出低电平。
综上所述，在第三阶段T3中，由于第三传输门TG3和第四传输门TG4均处于截止状态，使得锁存模块10的锁存功能和锁存输出模块20的输入端处于关闭状态。因此，第一时钟信号端CLKB和第二时钟信号端CLK输入的信号无法进入移位寄存器单元中，从而避免了第一时钟信号端CLKB和第二时钟信号端CLK输入信号的频繁翻转造成的大量无用功。所以，第三阶段T3为信号隔离阶段。
需要说明的是，T1～T3阶段可以称为移位寄存器单元的工作时间。本级信号输出端Output只有在T2阶段，即移位寄存器的数据输出阶段，才输出高电平，其它非输出时间均输出低电平。
此后，直到下一次第一信号输入端OUT(n-1)为高电平的时间内，该移位寄存器单元处于非工作状态。在非工作状态下，由于第三传输门TG3和第四传输门TG4处于截止状态，因此即使第一时钟信号CLKB、第二时钟信号端CLK的输入信号翻转，也不会输入至移位寄存器单元内，从而不会造成大量无用功耗。
应当注意，扫描方向控制模块30和逻辑放大模块40并不是必需的，因此在以上描述中，可以省略对相应的电路元件和相应的信号(例 如，第一电压控制端CN信号、第二电压控制端CNB信号以及使能信号端EN的信号)的描述。此时，从第一信号输入端OUT(n-1)输入的信号直接输入到锁存模块10的输入端Input_S，而锁存输出模块20的输出信号直接输出到本级信号输出端Output。
本发明实施例还提供一种显示装置，包括如上所述的任意一种栅极驱动电路。该显示装置具有与本发明前述实施例提供的栅极驱动电路相同的有益效果，此处不再赘述。该显示装置具体可以为液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的液晶显示产品或者部件。
本发明实施例还提供一种移位寄存器单元的驱动方法，在第一电压控制端CN、使能信号端EN、第二电压端VDD输入高电平并且第一电压端VSS输入低电平的情况下，所述方法可以包括：
在锁存开启阶段T1，第一信号输入端OUT(n-1)、第一时钟信号端CLKB输入高电平，并且第二时钟信号端CLK输入低电平。
扫描方向控制模块30将第一信号输入端OUT(n-1)输入的高电平传输至锁存模块10。锁存模块10根据第一信号输入端OUT(n-1)输入的高电平和第一时钟信号端CLKB输入的高电平开启锁存模块10的锁存功能，将第一信号输入端OUT(n-1)输入的高电平进行锁存。
锁存模块10同时开启锁存输出模块20的输入端，将第二时钟信号端CLK输入的低电平输出至逻辑放大模块40。
逻辑放大模块40在使能信号端EN输入的高电平的控制下，将锁存输出模块20输出的低电平进行放大处理后输出至本级信号输出端Output，使得所述本级信号输出端Output输出低电平。
在数据输出阶段T2，第一信号输入端OUT(n-1)、第一时钟信号端CLKB输入低电平，并且第二时钟信号端CLK输入高电平。
扫描方向控制模块30将第一信号输入端OUT(n-1)输入的低电平传输至锁存模块10。锁存模块10根据第一信号输入端OUT(n-1)输入的低电平和第一时钟信号端CLKB输入的低电平，将锁存输出模块20的输入端继续维持开启状态。
锁存输出模块20将第二时钟信号端CLK输入的高电平输出至逻辑放大模块40。
逻辑放大模块40在使能信号端EN输入的高电平的控制下，将锁存输出模块20输出的高电平进行放大处理后输出至本级信号输出端Output，使得本级信号输出端Output输出高电平。
在信号隔离阶段T3，第一时钟信号端CLKB输入高电平，并且第一信号输入端OUT(n-1)、第二时钟信号端CLK输入低电平。
扫描方向控制模块30将第一信号输入端OUT(n-1)输入的低电平传输至锁存模块10。锁存模块10根据第一信号输入端OUT(n-1)输入的低电平和第一时钟信号端CLKB输入的高电平将所述锁存模块10的锁存功能和锁存输出模块20的输入端关闭。锁存模块10将第一时钟信号端CLKB输入的信号进行隔离。
锁存输出模块20将第二时钟信号端CLK输入的信号进行隔离，并将第一电压输入端VSS输入的低电平输出至逻辑放大模块40。
逻辑放大模块40使能信号端EN输入的高电平的控制下，将锁存输出模块20输出的低电平进行放大处理后输出至本级信号输出端Output，使得所述本级信号输出端Output输出低电平。
这样一来，在此后直到下一次第一信号输入端OUT(n-1)为高电平的时间内，该移位寄存器单元处于非工作状态。在非工作状态下，由于锁存模块10的锁存功能和锁存输出模块20的输入端关闭，因此即使第一时钟信号CLKB、第二时钟信号端CLK的输入信号进行翻转，也不会输入至移位寄存器单元内。，从而不会造成大量无用功耗。
应当注意，扫描方向控制模块30和逻辑放大模块40并不是必需的，因此在以上描述中，可以省略对相应的模块和相应的信号(例如，第一电压控制端CN信号、第二电压控制端CNB信号以及使能信号端EN的信号)的描述。此时，从第一信号输入端OUT(n-1)输入的信号直接输入到锁存模块10的输入端Input_S，而锁存输出模块20的输出信号直接输出到本级信号输出端Output。
本领域普通技术人员可以理解，实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并 不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种移位寄存器单元，包括锁存模块和锁存输出模块，
    其中，所述锁存模块分别连接第一电压端、第二电压端、第一时钟信号端、输入端以及所述锁存输出模块的控制端，所述锁存模块用于根据所述锁存模块的输入端输入的信号和所述第一时钟信号端输入的信号，控制所述锁存模块的锁存功能和所述锁存输出模块的输入端的启闭；
    并且其中，所述锁存输出模块分别连接所述第一电压端、第二时钟信号端、本级信号输出端以及所述锁存模块的输出端，所述锁存输出模块用于在所述锁存输出模块的输入端开启状态下，将所述第二时钟信号端输入的信号输出至所述本级信号输出端，在所述锁存输出模块的输入端关闭状态下，将所述第二时钟信号端输入的信号进行隔离。
  2. 根据权利要求1所述的移位寄存器单元，还包括扫描方向控制模块，所述扫描方向控制模块分别连接第一信号输入端、第二信号输入端、第一电压控制端、第二电压控制端以及所述锁存模块的输入端，所述扫描方向控制模块用于根据所述第一电压控制端和所述第二电压控制端输入的电压，将所述第一信号输入端或所述第二信号输入端输入的信号传输至所述锁存模块的输入端。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述扫描方向控制模块包括：
    第一传输门，其输入端连接所述第一信号输入端，第一控制端连接所述第一电压控制端，第二控制端连接所述第二电压控制端，输出端与所述锁存模块的输入端相连接；以及
    第二传输门，其输入端连接所述第二信号输入端，第一控制端连接所述第二电压控制端，第二控制端连接所述第一电压控制端，输出端与所述锁存模块的输入端相连接。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述锁存模块包括：
    第一晶体管，其栅极连接所述第一传输门以及所述第二传输门的输出端；
    第二晶体管，其栅极连接所述第一传输门以及所述第二传输门的输出端，第一极连接所述第一电压端，第二极与所述第一晶体管的第二极相连接；
    第一反相器，其输入端与所述第一晶体管的第二极和所述第二晶体管的第二极相连接，输出端连接第二反相器的输入端；
    第二反相器，其输入端与所述第一反相器的输出端相连接，输出端连接所述锁存输出模块的控制端；
    第三传输门，其输入端连接所述第一时钟信号端，输出端连接所述第一晶体管的第一极，第一控制端连接所述第一反相器的输出端，第二控制端与所述第二反相器的输出端相连接；以及
    第三晶体管，其栅极连接所述第一反相器的输出端，第一极连接所述第二电压端，第二极与所述第一晶体管的第一极相连接。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述第一晶体管、所述第三晶体管为P型晶体管，所述第二晶体管为N型晶体管，所述第一极为源极，所述第二极为漏极。
  6. 根据权利要求4所述的移位寄存器单元，其中，所述锁存输出模块包括：
    第四传输门，其输入端连接所述第二时钟信号端，第一控制端连接所述第一反相器的输出端，第二控制端连接第二反相器的输出端；以及
    第四晶体管，其栅极连接所述第二反相器的输出端，第一极连接所述第一电压端，第二极连接所述第四传输门的输出端。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述第四晶体管为N型晶体管，所述第一极为源极，所述第二极为漏极。
  8. 根据权利要求6所述的移位寄存器单元，还包括逻辑放大模块，所述逻辑放大模块分别连接所述锁存输出模块的输出端、第三信号输出端、使能信号端以及所述本级信号输出端，所述锁存输出模块的输出端与第三信号输出端相连接，所述逻辑放大模块用于在所述使能信号端输入信号的控制下，将所述锁存输出模块输出的信号进行放大处理后输出至所述本级信号输出端。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述逻辑放大模块包括：
    与非门，其第一输入端连接所述第三信号输出端以及所述第四传输门的输出端，第二输入端连接所述使能信号端；以及
    第三反相器，其输入端与所述与非门的输出端相连接，输出端连接所述本级信号输出端。
  10. 一种栅极驱动电路，包括至少两级如权利要求8或9所述的移位寄存器单元，
    其中，除第一级移位寄存器单元外，其余每个移位寄存器单元的第一信号输入端与其相邻的上一级移位寄存器单元的第三信号输出端相连接；
    并且其中，除最后一级移位寄存器单元外，每一级移位寄存器单元的第二信号输入端与其相邻的下一级移位寄存器的第三信号输出端相连接。
  11. 一种显示装置，包括如权利要求10所述的栅极驱动电路。
  12. 一种用于如权利要求1-9中任一项所述移位寄存器单元的驱动方法，所述第二电压端输入高电平并且第一电压端输入低电平，所述方法包括：
    在锁存开启阶段，所述锁存模块的输入端、所述第一时钟信号端输入高电平，并且所述第二时钟信号端输入低电平，所述锁存模块根据所述锁存模块的输入端和所述第一时钟信号端输入的高电平开启所述锁存模块的锁存功能，将所述第一信号输入端输入的高电平进行锁存，并且开启锁存输出模块的输入端，将所述第二时钟信号端输入的低电平输出至所述本级信号输出端，使得所述本级信号输出端输出低电平；
    在数据输出阶段，所述锁存模块的输入端、所述第一时钟信号端输入低电平，并且所述第二时钟信号端输入高电平，所述锁存模块根据所述锁存模块的输入端和所述第一时钟信号端输入的低电平，将所述锁存输出模块的输入端继续维持开启状态，所述锁存输出模块将所述第二时钟信号端输入的高电平输出至所述本级信号输出端，使得所述本级信号输出端输出高电平；以及
    在信号隔离阶段，所述第一时钟信号端输入高电平，并且所述锁存模块的输入端、所述第二时钟信号端输入低电平，所述锁存模块根据所述锁存模块的输入端输入的低电平和所述第一时钟信号端输入 的高电平将所述锁存模块的锁存功能和所述锁存输出模块的输入端关闭，所述锁存模块将所述第一时钟信号端输入的信号进行隔离，所述锁存输出模块将所述第二时钟信号端输入的信号进行隔离，并将第一电压输入端输入的低电平输出至所述本级信号输出端，使得所述本级信号输出端输出低电平。
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