WO2016090853A1 - 阵列基板及其制造方法和全反射式液晶显示器 - Google Patents

阵列基板及其制造方法和全反射式液晶显示器 Download PDF

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WO2016090853A1
WO2016090853A1 PCT/CN2015/079580 CN2015079580W WO2016090853A1 WO 2016090853 A1 WO2016090853 A1 WO 2016090853A1 CN 2015079580 W CN2015079580 W CN 2015079580W WO 2016090853 A1 WO2016090853 A1 WO 2016090853A1
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layer
array substrate
source
reflective metal
thin film
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French (fr)
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吕志军
李太亮
高涛
宁策
孙双
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BOE Technology Group Co Ltd
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    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
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    • G02F2203/00—Function characteristic
    • G02F2203/02—Function characteristic reflective

Definitions

  • Embodiments of the present invention generally relate to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same, and a total reflection type liquid crystal display including the array substrate.
  • TFT Thin Film Transistor
  • LCDs Liquid Crystal Display
  • Reflective type TFT-LCD Reflective type TFT-LCD
  • Reflective liquid crystal display not only utilizes and modulates ambient light to meet display requirements, saves electricity, saves energy, and maintains the advantages and characteristics of existing liquid crystal display, which has become a major development trend of liquid crystal display today.
  • TN twisted nematic
  • STN super twisted nematic
  • the introduction of the resin layer as the planarization layer improves the power consumption of the entire device, and improves the aperture ratio and transmittance.
  • the flatness of the resin layer is critical to the reflectivity of the reflective LCD. Even with the same reflective metal, the same reflective structure is deposited on a resin layer of varying flatness, and the final reflectivity of the reflective device varies greatly.
  • the present invention has been made in order to overcome at least one of the above and other problems and disadvantages of the prior art.
  • an array substrate comprising a substrate, a plurality of pixel regions on the substrate, and thin film transistors formed in each of the pixel regions, each of the pixel regions including a pixel electrode region, the thin film transistor Including stacking formed on a substrate a gate layer, and a source/drain layer, the array substrate further comprising a planarization layer and a reflective metal layer sequentially formed on the substrate and covering at least the pixel electrode region and the thin film transistor, the reflective metal layer and the thin film transistor The drain is electrically connected, and at least one of the gate layer and the source/drain layers is formed of a single layer of metal.
  • the gate layer and the source/drain layers may each be formed of a single layer of metal.
  • the gate layer and the source/drain layers may each be of the same metal shape.
  • the gate layer and the source/drain layers may have the same thickness.
  • the metal may include one of molybdenum, copper, and aluminum.
  • the gate layer and the source/drain layers may each be formed of a molybdenum layer having a thickness of 2,200 angstroms.
  • a portion of the reflective metal layer covering the pixel electrode region may be substantially flat.
  • the reflective metal layer may be formed of one of Al, Ag, and AlNd.
  • the planarization layer may include a resin layer.
  • the above array substrate may further include a peripheral lead region, wherein the reflective metal layer may also be formed on the peripheral lead region, and the indium tin oxide layer may be covered on a portion of the reflective metal layer in the peripheral lead region.
  • a total reflection type liquid crystal display comprising the above array substrate is provided.
  • a method of fabricating an array substrate comprising: providing a substrate including a plurality of pixel regions to which a plurality of pixels are to be formed, each pixel region including a pixel electrode to be formed with a pixel electrode a thin film transistor including a gate layer and a source/drain layer laminated on the substrate, at least one of the gate layer and the source/drain layer being formed of a single layer of metal; A planarization layer and a reflective metal layer covering at least the pixel electrode region and the thin film transistor are sequentially formed on the substrate, wherein the reflective metal layer is electrically connected to the drain of the thin film transistor.
  • both the gate layer and the source/drain layers may be formed of a single layer of metal.
  • both the gate layer and the source/drain layers may be formed of the same metal.
  • the gate layer and the source/drain layers may have the same thickness.
  • the metal may include one of molybdenum, copper, and aluminum.
  • the gate layer and the source/drain layers may each be formed of a molybdenum layer having a thickness of 2,200 angstroms.
  • the portion of the reflective metal layer overlying the pixel electrode region may be substantially flat.
  • the reflective metal layer may be formed of one of Al, Ag, and AlNd.
  • the planarization layer may include a resin layer.
  • the substrate used in the above method may further include a peripheral lead region, and the reflective metal layer is further formed on the peripheral lead region, and the method may further include forming an indium tin oxide layer covering a portion of the reflective metal layer in the peripheral lead region on the substrate.
  • FIG. 1 is a cross-sectional view of an array substrate for a total reflection type liquid crystal display according to an embodiment of the present invention
  • FIG. 2 is a flow chart of a method for fabricating an array substrate in accordance with an embodiment of the present invention.
  • FIG. 1 illustrates the structure of an array substrate of an exemplary embodiment of the present invention.
  • the array substrate mainly includes a substrate 10, a plurality of pixel regions on the substrate defined by mutually intersecting data lines and gate lines (not shown), and thin film transistors formed in each of the pixel regions. T, each pixel region includes a pixel electrode region P.
  • the peripheral region B of such an array substrate can be used as a wire bonding region.
  • the thin film transistor T includes a gate layer 21, a gate insulating layer 22, an active layer 23, and a source/drain layer which are sequentially stacked on the substrate 10, and a source 24 of the thin film transistor T is formed in the source/drain layer and Drain 25.
  • the array substrate further includes a passivation layer 30, a planarization layer 40, and a reflective metal layer 50 which are sequentially formed on the substrate 10 and cover at least the pixel electrode region P and the thin film transistor T.
  • the planarization layer 40 may be formed of a resin.
  • the reflective metal layer 50 is electrically connected to the drain electrode 25 of the thin film transistor T, for example, through the passivation layer 30 and the via hole 31 formed in the planarization layer 40, thereby also functioning as a pixel electrode.
  • Table 1 below shows measurement data for the reflectance of some metals.
  • Al, Ag, and AlNd have high reflectance and can achieve approximate specular reflection, and are preferably used as a reflective metal layer in a TFT array substrate.
  • the reflectivity of Ag is extremely high, its cost and process are complicated, and it is not suitable for mass production.
  • the reflectivity of AlNd is slightly lower than that of Ag, but the price is low, and AlNd with simple process can replace Ag to achieve mass production.
  • AlNd is selected to form the reflective metal layer.
  • the thin film transistor T forming region and the pixel electrode region P are There is a step difference or a height difference h between them.
  • the flatness of the planarization layer is critical to the reflectivity of the reflective LCD.
  • most of the planarization layers, such as the resin layer are surface-followed and are sensitive to the underlying undulations, although a flat layer with a high thickness (usually greater than 1 um) can reduce the retardation to some extent.
  • the reflective metal is highly dependent on the overall flatness. Even with the same reflective metal, the same reflective structure is deposited on a flattened layer of varying flatness, and the final reflectivity of the reflective device can vary widely.
  • the gate layer and the source/drain layers of the thin film transistor are both of a multilayer or composite metal structure having a large thickness, and a gate layer and a source/drain layer are not formed in the pixel electrode region.
  • a large step difference or height between the thin film transistor formation region and the pixel electrode region and the overall flatness of the deposited reflective metal layer is poor, particularly in the pixel region, resulting in a low reflectance of the finally patterned reflective metal layer.
  • the planarization layer can have better flatness as a whole, so that (for example, deposition) is formed on the planarization layer.
  • the reflectivity of the reflective metal layer on the upper side is improved to reflect ambient light in a manner closer to specular reflection.
  • At least one or all of the gate layer and the source/drain layers of the thin film transistor T are formed of a single layer of metal, reducing the step difference or height difference h between the thin film transistor and the pixel electrode region, improving the final formation.
  • the overall flatness of the reflective metal layer in the pixel region increases the reflectivity of the reflective metal layer.
  • Table 2 below shows the reflectance of the AlNd layer measured under different conditions. Wherein columns A, B and C indicate the reflectivity of the patterned reflective metal layer formed of AlNd when the thin film transistors having different material electrode structures are formed in the pixel region, and the column D indicates that they are formed directly on the completely flat surface. The reflectivity of the AlNd layer.
  • the gate layer and the source/drain layers of the thin film transistor T are, for example, each having a thickness of 2,200 ⁇ .
  • the molybdenum (Mo) layer is formed to have a thickness of both the conventional gate layer and the source/drain layers.
  • the thickness is 2,200 angstroms.
  • the average reflectance (81.210% or 81.144%) of the AlNd layer formed as the reflective metal layer is closer to the direct reflection than the average reflectance (64.503%) of the conventional composite electrode structure.
  • the average reflectance of the AlNd layer on the surface (96.485%), thereby reflecting ambient light in a manner closer to specular reflection.
  • the reflectance of the same reflective metal differs depending on deposition conditions and the like. After the same metal was deposited and patterned at different temperatures (column A: 240 ° C; column C: 180 ° C), the reflectance did not change much, such as the single-layer Mo electrode in columns A and C; the deposited metal was not patterned (D When the column is), the reflectance is the highest.
  • the reflective metal layer formed in the peripheral region can realize pure specular reflection, and the reflectance is high, and a patterned structure is formed in the pixel region, and there is a step or a height fluctuation.
  • the present invention is achieved by making at least one or all of a gate layer and a source/drain layer of a thin film transistor a single layer metal.
  • the formation is such that the aforementioned step or height difference in the pixel region is reduced, so that the reflectance of the reflective metal layer can be remarkably improved.
  • the thickness is The Mo layer is described as an example. However, when other metals are used, metal layers of different thicknesses may be used depending on the conductivity of the metal, the etching rate, and the like.
  • the thickness is approximately When the passivation layer and/or the gate insulating layer are etched, etching of the underlying gate layer or the source/drain layers is not avoided. It has been proved that in order to ensure that the non-metal layer (passivation layer and/or gate insulating layer) is etched without residue, it is generally required to increase the etching time by 15%-30%.
  • the inventors have found that in conventional reflective liquid crystal displays, Mo/AlNd/Mo and others are due to differences in the etching rate of the metal and the unevenness of the deposited metal due to the presence of this portion of the overetch.
  • the top metal Mo may be partially etched, and in the case where the developer strongly reacts to AlNd, the central metal AlNd may not be well protected and corroded.
  • the gate layer and the source/drain layers of the thin film transistor are formed of a single layer of metal, it is possible to prevent the AlNd caused by the overetch from being corroded and causing interruption of signal transmission.
  • the gate layer and the source/drain layers of the thin film transistor may be formed using any suitable metal.
  • the gate layer 21 and the source/drain layers 24, 25 of the thin film transistor T may each be formed of the same metal, for example, one of molybdenum, copper, and aluminum.
  • the gate layer and the source/drain layers may have the same thickness.
  • the passivation layer and the planarization layer are substantially flat in the pixel electrode region, and in the embodiment of the invention, the reflective metal layer is covered
  • the portion on the pixel electrode region is also substantially flat, and due to the improved reflectance, it is possible to reflect ambient light in a manner that approximates specular reflection, thereby improving light utilization, brightness, and contrast of the liquid crystal display.
  • the reflective metal layer 50 may also be formed in the peripheral lead region B.
  • the portion of the reflective metal layer 50 formed in the peripheral lead region B is spaced apart from the portion formed in the pixel region (P+T region), and passes through the via 32 passing through the passivation layer 30 and the gate insulating layer 22.
  • the portion of the reflective metal layer 50 located in the peripheral lead region may also be covered with an indium tin oxide (ITO) layer 60, thereby realizing the gate layer 21 by using the reflective metal layer 50 and the ITO layer 60. Lead out.
  • ITO indium tin oxide
  • the source and drain of the thin film transistor can also be taken out by the portion of the reflective metal layer located in the peripheral lead region.
  • the array substrate according to the present invention can be used in a total reflection type liquid crystal display to improve light utilization efficiency, brightness, and contrast of the liquid crystal display.
  • step S1 a substrate 10, such as a glass substrate, is provided.
  • the substrate is divided into a plurality of regions, including a plurality of pixel regions P, which are generally located at the center, and a plurality of pixels, and peripheral leads.
  • a bonding region each of which includes a pixel electrode region where a pixel electrode is to be formed and a region where a thin film transistor is to be formed.
  • a thin film transistor T is formed in each of the pixel regions, which can sequentially laminate and pattern the gate layer 21, the gate insulating layer 22, the active layer 23, and the source/drain layers on the substrate Forming, the source 24 and the drain 25 of the thin film transistor T are formed in the source/drain layers.
  • at least one of the gate layer and the source/drain layers is formed of a single layer metal, so that a step difference or a height difference between a region where the thin film transistor is located and the pixel electrode region can be reduced.
  • both the gate layer and the source/drain layers can be formed from a single layer of metal, such as one of molybdenum, copper, and aluminum.
  • the gate layer and the source/drain layers may be formed of the same metal, thereby simplifying the process, for example, may have the same thickness, such as being formed of a molybdenum layer having a thickness of 2,200 angstroms.
  • a planarization layer 40 and a reflective metal layer 50 covering at least the pixel electrode region P and the thin film transistor T are sequentially formed on the substrate, wherein the reflective metal layer 50 is electrically connected to the drain of the thin film transistor.
  • the passivation layer 30 covering at least the pixel electrode region P and the thin film transistor T is formed on the substrate 10 before the planarization layer is formed.
  • the reflective metal layer 50 is electrically connected to the drain electrode 25 of the thin film transistor T, for example, through the via hole 31 formed in the passivation layer 30 and the planarization layer 40, thereby also functioning as a pixel electrode.
  • the planarization layer 40 may be formed of a resin. In one example, as shown in FIG.
  • the portion of the reflective metal layer 50 overlying the pixel electrode region P may be substantially flat, which may be formed of one of Al, Ag, and AlNd.
  • the process of forming each layer is not limited, and includes, for example, a semiconductor process such as deposition, sputtering, or the like.

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Abstract

一种阵列基板，包括基板(10)、位于基板(10)上的多个像素区域、和形成在每个像素区域中的薄膜晶体管(T)，每个像素区域包括像素电极区域(P)，该薄膜晶体管(T)包括层叠形成在基板(10)上的栅极层(21)和源/漏极层，该阵列基板还包括依次形成在基板(10)上并至少覆盖在像素电极区域(P)和薄膜晶体管(T)上的平坦化层(40)和反射金属层(50)，该反射金属层(50)与薄膜晶体管(T)的漏极(25)电连接，并且栅极层(21)和源/漏极层中的至少一个由单层金属形成。还提供了制造该阵列基板的方法和包括该阵列基板的全反射式液晶显示器。

Description

阵列基板及其制造方法和全反射式液晶显示器 技术领域
本发明的实施例一般地涉及显示技术领域，并且具体地，涉及一种阵列基板及其制造方法、和包括该阵列基板的全反射式液晶显示器。
背景技术
自20世纪90年代以来，人们试图通过不采用背照光的方法来实现显示，并且寻找实现薄型化、重量轻及低功耗的新型TFT(薄膜晶体管)LCD(液晶显示)。因该种方法是利用反射环境光来显示图像，故将其称为反射式薄膜晶体管液晶显示(Reflective typeTFT-LCD)。
反射式液晶显示不仅利用并调制环境光满足显示需求，省电、节能，而且保持了现有液晶显示的优势与特点，已成为当今液晶显示一大发展趋势。但由于普通扭曲向列型(TN)LCD、超扭曲向列型(STN)LCD必须采用偏光片，故其显示底色灰暗，对比度低且显示质量差。
对于普通TFT-LCD而言，作为平坦化层的树脂层的引入，改善了器件整体的功耗，提高了开口率和透过率等。但对于全反射模式的LCD来说，树脂层的平坦性对于反射式LCD的反射率的影响至关重要。即便是同样的反射金属，同样的反射结构，沉积在平坦性不等的树脂层上，反射器件的最终反射率会差别很大。
发明内容
为了克服现有技术存在的上述和其它问题和缺陷中的至少一种，提出了本发明。
根据本发明的一个方面，提出了一种阵列基板，包括基板、位于基板上的多个像素区域、和形成在每个像素区域中的薄膜晶体管，每个像素区域包括像素电极区域，该薄膜晶体管包括层叠形成在基板上 的栅极层、和源/漏极层，该阵列基板还包括依次形成在基板上并至少覆盖在像素电极区域和薄膜晶体管上的平坦化层和反射金属层，该反射金属层与薄膜晶体管的漏极电连接，并且栅极层和源/漏极层中的至少一个由单层金属形成。
在上述阵列基板中，栅极层和源/漏极层可以均由单层金属形成。
在上述阵列基板中，栅极层和源/漏极层可以均由同一种金属形。
在上述阵列基板中，栅极层和源/漏极层可以具有相同的厚度。
在上述阵列基板中，所述金属可以包括钼、铜和铝中的一种。
在上述阵列基板中，栅极层和源/漏极层可以均由厚度为2200埃的钼层形成。
在上述阵列基板中，反射金属层覆盖在像素电极区域上的部分可以是基本上平坦的。
在上述阵列基板中，反射金属层可以由Al、Ag和AlNd中的一种形成。
在上述阵列基板中，平坦化层可以包括树脂层。
上述阵列基板还可以包括周边引线区域，其中反射金属层还可以形成在周边引线区域上，并且在反射金属层位于周边引线区域中的部分上可以覆盖有氧化铟锡层。
根据本发明的另一个方面，提供了一种全反射式液晶显示器，包括上述阵列基板。
根据本发明的再一个方面，提供了一种制造阵列基板的方法，包括：提供一基板，该基板包括将形成多个像素的多个像素区域，每个像素区域包括将形成像素电极的像素电极区域；在像素区域中形成薄膜晶体管，该薄膜晶体管包括层叠形成在基板上的栅极层和源/漏极层，栅极层和源/漏极层中的至少一个由单层金属形成；以及在基板上依次形成至少覆盖在像素电极区域和薄膜晶体管上的平坦化层和反射金属层，其中使得反射金属层与薄膜晶体管的漏极电连接。
在上述方法中，可以由单层金属形成栅极层和源/漏极层二者。
在上述方法中，可以由同一种金属形成栅极层和源/漏极层二者。
在上述方法中，栅极层和源/漏极层可以具有相同的厚度。
在上述方法中，所述金属可以包括钼、铜和铝中的一种。
在上述方法中，栅极层和源/漏极层可以均由厚度为2200埃的钼层形成。
在上述方法中，反射金属层覆盖在像素电极区域上的部分可以是基本上平坦的。
在上述方法中，反射金属层可以由Al、Ag和AlNd中的一种形成。
在上述方法中，平坦化层可以包括树脂层。
上述方法所采用的基板还可以包括周边引线区域，反射金属层还形成在周边引线区域上，该方法还可以包括在基板上形成覆盖反射金属层位于周边引线区域中的部分的氧化铟锡层。
通过下文中参照附图对本发明所作的详细描述，本发明的其它目的和优点将显而易见，并可帮助对本发明有全面的理解。
附图说明
通过参考附图能够更加清楚地理解本发明的特征和优点，附图是示意性的而不应理解为对本发明进行任何限制，在附图中：
图1是根据本发明的实施例的用于全反射式液晶显示器的阵列基板的剖视图；以及
图2是根据本发明的实施例的用于制造阵列基板的方法的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
另外，在下面的详细描述中，为便于说明，阐述了许多具体的细节以提供对本发明的实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其它情况下，公知的结构和装置以图示的方式体现以简化附图。
图1图示了本发明的一个示例性实施例的阵列基板的结构。如图所示，该阵列基板主要包括基板10、位于基板上的由相互交叉的数据线和栅极线(未示出)限定的多个像素区域、和形成在每个像素区域中的薄膜晶体管T，每个像素区域包括像素电极区域P。如可以理解的那样，这种阵列基板的周边区域B可以用作引线键合区域。
薄膜晶体管T包括依次层叠形成在基板10上的栅极层21、栅极绝缘层22、有源层23、和源/漏极层，源/漏极层中形成薄膜晶体管T的源极24和漏极25。
该阵列基板还包括依次形成在基板10上并至少覆盖在像素电极区域P和薄膜晶体管T上的钝化层30、平坦化层40和反射金属层50。在一个示例中，平坦化层40可以由树脂形成。反射金属层50例如通过钝化层30和平坦化层40中形成的过孔31与薄膜晶体管T的漏极25电连接，从而还用作像素电极。
下表1示出了一些金属的反射率的测量数据。
从表1中可以看出，Al、Ag和AlNd的反射率较高，能够实现近似镜面反射，优选用作TFT阵列基板中的反射金属层。另一方面，虽然Ag反射率极高，但其成本及工艺制程较复杂，不适于量产工艺；AlNd的反射率稍低于Ag，但价格低廉，制程简单的AlNd可以替代Ag来实现量产。在本发明的一个示例中，选用AlNd来形成反射金属层。
表1
Figure PCTCN2015079580-appb-000001
如图1所示，在像素区域中形成薄膜晶体管T的区域中，由于薄膜晶体管T的各层的形成和层叠，使得在最终形成的阵列基板中，薄膜晶体管T形成区域与像素电极区域P之间存在段差或高度差h。如前所述，对于全反射模式的LCD来说，平坦化层的平坦性对于反射式LCD的反射率的影响至关重要。但大多数平坦化层，如树脂层，都是形貌追随型铺展，对底层起伏度较敏感，虽然，高的厚度(通常大于1um)的平坦化层可以在一定程度上减小段差，但在反射模式中，反射金属对于整体的平坦性依赖作用很大。即便是同样的反射金属，同样的反射结构，沉积在平坦性不等的平坦化层上，反射器件的最终反射率会差别很大。
传统上，薄膜晶体管的栅极层和源/漏极层都是采用多层或复合型金属结构，具有较大的厚度，而在像素电极区域中未形成栅极层和源/漏极层，导致薄膜晶体管形成区域与像素电极区域之间存在大的段差或高度，所沉积的反射金属层的整体平坦性差，特别是在像素区域内，导致最终图案化形成的反射金属层的反射率低。
本发明人发现，通过减小段差，尤其是减小像素区域内的上述段差或高度差h，能够使平坦化层整体上具有较好的平坦性，使得形成(例如，沉积)在平坦化层上的反射金属层的反射率得到提高，以更加接近镜面反射的方式反射环境光。
在本发明中，薄膜晶体管T的栅极层和源/漏极层中的至少一个或者全部由单层金属形成，减小薄膜晶体管与像素电极区域之间的段差或高度差h，改善最终形成的反射金属层在像素区域内的整体平坦性，从而提高反射金属层的反射率。
下表2示出了不同条件下测量的AlNd层的反射率。其中，A、B和C栏表示在具有不同材料电极结构的薄膜晶体管形成在像素区域内时由AlNd形成的图案化的反射金属层的反射率，而D栏表示直接形成在完全平坦的表面上的AlNd层的反射率。
表2
Figure PCTCN2015079580-appb-000002
在本发明的一个示例中，如表2所示，薄膜晶体管T的栅极层和源/漏极层例如都由厚度为2200埃
Figure PCTCN2015079580-appb-000003
的钼(Mo)层形成，与传统的栅极层和源/漏极层都采用厚度为
Figure PCTCN2015079580-appb-000004
的Mo/AlNd/Mo复合结构(即，厚度分别为
Figure PCTCN2015079580-appb-000005
和
Figure PCTCN2015079580-appb-000006
的Mo层AlNd层和Mo层从下至上依次层叠)的薄膜晶体管相比，虽然二者厚度仅差别
Figure PCTCN2015079580-appb-000007
Figure PCTCN2015079580-appb-000008
但明显地，这种厚度的减小导致像素区域内的前述段差或高度差减小，使得作为反射金属层的AlNd层的平均反射率提高近26％(＝(81.210-64.503)/64.503)。
此外，在本发明的薄膜晶体管T的栅极层和源/漏极层例如都由厚度为2200埃
Figure PCTCN2015079580-appb-000009
的钼(Mo)层形成时，作为反射金属层形成的AlNd层的平均反射率(81.210％或81.144％)比传统的复合电极结构的平均反射率(64.503％)更接近直接形成在完全平坦的表面上的AlNd层的平均反射率(96.485％)，从而以更加接近镜面反射的方式反射环境光。
此外，从表2可知，对于相同的反射模式中，相同的反射金属的反射率会因沉积条件等方面不同而不同。相同金属在不同温度(A栏：240℃；C栏：180℃)下沉积并形成图案后，反射率变化不大，如A栏和C栏的单层Mo电极；沉积金属未形成图案(D栏)时，反射率最高。在阵列基板中，由于周边区域未形成图案且周边为平整结构，形成在周边区域的反射金属层能够实现纯镜面反射，反射率高，而像素区域中形成有图案化结构，存在段差或高度起伏，镜面反射不完全，反射率降低。而与传统的栅极层和源/漏极层都采用复合电极结构的薄膜晶体管相比，本发明通过使薄膜晶体管的栅极层和源/漏极层中的至少一个或者全部由单层金属形成，使得像素区域内的前述段差或高度差减小，从而明显地能够提高反射金属层的反射率。
可以理解，在表2的示例中，以厚度为
Figure PCTCN2015079580-appb-000010
的Mo层为例进行了比较说明，但在采用其它金属时，根据金属的导电率、刻蚀速率等方面的不同，可以采用不同厚度的金属层。
在制造阵列基板的过程中，在对厚度约为
Figure PCTCN2015079580-appb-000011
的钝化层和/或栅极绝缘层进行刻蚀时，避免不了对底层栅极层或源/漏极层的刻蚀。实践证明，为保证非金属层(钝化层和/或栅极绝缘层)被刻透并无残留，一般需要增加15％-30％的过刻时间。本发明人发现，在传统反射式液晶显示器中，由于因为这部分过刻的存在，以及设备对于金属的刻蚀速度和沉积金属的不均匀性等因素的差异，对于Mo/AlNd/Mo以及其它“复合型”电极结构中，顶层金属Mo有可能被部分刻透，在显影液对AlNd有强烈的反应的情况下，进而导致中心金属AlNd不能被很好的保护而被腐蚀。而在本发明中，由于薄膜晶体管的栅极层和源/漏极层中的至少一个或者全部由单层金属形成，能够避免过刻引起的AlNd被腐蚀而导致信号传输中断。
可以采用任何合适的金属形成薄膜晶体管的栅极层和源/漏极层。在本发明的一个示例中，薄膜晶体管T的栅极层21和源/漏极层24、25可以均由同一种金属形成，例如，由钼、铜和铝中的一种形成。在另一个示例中，栅极层和源/漏极层可以具有相同的厚度。
由于在像素电极区域内未形成图案化结构，钝化层和平坦化层在像素电极区域中是基本上平坦的，而在本发明的实施例中，反射金属层覆盖在 像素电极区域上的部分也是基本上平坦的，并且由于提高的反射率，因此能够以近似镜面反射的方式反射环境光，从而提高液晶显示器的光利用率、亮度和对比度。
如图1所示，在一个示例中，反射金属层50还可以形成在周边引线区域B中。反射金属层50形成在周边引线区域B中的部分与形成在像素区域(P+T区域)中的部分是隔开的，并通过穿过钝化层30和栅极绝缘层22的过孔32与栅极层21电连接，在反射金属层50位于周边引线区域中的部分上还可以覆盖有氧化铟锡(ITO)层60，从而利用反射金属层50和ITO层60实现栅极层21的引出。当然，虽然未示出，但薄膜晶体管的源极和漏极也可以通过反射金属层位于周边引线区域中的部分引出。
根据本发明的阵列基板可以用在全反射式液晶显示器中，提高液晶显示器的光利用率、亮度和对比度。
以下将描述本发明的用于制造上述阵列基板的方法。图2示出了本发明的一个实施例的用于制造阵列基板的方法的流程。首先，在步骤S1中，提供一基板10，例如玻璃基板，如图1所示，该基板上分成多个区域，包括通常位于中央的将形成多个像素的多个像素区域P以及周边的引线键合区域，每个像素区域包括将形成像素电极的像素电极区域和将形成薄膜晶体管的区域。
在步骤S2中，在每个像素区域中形成薄膜晶体管T，其可以通过在基板上的依次层叠并图案化栅极层21、栅极绝缘层22、有源层23、和源/漏极层而形成，源/漏极层中形成薄膜晶体管T的源极24和漏极25。根据本发明的实施例，栅极层和源/漏极层中的至少一个由单层金属形成，从而能够减小薄膜晶体管所在区域与像素电极区域之间的段差或高度差。在一个示例中，可以由单层金属，如钼、铜和铝中的一种，形成栅极层和源/漏极层二者。栅极层和源/漏极层可以由同一种金属形成，从而简化工艺，例如，可以具有相同的厚度，如均由厚度为2200埃的钼层形成。
在步骤S3中，在基板上依次形成至少覆盖在像素电极区域P和薄膜晶体管T上的平坦化层40和反射金属层50，其中使得反射金属层50与薄膜晶体管的漏极电连接。在一个示例中，在形成平坦化层之前，在基板10上形成至少覆盖在像素电极区域P和薄膜晶体管T上的钝化层30。在 一个示例中，反射金属层50例如通过钝化层30和平坦化层40中形成的过孔31与薄膜晶体管T的漏极25电连接，从而还用作像素电极。例如，平坦化层40可以由树脂形成。在一个示例中，如图1所示，反射金属层50覆盖在像素电极区域P上的部分可以是基本上平坦的，其可以由Al、Ag和AlNd中的一种形成。在本发明中，形成各层的工艺不受限制，例如包括沉积、溅射等半导体工艺。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (21)

  1. 一种阵列基板，包括基板、位于基板上的多个像素区域、和形成在每个像素区域中的薄膜晶体管，每个像素区域包括像素电极区域，
    该薄膜晶体管包括层叠形成在基板上的栅极层和源/漏极层，
    该阵列基板还包括依次形成在基板上并至少覆盖在像素电极区域和薄膜晶体管上的平坦化层和反射金属层，
    该反射金属层与薄膜晶体管的漏极电连接，并且
    栅极层和源/漏极层中的至少一个由单层金属形成。
  2. 根据权利要求1所述的阵列基板，其中栅极层和源/漏极层均由单层金属形成。
  3. 根据权利要求2所述的阵列基板，其中栅极层和源/漏极层由同一种金属形成。
  4. 根据权利要求3所述的阵列基板，其中栅极层和源/漏极层具有相同的厚度。
  5. 根据权利要求3所述的阵列基板，其中所述金属包括钼、铜和铝中的一种。
  6. 根据权利要求4所述的阵列基板，其中栅极层和源/漏极层均由厚度为2200埃的钼层形成。
  7. 根据权利要求1-6中任一项所述的阵列基板，其中反射金属层覆盖在像素电极区域上的部分是基本上平坦的。
  8. 根据权利要求7所述的阵列基板，其中反射金属层由Al、Ag和AlNd中的一种形成。
  9. 根据权利要求1-6中任一项所述的阵列基板，其中平坦化层包括树脂层。
  10. 根据权利要求1-6中任一项所述的阵列基板，还包括周边引线区域，其中
    反射金属层还形成在周边引线区域上，并且
    在反射金属层位于周边引线区域中的部分上覆盖有氧化铟锡层。
  11. 一种全反射式液晶显示器，包括权利要求1-10中任一项所述的阵列基板。
  12. 一种制造阵列基板的方法，包括：
    提供一基板，该基板包括将形成多个像素的多个像素区域，每个像素区域包括将形成像素电极的像素电极区域；
    在像素区域中形成薄膜晶体管，该薄膜晶体管包括层叠形成在基板上的栅极层和源/漏极层，栅极层和源/漏极层中的至少一个由单层金属形成；以及
    在基板上依次形成至少覆盖在像素电极区域和薄膜晶体管上的平坦化层和反射金属层，其中使得反射金属层与薄膜晶体管的漏极电连接。
  13. 根据权利要求12所述的方法，其中栅极层和源/漏极层均由单层金属形成。
  14. 根据权利要求13所述的方法，其中栅极层和源/漏极层由同一种金属形成。
  15. 根据权利要求14所述的方法，其中栅极层和源/漏极层具有相同的厚度。
  16. 根据权利要求14所述的方法，其中所述金属包括钼、铜和铝中的一种。
  17. 根据权利要求15所述的方法，其中栅极层和源/漏极层均由厚度为2200埃的钼层形成。
  18. 根据权利要求12-17中任一项所述的方法，其中反射金属层覆盖在像素电极区域上的部分是基本上平坦的。
  19. 根据权利要求18所述的方法，其中反射金属层由Al、Ag和AlNd中的一种形成。
  20. 根据权利要求12-17中任一项所述的方法，其中平坦化层包括树脂层。
  21. 根据权利要求12-17中任一项所述的方法，其中所述基板还包括周边引线区域，反射金属层还形成在周边引线区域上，该方法还包括：
    在基板上形成覆盖反射金属层位于周边引线区域中的部分的氧化铟锡层。
PCT/CN2015/079580 2014-12-10 2015-05-22 阵列基板及其制造方法和全反射式液晶显示器 Ceased WO2016090853A1 (zh)

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