WO2016101654A1 - 横向绝缘栅双极型晶体管 - Google Patents

横向绝缘栅双极型晶体管 Download PDF

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WO2016101654A1
WO2016101654A1 PCT/CN2015/089302 CN2015089302W WO2016101654A1 WO 2016101654 A1 WO2016101654 A1 WO 2016101654A1 CN 2015089302 W CN2015089302 W CN 2015089302W WO 2016101654 A1 WO2016101654 A1 WO 2016101654A1
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bipolar transistor
gate bipolar
region
insulated gate
lateral insulated
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French (fr)
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祁树坤
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Priority to JP2017533840A priority Critical patent/JP6430650B2/ja
Priority to US15/538,450 priority patent/US9905680B2/en
Priority to EP15871728.0A priority patent/EP3240039B1/en
Publication of WO2016101654A1 publication Critical patent/WO2016101654A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/421—Insulated-gate bipolar transistors [IGBT] on insulating layers or insulating substrates, e.g. thin-film IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices

Definitions

  • This invention relates to semiconductor processes, and more particularly to a laterally insulated gate bipolar transistor.
  • Lateral Insulated-Gate Bipolar Transistor (Lateral Insulated-Gate Bipolar Transistor, LIGBT) is commonly used in the output stage of high-voltage power driving integrated circuits.
  • LIGBT Lateral Insulated-Gate Bipolar Transistor
  • LDMOS metal-oxide-semiconductor field-effect transistors
  • the LIGBT structure is injected by electrons and holes. The formation of a conductance modulation effect can result in a lower on-resistance.
  • the turn-off time is long, so there is a problem that the power consumption is too large. Since the on-resistance and the off-time are inversely related to the hole concentration, how to balance the on-resistance and the off-time is the direction for continuous improvement of the LIGBT device.
  • a lateral insulated gate bipolar transistor comprising a substrate, an anode end and a cathode end on the substrate, and a drift region and a gate between the anode end and the cathode end, the anode end including N on the substrate Type buffer, P well in N-type buffer, N-region in P-well, two P+ shallow junctions on P-well surface and N+ shallow junction between these two P+ shallow junctions.
  • the P+ shallow junction and the P-well are longitudinally implanted, and the P+ shallow junction is laterally implanted, thereby realizing efficient injection of holes and reducing on-resistance; when the reverse is turned off, N
  • the type buffer, N-zone, and N+ shallow junction form a path for quickly extracting minority carriers (holes), achieving the purpose of fast turn-off and reducing the off-state loss.
  • FIG. 1 is a schematic cross-sectional view of a laterally insulated gate bipolar transistor in an embodiment
  • Figure 2 is a schematic illustration of the flow of holes in the device of Figure 1 with the anode forward biased.
  • FIG. 1 is a schematic cross-sectional view of a laterally insulated gate bipolar transistor including a substrate 10, an anode terminal and a cathode terminal on a substrate 10, and between an anode terminal and a cathode terminal, in an embodiment.
  • the anode end includes an N-type buffer 51 on the substrate, a P-well 53 in the N-type buffer 51, an N-region 55 in the P-well 53, and two P+ shallow junctions 57 on the surface of the P-well 53. N+ shallow junction 59 between junctions 57, and anode metal 52 as the electrode of the collector.
  • the cathode end includes a P+ region 41 on the substrate 10, a P-type body region 43 between the P+ region 41 and the anode terminal, an N+ region 45 on the surface of the P-type body region 43, and a cathode metal 42 as an electrode of the emitter.
  • Gate 62 includes a gate oxide layer (not shown in FIG. 1) and a polysilicon gate on the gate oxide layer.
  • the gate 62 when the gate 62 is forward biased, the device channel is opened, and the electron current flows from the N+ region 45 of the emitter through the channel of the P-type body region 43 to the drift region 30, N.
  • Type buffer 51 When the P+ shallow junction 57 at the anode end is forward biased and the bias voltage is low, the holes begin to be injected downward into the N-type buffer 51 from the P+ shallow junction 57 and the P well 53 at the anode end; The bias voltage on the metal 52 is increased, and the P+ shallow junction 57 is also laterally injected into the drift region 30 through the N-type buffer 51, thereby realizing high-efficiency multipath majority carrier hole injection, greatly reducing the conduction. Through resistance.
  • the anode When the lateral insulated gate bipolar transistor is turned off, the anode is reverse biased, and the N+ shallow junction 59, the N-region 55, and the N-type buffer 51 form a low-impedance path for electron injection, and the drift region 30 begins to be extracted faster. Residual minority carrier holes are used for fast shutdown, thus ensuring faster switching speeds. Therefore, when the device is conducting, the P+ shallow junction 57, the P well 53 is longitudinally implanted and the P+ shallow junction 57 is laterally injected, thereby achieving efficient injection of holes and reducing on-resistance; when the reverse is turned off, the N-type buffer is turned off. 51. The N-zone 55 and the N+ shallow junction 59 form a path for rapidly extracting the minority (hole), achieving the purpose of fast shutdown and reducing the off-state loss.
  • the doping concentration of each region satisfies the following relationship: the doping concentration of the N-type buffer 51 is smaller than that of the P well 53, and the doping concentration of the P well 53 is slightly smaller than the N-region 55, the N-region The doping concentration of 55 is less than two P+ shallow junctions 57 and N+ shallow junctions 59.
  • N-zone 55 is the key to minority carrier lifetime control.
  • Figure 2 shows the flow of holes when the anode is forward biased with arrows.
  • the one of the two P+ shallow junctions 57 near the cathode end and the N+ shallow junction 59 are provided on the surface of the N-zone 55.
  • the doping concentration of the N-type buffer region 51 is about 10 15 /cm 3
  • the doping concentration of the P-well 53 is about 10 17 /cm 3
  • the impurity concentration is about 10 20 /cm 3 .
  • the anode end is first implanted with N-type ions, undergoes high temperature, and is pushed for a long time to form a deep and light N-type buffer 51, which can capture the minority when turned off. Then, P-type ions are implanted into the N-type buffer 51 and thermally annealed to form a P-well 53 which is implanted with N-type ions and annealed to form an N-region 55 having a certain depth and a deep junction depth as a channel for injecting electrons and extracting holes of a certain width. Then, it is injected to form P+ shallow junction 57 and N+ shallow junction 59.
  • Silicon-on-insulator (SOI) technology is gaining increasing importance in HVIC and SPIC applications, while IGBT devices are low on-resistance due to high input impedance and conductance modulation effects in power device applications. Increasingly important. Compared with bulk silicon isolation devices, SOI's LIGBT devices have low leakage, low on-resistance, high input impedance, high package density, fast switching, significant noise reduction and feasible under high temperature operation due to slot isolation. Sexuality, a wider range of applications in automotive electronics, home electronics and communications and industrial applications.
  • the LIGBT shown in FIG. 1 is a silicon-on-insulator type lateral insulated gate bipolar transistor (SOI-LIGBT) including a buried oxide layer 20 between a substrate 10 and a drift region 30, wherein the substrate 10 is a P-type substrate.
  • the drift region 30 is an N-type drift region.
  • the junction depth of the P+ region 41 is deep and extends to the buried oxide layer 20.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)

Abstract

一种横向绝缘栅双极型晶体管，包括衬底(10)、衬底上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区(30)和栅极(62)，所述阳极端包括衬底(10)上的N型缓冲区(51)，N型缓冲区(51)内的P阱(53)，P阱(53)内的N-区(55)，P阱(53)表面的两个P+浅结(57)和这两个P+浅结(57)之间的N+浅结(59)。

Description

横向绝缘栅双极型晶体管
【技术领域】
本发明涉及半导体工艺，特别是涉及一种横向绝缘栅双极型晶体管。
【背景技术】
横向绝缘栅双极型晶体管（Lateral Insulated-Gate Bipolar Transistor, LIGBT）常用于高压功率驱动集成电路的输出级，与横向双扩散金属氧化物半导体场效应管（LDMOS）的单载子降低导通电阻相比，LIGBT结构由于电子、空穴的双载子注入形成电导调制效应能带来较低的导通电阻。
但在关断时，LIGBT的漂移区中由于残留少子空穴，关断时间偏长，故存在功耗偏大的问题。由于导通电阻及和关断时间与空穴浓度呈相反关系，因此如何在导通电阻和关断时间之间取得平衡，成为LIGBT器件持续改进的方向。
【发明内容】
基于此，有必要提供一种在保证低导通电阻的基础上能够快速关断的横向绝缘栅双极型晶体管。
一种横向绝缘栅双极型晶体管，包括衬底、衬底上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区和栅极，所述阳极端包括衬底上的N型缓冲区，N型缓冲区内的P阱，P阱内的N-区，P阱表面的两个P+浅结和这两个P+浅结之间的N+浅结。
上述横向绝缘栅双极型晶体管在正向导通时，P+浅结、P阱纵向注入，P+浅结横向注入，实现了空穴的高效注入，降低了导通电阻；反向关断时，N型缓冲区、N-区、N+浅结形成快速抽取少子（空穴）的路径，达到快速关断的目的，降低了关态损耗。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中横向绝缘栅双极型晶体管的截面示意图；
图2是图1所示器件在阳极正向偏置时空穴的流向示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1是一实施例中横向绝缘栅双极型晶体管的截面示意图，横向绝缘栅双极型晶体管包括衬底10、衬底10上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区30和栅极62。阳极端包括衬底上的N型缓冲区51，N型缓冲区51内的P阱53，P阱53内的N-区55，P阱53表面的两个P+浅结57，两个P+浅结57之间的N+浅结59，以及作为集电极的电极的阳极金属52。阴极端包括衬底10上的P+区41，P+区41与阳极端之间的P型体区43，P型体区43表面的N+区45，以及作为发射极的电极的阴极金属42。栅极62包括栅氧化层（图1中未示）和栅氧化层上的多晶硅栅。
上述横向绝缘栅双极型晶体管，当栅极62正向偏置时，器件沟道打开，电子电流由发射极的N+区45穿过P型体区43的沟道先后进入漂移区30、N型缓冲区51。而当阳极端的P+浅结57正向偏置且偏置电压较低时，空穴开始由阳极端的P+浅结57和P阱53向下注入进N型缓冲区51中；随着阳极金属52上的偏置电压升高，P+浅结57横向也经N型缓冲区51注入空穴进漂移区30，实现了高效率多路径的多数载流子空穴注入，极大降低了导通电阻。当横向绝缘栅双极型晶体管关断时，阳极反向偏置，N+浅结59、N-区55、N型缓冲区51形成电子注入的低阻路径，开始较快地抽取漂移区30中残余的少数载流子空穴，达到快速关断的目的，从而保证了较快的开关速度。因此，器件正向导通时，P+浅结57、P阱53纵向注入与P+浅结57横向注入，实现了空穴的高效注入，降低了导通电阻；反向关断时，N型缓冲区51、N-区55、N+浅结59形成快速抽取少子（空穴）的路径，达到快速关断的目的，降低了关态损耗。
在图1所示实施例中，各个区域的掺杂浓度满足如下关系：N型缓冲区51的掺杂浓度小于P阱53，P阱53的掺杂浓度略小于N-区55，N-区55的掺杂浓度小于两个P+浅结57及N+浅结59。N-区55是少子寿命控制的关键，为其设计合适的掺杂浓度，就能够形成纵向（P+浅结57→N-区55→P阱53）的VPNP。图2用箭头示出了阳极正向偏置时空穴的流向。为了获得理想的载流子流动路径，在图1和图2所示实施例中，两个P+浅结57中靠近阴极端的那个以及N+浅结59设于N-区55的表面。
在其中一个实施例中，N型缓冲区51的掺杂浓度约为1015/cm3， P阱53的掺杂浓度约为1017/cm3， P+浅结57和N+浅结59的掺杂浓度约为1020/cm3。
在制造时，阳极端先通过注入N型离子，经历高温、长时间推阱，形成深且淡的N型缓冲区51，可以在关断时俘获少子。之后向N型缓冲区51中注入P型离子并热退火形成P阱53，注入N型离子并退火形成一定深度纵向结深的N-区55，作为一定宽度的注入电子、抽取空穴的通道，再之后注入形成P+浅结57、N+浅结59。
绝缘体上硅（SOI）技术正在HVIC及SPIC应用领域体现出愈来愈大的重要性，而IGBT器件则由于高输入阻抗及电导调制效应带来的低导通电阻特性，在功率器件应用领域中日益占据重要地位。相比于体硅结隔离型器件，SOI的LIGBT器件由于槽式隔离带来的低漏电、低开态电阻、高输入阻抗、高封装密度、快速开关、降噪效果显著及高温工作下的可行性，在汽车电子、家用电子及通信和工业应用上取得较为广泛的应用。尤为重要的是需要高效率的空穴注入及显著的电导调制效应来降低开态电阻，但也相应增加了器件关断时，少子空穴无法较快湮灭引起的关断损耗。图1所示的LIGBT为绝缘体上硅型横向绝缘栅双极型晶体管（SOI-LIGBT），包括位于衬底10和漂移区30之间的埋氧层20，其中衬底10为P型衬底，漂移区30为N型漂移区。P+区41的结深较深，一直延伸至埋氧层20。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种横向绝缘栅双极型晶体管，包括衬底、位于衬底上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区和栅极，所述阳极端包括衬底上的N型缓冲区，位于所述N型缓冲区内的P阱，位于所述P阱内的N-区，以及位于所述P阱表面的两个P+浅结和位于所述两个P+浅结之间的N+浅结。
  2. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述N型缓冲区的掺杂浓度小于所述P阱，所述P阱的掺杂浓度小于所述N-区，所述N-区的掺杂浓度小于所述两个P+浅结和N+浅结。
  3. 根据权利要求2所述的横向绝缘栅双极型晶体管，其特征在于，所述N型缓冲区的掺杂浓度为1*1015~1*1016/cm3，所述P阱的掺杂浓度为1*1017~1*1018/cm3，所述两个P+浅结和N+浅结的掺杂浓度为1*1020~1*1021/cm3。
  4. 根据权利要求3所述的横向绝缘栅双极型晶体管，其特征在于，所述N型缓冲区的掺杂浓度为5*1015/cm3，所述P阱的掺杂浓度为8*1017/cm3。
  5. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述横向绝缘栅双极型晶体管为绝缘体上硅型横向绝缘栅双极型晶体管，所述横向绝缘栅双极型晶体管还包括位于衬底和漂移区之间的埋氧层。
  6. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述衬底为P型衬底，所述漂移区为N型漂移区。
  7. 根据权利要求6所述的横向绝缘栅双极型晶体管，其特征在于，所述阴极端包括位于所述衬底上的P+区，位于所述P+区与阳极端之间的P型体区，以及位于所述P型体区表面的N+区。
  8. 根据权利要求7所述的横向绝缘栅双极型晶体管，其特征在于，所述P+区延伸至所述埋氧层。
  9. 根据权利要求7所述的横向绝缘栅双极型晶体管，其特征在于，所述阳极端还包括阳极金属、所述阴极端还包括阴极金属，所述栅极包括栅氧化层和栅氧化层上的多晶硅栅。
  10. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述两个P+浅结中更靠近所述阴极端的一个和所述N+浅结设于所述N-区的表面。
PCT/CN2015/089302 2014-12-22 2015-09-10 横向绝缘栅双极型晶体管 Ceased WO2016101654A1 (zh)

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JP2017533840A JP6430650B2 (ja) 2014-12-22 2015-09-10 横型絶縁ゲートバイポーラトランジスタ
US15/538,450 US9905680B2 (en) 2014-12-22 2015-09-10 Lateral insulated-gate bipolar transistor
EP15871728.0A EP3240039B1 (en) 2014-12-22 2015-09-10 Lateral insulated-gate bipolar transistor

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