WO2016101719A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

Info

Publication number
WO2016101719A1
WO2016101719A1 PCT/CN2015/094175 CN2015094175W WO2016101719A1 WO 2016101719 A1 WO2016101719 A1 WO 2016101719A1 CN 2015094175 W CN2015094175 W CN 2015094175W WO 2016101719 A1 WO2016101719 A1 WO 2016101719A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
source
drain
active layer
doped region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/094175
Other languages
English (en)
French (fr)
Inventor
石磊
许晓伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US15/104,524 priority Critical patent/US20160365458A1/en
Priority to EP15866397.1A priority patent/EP3070746A4/en
Publication of WO2016101719A1 publication Critical patent/WO2016101719A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/023—Manufacture or treatment of FETs having insulated gates [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate, a method for fabricating the same, and a display device having the array substrate.
  • each pixel is driven by a TFT (Thin Film Transistor) integrated behind the pixel, so that it can be high speed and high. Brightness, high contrast display screen information.
  • TFT Thin Film Transistor
  • polysilicon or amorphous silicon is often used to fabricate TFTs.
  • the carrier mobility of polycrystalline silicon is 10-200 cm 2 /V, which is significantly higher than the carrier mobility of amorphous silicon (1 cm 2 /V), so polycrystalline silicon has higher capacitance and storage than amorphous silicon.
  • TFTs are generally formed on glass substrates. Due to the thermodynamic limitations of glass, the crystallization characteristics of polysilicon TFTs and the process of annealing after ion implantation are often not effectively restored, and large in the case of reverse bias voltage. Leakage current affects the normal use of the TFT.
  • LDD Lightly Doped Drain
  • the present invention is directed to an array substrate, a method of fabricating the same, and a display device having the same, to overcome the light doped drain region (LDD) provided in the prior art for reducing the off current of the TFT.
  • LDD light doped drain region
  • an array substrate includes a substrate on which a first gate electrode and a first gate insulating layer are sequentially disposed, and an active layer is disposed on the first gate insulating layer, and the active layer is provided.
  • the second gate insulating layer, the second gate electrode, the third gate insulating layer and the source and drain electrodes are sequentially disposed on the layer, and the source and drain electrodes are on the third gate insulating layer:
  • the outer two-side regions of the active layer corresponding to the second gate are respectively source and drain lightly doped regions and source and drain heavily doped regions, wherein the source lightly doped regions and the lightly doped light are doped
  • the region is adjacent to the second gate, the source heavily doped region is adjacent to the source lightly doped region and the drain heavily doped region is adjacent to the drain lightly doped region, the source and drain electrodes are opposite to the source and drain Doped region electrical connection;
  • the first gate is disposed under the drain light doped region corresponding to the drain electrode or the first gate includes a first gate first sub-portion and a first gate second sub-portion. They are respectively disposed under the source light-doped region and the drain light-doped region corresponding to the source and drain electrodes.
  • the active layer is a polycrystalline active layer formed by crystallization treatment of an amorphized oxide.
  • the active layer is low temperature polysilicon.
  • the third gate insulating layer and the second gate insulating layer are provided with via holes, and the source and drain electrodes are in contact with the source and drain heavily doped regions through via holes.
  • a buffer layer is further disposed between the substrate and the first gate.
  • a display device comprising the above array substrate.
  • a method for fabricating an array substrate including:
  • the first gate is disposed under the drain light doped region corresponding to the drain electrode or the first gate includes a first gate first sub-portion and a first gate second sub-portion.
  • the source light-doped region and the light-doped region are respectively disposed under the source and drain electrode corresponding regions.
  • the active layer is a polycrystalline active layer formed by a crystallization treatment process from an amorphized oxide.
  • the active layer is low temperature polysilicon
  • the crystallization treatment process is excimer laser annealing.
  • the step of performing source, drain heavily doping, and source and drain light doping on the outer two sides of the region of the active layer corresponding to the second gate specifically includes:
  • the photoresist is stripped, and the active layer region not blocked by the second gate is again subjected to light doping treatment.
  • the first gate 3 (bottom gate) and the second gate 7 (top gate) are disposed and an LDD structure is employed.
  • the bottom gate is also opened at the same time, so that the LDD region also induces carriers, so that the LDD region acts on the bottom gate electric field.
  • the adverse effect of the on-state current Ion due to light doping can be avoided; on the other hand, when the top gate electric field of the TFT is removed, it is turned off. At this time, the bottom gate also removes its electric field, which reduces the off-state leakage current of the TFT, that is, the advantage of using the LDD structure to reduce the off-state leakage current Ioff.
  • FIG. 6 are schematic structural diagrams of respective fabrication steps of an array substrate according to an embodiment of the invention.
  • FIG. 7 is a schematic structural view of an array substrate according to another embodiment of the present invention.
  • FIG. 8 is a flow chart of a method of fabricating an array substrate according to an embodiment of the invention.
  • an embodiment of the present invention provides an array substrate 100 including a substrate 1 , which is provided with an (optional) buffer layer 2 , a first gate 3 (ie, a bottom gate), and a first
  • the gate insulating layer 4 is provided with an active layer 5 on the first gate insulating layer 4, and the second gate insulating layer 6 and the second gate 7 (ie, the top gate) are sequentially disposed on the active layer 5
  • the tri-gate insulating layer 11, the source electrode 12, and the drain electrode 13 are on the third gate insulating layer 11.
  • the outer side regions of the region of the active layer 5 corresponding to the second gate 7 are source and drain lightly doped regions 91 and 101 and source and drain heavily doped regions 92 and 102, respectively, wherein the source is light.
  • the doped region 91 and the drain lightly doped region 101 are adjacent to portions of the active layer 5 corresponding to the second gate 7 and are respectively located on both sides of the portion, and the source heavily doped region 92 is adjacent to the source lightly doped region 91 and the drain heavily doped region 102 is in close proximity to the drain lightly doped region 101.
  • the first gate 3 is divided into two parts, and includes a first gate first sub-portion 31 and a first gate second sub-portion 32, which are respectively disposed on the source and drain electrodes 12 and 13 Below the corresponding lightly doped regions, that is, below the source lightly doped region 91 and the drain lightly doped region 101, respectively.
  • the first gate 3 (bottom gate) and the second gate 7 (top gate) are provided and an LDD structure is employed.
  • the bottom gate is also opened at the same time, so that the LDD region also induces carriers, so that the LDD region acts on the bottom gate electric field.
  • the adverse effect of the on-state current Ion due to light doping can be avoided; on the other hand, when the top gate electric field of the TFT is removed, it is turned off. At this time, the bottom gate also removes its electric field, which reduces the off-state leakage current of the TFT, that is, the advantage of using the LDD structure to reduce the off-state leakage current Ioff.
  • the active layer 5 is a polycrystalline active layer formed by crystallization treatment of an amorphized oxide, wherein the active layer 5 is low temperature polysilicon.
  • the third gate insulating layer 11 and the second gate insulating layer 6 are provided with via holes 16 and 17, and the source electrode 12 and the drain electrode 13 pass through the via holes 16 and 17, respectively, and the source and drain electrodes.
  • the heavily doped regions 92 and 102 are in contact connection.
  • the source and drain heavily doped regions 92 and 102 are located outside the source and drain light doped regions 91 and 101, away from the active layer 5.
  • the off-state leakage current of the TFT is reduced by the LDD structure, and the on-state current of the TFT is improved by the bottom gate structure, thereby improving the yield of the product.
  • FIG. 7 a schematic structural view of an array substrate according to another embodiment of the present invention is shown.
  • only a portion of the first gate 3 is disposed under the drain light doping region 101 corresponding to the drain electrode 13 .
  • the first gate 3 and the second gate 7 are simultaneously provided, and the advantage of the off-state current is reduced by the LDD.
  • the bottom gate when the TFT is working, that is, when the top gate is applied with a gate voltage, the bottom gate is also opened at the same time, so that the LDD region also induces carriers, so that the LDD region acts on the bottom gate electric field.
  • the adverse effects of the on-state current Ion due to light doping can be avoided.
  • the top gate electric field of the TFT is removed, it is in a closed state. At this time, the bottom gate also removes its electric field, which reduces the off-state leakage current of the TFT, that is, the LDD structure can be used to reduce the off-state leakage current Ioff. advantage.
  • an embodiment of the present invention further provides a display device, including the array base described in any of the foregoing embodiments. board.
  • the array substrate includes, but is not limited to, a liquid crystal display, a liquid crystal television, a liquid crystal display, etc., and may also be a display device that requires a display module such as a digital photo frame, an electronic paper, or a mobile phone.
  • a method for fabricating an array substrate according to an embodiment of the present invention will be described below with reference to FIG. 8.
  • the specific steps include:
  • Step S31 forming a pattern of the first gate on the substrate; alternatively, first forming a buffer layer on the substrate, and then forming a pattern of the first gate on the buffer layer; and if necessary, on the substrate or the buffer layer Forming a first gate structure including a first gate first sub-portion and a first gate second sub-portion, or forming a first gate structure having only one portion;
  • Step S32 forming a first gate insulating layer on the substrate on which the above steps are completed;
  • Step S33 forming an active layer on the substrate on which the above steps are completed;
  • Step S34 forming a second gate insulating layer on the substrate on which the above steps are completed;
  • Step S35 forming a pattern of the second gate on the substrate on which the above steps are completed;
  • Step S36 performing source and drain heavily doping and source and drain light doping on the outer two sides of the active layer corresponding to the second gate, wherein the source lightly doped region and the drain lightly doped region are tight. Portions of the active layer corresponding to the second gate and respectively on both sides of the portion, the source heavily doped region is next to the source lightly doped region and the drain heavily doped region is next to the drain Lightly doped area;
  • Step S37 forming a third gate insulating layer on the substrate on which the above steps are completed, and forming a via hole;
  • Step S38 forming source and drain electrode patterns on the substrate on which the above steps are completed, and the source and drain electrodes are electrically connected to the source and drain heavily doped regions through via holes;
  • the first gate is disposed under the drain light doped region corresponding to the drain electrode.
  • the first gate when the first gate is divided into two parts, that is, the first gate first sub-portion 31 and the first gate second sub-portion 32, the first gate is The sub-portions are respectively disposed under the lightly doped regions corresponding to the source and drain electrodes.
  • the active layer is a polycrystalline active layer formed by an amorphized oxide through a crystallization process
  • the active layer is low temperature polysilicon
  • the crystallization process is Molecular laser annealing facilitates adhesion between layers.
  • step S36 of performing source, drain heavily doping, and source and drain light doping on the outer side regions of the region of the active layer corresponding to the second gate is specifically performed.
  • the photoresist 8 is left, and there is a critical dimension (CD) deviation 14 between the photoresist 8 and the second gate 7, which is active without being blocked by the photoresist 8.
  • the layer region is subjected to heavy doping treatment;
  • the photoresist 8 is stripped, and the active layer region not blocked by the second gate 7 is again subjected to light doping treatment.
  • the off-state leakage current of the TFT is reduced by the LDD structure, and the on-state current of the TFT is improved by the bottom gate structure, thereby improving the yield of the product.
  • Step S1 depositing a buffer layer 2 on the glass substrate 1 by plasma enhanced chemical vapor deposition (PECVD), and the material of the buffer layer 2 may be SiNx, SiOx or a mixed material of the two;
  • PECVD plasma enhanced chemical vapor deposition
  • Step S2 On the basis of completing step S1, a first gate 3 (ie, a bottom gate) is formed by a sputtering method, and a bottom gate pattern is formed by photolithography and etching processes, as shown in FIG.
  • the first gate 3 is divided into two portions, which are respectively disposed under the lightly doped regions corresponding to the subsequent source and drain electrodes.
  • Step S3 the first gate insulating layer 4 is formed by a PECVD method, and the active layer 5 is formed by PECVD, and then the amorphized active layer is formed by a crystallization technique such as an excimer laser annealing (ELA) technique. Crystal state, as shown in Figure 2.
  • ELA excimer laser annealing
  • Step S4 forming a second gate insulating layer 6 by a PECVD method on the substrate on which the above steps are completed, and then forming a second gate electrode 7 (ie, a top gate) by using a sputtering process, and then forming a top gate pattern by using a photolithography or etching process.
  • a second gate electrode 7 ie, a top gate
  • the process of removing the photoresist 8 is not performed after the top gate structure is wet-etched, that is, the photoresist 8 is left, and there is a CD deviation 14 between the photoresist 8 and the second gate 7 (Critical Dimension Bias). Deviation), as shown in Figure 3.
  • Step S5 on the substrate on which the above steps are completed, performing source and drain heavily doping on the active layer not blocked by the photoresist 8, forming source and drain heavily doped regions 92 and 102, the purpose of which is to achieve metal and Good contact of the electrode, after the heavy doping process is performed, the photoresist 8 is removed, and then the active layer portion not blocked by the second gate 7 is lightly doped to form an LDD structure, wherein the source and the drain are heavily doped.
  • the impurity region is not affected by the light doping process, as shown in Figure 4.
  • the source lightly doped region 91 and the drain lightly doped region 101 are next to the second gate 7
  • the source heavily doped region 92 is next to the source lightly doped region 91
  • the drain heavily doped region 102 is next to The lightly doped region 101 is drained.
  • the source, the heavy-duty doping and the light-doping treatment performed in this step can be performed by the existing process, and the improvement points in the patent application are source, drain heavily doped and lightly doped. Positional relationship, not in the process itself.
  • Step S6 on the substrate on which the above steps are completed, the third gate insulating layer 11 is formed by a PECVD process, and then the photolithography and etching processes of the source and drain metal electrode via holes are performed to form via holes 16 and 17, as shown in FIG. 5. Shown.
  • Step S7 depositing a source and a drain metal film on the substrate on which the above steps are completed, and using a sputtering process
  • the source and drain metal electrode layers are patterned, and the patterns of the source electrode 12 and the drain electrode 13 are formed by photolithography and etching processes, as shown in FIG. 6.

Landscapes

  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

提供了一种阵列基板及其制作方法和包括该阵列基板的显示装置。该阵列基板包括基板（1），基板上依次设有第一栅极（3）、第一栅绝缘层（4）、有源层（5）、第二栅绝缘层（6）、第二栅极（7）、第三栅绝缘层（11）和源、漏电极（12，13），有源层的与第二栅极相对应的区域的外部两侧区域分别为源、漏轻掺杂区域（91，101）和源、漏重掺杂区域（92，102），源、漏电极与源、漏重掺杂区域电连接；第一栅极设置于漏电极所对应的漏轻掺杂区域的下方或第一栅极包括第一栅极第一子部分（31）和第一栅极第二子部分（32），分别设置于源、漏电极对应的源轻掺杂区域和漏轻掺杂区域的下方。

Description

阵列基板及其制作方法和显示装置
本申请要求于2014年12月22日递交的、申请号为201410806984.2、发明名称为“一种显示装置、阵列基板及其制作方法”的中国专利申请的优先权，其全部内容通过引用并入本申请中。
技术领域
本发明涉及显示工艺技术领域，特别涉及一种阵列基板及其制作方法和具有所述阵列基板的显示装置。
背景技术
在LCD(液晶显示器)或OLED(有机发光二极管)显示器中，每个像素点都是由集成在像素点后面的TFT(Thin Film Transistor，薄膜场效应晶体管)来驱动，从而可以以高速度、高亮度、高对比度显示屏幕信息。在现有的技术中，多采用多晶硅或非晶硅来制造TFT。多晶硅的载流子迁移率为10-200cm2/V，明显高于非晶硅的载流子迁移率(1cm2/V)，所以多晶硅相对于非晶硅具有更高的电容性和存储性。
对于LCD和OLED，TFT一般形成于玻璃基板上，由于玻璃的热力学限制，多晶硅TFT的结晶特性及离子注入后退火的过程往往不能得到有效的恢复，在反偏电压的情况下会出现较大的漏电流，影响TFT的正常使用。
为了抑制TFT的漏电流，一般采用在TFT的栅极和源、漏极间进行轻掺杂的方式，尤其是在一些短沟道的情况下，轻掺杂漏区(Lightly Doped Drain，LDD)的宽度范围仅为0.3-1μm。由于轻掺杂漏区的设置，在TFT正常工作时，往往开态电流会受到影响，导致正常工作的TFT电阻过大，功耗增大。
发明内容
由此，本发明旨在提供一种阵列基板及其制作方法和具有所述阵列基板的显示装置，以克服现有技术中由于为了降低TFT关态电流而设置的轻掺杂漏区(LDD)结构所导致的TFT工作时开态电流降低的问题。
根据本发明一方面，提供一种阵列基板包括基板，所述基板上依次设有第一栅极、第一栅绝缘层，所述第一栅绝缘层上设有有源层，所述有源层上依次设有第二栅绝缘层、第二栅极、第三栅绝缘层和源、漏电极，所述源、漏电极在第三栅绝缘层上：
所述有源层的与第二栅极相对应的区域的外部两侧区域分别为源、漏轻掺杂区域和源、漏重掺杂区域，其中，源轻掺杂区域和漏轻掺杂区域紧邻第二栅极，源重掺杂区域紧邻所述源轻掺杂区域并且所述漏重掺杂区域紧邻所述漏轻掺杂区域，所述源、漏电极与所述源、漏重掺杂区域电连接；
其中，所述第一栅极设置于所述漏电极所对应的漏轻掺杂区域的下方或所述第一栅极包括第一栅极第一子部分和第一栅极第二子部分，分别设置于所述源、漏电极对应的源轻掺杂区域和漏轻掺杂区域的下方。
优选地，所述有源层为由非晶化的氧化物通过晶化处理后形成的多晶状态有源层。
优选地，所述有源层为低温多晶硅。
优选地，所述第三栅绝缘层和第二栅绝缘层上设有过孔，所述源、漏电极通过过孔与源、漏重掺杂区域接触连接。
优选地，所述基板和第一栅极之间还设有缓冲层。
根据本发明的另一方面，还提供一种显示装置，包括上述的阵列基板。
根据本发明的再一方面，还提供一种阵列基板的制作方法，包括：
在基板上形成第一栅极的图形；
在完成上述步骤的基板上形成第一栅绝缘层；
在完成上述步骤的基板上形成有源层，
在完成上述步骤的基板上形成第二栅绝缘层；
在完成上述步骤的基板上形成第二栅极的图形；
对有源层的与第二栅极相对应的区域的外部两侧区域进行源、漏重掺杂和源、漏轻掺杂，其中源轻掺杂区域和漏轻掺杂区域紧邻与第二栅极相对应的有源层，源重掺杂区域紧邻所述源轻掺杂区域并且所述漏重掺杂区域紧邻所述漏轻掺杂区域；
在完成上述步骤的基板上形成第三栅绝缘层，并且形成过孔，
在完成上述步骤的基板上形成源、漏电极的图形，所述源、漏电极与所述源、漏重掺杂区域通过过孔电连接；
其中，所述第一栅极设置于所述漏电极所对应的漏轻掺杂区域的下方或所述第一栅极包括第一栅极第一子部分和第一栅极第二子部分，分别设置于所述源、漏电极对应区域的源轻掺杂区域和漏轻掺杂区域的下方。
优选地，所述有源层为由非晶化的氧化物通过晶化处理工艺形成的多晶状态有源层。
优选地，有源层为低温多晶硅，且所述晶化处理工艺为准分子激光退火。
优选地，所述对有源层的与第二栅极相对应的区域的外部两侧区域进行源、漏重掺杂和源、漏轻掺杂的步骤具体包括：
待第二栅极刻蚀完成后，保留光刻胶，其中所述光刻胶与第二栅极之间存在临界尺寸(CD)偏差，对未被光刻胶阻挡的有源层区域进行重掺杂处理；
剥离光刻胶，对未被第二栅极阻挡的有源层区域再次进行轻掺杂处理。
通过本发明的阵列基板，设置第一栅极3(底栅)和第二栅极7(顶栅)并且采用LDD结构。一方面，结合底栅结构的工作原理，在TFT工作时，即顶栅加有栅压时，底栅也同时打开，令LDD区域也感生出载流子，这样LDD区域在底栅电场的作用下，加上轻掺杂区域产生的载流子，即可避免由于轻掺杂而导致的开态电流Ion降低的不利后果；另一方面，当TFT的顶栅电场去除后，其处于关闭状态，此时底栅也撤去其电场，降低了TFT关态漏电流，即，正好利用了LDD结构能够降低关态漏电流Ioff的优点。
附图说明
图1～图6为根据本发明一实施例的阵列基板的各个制作步骤中的结构示意图；
图7为根据本发明另一实施例的阵列基板的结构示意图；
图8为根据本发明实施例的阵列基板的制作方法的流程图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不是用来限制本发明的范围。
如图6所示，本发明实施例提供一种阵列基板100，包括基板1，所述基板1上设有(可选的)缓冲层2、第一栅极3(即底栅)和第一栅绝缘层4，所述第一栅绝缘层4上设有有源层5，所述有源层5上依次设有第二栅绝缘层6、第二栅极7(即顶栅)、第三栅绝缘层11、源电极12和漏电极13，所述源电极12和漏电极13在第三栅绝缘层11上。该有源层5的与第二栅极7相对应的区域的外部两侧区域分别为源、漏轻掺杂区域91和101以及源、漏重掺杂区域92和102，其中，该源轻掺杂区域91和漏轻掺杂区域101紧邻有源层5的与第二栅极7相对应的部分且分别处于该部分的两侧，源重掺杂区域92紧邻所述源轻掺杂区域91并且所述漏重掺杂区域102紧邻所述漏轻掺杂区域101。源、漏电极12和13与所述源、漏重掺杂区域92和102 电连接。
需要说明的是，该第一栅极3分为两个部分，包括第一栅极第一子部分31和第一栅极第二子部分32，分别设置于所述源、漏电极12和13对应的轻掺杂区域的下方，即，分别位于源轻掺杂区域91和漏轻掺杂区域101的下方。
本实施例的阵列基板中，设置第一栅极3(底栅)和第二栅极7(顶栅)并且采用LDD结构。一方面，结合底栅结构的工作原理，在TFT工作时，即顶栅加有栅压时，底栅也同时打开，令LDD区域也感生出载流子，这样LDD区域在底栅电场的作用下，加上轻掺杂区域产生的载流子，即可避免由于轻掺杂而导致的开态电流Ion降低的不利后果；另一方面，当TFT的顶栅电场去除后，其处于关闭状态，此时底栅也撤去其电场，降低了TFT关态漏电流，即，正好利用了LDD结构能够降低关态漏电流Ioff的优点。
在一实施例中，所述有源层5为由非晶化的氧化物通过晶化处理后形成的多晶状态有源层，其中，该有源层5为低温多晶硅。
在一实施例中，所述第三栅绝缘层11和第二栅绝缘层6上设有过孔16和17，所述源电极12和漏电极13分别通过过孔16和17与源、漏重掺杂区域92和102接触连接。其中，所述源、漏重掺杂区域92和102位于源、漏轻掺杂区域91和101外侧，远离所述有源层5。
在本发明提供的阵列基板中，通过LDD结构降低TFT关态漏电流，同时通过底栅结构提高TFT开态电流，从而提高了产品良品率。
如图7所示，示出了根据本发明另一实施例的阵列基板的结构示意图。在本实施例中，第一栅极3只有一部分，其设置于所述漏电极13所对应的漏轻掺杂区域101下方即可。
同样地，在本实施例的阵列基板中，同时设置该第一栅极3和第二栅极7，并且利用LDD降低关态电流的优点。一方面，结合底栅结构的工作原理，在TFT工作时，即顶栅加有栅压时，底栅也同时打开，令LDD区域也感生出载流子，这样LDD区域在底栅电场的作用下，加上轻掺杂区域产生的载流子，即可避免由于轻掺杂而导致的开态电流Ion降低的不利后果。另一方面，当TFT的顶栅电场去除后，其处于关闭状态，此时底栅也撤去其电场，降低了TFT关态漏电流，即，正好利用了LDD结构能够降低关态漏电流Ioff的优点。
另外，本发明实施例还提供一种显示装置，包括前述任一实施例所述的阵列基 板。该阵列基板包括但不限于液晶显示器、液晶电视、液晶显示屏等设备，还可以为数码相框、电子纸、手机等需要显示模组的显示装置。
下面将参考图8，描述根据本发明实施例的阵列基板的制作方法，具体步骤包括：
步骤S31、在基板上形成第一栅极的图形；可选地，也可以先在基板上形成缓冲层，然后在缓冲层上形成第一栅极的图形；根据需要，可以在基板或缓冲层上形成包括第一栅极第一子部分和第一栅极第二子部分的第一栅极结构，也可以形成仅有一个部分的第一栅极结构；
步骤S32、在完成上述步骤的基板上形成第一栅绝缘层；
步骤S33、在完成上述步骤的基板上形成有源层；
步骤S34、在完成上述步骤的基板上形成第二栅绝缘层；
步骤S35、在完成上述步骤的基板上形成第二栅极的图形；
步骤S36、对有源层的与第二栅极相对应的区域的外部两侧区域进行源、漏重掺杂和源、漏轻掺杂，其中源轻掺杂区域和漏轻掺杂区域紧挨有源层的与第二栅极相对应的部分并且分别处于该部分的两侧，源重掺杂区域紧挨所述源轻掺杂区域并且所述漏重掺杂区域紧挨所述漏轻掺杂区域；
步骤S37、在完成上述步骤的基板上形成第三栅绝缘层，并形成过孔；
步骤S38、在完成上述步骤的基板上形成源、漏电极图形，所述源、漏电极与所述源、漏重掺杂区域通过过孔电连接；
其中，所述第一栅极设置于所述漏电极对应的漏轻掺杂区域下方。在还一实施例中，当所述第一栅极分为两个部分，即包括第一栅极第一子部分31和第一栅极第二子部分32时，第一栅极的这两个子部分分别设置于所述源、漏电极对应的轻掺杂区域下方。
在一实施例中，所述有源层为由非晶化的氧化物通过晶化处理工艺形成的多晶状态有源层，该有源层为低温多晶硅，且所述晶化处理工艺为准分子激光退火，利于各膜层之间的贴附。
在一实施例中，例如如图3所示，对有源层的与第二栅极相对应的区域的外部两侧区域进行源、漏重掺杂和源、漏轻掺杂的步骤S36具体包括：
待第二栅极刻蚀完成后，保留光刻胶8，所述光刻胶8与第二栅极7之间存在临界尺寸(CD)偏差14，对未被光刻胶8阻挡的有源层区域进行重掺杂处理；
剥离光刻胶8，对未被第二栅极7阻挡的有源层区域再次进行轻掺杂处理。
本发明提供的阵列基板的制作方法中，通过LDD结构降低TFT关态漏电流，同时通过底栅结构提高TFT开态电流，从而提高了产品良品率。
下面结合附图1-6具体描述根据本发明实施例的阵列基板的制作方法的一个具体实例，包括如下步骤：
步骤S1、在玻璃基板1上利用等离子体增强化学气相沉积(PECVD)沉积缓冲层2，该缓冲层2的材料可以选用SiNx、SiOx或两者的混合材料；
步骤S2、在完成步骤S1的基础上采用溅射方法制作第一栅极3(即底栅)，通过光刻、刻蚀工艺，形成底栅图形，如图1所示。在该示例中，第一栅极3分为两个部分，分别设置于后续源、漏电极对应的轻掺杂区域下方。
步骤S3、利用PECVD方法制作第一栅绝缘层4，再利用PECVD制作有源层5，之后再通过晶化技术，如准分子激光退火(ELA)技术，使非晶化的有源层形成多晶状态，如图2所示。
步骤S4、在完成上述步骤的基板上利用PECVD方法制作第二栅绝缘层6，再利用溅射技术制作第二栅极7(即顶栅)，之后利用光刻、刻蚀工艺形成顶栅图形，且在湿刻完顶栅结构后不进行去除光刻胶8工艺，即保留光刻胶8，该光刻胶8与第二栅极7之间存在CD偏差14(Critical Dimension Bias，临界尺寸偏差)，如图3所示。
步骤S5、在完成上述步骤的基板上，在未被光刻胶8阻挡的有源层上进行源、漏重掺杂，形成源、漏重掺杂区域92和102，其目的是实现和金属电极的良好接触，在进行完重掺杂工艺后去除光刻胶8，之后对未被第二栅极7阻挡的有源层部分进行轻掺杂，形成LDD结构，其中，源、漏重掺杂区域不会被轻掺杂工艺所影响，如图4所示。其中，源轻掺杂区域91和漏轻掺杂区域101紧挨第二栅极7，源重掺杂区域92紧挨所述源轻掺杂区域91并且所述漏重掺杂区域102紧挨所述漏轻掺杂区域101。
需要说明的是，本步骤中进行的源、漏重掺杂和轻掺杂处理，采用现有工艺方法即可，本专利申请中的改进点为源、漏重掺杂和轻掺杂处理的位置关系，而不在工艺本身。
步骤S6、在完成上述步骤的基板上，利用PECVD工艺制做第三栅绝缘层11，之后进行源、漏金属电极过孔的光刻、刻蚀工艺，形成过孔16和17，如图5所示。
步骤S7、在完成上述步骤的基板上，沉积源、漏金属薄膜，利用溅射工艺制作 源、漏金属电极层，并利用光刻、刻蚀工艺形成源电极12和漏电极13的图形，如图6所示。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和变型，这些改进和变型也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，包括基板，所述基板上依次设有第一栅极、第一栅绝缘层，所述第一栅绝缘层上设有有源层，所述有源层上依次设有第二栅绝缘层、第二栅极、第三栅绝缘层和源、漏电极，所述源、漏电极在第三栅绝缘层上；
    所述有源层的与第二栅极相对应的区域的外部两侧区域分别为源、漏轻掺杂区域和源、漏重掺杂区域，其中，源轻掺杂区域和漏轻掺杂区域紧邻第二栅极，源重掺杂区域紧邻所述源轻掺杂区域并且所述漏重掺杂区域紧邻所述漏轻掺杂区域，所述源、漏电极与所述源、漏重掺杂区域电连接；
    其中，所述第一栅极设置于所述漏电极所对应的漏轻掺杂区域的下方；或所述第一栅极包括第一栅极第一子部分和第一栅极第二子部分，分别设置于所述源、漏电极对应的源轻掺杂区域和漏轻掺杂区域的下方。
  2. 根据权利要求1所述的阵列基板，其中，所述有源层为由非晶化的氧化物通过晶化处理后形成的多晶状态有源层。
  3. 根据权利要求2所述的阵列基板，其中，所述有源层为低温多晶硅。
  4. 根据权利要求1所述的阵列基板，其中，所述第三栅绝缘层和第二栅绝缘层上设有过孔，所述源、漏电极通过过孔与源、漏重掺杂区域接触连接。
  5. 如权利要求1所述的阵列基板，其中，所述基板和第一栅极之间还设有缓冲层。
  6. 一种显示装置，包括权利要求1-5任一项所述的阵列基板。
  7. 一种阵列基板的制作方法，包括：
    在基板上形成第一栅极的图形；
    在完成上述步骤的基板上形成第一栅绝缘层；
    在完成上述步骤的基板上形成有源层；
    在完成上述步骤的基板上形成第二栅绝缘层；
    在完成上述步骤的基板上形成第二栅极的图形；
    对有源层的与第二栅极相对应的区域的外部两侧区域进行源、漏重掺杂和源、漏轻掺杂，其中源轻掺杂区域和漏轻掺杂区域紧邻与第二栅极相对应的有源层，源重掺杂区域紧邻所述源轻掺杂区域并且所述漏重掺杂区域紧邻所述漏轻掺杂区域；
    在完成上述步骤的基板上形成第三栅绝缘层，并且形成过孔；
    在完成上述步骤的基板上形成源、漏电极的图形，所述源、漏电极与所述源、漏重掺杂区域通过过孔电连接；
    其中，所述第一栅极设置于所述漏电极所对应的漏轻掺杂区域的下方或所述第一栅极包括第一栅极第一子部分和第一栅极第二子部分，分别设置于所述源、漏电极对应区域的源轻掺杂区域和漏轻掺杂区域的下方。
  8. 根据权利要求7所述的制作方法，其中，所述有源层为由非晶化的氧化物通过晶化处理工艺形成的多晶状态有源层。
  9. 根据权利要求8所述的制作方法，其中，所述有源层为低温多晶硅，且所述晶化处理工艺为准分子激光退火。
  10. 根据权利要求7所述的制作方法，其中，所述对有源层的与第二栅极相对应的区域的外部两侧区域进行源、漏重掺杂和源、漏轻掺杂的步骤包括：
    待第二栅极刻蚀完成后，保留光刻胶，其中所述光刻胶与第二栅极之间存在临界尺寸偏差，对未被光刻胶阻挡的有源层区域进行重掺杂处理；
    剥离光刻胶，对未被第二栅极阻挡的有源层区域进行轻掺杂处理。
PCT/CN2015/094175 2014-12-22 2015-11-10 阵列基板及其制作方法和显示装置 Ceased WO2016101719A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/104,524 US20160365458A1 (en) 2014-12-22 2015-11-10 Array substrate, method for producing the same and display device
EP15866397.1A EP3070746A4 (en) 2014-12-22 2015-11-10 Array substrate, manufacturing method thereof and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410806984.2 2014-12-22
CN201410806984 2014-12-22

Publications (1)

Publication Number Publication Date
WO2016101719A1 true WO2016101719A1 (zh) 2016-06-30

Family

ID=52853958

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/094175 Ceased WO2016101719A1 (zh) 2014-12-22 2015-11-10 阵列基板及其制作方法和显示装置

Country Status (4)

Country Link
US (1) US20160365458A1 (zh)
EP (1) EP3070746A4 (zh)
CN (2) CN204391121U (zh)
WO (1) WO2016101719A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN204391121U (zh) * 2014-12-22 2015-06-10 京东方科技集团股份有限公司 一种显示装置、阵列基板及薄膜晶体管
CN104966696B (zh) * 2015-05-06 2017-11-28 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN104882414B (zh) * 2015-05-06 2018-07-10 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
US9768254B2 (en) 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors
CN105070764A (zh) * 2015-08-31 2015-11-18 深圳市华星光电技术有限公司 Tft、阵列基板、显示装置及tft的制备方法
CN105206216A (zh) * 2015-10-23 2015-12-30 武汉华星光电技术有限公司 显示装置及其应用在栅极驱动电路中的移位寄存电路
CN105390451B (zh) * 2015-12-03 2018-03-30 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法
CN105405893B (zh) * 2015-12-21 2018-09-14 华南理工大学 一种平面分离双栅薄膜晶体管及其制备方法
CN105762155A (zh) * 2016-03-07 2016-07-13 深圳市华星光电技术有限公司 薄膜晶体管阵列面板及其制作方法
CN107086227B (zh) * 2017-05-11 2020-02-21 京东方科技集团股份有限公司 发光电路、电子装置、薄膜晶体管及其制备方法
CN110212035B (zh) * 2018-08-10 2023-12-19 友达光电股份有限公司 晶体管结构及其操作方法
CN109742155B (zh) * 2019-01-09 2021-01-15 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、器件、芯片及显示装置
CN110379821A (zh) * 2019-07-18 2019-10-25 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制造方法
TWI798830B (zh) 2021-09-13 2023-04-11 友達光電股份有限公司 薄膜電晶體

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100051948A1 (en) * 2008-09-01 2010-03-04 Seiko Epson Corporation Thin film transistor, electro-optic device, and electronic apparatus
CN103383946A (zh) * 2013-07-12 2013-11-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
CN104022126A (zh) * 2014-05-28 2014-09-03 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN104319279A (zh) * 2014-11-10 2015-01-28 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN204243045U (zh) * 2014-12-22 2015-04-01 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN104538458A (zh) * 2014-12-22 2015-04-22 京东方科技集团股份有限公司 一种显示装置、阵列基板、薄膜晶体管及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950026032A (ko) * 1994-02-25 1995-09-18 김광호 다결정실리콘 박막트랜지스터의 제조방법
CN101131519A (zh) * 2006-08-24 2008-02-27 精工爱普生株式会社 电光装置用基板、电光装置以及电子设备
JP5796760B2 (ja) * 2009-07-29 2015-10-21 Ｎｌｔテクノロジー株式会社 トランジスタ回路
WO2011027705A1 (ja) * 2009-09-01 2011-03-10 シャープ株式会社 半導体装置、アクティブマトリクス基板、及び表示装置
US9553200B2 (en) * 2012-02-29 2017-01-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN103151388B (zh) * 2013-03-05 2015-11-11 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管及其制备方法、阵列基板
KR102227474B1 (ko) * 2013-11-05 2021-03-15 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판, 유기발광표시장치 및 박막트랜지스터 어레이 기판의 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100051948A1 (en) * 2008-09-01 2010-03-04 Seiko Epson Corporation Thin film transistor, electro-optic device, and electronic apparatus
CN103383946A (zh) * 2013-07-12 2013-11-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
CN104022126A (zh) * 2014-05-28 2014-09-03 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN104319279A (zh) * 2014-11-10 2015-01-28 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN204243045U (zh) * 2014-12-22 2015-04-01 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN104538458A (zh) * 2014-12-22 2015-04-22 京东方科技集团股份有限公司 一种显示装置、阵列基板、薄膜晶体管及其制作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3070746A4 *

Also Published As

Publication number Publication date
CN104538458A (zh) 2015-04-22
EP3070746A4 (en) 2017-09-06
CN204391121U (zh) 2015-06-10
EP3070746A1 (en) 2016-09-21
US20160365458A1 (en) 2016-12-15

Similar Documents

Publication Publication Date Title
WO2016101719A1 (zh) 阵列基板及其制作方法和显示装置
US10895774B2 (en) Array substrate, manufacturing method, display panel and display device
CN104362125B (zh) 阵列基板及其制作方法、显示装置
US9768323B2 (en) Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
US9922995B2 (en) Structure of dual gate oxide semiconductor TFT substrate including TFT having top and bottom gates
US9799677B2 (en) Structure of dual gate oxide semiconductor TFT substrate
CN103022149B (zh) 薄膜晶体管、阵列基板及制造方法和显示器件
KR102080732B1 (ko) 이중 게이트 구조를 기반으로 한 저온 폴리 실리콘 박막 트랜지스터 및 그 제조 방법
US11355519B2 (en) Array substrate, manufacturing method thereof, and display device
US20160276376A1 (en) Array substrate, method for fabricating the same, and display device
US20210126022A1 (en) Array substrate and method for manufacturing same
CN105097550A (zh) 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
US20170255044A1 (en) Tft substrates and the manufacturing methods thereof
US10409115B2 (en) Liquid crystal display panel, array substrate and manufacturing method thereof
CN106847703A (zh) 低温多晶硅薄膜晶体管的制造方法和显示装置
WO2018214732A1 (zh) 阵列基板及其制备方法、显示装置
WO2017070868A1 (zh) N型tft的制作方法
WO2017173712A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
US20200321475A1 (en) Manufacturing method for ltps tft substrate
WO2018149218A1 (zh) 薄膜晶体管及其制备方法、阵列基板及电子设备
WO2017193667A1 (zh) 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
CN108565247A (zh) Ltps tft基板的制作方法及ltps tft基板
KR100946560B1 (ko) 박막트랜지스터의 제조방법
US20170301705A1 (en) Ltps pixel unit and manufacturing method for the same
US10629746B2 (en) Array substrate and manufacturing method thereof

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15104524

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2015866397

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2015866397

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15866397

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE