WO2016107290A1 - 薄膜晶体管及其制作方法、阵列基板及其制作方法 - Google Patents

薄膜晶体管及其制作方法、阵列基板及其制作方法 Download PDF

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WO2016107290A1
WO2016107290A1 PCT/CN2015/094280 CN2015094280W WO2016107290A1 WO 2016107290 A1 WO2016107290 A1 WO 2016107290A1 CN 2015094280 W CN2015094280 W CN 2015094280W WO 2016107290 A1 WO2016107290 A1 WO 2016107290A1
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region
photoresist
active layer
ohmic contact
gate
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French (fr)
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左岳平
李良坚
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to EP15856162.1A priority Critical patent/EP3242319B1/en
Priority to US15/038,174 priority patent/US9935177B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor and a method for fabricating the same, an array substrate, and a method of fabricating the same.
  • the liquid crystal display mainly comprises an array substrate.
  • the array substrate is provided with an array of pixel units, and each of the pixel units is provided with a thin film transistor and a pixel electrode, wherein the thin film transistor controls a voltage applied to the pixel electrode.
  • the thin film transistor includes an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source, and a drain which are sequentially disposed.
  • the thin film transistor of the above structure when the thin film transistor is turned off, there is still a current inside the thin film transistor, and this current is generally referred to as a leak current of the thin film transistor.
  • the leakage current of the thin film transistor includes a thin film transistor body leakage current between the source and the drain, a leakage current between the gate and the source, and a thin film transistor edge leakage composed of a drain current between the gate and the drain. The current, in which the leakage current of the thin film transistor accounts for a large proportion of the leakage current of the thin film transistor body.
  • the excessive leakage current of the thin film transistor causes an adverse phenomenon such as a gray scale deviation of the pixel electrode of the liquid crystal display and a large energy consumption of the liquid crystal display.
  • the technical problem to be solved by the present invention is to provide a method for fabricating a thin film transistor and a method for fabricating the array substrate, which can reduce leakage current of the thin film transistor.
  • an aspect of the present invention provides a method of fabricating a thin film transistor, comprising the following steps:
  • the gate metal layer is over-etched to form a gate, and both ends of the photoresist are suspended;
  • the step S04 further includes:
  • Forming the photoresist to include a fully reserved region and a partial retention region at both ends of the fully-retained region
  • Step S05 further includes:
  • the partial retention region of the photoresist is removed by an ashing process such that the gate pre-structure covered under the partially suspended portion of the portion of the retention region exposes a portion and thins the fully-retained region.
  • the ohmic contact region includes a source ohmic contact region and a drain ohmic contact region, and the step S06 further includes:
  • the step S07 further includes:
  • the step S08 further includes:
  • the step S04 further includes:
  • Forming the photoresist to include a fully reserved region and a partial retention region at one end of the fully reserved region
  • Step S05 further includes:
  • the partial retention region of the photoresist is removed by an ashing process and the fully retained region is thinned.
  • the ohmic contact region includes a source ohmic contact region and a drain ohmic contact region, and the step S06 further includes:
  • the step S07 further includes:
  • the step S08 further includes:
  • the step S04 further includes:
  • Forming the photoresist to include a fully reserved region and a partial retention region at both ends of the fully-retained region
  • the step S05 further includes:
  • the ohmic contact region includes a source ohmic contact region and a drain ohmic contact region, and the step S06 further includes:
  • the step S07 further includes:
  • the step S08 further includes:
  • the ohmic contact region includes a source ohmic contact region and a drain ohmic contact region, and the step S06 further includes:
  • the step S07 further includes:
  • the step S08 further includes:
  • the step S04 further includes:
  • Forming a layer of the photoresist on the gate metal layer masking the photoresist with a gray scale mask, patterning the photoresist after exposure and development, and the photoresist is completely dropped
  • the photoresist corresponding to the completely transparent region of the gray-scale mask is removed, and the partial light-transmissive region of the gray-scale mask corresponds to the photolithography
  • the glue portion remains to form the partial retention region, and the photoresist corresponding to the light-shielding region of the gray-scale mask is completely left to form the complete retention region.
  • another aspect of the present invention provides a method of fabricating a thin film transistor, comprising the steps of:
  • the gate metal layer is over-etched to form a gate, and both ends of the photoresist are suspended;
  • the step S04 further includes:
  • Forming the photoresist to include a fully reserved region and a partial retention region at one end of the fully reserved region
  • Step S05 further includes:
  • the partial retention region of the photoresist is removed by an ashing process such that only one end of the photoresist that is not completely connected to the partial retention region is suspended.
  • the ohmic contact region includes a source ohmic contact region and a drain ohmic contact region, and the step S07 further includes:
  • the ohmic contact region includes a source ohmic contact region and a drain ohmic contact region, and the step S07 further includes:
  • the step S04 further includes:
  • the photoresist is completely disposed in a region where the active layer is located, and the photoresist corresponding to the completely transparent region of the gray-scale mask is removed, and a part of the transparent region of the gray-scale mask corresponds to
  • the photoresist partially remains to form the partial retention region, and the photoresist corresponding to the light-shielding region of the gray-scale mask is completely left to form the complete retention region.
  • still another aspect of the present invention provides a thin film transistor including an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source and a drain, and the interlayer insulating layer and a via hole corresponding to the source and the drain is disposed on the gate insulating layer;
  • the active layer includes a source ohmic contact region connected to the source, a drain ohmic contact region connected to the drain, a channel region under the gate for serving as a channel, and a lightly doped region between the drain ohmic contact region and the channel region, or
  • the active layer includes a source ohmic contact region connected to the source, a drain ohmic contact region connected to the drain, a channel region under the gate for serving as a channel, and Two lightly doped regions between the drain ohmic contact region and the channel region and between the source ohmic contact region and the channel region.
  • Still another aspect of the present invention provides a method of fabricating an array substrate comprising the method of fabricating a thin film transistor as described above.
  • Still another aspect of the present invention provides an array substrate including the thin film transistor as described above.
  • Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, the method of fabricating the thin film transistor including forming an active layer, a gate insulating layer, a gate, an interlayer insulating layer, a source and a drain on a substrate
  • the active layer includes a source ohmic contact region, a drain ohmic contact region, a channel region, and one or two lightly doped regions.
  • the lightly doped region increases the series resistance between the source and the drain, reducing leakage.
  • the electric field at the extreme edge or simultaneously reducing the fringe electric field of the source and the drain suppresses the generation of carriers, thereby reducing the leakage current of the thin film transistor.
  • the embodiment of the present invention further provides a method for fabricating an array substrate, and the method for fabricating the array substrate includes the method for fabricating any of the thin film transistors described above.
  • FIG. 1 is a schematic view of a first thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic view of a second thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a flow chart of a first manufacturing method of the thin film transistor shown in FIG. 1;
  • FIG. 4 is a schematic view showing a manufacturing process of the manufacturing method of FIG. 3;
  • FIG. 5 is a partial schematic view showing a second method of fabricating the thin film transistor shown in FIG. 1;
  • FIG. 6 is a partial schematic view showing a third method of fabricating the thin film transistor shown in FIG. 1;
  • FIG. 7 is a flow chart of a first manufacturing method of the thin film transistor shown in FIG. 2;
  • FIG. 8 is a schematic view showing a manufacturing process of the manufacturing method of FIG. 7;
  • FIG. 9 is a partial schematic view showing a second method of fabricating the thin film transistor shown in FIG. 2;
  • FIG. 10 is a partial schematic view showing a third method of fabricating the thin film transistor shown in FIG.
  • 1 substrate substrate
  • 2 active layer
  • 21 source ohmic contact
  • 22 drain ohmic contact
  • 23 lightly doped region
  • 24-channel region 3
  • gate insulating layer Metal layer
  • 41 gate pre-structure
  • 42 gate
  • 5 resist
  • 51 completely reserved
  • 52 partially reserved
  • 6 interlayer insulating layer
  • 7 via
  • 8 source
  • 9 Drain.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor, and the method for fabricating the thin film transistor includes:
  • An active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source and a drain are formed on the base substrate, and an interlayer insulating layer and a gate insulating layer are disposed corresponding to the source and the drain Holes are formed to form a thin film transistor as shown in FIG. 1 or 2.
  • the active layer 2 includes a source ohmic contact region 21 connected to the source electrode 8, a drain ohmic contact region 22 connected to the drain electrode 9, and a gate electrode 42. a lower channel region 24 for the channel and a lightly doped region 23 between the drain ohmic contact region 22 and the channel region 24, or
  • the active layer 2 includes a source ohmic contact region 21 connected to the source electrode 8, a drain ohmic contact region 22 connected to the drain electrode 9, and a gate electrode 42 under the gate electrode 42.
  • the active layer 2 formed since the hot carriers forming the leakage current are mainly concentrated near the drain 9, the active layer 2 formed only includes the lightly doped region 23 between the drain ohmic contact region 22 and the channel region 24, The leakage current of the thin film transistor can be effectively reduced. Compared with the thin film transistor in which the active layer 2 shown in FIG. 2 includes two lightly doped regions 23, the active layer 2 is formed only to include the ohmic contact region at the drain. When the lightly doped region 23 between the 22 and the channel region 24 is used, the mobility of carriers of the thin film transistor is higher, and the on-state current of the thin film transistor is larger, thereby making the overall performance of the thin film transistor better.
  • the method of fabricating the thin film transistor may further include other steps, for example, forming a buffer layer between the base substrate 1 and the active layer 2, wherein the buffer layer is used to laminate the substrate 1 and the active layer 2 isolation, avoiding the substrate substrate 1
  • the impurities enter the active layer 2, affecting the performance of the thin film transistor, and the buffer layer can also reduce the influence of the temperature on the substrate 1 during the process of forming the active layer 2.
  • the material of the buffer layer is preferably silicon oxide or silicon nitride.
  • the embodiment of the invention provides a method for fabricating a thin film transistor, which comprises forming an active layer, a gate insulating layer, a gate, an interlayer insulating layer, a source and a drain on a substrate.
  • the active layer includes a source ohmic contact region, a drain ohmic contact region, a channel region, and one or two lightly doped regions.
  • the lightly doped region increases the series resistance between the source and the drain, and the drain is lowered.
  • the electric field at the edge or simultaneously reducing the fringe electric field of the source and the drain suppresses the generation of carriers, thereby reducing the leakage current of the thin film transistor.
  • Embodiments of the present invention provide three methods of fabricating the thin film transistor as shown in FIG.
  • step S301 the active layer 2 is formed on the base substrate 1.
  • a layer of amorphous silicon is formed on the base substrate 1, and the amorphous silicon is converted into polycrystalline silicon by a crystallization process.
  • the crystallization process includes a laser annealing process, a metal induction process, and the like.
  • the crystallization process in the embodiment of the present invention is preferably a laser annealing process.
  • the basic principle of the laser annealing process is to irradiate the surface of the amorphous silicon with a high-energy excimer laser to melt, cool, and recrystallize the amorphous silicon. Thereby, amorphous silicon is converted into polycrystalline silicon.
  • a layer of photoresist is coated on the polysilicon, and after exposing, developing, etching, and stripping the photoresist, the active layer 2 is formed.
  • step S302 a gate insulating layer 3 is formed over the active layer 2.
  • the gate insulating layer 3 is formed on the base substrate 1 which has passed through step S301 by plasma enhanced chemical vapor deposition or the like.
  • step S303 the gate metal layer 4 is formed over the gate insulating layer 3.
  • a gate metal layer 4 is formed on the base substrate 1 which has passed through step S302 by sputtering, thermal evaporation or the like.
  • Step S304 forming a patterned photoresist on the gate metal layer 4 5.
  • the photoresist 5 completely falls within the area where the active layer 2 is located, and the photoresist 5 includes a completely reserved region 51 and a partial retention region 52 at both ends of the completely reserved region.
  • Step S305 the gate metal layer 4 is over-etched to form a gate pre-structure 41 such that a portion of the remaining region 52 located at one end of the fully-retained region 51 is suspended, and a portion of the remaining region 52 at the other end of the fully-retained region is partially suspended.
  • the gate metal layer 4 is subjected to a certain amount of over-etching so that the size of the gate pre-structure 41 formed after the etching is smaller than the size of the patterned photoresist 5, so that the portion located at one end of the fully-retained region 51 remains.
  • the region 52 is suspended, and the portion of the reserved portion 52 located at the other end of the completely reserved region is suspended.
  • Step S306 the partial retention region 52 of the photoresist 5 is removed by the ashing process, so that the gate pre-structure 41 covered under the partially suspended partial retention region 52 is exposed, and the fully-retained region 51 is thinned.
  • Step S307 ion implantation is performed on the active layer 2 such that a region of the active layer 2 that is not blocked by the photoresist 5 and the gate pre-structure 41 becomes the source ohmic contact region 21 and the drain ohmic contact region 22.
  • a P element is doped into the active layer 2 by ion implantation, wherein P in the region of the active layer 2 that is not blocked by the photoresist 5 and the gate pre-structure 41
  • the element is doped to increase the electron concentration of the region to form the source ohmic contact region 21 and the drain ohmic contact region 22, and the active layer 2 is blocked by the photoresist 5 and/or the gate pre-structure 41. There is no P element incorporation in the area.
  • Step S308, etching removes the portion of the exposed gate pre-structure 41 that is not covered by the photoresist 5 to form the gate electrode 42. As shown, the gate electrode 42 is covered with the photoresist 5.
  • Step S309 performing ion implantation on the active layer 2 such that a region of the active layer 2 exposed after etching the gate pre-structure 41 becomes a lightly doped region 23, and the photoresist 5 and the gate of the active layer 2 are The region where the pole 42 is simultaneously blocked becomes the channel region 24.
  • the method of ion implantation is applied to the active layer 2 Incorporating less P elements than in step S307, wherein the region of the active layer 2 exposed after etching the gate pre-structure 41 becomes the lightly doped region 23, and the photoresist 5 and the gate of the active layer 2 are The region where the pole 42 is simultaneously shielded is still doped without the P element and becomes the channel region 24.
  • step S310 the photoresist 5 is stripped.
  • Step S311 an interlayer insulating layer 6 is formed over the gate electrode 42, and a via hole 7 corresponding to the source electrode 8 and the drain electrode 9 is formed in the interlayer insulating layer 6 and the gate insulating layer 3 through a patterning process.
  • the interlayer insulating layer 6 is formed on the substrate 1 through the step S310 by plasma enhanced chemical vapor deposition or the like, and includes photolithography, masking, exposure, development, etching, and lift-off lithography.
  • a patterning process of the glue forms via holes 7 corresponding to the source 8 and the drain 9 in the interlayer insulating layer 6 and the gate insulating layer 3, wherein the via holes 7 are respectively located at the source ohmic contact region 21 and the drain ohms Above the contact zone 22.
  • Step S312 forming a source/drain metal layer over the interlayer insulating layer 6 and in the via hole 7, and then forming a source electrode 8 and a drain electrode 9 through a patterning process, and the source electrode 8 and the drain electrode 9 respectively pass through the via hole 7 and the source
  • the very ohmic contact region 21 and the drain ohmic contact region 22 are electrically connected.
  • a source/drain metal layer on the substrate 1 through the step S311 by sputtering, thermal evaporation, or the like, wherein an active drain metal layer is also formed in the via hole 7, and then using a photoresist including coating
  • the masking process of masking, exposing, developing, etching and stripping the photoresist forms a source 8 and a drain 9, and the source 8 and the drain 9 pass through the via 7 respectively with the source ohmic contact region 21 and the drain
  • the very ohmic contact regions 22 are electrically connected.
  • the second manufacturing method includes the following steps. Steps S501 to S503 in the second method are the same as steps S301 to S303 in the first method, and steps S510 to S511 are the same as steps S311 to S312. FIG. 5 only shows Schematic diagram of steps S504 to S509:
  • step S501 the active layer 2 is formed on the base substrate 1.
  • Step S502 forming a gate insulating layer 3 over the active layer 2.
  • step S503 the gate metal layer 4 is formed over the gate insulating layer 3.
  • Step S504 forming a patterned photoresist on the gate metal layer 4 5.
  • the photoresist 5 completely falls within the area where the active layer 2 is located, and the photoresist 5 includes a completely reserved region 51 and a partial retention region 52 at one end of the fully-retained region.
  • Step S505 the gate metal layer 4 is over-etched to form the gate electrode 42 such that the partial retention region 52 is suspended, and the end of the completely reserved region 51 not connected to the partial retention region is suspended.
  • Step S506 the partial retention region 52 of the photoresist 5 is removed by the ashing process, and the fully-retained region 51 is thinned.
  • the photoresist 5 of the fully-retained region here is thinned, the overall thickness of the fully-retained region 52 is still sufficiently thick to allow ions to pass through during subsequent ion implantation.
  • Step S507 ion implantation is performed on the active layer 2 such that a region of the active layer 2 that is not blocked by the photoresist 5 and the gate electrode 42 becomes a source ohmic contact region 21 and a drain ohmic contact region 22.
  • a P element is doped into the active layer 2 by ion implantation, wherein a region of the active layer 2 that is not blocked by the photoresist 5 and the gate 42 has a P element doping
  • the source ohmic contact region 21 and the drain ohmic contact region 22 are formed, and the region of the active layer 2 that is blocked by the photoresist 5 and/or the gate electrode 42 has no P element doping.
  • step S508 the photoresist 5 is stripped.
  • step S509 the active layer 2 is ion-implanted so that the region of the active layer exposed by the stripping of the photoresist 5 becomes the lightly doped region 23, and the region blocked by the gate 42 becomes the channel region 24.
  • a P element which is less than the step S507 is doped into the active layer 2 by ion implantation, wherein the exposed region after the photoresist 5 is peeled off becomes the lightly doped region 23, which is blocked by the gate 42 The region is still free of P-doping and becomes the channel region 24.
  • step S510 an interlayer insulating layer 6 is formed over the gate electrode 42, and a via hole 7 corresponding to the source electrode 8 and the drain electrode 9 is formed in the interlayer insulating layer 6 and the gate insulating layer 3 through a patterning process.
  • Step S511 forming a source and a drain in the upper portion of the interlayer insulating layer 6 and in the via hole 7.
  • the metal layer is then formed into a source 8 and a drain 9 by a patterning process, and the source 8 and the drain 9 are electrically connected to the source ohmic contact region 21 and the drain ohmic contact region 22 through vias 7, respectively.
  • the third manufacturing method specifically includes the following steps. Steps S601 to S603 in the third method are the same as steps S301 to S303 in the first method, and steps S609 to S610 are the same as steps S311 to S312. FIG. 6 only shows A schematic diagram of steps S604 to S608:
  • step S601 the active layer 2 is formed on the base substrate 1.
  • Step S602 forming a gate insulating layer 3 over the active layer 2.
  • step S603 the gate metal layer 4 is formed over the gate insulating layer 3.
  • Step S604 forming a patterned photoresist 5 over the gate metal layer 4, the photoresist 5 completely falls in the region where the active layer 2 is located, and the photoresist 5 includes the completely reserved region 51 and is located in the completely reserved region. A partial retention area 52 at one end.
  • Step S605 the gate metal layer 4 is over-etched to form the gate electrode 42 such that the partial retention region 52 is suspended, and the end of the complete retention region 51 not connected to the partial retention region 52 is suspended.
  • step S606 the partial retention region 52 of the photoresist 5 is removed by the ashing process, and the fully-retained region 51 is thinned.
  • the overall thickness of the completely-retained region is small, so that a small amount of ions can pass through in the subsequent ion implantation process.
  • Step S607 performing ion implantation on the active layer 2 such that a region of the active layer 2 that is not blocked by the photoresist 5 and the gate electrode 42 becomes a source ohmic contact region 21 and a drain ohmic contact region 22, and the active layer 2
  • the region blocked only by the photoresist 5 becomes the lightly doped region 23, and the region of the active layer 2 which is simultaneously blocked by the photoresist 5 and the gate electrode 42 becomes the channel region 24.
  • a P element is doped into the active layer 2 by ion implantation, wherein a region of the active layer 2 that is not blocked by the photoresist 5 and the gate 42 is doped a large amount, As the source ohmic contact region 21 and the drain ohmic contact region 22, the region of the active layer 2 that is only blocked by the photoresist 5 is implanted with a small amount of ions, and the doping amount is small. As the lightly doped region 23, the region of the active layer 2 which is simultaneously blocked by the photoresist 5 and the gate electrode 42 is not ion-implanted (i.e., zero-doped) to become the channel region 24.
  • step S608 the photoresist 5 is peeled off.
  • step S609 an interlayer insulating layer 6 is formed over the gate electrode 42, and a via hole 7 corresponding to the source electrode 8 and the drain electrode 9 is formed in the interlayer insulating layer 6 and the gate insulating layer 3 through a patterning process.
  • Step S610 forming a source/drain metal layer over the interlayer insulating layer 6 and in the via hole 7, and then forming a source electrode 8 and a drain electrode 9 through a patterning process, and the source electrode 8 and the drain electrode 9 respectively pass through the via hole 7 and the source
  • the very ohmic contact region 21 and the drain ohmic contact region 22 are electrically connected.
  • Embodiments of the present invention provide three methods of fabricating the thin film transistor as shown in FIG. 2.
  • the first manufacturing method specifically includes the steps shown in FIG. 7, wherein the steps S701 to S703 in the first method are the same as the steps S301 to S303 in the first method in the second embodiment, and the steps S711 to S712 and the steps are the same. S311 to S312 are the same, and FIG. 8 only shows a schematic diagram of steps S704 to S710:
  • step S701 the active layer 2 is formed on the base substrate 1.
  • step S702 the gate insulating layer 3 is formed over the active layer 2.
  • step S703 the gate metal layer 4 is formed over the gate insulating layer 3.
  • Step S704 forming a patterned photoresist 5 over the gate metal layer 4, the photoresist 5 completely falls in the region where the active layer 2 is located, and the photoresist 5 includes the completely reserved region 51 and is completely retained. A portion of the area at both ends of the zone is reserved 52.
  • Step S705 the gate metal layer 4 is over-etched to form a gate pre-structure 41 such that a portion of the remaining region 52 located at both ends of the fully-retained region 51 is partially suspended.
  • step S706 the partial retention region 52 of the photoresist 5 is removed by the ashing process, so that the gate pre-structure 41 covered under the partial retention region is exposed, and the fully-retained region 51 is thinned.
  • the fully-retained region 51 here is thinned, the overall thickness of the fully-retained region is still sufficiently thick to cause ions during subsequent ion implantation. Unable to pass.
  • Step S707 ion implantation is performed on the active layer 2 such that a region of the active layer 2 that is not blocked by the photoresist 5 and the gate pre-structure 41 becomes the source ohmic contact region 21 and the drain ohmic contact region 22.
  • a P element is doped into the active layer 2 by ion implantation, wherein a region of the active layer 2 that is not blocked by the photoresist 5 and the gate 42 has a P element doping
  • the source ohmic contact region 21 and the drain ohmic contact region 22 are formed, and the region of the active layer 2 that is blocked by the photoresist 5 and/or the gate pre-structure 41 has no P element doping.
  • Step S708 using the occlusion of the photoresist 5, removing the exposed portion of the gate pre-structure 41 by etching to form the gate electrode 42, and the formed gate electrode 42 is covered with the photoresist 5.
  • Step S709 performing ion implantation on the active layer 2, so that the region of the active layer 2 exposed by etching the gate pre-structure 41 becomes two lightly doped regions 23, while the photoresist 5 and the gate 42 are simultaneously The occluded area becomes the channel region 24.
  • step S707 by ion implantation, wherein the active layer 2 is exposed after etching the gate pre-structure 41
  • the region becomes two lightly doped regions 23, and the region of the active layer 2 which is simultaneously blocked by the photoresist 5 and the gate electrode 42 is still doped without the P element, and becomes the channel region 24.
  • step S710 the photoresist 5 is peeled off.
  • step S711 an interlayer insulating layer 6 is formed over the gate electrode 42, and a via hole 7 corresponding to the source electrode 8 and the drain electrode 9 is formed in the interlayer insulating layer 6 and the gate insulating layer 3 through a patterning process.
  • Step S712 forming a source/drain metal layer over the interlayer insulating layer 6 and in the via hole 7, and then forming a source electrode 8 and a drain electrode 9 through a patterning process, and the source electrode 8 and the drain electrode 9 respectively pass through the via hole 7 and the source
  • the very ohmic contact region 21 and the drain ohmic contact region 22 are electrically connected.
  • the second manufacturing method specifically includes the following steps, wherein steps S901 to S903 in the second method are the same as steps S301 to S303 in the first method in the second embodiment, and steps S909 to S910 are the same as steps S311 to S312.
  • Figure 9 shows only the steps Schematic diagram of S904 to step S908:
  • step S901 the active layer 2 is formed on the base substrate 1.
  • step S902 the gate insulating layer 3 is formed over the active layer 2.
  • step S903 the gate metal layer 4 is formed over the gate insulating layer 3.
  • Step S904 forming a patterned photoresist 5 over the gate metal layer 4, and the photoresist 5 completely falls within the area where the active layer 2 is located.
  • the photoresist 5 here is thick, and ions cannot pass through during the subsequent ion implantation process.
  • step S905 the gate metal layer 4 is over-etched to form the gate electrode 42, and both ends of the photoresist 5 are suspended.
  • Step S906 ion implantation is performed on the active layer 2 such that a region of the active layer 2 that is not blocked by the photoresist 5 and the gate electrode 42 becomes the source ohmic contact region 21 and the drain ohmic contact region 22.
  • a P element is doped into the active layer 2 by ion implantation, wherein a region of the active layer 2 that is not blocked by the photoresist 5 and the gate 42 has a P element doping
  • the source ohmic contact region 21 and the drain ohmic contact region 22 are formed, and the region of the active layer 2 that is blocked by the photoresist 5 and/or the gate electrode 42 has no P element doping.
  • step S907 the photoresist 5 is peeled off.
  • Step S908 performing ion implantation on the active layer 2 such that the region of the active layer 2 exposed by the stripping photoresist 5 becomes two lightly doped regions 23, while the region of the active layer 2 blocked by the gate 42 It becomes the channel region 24.
  • a P element which is less than the step S906 is doped into the active layer 2 by the method of ion implantation, so that the exposed area of the active layer 2 after peeling off the photoresist 5 becomes two
  • the lightly doped region 23, the region of the active layer 2 that is blocked by the gate 42 is still doped with the P element to become the channel region 24.
  • step S909 an interlayer insulating layer 6 is formed over the gate electrode 42, and a via hole 7 corresponding to the source electrode 8 and the drain electrode 9 is formed in the interlayer insulating layer 6 and the gate insulating layer 3 through a patterning process.
  • Step S910 forming a source and a drain in the upper layer of the interlayer insulating layer 6 and in the via hole 7.
  • the metal layer is then formed into a source 8 and a drain 9 by a patterning process, and the source 8 and the drain 9 are electrically connected to the source ohmic contact region 21 and the drain ohmic contact region 22 through vias 7, respectively.
  • the third manufacturing method specifically includes the following steps, wherein the steps S1001 to S1003 in the third method are the same as the steps S301 to S303 in the first method in the second embodiment, and the steps S1008 to S1009 are the same as the steps S311 to S312.
  • FIG. 10 only shows a schematic diagram of steps S1004 to S1007:
  • step S1001 the active layer 2 is formed on the base substrate 1.
  • step S1002 a gate insulating layer 3 is formed over the active layer 2.
  • step S1003 the gate metal layer 4 is formed over the gate insulating layer 3.
  • step S1004 a patterned photoresist 5 is formed over the gate metal layer 4, and the photoresist 5 completely falls within the area where the active layer 2 is located.
  • the photoresist 5 herein is thin, and a part of ions can pass through in the subsequent ion implantation process.
  • step S1005 the gate metal layer 4 is over-etched to form the gate electrode 42, and both ends of the photoresist 5 are suspended.
  • Step S1006 performing ion implantation on the active layer 2 such that a region of the active layer 2 that is not blocked by the photoresist 5 and the gate electrode 42 becomes a 21 and a drain ohmic contact region 22, and only the active layer 2 is photolithographically patterned.
  • the region blocked by the glue 5 becomes two lightly doped regions 23, and the region of the active layer 2 which is simultaneously blocked by the photoresist 5 and the gate electrode 42 becomes the channel region 24.
  • a P element is doped into the active layer 2 by ion implantation, wherein a region of the active layer 2 that is not blocked by the photoresist 5 and the gate electrode 42 becomes a source ohmic contact
  • the region 21 and the drain ohmic contact region 22 the region of the active layer 2 that is only blocked by the photoresist 5 becomes two lightly doped regions 23, and the active layer 2 is simultaneously blocked by the photoresist 5 and the gate electrode 42.
  • the region becomes the channel region 24.
  • step S1007 the photoresist 5 is peeled off.
  • Step S1008 an interlayer insulating layer 6 is formed over the gate electrode 42, and a via hole 7 corresponding to the source electrode 8 and the drain electrode 9 is formed in the interlayer insulating layer 6 and the gate insulating layer 3 through a patterning process.
  • Step S1009 forming a source and drain in the upper layer of the interlayer insulating layer 6 and in the via hole 7.
  • the electrode metal layer is then patterned by a patterning process to form a source 8 and a drain 9 which are electrically connected to the source ohmic contact region 21 and the drain ohmic contact region 22 through vias 7, respectively.
  • step S304, the step S504 and the step S604 described in the second embodiment, and the step S704 described in the third embodiment specifically include:
  • a photoresist 5 is formed on the gate metal layer 4, the photoresist 5 is covered with a gray-scale mask, and the photoresist 5 is patterned by exposure and development, and the photoresist 5 completely falls on the active layer 2.
  • the photoresist 5 corresponding to the completely transparent region of the gray-scale mask is removed, and the photoresist portion 5 corresponding to the partial light-transmissive region of the gray-scale mask remains, forming a partial retention region 52, gray scale
  • the photoresist 5 corresponding to the light-shielding region of the mask is completely left to form a completely reserved region 51.
  • the method of fabricating the thin film transistor provided by the embodiment of the present invention can make the active layer 2 of the formed thin film transistor include the source ohmic contact region 21 without increasing the number of the mask.
  • the drain ohmic contact region 22, the lightly doped region 23 and the channel region 24 are simple in fabrication and low in cost.
  • the length of the lightly doped region 23 formed by using the above various methods is determined by the amount of overetching when the gate pre-structure 41 or the gate electrode 42 is formed, due to the amount of over-etching during the etching process. Precisely controllable, therefore, the length of the lightly doped region 23 formed is accurate, thereby avoiding the excessive length of the lightly doped region 23 resulting in low carrier mobility of the thin film transistor or the length of the lightly doped region 23 being too small. This makes it impossible to reduce the leakage current of the thin film transistor.
  • each of the manufacturing methods in the second embodiment may further include: in step S301, step S501, and step S601, and each of the manufacturing methods in the third embodiment, before step S701, step S901, and step S1001.
  • a buffer layer is formed on the base substrate 1.
  • an embodiment of the present invention further provides a method for fabricating an array substrate,
  • the method of fabricating the array substrate includes the method of fabricating any of the thin film transistors described above. It should be noted that the method for fabricating the array substrate further includes the steps of forming a structure such as a passivation layer and a pixel electrode, which will not be further described in the embodiments of the present invention.
  • an embodiment of the present invention further provides an array substrate including a thin film transistor fabricated by the fabrication method as described above.

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Abstract

一种薄膜晶体管及其制作方法、包括该薄膜晶体管的阵列基板及该阵列基板的制作方法，涉及显示技术领域，能够减少薄膜晶体管的漏电流。该薄膜晶体管包括：形成在衬底基板(1)上的有源层(2)、栅极绝缘层(3)、栅极(42)、层间绝缘层(6)、源极(8)和漏极(9)，层间绝缘层(6)和栅极绝缘层(3)上设置有对应于源极(8)和漏极(9)的过孔(7)；有源层(2)包括与源极(8)连接的源极欧姆接触区(21)、与漏极(9)连接的漏极欧姆接触区(22)、位于栅极(42)下方的用于作为沟道的沟道区(24)以及位于漏极欧姆接触区(22)与沟道区(24)之间的轻掺杂区(23)，或者，有源层(2)包括与源极(8)连接的源极欧姆接触区(21)、与漏极(9)连接的漏极欧姆接触区(22)、位于栅极(42)下方的用于作为沟道的沟道区(24)以及位于漏极欧姆接触区(22)与沟道区(24)之间和源极欧姆接触区(21)与沟道区(24)之间的两个轻掺杂区(23)。

Description

薄膜晶体管及其制作方法、阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及薄膜晶体管及其制作方法、阵列基板及其制作方法。
背景技术
液晶显示器主要包括阵列基板，阵列基板上设置有阵列排布的像素单元，每个像素单元内设置有薄膜晶体管和像素电极，其中，薄膜晶体管控制对像素电极施加电压。
具体地，薄膜晶体管包括依次设置的有源层、栅极绝缘层、栅极、层间绝缘层、源极和漏极。对于上述结构的薄膜晶体管而言，当薄膜晶体管处于关闭状态时，薄膜晶体管内部仍有电流存在，通常将此电流称为薄膜晶体管的漏电流。具体地，薄膜晶体管的漏电流包括源极和漏极之间的薄膜晶体管主体漏电流、栅极与源极之间的漏电流和栅极与漏极之间的漏电流组成的薄膜晶体管边缘漏电流，其中，薄膜晶体管的漏电流中薄膜晶体管主体漏电流所占比例较大。
薄膜晶体管的漏电流过大会造成液晶显示器的像素电极显示灰度偏差、液晶显示器能耗变大等不利现象出现。
发明内容
本发明所要解决的技术问题在于提供一种薄膜晶体管的制作方法及阵列基板的制作方法，能够减少薄膜晶体管的漏电流。
为解决上述技术问题，本发明一个方面提供了一种薄膜晶体管的制作方法，包括以下步骤：
S01，在衬底基板上形成有源层；
S02，在所述有源层上方形成栅极绝缘层；
S03，在所述栅极绝缘层上方形成栅极金属层；
S04，形成一层图案化的光刻胶，所述光刻胶完全落在所述有 源层所在区域内；
S05，对所述栅极金属层进行过刻蚀，以形成栅极，并使得所述光刻胶的两端悬空；
S06，对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和所述栅极遮挡的区域成为欧姆接触区；
S07，去除部分栅极和/或其上方的部分光刻胶，以暴露出所述有源层的与所述欧姆接触区相邻的部分；
S08，对所述有源层进行离子注入，使得暴露出的所述有源层的与欧姆接触区相邻的部分成为轻掺杂区，而所述有源层的被所述光刻胶和/或所述栅极遮挡的区域成为沟道区；
S09，剥离所述光刻胶；
S10，在所述栅极上方形成层间绝缘层，并且在所述欧姆接触区的上方，通过构图工艺，在所述层间绝缘层和所述栅极绝缘层中形成过孔；
S11，在层间绝缘层上方和所述过孔内形成源漏极金属层，通过构图工艺形成源极和漏极，所述源极和所述漏极分别通过所述过孔与所述欧姆接触区电连接。
优选地，所述步骤S04进一步包括：
将所述光刻胶形成为包括完全保留区和位于所述完全保留区两端的部分保留区，并且
步骤S05进一步包括：
对所述栅极金属层进行过刻蚀，形成栅极预结构，使得位于所述完全保留区一端的所述部分保留区悬空，位于所述完全保留区另一端的所述部分保留区部分悬空；以及
通过灰化工艺，去除所述光刻胶的所述部分保留区，使得部分悬空的所述部分保留区下方覆盖的所述栅极预结构暴露出一部分，并使所述完全保留区减薄。
优选地，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S06进一步包括：
对所述有源层进行离子注入，使得所述有源层的未被所述光 刻胶和/或所述栅极预结构遮挡的区域成为所述源极欧姆接触区和所述漏极欧姆接触区，
所述步骤S07进一步包括：
刻蚀去除所述栅极预结构的暴露部分，以形成所述栅极，所述栅极上覆盖有所述光刻胶，从而暴露出所述有源层的与所述漏极欧姆接触区相邻的部分，以及
所述步骤S08进一步包括：
对所述有源层进行离子注入，使得暴露出的所述有源层的与所述漏极欧姆接触区相邻的部分成为所述轻掺杂区，而所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为沟道区。
优选地，所述步骤S04进一步包括：
将所述光刻胶形成为包括完全保留区和位于所述完全保留区一端的部分保留区，并且
步骤S05进一步包括：
对所述栅极金属层进行过刻蚀，以形成所述栅极，使得所述部分保留区悬空，所述完全保留区未与所述部分保留区连接的一端悬空；以及
通过灰化工艺，去除所述光刻胶的所述部分保留区，并使所述完全保留区减薄。
优选地，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S06进一步包括：
对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域分别成为所述源极欧姆接触区和所述漏极欧姆接触区，
所述步骤S07进一步包括：
剥离所述光刻胶，以暴露出所述有源层的与所述漏极欧姆接触区相邻的部分，并且
所述步骤S08进一步包括：
对所述有源层进行离子注入，使得暴露出的所述有源层的与所述漏极欧姆接触区相邻的部分成为轻掺杂区，而所述有源层的 被所述光刻胶遮挡的区域成为沟道区。
优选地，所述步骤S04进一步包括：
将所述光刻胶形成为包括完全保留区和位于所述完全保留区两端的部分保留区，并且
所述步骤S05进一步包括：
对所述栅极金属层进行过刻蚀，以形成栅极预结构，使得位于所述完全保留区两端的所述部分保留区均部分悬空；
通过灰化工艺，去除所述光刻胶的所述部分保留区，使得所述部分保留区下方覆盖的所述栅极预结构从所述完全保留区的两端分别暴露出一部分，并使所述完全保留区减薄。
优选地，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S06进一步包括：
对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极预结构遮挡的区域分别成为所述源极欧姆接触区和所述漏极欧姆接触区，以及
所述步骤S07进一步包括：
刻蚀去除所述栅极预结构的暴露部分，以形成所述栅极，并且暴露出所述有源层的与所述源极欧姆接触区和所述漏极欧姆接触区相邻的两个部分，其中所述栅极上覆盖有所述光刻胶，以及
所述步骤S08进一步包括：
对所述有源层进行离子注入，使得所述有源层的在刻蚀所述栅极预结构后暴露出的两个区域成为所述轻掺杂区，以及所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为所述沟道区。
优选地，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S06进一步包括：
对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域成为所述源极欧姆接触区和所述漏极欧姆接触区，
所述步骤S07进一步包括：
剥离所述光刻胶，以暴露出所述有源层的与所述源极欧姆接触区和所述漏极欧姆接触区相邻的两个部分，以及
所述步骤S08进一步包括：
对所述有源层进行离子注入，使得所述有源层的在剥离所述光刻胶后暴露的两个区域成为所述轻掺杂区，并且所述有源层的被所述栅极遮挡的区域成为所述沟道区。
优选地，所述步骤S04进一步包括：
在所述栅极金属层上形成一层所述光刻胶，使用灰阶掩膜板遮盖所述光刻胶，经过曝光和显影使所述光刻胶图案化，所述光刻胶完全落在所述有源层所在区域内，所述灰阶掩膜板的完全透光区对应的所述光刻胶被去除，所述灰阶掩膜板的部分透光区对应的所述光刻胶部分残留，形成所述部分保留区，所述灰阶掩膜板的遮光区对应的所述光刻胶完全残留，形成所述完全保留区。
为解决上述技术问题，本发明的另一个方面提供了一种薄膜晶体管的制作方法，包括以下步骤：
S01，在衬底基板上形成有源层；
S02，在所述有源层上方形成栅极绝缘层；
S03，在所述栅极绝缘层上方形成栅极金属层；
S04，形成一层图案化的光刻胶，所述光刻胶完全落在所述有源层所在区域内；
S05，对所述栅极金属层进行过刻蚀，以形成栅极，并使得所述光刻胶的两端悬空；
S06，对所述光刻胶进行减薄，以使得离子能够从中透过；
S07，对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域成为欧姆接触区，所述有源层的仅被所述光刻胶遮挡的区域成为轻掺杂区，而所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为沟道区；
S08，剥离所述光刻胶；
S09，在所述栅极上方形成层间绝缘层，并且在所述欧姆接触区的上方，通过构图工艺，在所述层间绝缘层和所述栅极绝缘层 中形成过孔；
S10，在层间绝缘层上方和所述过孔内形成源漏极金属层，通过构图工艺形成源极和漏极，所述源极和所述漏极分别通过所述过孔与所述欧姆接触区电连接。
优选地，所述步骤S04进一步包括：
将所述光刻胶形成为包括完全保留区和位于所述完全保留区一端的部分保留区，并且
步骤S05进一步包括：
对所述栅极金属层进行过刻蚀，以形成所述栅极，使得所述部分保留区悬空，所述完全保留区未与所述部分保留区连接的一端悬空；以及
通过灰化工艺，去除所述光刻胶的所述部分保留区，使得仅所述光刻胶的完全保留区未与所述部分保留区连接的一端悬空。
优选地，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S07进一步包括：
对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域成为所述源极欧姆接触区和所述漏极欧姆接触区，所述有源层的仅被所述光刻胶遮挡的区域成为轻掺杂区，而所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为沟道区。
优选地，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S07进一步包括：
对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域成为所述源极欧姆接触区和所述漏极欧姆接触区，所述有源层的仅被所述光刻胶遮挡的两个区域成为轻掺杂区，而所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为沟道区。
优选地，其特征在于，所述步骤S04进一步包括：
在所述栅极金属层上形成一层所述光刻胶，使用灰阶掩膜板遮盖所述光刻胶，经过曝光和显影使所述光刻胶图案化，所述光 刻胶完全落在所述有源层所在区域内，所述灰阶掩膜板的完全透光区对应的所述光刻胶被去除，所述灰阶掩膜板的部分透光区对应的所述光刻胶部分残留，形成所述部分保留区，所述灰阶掩膜板的遮光区对应的所述光刻胶完全残留，形成所述完全保留区。
为解决上述技术问题，本发明的又一个方面提供了一种薄膜晶体管，包括有源层、栅极绝缘层、栅极、层间绝缘层、源极和漏极，所述层间绝缘层和所述栅极绝缘层上设置有对应于所述源极和所述漏极的过孔；
所述有源层包括与所述源极连接的源极欧姆接触区、与所述漏极连接的漏极欧姆接触区、位于所述栅极下方的用于作为沟道的沟道区以及位于所述漏极欧姆接触区与所述沟道区之间的轻掺杂区，或者，
所述有源层包括与所述源极连接的源极欧姆接触区、与所述漏极连接的漏极欧姆接触区、位于所述栅极下方的用于作为沟道的沟道区以及位于所述漏极欧姆接触区与所述沟道区之间和所述源极欧姆接触区与所述沟道区之间的两个轻掺杂区。
为解决上述技术问题，本发明的再一个方面提供了一种阵列基板的制作方法，其包括如上所述的薄膜晶体管的制作方法。
为解决上述技术问题，本发明的再又一个方面提供了一种阵列基板，其包括如上所述的薄膜晶体管。
本发明实施例提供了一种薄膜晶体管及其制作方法，该薄膜晶体管的制作方法包括在衬底基板上形成有源层、栅极绝缘层、栅极、层间绝缘层、源极和漏极，有源层包括源极欧姆接触区、漏极欧姆接触区、沟道区以及一个或者两个轻掺杂区，轻掺杂区增加了源极和漏极之间的串联电阻，降低了漏极边缘的电场或者同时降低源极和漏极的边缘电场，抑制了载流子的产生，从而可以减小薄膜晶体管的漏电流。
此外，本发明实施例还提供了一种阵列基板的制作方法，该阵列基板的制作方法包括以上所述的任一种薄膜晶体管的制作方法。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例的第一种薄膜晶体管的示意图；
图2为本发明实施例的第二种薄膜晶体管的示意图；
图3为图1所示的薄膜晶体管的第一种制作方法流程图；
图4为图3的制作方法的制作过程示意图；
图5为图1所示的薄膜晶体管的第二种制作方法的部分过程示意图；
图6为图1所示的薄膜晶体管的第三种制作方法的部分过程示意图；
图7为图2所示的薄膜晶体管的第一种制作方法流程图；
图8为图7的制作方法的制作过程示意图；
图9为图2所示的薄膜晶体管的第二种制作方法的部分过程示意图；
图10为图2所示的薄膜晶体管的第三种制作方法的部分过程示意图。
附图标记说明：
1—衬底基板；2—有源层；21—源极欧姆接触；22—漏极欧姆接触；23—轻掺杂区；24—沟道区；3—栅极绝缘层；4—栅极金属层；41—栅极预结构；42—栅极；5—光刻胶；51—完全保留区；52—部分保留区；6—层间绝缘层；7—过孔；8—源极；9—漏极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
本发明实施例提供了一种薄膜晶体管的制作方法，该薄膜晶体管的制作方法包括：
在衬底基板上形成有源层、栅极绝缘层、栅极、层间绝缘层、源极和漏极，层间绝缘层和栅极绝缘层中设置有对应于源极和漏极的过孔，以形成如图1或图2所示的薄膜晶体管。
其中，形成的薄膜晶体管的结构如图1所示时，有源层2包括与源极8连接的源极欧姆接触区21、与漏极9连接的漏极欧姆接触区22、位于栅极42下方的用于作为沟道的沟道区24以及位于漏极欧姆接触区22与沟道区24之间的轻掺杂区23，或者，
形成的薄膜晶体管的结构如图2所示时，有源层2包括与源极8连接的源极欧姆接触区21、与漏极9连接的漏极欧姆接触区22、位于栅极42下方的用于作为沟道的沟道区24以及位于漏极欧姆接触区22与沟道区24之间和源极欧姆接触区21与沟道区24之间的两个轻掺杂区23。
其中，由于形成漏电流的热载流子主要集中于漏极9附近，因此，形成的有源层2仅包括位于漏极欧姆接触区22与沟道区24之间的轻掺杂区23，即可有效降低薄膜晶体管的漏电流，与图2所示的形成的有源层2包括两个轻掺杂区23的薄膜晶体管相比，形成的有源层2仅包括位于漏极欧姆接触区22与沟道区24之间的轻掺杂区23时，薄膜晶体管的载流子的迁移率更高，薄膜晶体管的开态电流更大，进而使得薄膜晶体管的综合性能更好。
进一步地，薄膜晶体管的制作方法还可以包括其他步骤，例如，形成位于衬底基板1与有源层2之间的缓冲层的步骤，其中，缓冲层用于将衬底基板1与有源层2隔绝，避免衬底基板1中的 杂质进入有源层2，影响薄膜晶体管的性能，此外缓冲层还可减少形成有源层2的过程中温度对衬底基板1的影响。缓冲层的材质优选为氧化硅或者氮化硅。
本发明实施例提供了一种薄膜晶体管的制作方法，该薄膜晶体管的制作方法包括在衬底基板上形成有源层、栅极绝缘层、栅极、层间绝缘层、源极和漏极，有源层包括源极欧姆接触区、漏极欧姆接触区、沟道区以及一个或者两个轻掺杂区，轻掺杂区增加了源极和漏极之间的串联电阻，降低了漏极边缘的电场或者同时降低源极和漏极的边缘电场，抑制了载流子的产生，从而可以减小薄膜晶体管的漏电流。
实施例二
本发明实施例提供了三种如图1所示的薄膜晶体管的制作方法。
第一种制作方法的流程图如图3所示，制作过程的示意图如图4所示：
步骤S301、在衬底基板1上形成有源层2。
首先，在衬底基板1上形成一层非晶硅，经过晶化工艺使非晶硅转变为多晶硅。晶化工艺包括激光退火工艺、金属诱导工艺等。本发明实施例中的晶化工艺优选为激光退火工艺，具体地，激光退火工艺的基本原理为利用高能量的准分子激光照射到非晶硅表面，使非晶硅融化、冷却、再结晶，从而使非晶硅转变为多晶硅。然后，在多晶硅上涂覆一层光刻胶，经过曝光、显影、刻蚀和剥离光刻胶后，形成有源层2。
步骤S302、在有源层2的上方形成栅极绝缘层3。
通过等离子体增强化学气相沉积等方法在经过步骤S301的衬底基板1上形成栅极绝缘层3。
步骤S303、在栅极绝缘层3的上方形成栅极金属层4。
通过溅射、热蒸发等方法在经过步骤S302的衬底基板1上形成一层栅极金属层4。
步骤S304、在栅极金属层4的上方形成一层图案化的光刻胶 5，光刻胶5完全落在有源层2所在区域内，光刻胶5包括完全保留区51和位于完全保留区两端的部分保留区52。
步骤S305、对栅极金属层4进行过刻蚀，形成栅极预结构41，使得位于完全保留区51一端的部分保留区52悬空，位于完全保留区另一端的部分保留区52部分悬空。
对栅极金属层4进行一定量的过刻蚀，以使得刻蚀后形成的栅极预结构41的尺寸小于图案化的光刻胶5的尺寸，进而使得位于完全保留区51一端的部分保留区52悬空，位于完全保留区另一端的部分保留区部分52悬空。
步骤S306、通过灰化工艺，去除光刻胶5的部分保留区52，使得部分悬空的部分保留区52下方覆盖的栅极预结构41暴露，并使完全保留区51减薄。
需要说明的是，虽然此处的完全保留区减薄，但完全保留区的总体厚度仍足够厚，使得在后续的离子注入过程中使得离子无法通过。
步骤S307、对有源层2进行离子注入，使得有源层2的未被光刻胶5和栅极预结构41遮挡的区域成为源极欧姆接触区21和漏极欧姆接触区22。
示例性地，在该方法中，通过离子注入的方法向有源层2中掺入P元素，其中，有源层2的未被光刻胶5和栅极预结构41遮挡的区域中有P元素掺入，从而增加了该区域的电子浓度，以形成源极欧姆接触区21和漏极欧姆接触区22，而有源层2的被光刻胶5和/或栅极预结构41遮挡的区域没有P元素掺入。
步骤S308、刻蚀去除暴露的栅极预结构41的未被光刻胶5覆盖的部分，以形成栅极42，如图所示，栅极42上覆盖有光刻胶5。
步骤S309、对有源层2进行离子注入，使得有源层2的在刻蚀栅极预结构41后而暴露的区域成为轻掺杂区23，有源层2的被光刻胶5和栅极42同时遮挡的区域成为沟道区24。
示例性地，在该方法中，通过离子注入的方法向有源层2中 掺入与步骤S307相比较少的P元素，其中，有源层2的在刻蚀栅极预结构41后暴露的区域成为轻掺杂区23，有源层2的被光刻胶5和栅极42同时遮挡的区域仍无P元素掺入，成为沟道区24。
步骤S310、剥离光刻胶5。
步骤S311、在栅极42的上方形成层间绝缘层6，并且经过构图工艺，在层间绝缘层6和栅极绝缘层3中形成对应于源极8和漏极9的过孔7。
通过等离子体增强化学气相沉积等方法在经过步骤S310的衬底基板1上形成层间绝缘层6，经过包括涂覆光刻胶、使用掩膜板遮盖、曝光、显影、刻蚀和剥离光刻胶的构图工艺，在层间绝缘层6和栅极绝缘层3中形成对应于源极8和漏极9的过孔7，其中这些过孔7分别位于源极欧姆接触区21和漏极欧姆接触区22的上方。
步骤S312、在层间绝缘层6的上方以及过孔7中形成源漏极金属层，然后通过构图工艺形成源极8和漏极9，源极8和漏极9通过过孔7分别与源极欧姆接触区21和漏极欧姆接触区22电连接。
通过溅射、热蒸发等方法在经过步骤S311的衬底基板1上形成源漏极金属层，其中，过孔7中也形成有源漏极金属层，然后经过包括涂覆光刻胶、使用掩膜板遮盖、曝光、显影、刻蚀和剥离光刻胶的构图工艺，形成源极8和漏极9，源极8和漏极9通过过孔7分别与源极欧姆接触区21和漏极欧姆接触区22电连接。
第二种制作方法包括以下步骤，该第二种方法中的步骤S501～S503与第一种方法中的步骤S301～S303相同，步骤S510～S511与步骤S311～S312相同，图5仅示出了步骤S504～步骤S509的示意图：
步骤S501、在衬底基板1上形成有源层2。
步骤S502、在有源层2的上方形成栅极绝缘层3。
步骤S503、在栅极绝缘层3的上方形成栅极金属层4。
步骤S504、在栅极金属层4的上方形成一层图案化的光刻胶 5，光刻胶5完全落在有源层2所在区域内，光刻胶5包括完全保留区51和位于完全保留区一端的部分保留区52。
步骤S505、对栅极金属层4进行过刻蚀，形成栅极42，使得部分保留区52悬空，完全保留区51未与部分保留区连接的一端悬空。
步骤S506、通过灰化工艺，去除光刻胶5的部分保留区52，并使完全保留区51减薄。
需要说明的是，虽然此处的完全保留区的光刻胶5减薄，但完全保留区52的总体厚度仍足够厚，从而在后续的离子注入过程中使得离子无法通过。
步骤S507、对有源层2进行离子注入，使得有源层2的未被光刻胶5和栅极42遮挡的区域成为源极欧姆接触区21和漏极欧姆接触区22。
示例性地，在该方法中，通过离子注入的方法向有源层2中掺入P元素，其中，有源层2的未被光刻胶5和栅极42遮挡的区域有P元素掺入，从而形成源极欧姆接触区21和漏极欧姆接触区22，而有源层2的被光刻胶5和/或栅极42遮挡的区域没有P元素掺入。
步骤S508、剥离光刻胶5。
步骤S509、对有源层2进行离子注入，使得有源层的因剥离光刻胶5后而暴露的区域成为轻掺杂区23，而被栅极42遮挡的区域成为沟道区24。
示例性地，通过离子注入的方法向有源层2中掺入与步骤S507相比较少的P元素，其中，剥离光刻胶5后暴露的区域成为轻掺杂区23，被栅极42遮挡的区域仍无P元素掺入，而成为沟道区24。
步骤S510、在栅极42的上方形成层间绝缘层6，并且经过构图工艺，在层间绝缘层6和栅极绝缘层3中形成对应于源极8和漏极9的过孔7。
步骤S511、在层间绝缘层6的上方以及过孔7中形成源漏极 金属层，然后通过构图工艺形成源极8和漏极9，源极8和漏极9通过过孔7分别与源极欧姆接触区21和漏极欧姆接触区22电连接。
第三种制作方法具体包括以下步骤，该第三种方法中的步骤S601～S603与第一种方法中的步骤S301～S303相同，步骤S609～S610与步骤S311～S312相同，图6仅示出了步骤S604～步骤S608的示意图：
步骤S601、在衬底基板1上形成有源层2。
步骤S602、在有源层2上方形成栅极绝缘层3。
步骤S603、在栅极绝缘层3上方形成栅极金属层4。
步骤S604、在栅极金属层4上方形成一层图案化的光刻胶5，光刻胶5完全落在有源层2所在区域内，光刻胶5包括完全保留区51和位于完全保留区一端的部分保留区52。
步骤S605、对栅极金属层4进行过刻蚀，形成栅极42，使得部分保留区52悬空，完全保留区51未与部分保留区52连接的一端悬空。
步骤S606、通过灰化工艺，去除光刻胶5的部分保留区52，并使完全保留区51减薄。
需要说明的是，此处完全保留区51减薄后，完全保留区的总体厚度较小，从而在后续的离子注入过程中使得少量离子能够通过。
步骤S607、对有源层2进行离子注入，使得有源层2的未被光刻胶5和栅极42遮挡的区域成为源极欧姆接触区21和漏极欧姆接触区22，有源层2的只被光刻胶5遮挡的区域成为轻掺杂区23，有源层2的被光刻胶5和栅极42同时遮挡的区域成为沟道区24。
示例性地，在该方法中，通过离子注入的方法向有源层2中掺入P元素，其中，有源层2的未被光刻胶5和栅极42遮挡的区域掺杂量大，成为源极欧姆接触区21和漏极欧姆接触区22，有源层2的只被光刻胶5遮挡的区域，被注入少量离子，掺杂量小， 而成为轻掺杂区23，有源层2的被光刻胶5和栅极42同时遮挡的区域没有离子注入(即，零掺杂)而成为沟道区24。
步骤S608、剥离光刻胶5。
步骤S609、在栅极42的上方形成层间绝缘层6，并且经过构图工艺，在层间绝缘层6和栅极绝缘层3中形成对应于源极8和漏极9的过孔7。
步骤S610、在层间绝缘层6的上方以及过孔7中形成源漏极金属层，然后通过构图工艺形成源极8和漏极9，源极8和漏极9通过过孔7分别与源极欧姆接触区21和漏极欧姆接触区22电连接。
实施例三
本发明实施例提供了三种如图2所示的薄膜晶体管的制作方法。
第一种制作方法具体包括如图7所示的步骤，其中该第一种方法中的步骤S701～S703与实施例二的第一种方法中的步骤S301～S303相同，步骤S711～S712与步骤S311～S312相同，图8仅示出了步骤S704～步骤S710的示意图：
步骤S701、在衬底基板1上形成有源层2。
步骤S702、在有源层2的上方形成栅极绝缘层3。
步骤S703、在栅极绝缘层3的上方形成栅极金属层4。
步骤S704、在栅极金属层4的上方形成一层图案化的光刻胶5，光刻胶5完全落在有源层2所在区域内，光刻胶5包括完全保留区51和位于完全保留区两端的部分保留区52。
步骤S705、对栅极金属层4进行过刻蚀，形成栅极预结构41，使得位于完全保留区51两端的部分保留区52部分悬空。
步骤S706、通过灰化工艺，去除光刻胶5的部分保留区52，使得部分保留区下方覆盖的栅极预结构41暴露，并使完全保留区51减薄。
需要说明的是，虽然此处的完全保留区51减薄，但完全保留区的总体厚度仍足够厚，从而在后续的离子注入过程中使得离子 无法通过。
步骤S707、对有源层2进行离子注入，使得有源层2的未被光刻胶5和栅极预结构41遮挡的区域成为源极欧姆接触区21和漏极欧姆接触区22。
示例性地，在该方法中，通过离子注入的方法向有源层2中掺入P元素，其中，有源层2的未被光刻胶5和栅极42遮挡的区域有P元素掺入，从而形成源极欧姆接触区21和漏极欧姆接触区22，而有源层2的被光刻胶5和/或栅极预结构41遮挡的区域没有P元素掺入。
步骤S708、利用光刻胶5的遮挡，对刻蚀去除栅极预结构41的暴露部分，而形成栅极42，形成的栅极42上覆盖有光刻胶5。
步骤S709、对有源层2进行离子注入，使得有源层2的因刻蚀栅极预结构41后而暴露的区域成为两个轻掺杂区23，同时光刻胶5和栅极42同时遮挡的区域成为沟道区24。
示例性地，在该方法中，通过离子注入的方法向有源层2中掺入与步骤S707相比较少的P元素，其中，有源层2的因刻蚀栅极预结构41后而暴露的区域成为两个轻掺杂区23，有源层2的被光刻胶5和栅极42同时遮挡的区域仍无P元素掺入，成为沟道区24。
步骤S710、剥离光刻胶5。
步骤S711、在栅极42的上方形成层间绝缘层6，并且经过构图工艺，在层间绝缘层6和栅极绝缘层3中形成对应于源极8和漏极9的过孔7。
步骤S712、在层间绝缘层6的上方以及过孔7中形成源漏极金属层，然后通过构图工艺形成源极8和漏极9，源极8和漏极9通过过孔7分别与源极欧姆接触区21和漏极欧姆接触区22电连接。
第二种制作方法具体包括以下步骤，其中该第二种方法中的步骤S901～S903与实施例二的第一种方法中的步骤S301～S303相同，步骤S909～S910与步骤S311～S312相同，图9仅示出了步骤 S904～步骤S908的示意图：
步骤S901、在衬底基板1上形成有源层2。
步骤S902、在有源层2的上方形成栅极绝缘层3。
步骤S903、在栅极绝缘层3的上方形成栅极金属层4。
步骤S904、在栅极金属层4的上方形成一层图案化的光刻胶5，光刻胶5完全落在有源层2所在区域内。
需要说明的是，此处的光刻胶5较厚，在后续的离子注入过程中离子无法从中通过。
步骤S905、对栅极金属层4进行过刻蚀，以形成栅极42，并使得光刻胶5的两端悬空。
步骤S906、对有源层2进行离子注入，使得有源层2的未被光刻胶5和栅极42遮挡的区域成为源极欧姆接触区21和漏极欧姆接触区22。
示例性地，在该方法中，通过离子注入的方法向有源层2中掺入P元素，其中，有源层2的未被光刻胶5和栅极42遮挡的区域有P元素掺入，从而形成源极欧姆接触区21和漏极欧姆接触区22，而有源层2的被光刻胶5和/或栅极42遮挡的区域没有P元素掺入。
步骤S907、剥离光刻胶5。
步骤S908、对有源层2进行离子注入，使得有源层2的因剥离光刻胶5而暴露的区域成为两个轻掺杂区23，同时有源层2的被栅极42遮挡的区域成为沟道区24。
示例性地，在该方法中，通过离子注入的方法向有源层2中掺入与步骤S906相比较少的P元素，使得有源层2的在剥离光刻胶5后暴露的区域成为两个轻掺杂区23，有源层2的被栅极42遮挡的区域仍无P元素掺入而成为沟道区24。
步骤S909、在栅极42的上方形成层间绝缘层6，并且经过构图工艺，在层间绝缘层6和栅极绝缘层3中形成对应于源极8和漏极9的过孔7。
步骤S910、在层间绝缘层6的上方以及过孔7中形成源漏极 金属层，然后通过构图工艺形成源极8和漏极9，源极8和漏极9通过过孔7分别与源极欧姆接触区21和漏极欧姆接触区22电连接。
第三种制作方法具体包括以下步骤，其中该第三种方法中的步骤S1001～S1003与实施例二的第一种方法中的步骤S301～S303相同，步骤S1008～S1009与步骤S311～S312相同，图10仅示出了步骤S1004～步骤S1007的示意图：
步骤S1001、在衬底基板1上形成有源层2。
步骤S1002、在有源层2的上方形成栅极绝缘层3。
步骤S1003、在栅极绝缘层3的上方形成栅极金属层4。
步骤S1004、在栅极金属层4的上方形成一层图案化的光刻胶5，光刻胶5完全落在有源层2所在区域内。
需要说明的是，此处的光刻胶5较薄，在后续的离子注入过程中可以使得部分离子通过。
步骤S1005、对栅极金属层4进行过刻蚀，以形成栅极42，并使得光刻胶5的两端悬空。
步骤S1006、对有源层2进行离子注入，使得有源层2的未被光刻胶5和栅极42遮挡的区域成为21和漏极欧姆接触区22，有源层2的只被光刻胶5遮挡的区域成为两个轻掺杂区23，有源层2的被光刻胶5和栅极42同时遮挡的区域成为沟道区24。
示例性地，在该方法中，通过离子注入的方法向有源层2中掺入P元素，其中，有源层2的未被光刻胶5和栅极42遮挡的区域成为源极欧姆接触区21和漏极欧姆接触区22，有源层2的只被光刻胶5遮挡的区域成为两个轻掺杂区23，有源层2的被光刻胶5和栅极42同时遮挡的区域成为沟道区24。
步骤S1007、剥离光刻胶5。
步骤S1008、在栅极42的上方形成层间绝缘层6，并且经过构图工艺，在层间绝缘层6和栅极绝缘层3中形成对应于源极8和漏极9的过孔7。
步骤S1009、在层间绝缘层6的上方以及过孔7中形成源漏 极金属层，然后通过构图工艺形成源极8和漏极9，源极8和漏极9通过过孔7分别与源极欧姆接触区21和漏极欧姆接触区22电连接。
实施例四
实施例二中所述的步骤S304、步骤S504和步骤S604，以及实施例三中所述的步骤S704具体包括：
在栅极金属层4上形成一层光刻胶5，使用灰阶掩膜板遮盖光刻胶5，经过曝光和显影使光刻胶5图案化，光刻胶5完全落在有源层2所在区域内，灰阶掩膜板的完全透光区对应的光刻胶5被去除，灰阶掩膜板的部分透光区对应的光刻胶5部分残留，形成部分保留区52，灰阶掩膜板的遮光区对应的光刻胶5完全残留，形成完全保留区51。
此时，本发明实施例提供的各种薄膜晶体管的制作方法中只需要使用4张掩膜板，而现有技术中的有源层不包括轻掺杂区的薄膜晶体管的制作过程中也需要使用4张掩膜板，因此，本发明实施例提供的薄膜晶体管的制作方法在不增加掩膜板的数量的基础上即可使形成的薄膜晶体管的有源层2包括源极欧姆接触区21、漏极欧姆接触区22、轻掺杂区23和沟道区24，制作方法简单，成本低。
进一步需要说明的是，使用上述各种方法形成的轻掺杂区23的长度由形成栅极预结构41或者栅极42时过刻蚀的量决定，由于在刻蚀过程中过刻蚀的量精确可控，因此，形成的轻掺杂区23的长度精确，进而避免出现轻掺杂区23的长度过大导致薄膜晶体管的载流子的迁移率低或者轻掺杂区23的长度过小导致无法减小薄膜晶体管的漏电流等问题。
此外，实施例二中的各个制作方法在步骤S301、步骤S501和步骤S601，以及实施例三中的各个制作方法在步骤S701、步骤S901和步骤S1001之前还可以包括：
在衬底基板1上形成缓冲层。
此外，本发明实施例还提供了一种阵列基板的制作方法，该 阵列基板的制作方法包括以上所述的任一种薄膜晶体管的制作方法。需要说明的是，阵列基板的制作方法还包括形成钝化层、像素电极等结构的步骤，本发明实施例不再一一赘述。
此外，本发明实施例还提供了一种阵列基板，其包括利用如上所述制作方法制作的薄膜晶体管。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种薄膜晶体管的制作方法，其特征在于，包括以下步骤：
    S01，在衬底基板上形成有源层；
    S02，在所述有源层上方形成栅极绝缘层；
    S03，在所述栅极绝缘层上方形成栅极金属层；
    S04，形成一层图案化的光刻胶，所述光刻胶完全落在所述有源层所在区域内；
    S05，对所述栅极金属层进行过刻蚀，以形成栅极，并使得所述光刻胶的两端悬空；
    S06，对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和所述栅极遮挡的区域成为欧姆接触区；
    S07，去除部分栅极和/或其上方的部分光刻胶，以暴露出所述有源层的与所述欧姆接触区相邻的部分；
    S08，对所述有源层进行离子注入，使得暴露出的所述有源层的与欧姆接触区相邻的部分成为轻掺杂区，而所述有源层的被所述光刻胶和/或所述栅极遮挡的区域成为沟道区；
    S09，剥离所述光刻胶；
    S10，在所述栅极上方形成层间绝缘层，并且在所述欧姆接触区的上方，通过构图工艺，在所述层间绝缘层和所述栅极绝缘层中形成过孔；
    S11，在层间绝缘层上方和所述过孔内形成源漏极金属层，通过构图工艺形成源极和漏极，所述源极和所述漏极分别通过所述过孔与所述欧姆接触区电连接。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述步骤S04进一步包括：
    将所述光刻胶形成为包括完全保留区和位于所述完全保留区两端的部分保留区，并且
    步骤S05进一步包括：
    对所述栅极金属层进行过刻蚀，形成栅极预结构，使得位于所述完全保留区一端的所述部分保留区悬空，位于所述完全保留区另一端的所述部分保留区部分悬空；以及
    通过灰化工艺，去除所述光刻胶的所述部分保留区，使得部分悬空的所述部分保留区下方覆盖的所述栅极预结构暴露出一部分，并使所述完全保留区减薄。
  3. 根据权利要求2所述的薄膜晶体管的制作方法，其特征在于，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S06进一步包括：
    对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极预结构遮挡的区域成为所述源极欧姆接触区和所述漏极欧姆接触区，
    所述步骤S07进一步包括：
    刻蚀去除所述栅极预结构的暴露部分，以形成所述栅极，所述栅极上覆盖有所述光刻胶，从而暴露出所述有源层的与所述漏极欧姆接触区相邻的部分，以及
    所述步骤S08进一步包括：
    对所述有源层进行离子注入，使得暴露出的所述有源层的与所述漏极欧姆接触区相邻的部分成为所述轻掺杂区，而所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为沟道区。
  4. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述步骤S04进一步包括：
    将所述光刻胶形成为包括完全保留区和位于所述完全保留区一端的部分保留区，并且
    步骤S05进一步包括：
    对所述栅极金属层进行过刻蚀，以形成所述栅极，使得所述部分保留区悬空，所述完全保留区未与所述部分保留区连接的一端悬空；以及
    通过灰化工艺，去除所述光刻胶的所述部分保留区，并使所述完全保留区减薄。
  5. 根据权利要求4所述的薄膜晶体管的制作方法，其特征在于，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S06进一步包括：
    对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域分别成为所述源极欧姆接触区和所述漏极欧姆接触区，
    所述步骤S07进一步包括：
    剥离所述光刻胶，以暴露出所述有源层的与所述漏极欧姆接触区相邻的部分，并且
    所述步骤S08进一步包括：
    对所述有源层进行离子注入，使得暴露出的所述有源层的与所述漏极欧姆接触区相邻的部分成为轻掺杂区，而所述有源层的被所述光刻胶遮挡的区域成为沟道区。
  6. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述步骤S04进一步包括：
    将所述光刻胶形成为包括完全保留区和位于所述完全保留区两端的部分保留区，并且
    所述步骤S05进一步包括：
    对所述栅极金属层进行过刻蚀，以形成栅极预结构，使得位于所述完全保留区两端的所述部分保留区均部分悬空；
    通过灰化工艺，去除所述光刻胶的所述部分保留区，使得所述部分保留区下方覆盖的所述栅极预结构从所述完全保留区的两端分别暴露出一部分，并使所述完全保留区减薄。
  7. 根据权利要求6所述的薄膜晶体管的制作方法，其特征在于，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且 所述步骤S06进一步包括：
    对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极预结构遮挡的区域分别成为所述源极欧姆接触区和所述漏极欧姆接触区，以及
    所述步骤S07进一步包括：
    刻蚀去除所述栅极预结构的暴露部分，以形成所述栅极，并且暴露出所述有源层的与所述源极欧姆接触区和所述漏极欧姆接触区相邻的两个部分，其中所述栅极上覆盖有所述光刻胶，以及
    所述步骤S08进一步包括：
    对所述有源层进行离子注入，使得所述有源层的在刻蚀所述栅极预结构后暴露出的两个区域成为所述轻掺杂区，以及所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为所述沟道区。
  8. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S06进一步包括：
    对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域成为所述源极欧姆接触区和所述漏极欧姆接触区，
    所述步骤S07进一步包括：
    剥离所述光刻胶，以暴露出所述有源层的与所述源极欧姆接触区和所述漏极欧姆接触区相邻的两个部分，以及
    所述步骤S08进一步包括：
    对所述有源层进行离子注入，使得所述有源层的在剥离所述光刻胶后暴露的两个区域成为所述轻掺杂区，并且所述有源层的被所述栅极遮挡的区域成为所述沟道区。
  9. 根据权利要求2至7中任一项所述的薄膜晶体管的制作方法，其特征在于，所述步骤S04进一步包括：
    在所述栅极金属层上形成一层所述光刻胶，使用灰阶掩膜板遮盖所述光刻胶，经过曝光和显影使所述光刻胶图案化，所述光刻胶完全落在所述有源层所在区域内，所述灰阶掩膜板的完全透光区对应的所述光刻胶被去除，所述灰阶掩膜板的部分透光区对应的所述光刻胶部分残留，形成所述部分保留区，所述灰阶掩膜板的遮光区对应的所述光刻胶完全残留，形成所述完全保留区。
  10. 一种薄膜晶体管的制作方法，其特征在于，包括以下步骤：
    S01，在衬底基板上形成有源层；
    S02，在所述有源层上方形成栅极绝缘层；
    S03，在所述栅极绝缘层上方形成栅极金属层；
    S04，形成一层图案化的光刻胶，所述光刻胶完全落在所述有源层所在区域内；
    S05，对所述栅极金属层进行过刻蚀，以形成栅极，并使得所述光刻胶的两端悬空；
    S06，对所述光刻胶进行减薄，以使得离子能够从中透过；
    S07，对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域成为欧姆接触区，所述有源层的仅被所述光刻胶遮挡的区域成为轻掺杂区，而所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为沟道区；
    S08，剥离所述光刻胶；
    S09，在所述栅极上方形成层间绝缘层，并且在所述欧姆接触区的上方，通过构图工艺，在所述层间绝缘层和所述栅极绝缘层中形成过孔；
    S10，在层间绝缘层上方和所述过孔内形成源漏极金属层，通过构图工艺形成源极和漏极，所述源极和所述漏极分别通过所述过孔与所述欧姆接触区电连接。
  11. 根据权利要求10所述的薄膜晶体管的制作方法，其特征 在于，所述步骤S04进一步包括：
    将所述光刻胶形成为包括完全保留区和位于所述完全保留区一端的部分保留区，并且
    步骤S05进一步包括：
    对所述栅极金属层进行过刻蚀，以形成所述栅极，使得所述部分保留区悬空，所述完全保留区未与所述部分保留区连接的一端悬空；以及
    通过灰化工艺，去除所述光刻胶的所述部分保留区，使得仅所述光刻胶的完全保留区未与所述部分保留区连接的一端悬空。
  12. 根据权利要求11所述的薄膜晶体管的制作方法，其特征在于，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S07进一步包括：
    对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域成为所述源极欧姆接触区和所述漏极欧姆接触区，所述有源层的仅被所述光刻胶遮挡的区域成为轻掺杂区，而所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为沟道区。
  13. 根据权利要求10所述的薄膜晶体管的制作方法，其特征在于，所述欧姆接触区包括源极欧姆接触区和漏极欧姆接触区，且所述步骤S07进一步包括：
    对所述有源层进行离子注入，使得所述有源层的未被所述光刻胶和/或所述栅极遮挡的区域成为所述源极欧姆接触区和所述漏极欧姆接触区，所述有源层的仅被所述光刻胶遮挡的两个区域成为轻掺杂区，而所述有源层的被所述光刻胶和所述栅极同时遮挡的区域成为沟道区。
  14. 根据权利要求11或12所述的薄膜晶体管的制作方法，其特征在于，所述步骤S04进一步包括：
    在所述栅极金属层上形成一层所述光刻胶，使用灰阶掩膜板遮盖所述光刻胶，经过曝光和显影使所述光刻胶图案化，所述光刻胶完全落在所述有源层所在区域内，所述灰阶掩膜板的完全透光区对应的所述光刻胶被去除，所述灰阶掩膜板的部分透光区对应的所述光刻胶部分残留，形成所述部分保留区，所述灰阶掩膜板的遮光区对应的所述光刻胶完全残留，形成所述完全保留区。
  15. 一种薄膜晶体管，包括有源层、栅极绝缘层、栅极、层间绝缘层、源极和漏极，所述层间绝缘层和所述栅极绝缘层上设置有对应于所述源极和所述漏极的过孔；
    所述有源层包括与所述源极连接的源极欧姆接触区、与所述漏极连接的漏极欧姆接触区、位于所述栅极下方的用于作为沟道的沟道区以及位于所述漏极欧姆接触区与所述沟道区之间的轻掺杂区，或者，
    所述有源层包括与所述源极连接的源极欧姆接触区、与所述漏极连接的漏极欧姆接触区、位于所述栅极下方的用于作为沟道的沟道区以及位于所述漏极欧姆接触区与所述沟道区之间和所述源极欧姆接触区与所述沟道区之间的两个轻掺杂区。
  16. 一种阵列基板的制作方法，其特征在于，包括如权利要求1-9任一项所述的薄膜晶体管的制作方法。
  17. 一种阵列基板，其特征在于，包括如权利要求15所述的薄膜晶体管。
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