WO2016119120A1 - 一种fec译码的装置及方法 - Google Patents

一种fec译码的装置及方法 Download PDF

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Publication number
WO2016119120A1
WO2016119120A1 PCT/CN2015/071624 CN2015071624W WO2016119120A1 WO 2016119120 A1 WO2016119120 A1 WO 2016119120A1 CN 2015071624 W CN2015071624 W CN 2015071624W WO 2016119120 A1 WO2016119120 A1 WO 2016119120A1
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decoded
group
codeword
decoding
checksum
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English (en)
French (fr)
Inventor
肖治宇
李沫
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2015/071624 priority Critical patent/WO2016119120A1/zh
Priority to CN201580073971.1A priority patent/CN107210755B/zh
Priority to EP15879331.5A priority patent/EP3242406B1/en
Publication of WO2016119120A1 publication Critical patent/WO2016119120A1/zh
Priority to US15/661,818 priority patent/US10505672B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H04L1/0053—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables specially adapted for power saving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/095—Error detection codes other than CRC and single parity bit codes
    • H03M13/096—Checksums
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H04L1/0058—Block-coded modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to an apparatus and method for FEC decoding.
  • optical fiber transmission has become the dominant data transmission mode in current communication systems due to its advantages of large information capacity, strong anti-interference ability and fast transmission speed.
  • the transmitting end performs forward error correction (FEC) encoding on the data to be transmitted, phase-modulates the FEC-encoded baseband signal, and transmits the phase-modulated data to the data.
  • FEC forward error correction
  • the transmission fiber is transmitted to the receiving end.
  • the receiving end recovers the baseband signal through coherent mediation, obtains the digital signal by analog-to-digital conversion of the baseband signal, and uses digital processing algorithm to perform dispersion compensation, clock recovery, depolarization multiplexing and carrier phase estimation on the digital signal.
  • the multi-level digital signal is output, and a log-likelihood ratio (LLR) of the data is obtained according to the multi-level digital signal, and FLC decoding is performed on the LLR of the transmitted data to obtain data to be transmitted by the transmitting end.
  • LLR log-likelihood ratio
  • the rate of fiber transmission is increasing, from 40Gb/s to 100Gb/s, and even up to 400Gb/s.
  • the amount of data required for FEC decoding is also increasing, and the power consumption required for FEC decoding is also increasing.
  • the conventional FEC decoding adopts an iterative decoding method, and presets the number of iterations N of each codeword, performs N iteration decoding for each codeword, and outputs the decoding result of the codeword.
  • M-N times of redundant iterative decoding causes waste of power consumption. Where M is a natural number less than N.
  • Embodiments of the present invention provide an apparatus and method for FEC decoding. When all codewords of the group to be decoded are decoded, no FEC decoding is performed, only sign bit decision is performed, and FEC decoding is reduced. Power consumption.
  • a first aspect of the embodiments of the present invention provides an FEC decoding apparatus, where the apparatus includes:
  • An acquiring unit configured to acquire a group to be decoded, where the group to be decoded includes a preset number of codewords
  • a first detecting unit configured to detect whether all codewords in the group to be decoded satisfy a checksum of 0
  • a determining unit configured to perform a sign bit decision on the group to be decoded when all code words in the group to be decoded satisfy a checksum of 0, and the sign bit is determined to be a non-negative number of 1, Negating a negative number to 0;
  • a second detecting unit configured to detect whether at least one codeword exists in the group to be decoded, and perform a sign bit decision when not all codewords in the group to be decoded satisfy a checksum of 0;
  • a recovery unit configured to perform data recovery on each codeword that has performed the symbol bit decision when there is at least one codeword that has performed the sign bit decision in the group to be decoded, and the data is restored to restore 0 to The negative of the maximum value of the analog-to-digital conversion, which restores 1 to a positive number of the maximum value of the analog-to-digital conversion;
  • the first decoding unit is configured to perform FEC decoding on each data-recovered codeword and each codeword that has not been subjected to the symbol bit decision to form a new group to be decoded.
  • the first detecting unit is specifically configured to detect whether all code words in the group to be decoded carry a decoding success identifier; when all code words in the group to be decoded carry a decoding success identifier, All codewords in the decoded group satisfy the checksum of 0; when at least one codeword in the group to be decoded does not carry the decoding success identifier, not all codewords in the group to be decoded Both satisfy the checksum of 0;
  • the device also includes:
  • a first check unit configured to calculate a checksum of each codeword after the FEC decoding in the new group to be decoded
  • a first adding unit configured to add a decoding success identifier to the codeword with the checksum of 0 after the FEC decoding in the new group to be decoded.
  • the device further includes:
  • a second decoding unit configured to perform FEC decoding on the group to be decoded when all codewords in the group to be decoded have not performed a sign bit decision
  • a second check unit configured to calculate a checksum of each codeword after the FEC decoding in the group to be decoded
  • a second adding unit configured to add a decoding success identifier to the codeword in which the checksum of the FEC decoding is 0 in the to-be-decoded group.
  • the apparatus further includes:
  • a third adding unit configured to add a determined identifier to each codeword in the group to be decoded
  • the second detecting unit is specifically configured to detect whether at least one codeword exists in the group to be decoded and carries the determined identifier
  • the device also includes:
  • a modifying unit is configured to change the determined identifier of each codeword that has undergone the sign bit decision to an undecided identifier.
  • the apparatus further includes:
  • An output unit configured to determine whether the number of decoding times of the first received codeword in the group to be decoded is up to a preset decoding iteration number, and if so, outputting the first received codeword according to the time series The decoding result.
  • a second aspect of the embodiments of the present invention provides a FEC decoding method, where the method includes:
  • the sign bit decision is to judge the non-negative number to be 1, and the negative number to be 0. ;
  • the codeword after each data recovery is combined with each codeword that has not been subjected to the sign bit decision.
  • the decoding group performs FEC decoding.
  • the detecting whether all codewords in the group to be decoded meet the checksum of 0 includes:
  • the FCC decoding is performed after the codeword after each data is restored and each codeword that has not been subjected to the sign bit decision is formed into a new group to be decoded.
  • the method further includes:
  • the method further includes:
  • the detecting whether the at least one codeword exists in the group to be decoded performs a sign bit decision includes:
  • the performing data recovery for each codeword that has performed the sign bit decision further includes:
  • the judged flag of each codeword that has undergone a sign bit decision is changed to an undecided flag.
  • the method further includes:
  • An embodiment of the present invention provides a decoding apparatus and method, which acquires a group to be decoded, and detects whether all codewords in the group to be decoded satisfy a checksum of 0; when all codewords in the group to be decoded are When both of the checksums are 0, the sign bit decision is performed on the group to be decoded.
  • each codeword in the group to be decoded Detecting whether each codeword in the group to be decoded has performed a sign bit decision when not all codewords in the group to be decoded satisfy a checksum of 0, when at least the group to be decoded exists in the group to be decoded
  • a codeword that has undergone a sign bit decision is performed, data recovery is performed on each codeword that has undergone the sign bit decision, and each code recovered message word and each codeword that has not been subjected to the sign bit decision are newly formed.
  • the group to be decoded performs FEC decoding.
  • the FEC decoding is not performed, and only the sign bit decision is performed, that is, in the process of performing multiple decodings for each codeword, not every time Both perform FEC decoding, reducing the power consumption required for FEC decoding.
  • FIG. 1 is a schematic structural diagram of an FEC decoding apparatus according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an FEC decoding apparatus according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of hardware of an FEC decoding apparatus according to an embodiment of the present disclosure
  • FIG. 4 is a flowchart of an FEC decoding method according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a FEC decoding method according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of an FEC decoding apparatus according to an embodiment of the present invention, where the apparatus includes:
  • the obtaining unit 101 is configured to acquire a group to be decoded, where the group to be decoded includes a preset number of code words.
  • the transmitting end divides the data to be sent into K code words, each code word contains transmission data of a preset length, and encodes K code words and sends them to the receiving end.
  • the receiving end decodes the received transmission data
  • the received transmission data is also divided into K codewords to be decoded, and each codeword to be decoded also includes transmission data of a preset length.
  • K is an integer greater than zero.
  • each time decoding a predetermined number of code words to be decoded are grouped into a group to be decoded, and each code word in the group to be decoded is arranged in the order of receiving the code words, and the code word received first
  • the codewords received in the front are arranged in the back.
  • the preset number of codewords to be decoded included in each group to be decoded may be set according to actual needs, and the preset length of the transmission data included in each codeword may also be It is set according to actual needs, and is not specifically limited here.
  • the 10000-bit transmission data is divided into 500 code words, and each code word contains 20-bit transmission data, wherein 19 bits are known data information bits, and 1 bit is a data encoding check bit.
  • the receiving end also divides the received transmission data into 500 code words, and each code word contains 20 bits of transmission data.
  • the codeword to be decoded is the decoded result of decoding the codeword FEC to be decoded last time. For example, the FEC decoding of the decoding group abcd is performed first, and then the FEC decoding of the decoding group efgh is performed. When decoding the decoding group cdef, the obtained codeword cd is performing FEC translation on abcd. The def obtained after the code is the ef obtained by performing FEC decoding on the defg, wherein a, b, c, d, e, f, g, h are all codewords to be decoded.
  • the first detecting unit 102 is configured to detect whether all codewords in the group to be decoded satisfy the checksum of 0, and if yes, enter the decision unit 103; if not, enter the second detecting unit 104.
  • the verification relationship of the codeword is set.
  • the verification relationship of the set codeword is that the checksum of all the data information in the codeword is 0.
  • the group to be decoded is detected when all the code words in the group to be decoded satisfy the checksum being 0. Include a preset number of codewords to be decoded, and calculate whether each codeword to be decoded satisfies a checksum of 0, and when each codeword to be decoded satisfies a checksum of 0, All code words in the group to be decoded are successfully decoded; when there is at least one codeword checksum to be decoded is not 0, not all code words in the group to be decoded are successfully decoded.
  • the determining unit 103 is configured to perform a sign bit decision on the group to be decoded, where the sign bit is determined to be a non-negative number decision of 1, and a negative number decision of 0.
  • FEC decoding is performed on the group to be decoded, and the decoding result does not change, and the group to be decoded is not needed.
  • FEC decoding repeatedly, performing a sign bit decision on the group to be decoded, and determining, by the group to be decoded, that the data greater than or equal to 0 is 1, that is, replacing the group to be decoded with 1 Data greater than or equal to 0; data of less than 0 in the group to be decoded is determined to be 0, that is, data replaced by 0 is replaced by 0, and the result of performing sign bit decision on the group to be decoded is used as a team The result of the iterative decoding of the decoding group is described.
  • FEC decoding is performed every decoding.
  • the FEC decoding is not performed, and only the sign bit decision is performed, and the sign bit decision is only for the group to be decoded.
  • the data in the data takes the sign bit and does not need to repeatedly perform complex FEC decoding, thereby reducing the power consumption required for FEC decoding.
  • the second detecting unit 104 is configured to detect whether there is at least one codeword in the group to be decoded, and perform a sign bit decision.
  • the recovery unit 105 is configured to perform data recovery on each codeword that has performed the symbol bit decision when there is at least one codeword that has performed the sign bit decision in the group to be decoded, and the data is restored to recover 0. Converts 1 to a positive number of the maximum value of the analog-to-digital conversion for the negative of the maximum value of the analog-to-digital conversion.
  • the first decoding unit 106 is configured to perform FEC decoding on each data-recovered codeword and each codeword that has not performed a symbol bit decision to form a new group to be decoded.
  • first detecting whether there is at least one codeword in the group to be decoded performs a sign bit decision.
  • the criterion for the decision is that when a codeword has undergone a sign bit decision, the data in the codeword is either 0 or 1. Then detecting whether all data in each codeword in the group to be decoded is 0 or 1, when all data in one codeword is 0 or 1, The codeword performs a sign bit decision; when there is data other than 0 and 1 in a codeword, the codeword has not been subjected to a sign bit decision.
  • a symbol bit decision is performed, and data recovery is performed on each codeword that has performed the sign bit decision.
  • the data recovery refers to restoring 0 in the codeword to a negative number of the maximum value of the analog to digital conversion, and restoring 1 to a positive number of the maximum value of the analog to digital conversion.
  • the maximum value of the analog to digital conversion is determined by the parameters of the analog to digital converter at the receiving end. For example, when the maximum value of the analog-to-digital conversion of the analog-to-digital converter at the receiving end is 31, data recovery is performed on the codeword that has performed the sign bit determination, and the 0 in the codeword is restored to -31, and 1 is restored to 31.
  • each codeword that has undergone the sign bit decision in the group to be decoded, and each codeword that has undergone the sign bit decision after data recovery and each of the original ones in the group to be decoded are not
  • the codewords that have undergone the sign bit decision form a new group to be decoded, perform FEC decoding on the new group to be decoded, and obtain the decoding result of the iterative decoding.
  • FEC decoding may be directly performed on the group to be decoded.
  • the FEC decoding is not performed, and only the sign bit decision is performed, that is, in the process of performing multiple decodings for each codeword, not every time Both perform FEC decoding, reducing the power consumption required for FEC decoding.
  • FIG. 2 is a schematic structural diagram of an FEC decoding apparatus according to an embodiment of the present invention, where the apparatus includes:
  • the obtaining unit 201 is configured to acquire a group to be decoded, where the group to be decoded includes a preset number of code words.
  • the acquisition unit 201 shown in FIG. 2 is similar to the acquisition unit 101 in the FEC decoding apparatus shown in FIG. 1. Referring to the description of the acquisition unit 101 in the FEC decoding apparatus shown in FIG. 1, details are not described herein again.
  • the first detecting unit 202 is configured to detect whether all code words in the group to be decoded carry a decoding success identifier, and if yes, enter the determining unit 203; if not, enter the second detecting unit 205.
  • Each codeword to be decoded in the group to be decoded calculates the codeword checksum after an iterative decoding on the codeword, and when the checksum of the codeword is 0, The codeword adds a decoding success indicator. And detecting whether all code words in the group to be decoded carry a decoding success identifier, that is, detecting the Whether all code words in the group to be decoded have a checksum of 0. When the codeword is used again as a codeword in the group to be decoded, it is not necessary to repeatedly calculate the checksum of the codeword, and it is only necessary to detect whether the codeword carries the decoding success identifier.
  • a checksum of all codewords in the group to be decoded is 0; when at least one code exists in the group to be decoded When the word does not carry the decoding success identifier, it indicates that at least one codeword checksum in the group to be decoded is not 0, that is, not all the codewords in the group to be decoded have a checksum of 0. .
  • the determining unit 203 is configured to perform a sign bit decision on the group to be decoded, where the sign bit is determined to be a non-negative number decision of 1, and a negative number decision of 0.
  • the third adding unit 204 is configured to add a determined identifier to each codeword in the group to be decoded.
  • the second detecting unit 205 is configured to detect whether at least one codeword exists in the group to be decoded, and if yes, enter the recovery unit 206; if not, enter the second decoding unit 211.
  • the recovery unit 206 is configured to perform data recovery for each codeword carrying the determined identifier, where the data is restored to return 0 to a negative value of the maximum value of the analog-to-digital conversion, and 1 is restored to the maximum value of the analog-to-digital conversion. A positive number.
  • detecting whether at least one codeword exists in the group to be decoded carries the determined identifier.
  • a codeword carries a judgement flag, it indicates that the codeword has performed a sign bit decision, that is, all data in the codeword is 0 and 1. Since the FEC decoding is to perform decoding on positive and negative numbers, it is necessary to perform data recovery on the codeword carrying the determined identifier.
  • the data recovery refers to restoring 0 in the codeword to a negative number of the maximum value of the analog to digital conversion, and restoring 1 to a positive number of the maximum value of the analog to digital conversion.
  • the maximum value of the analog to digital conversion is determined by the parameters of the analog to digital converter at the receiving end.
  • the first decoding unit 207 is configured to perform FEC decoding on each data-recovered codeword and each codeword that has not performed a symbol bit decision to form a new group to be decoded.
  • the modifying unit 208 is configured to change the determined identifier of each codeword that has performed the symbol bit decision to an undecided identifier.
  • the first check unit 209 is configured to calculate a checksum of each codeword after the FEC decoding in the new group to be decoded.
  • the first adding unit 210 is configured to add a decoding success identifier to the codeword with the checksum of 0 after the FEC decoding in the new group to be decoded.
  • the second decoding unit 211 is configured to perform FEC decoding on the group to be decoded.
  • the second check unit 212 is configured to calculate a checksum of each codeword after performing FEC decoding in the group to be decoded.
  • the second adding unit 213 is configured to add a decoding success identifier to the codeword with the checksum of 0 after FEC decoding in the group to be decoded.
  • FEC decoding may be directly performed on the group to be decoded.
  • Calculating a checksum of each codeword after performing FEC decoding in the group to be decoded, and adding a decoding success identifier to a codeword in which the checksum is 0 after FEC decoding in the group to be decoded Indicates that the codeword is successfully decoded.
  • the codeword is used as a codeword to be decoded in another group to be decoded, it is determined whether the codeword carries a decoding success identifier, and it can be determined whether the codeword has a checksum of 0, and no need to repeatedly calculate the codeword. The checksum of the codeword.
  • the output unit 214 is configured to determine whether the number of decoding times of the first received codeword in the group to be decoded is up to a preset decoding iteration number, and if yes, output the first received code according to the time series The result of the word decoding.
  • the codewords that are received first in the group to be decoded are arranged in time series, that is, the codewords in the first group to be decoded are determined, and the decoding of the codewords is determined. Whether the number of times reaches the preset decoding iteration number, and if so, the decoding result of the code word is output.
  • the preset number of decoding iterations can be set according to actual needs, and is not specifically limited herein.
  • Each iterative decoding actually decodes only the first received codewords in the group to be decoded according to the time series arrangement, and the number of decoding times of the first received codewords in the group to be decoded is arranged in time series.
  • the preset decoding iteration number is reached, the codeword that is received first in the time series arrangement must have completed decoding, and the decoding result of the codeword received first in the time series may be output.
  • the codeword f received first in time series is obtained, and it is determined whether the decoding number of the codeword f reaches the preset. The number of decoding iterations, if yes, the decoding result of the codeword f.
  • Each iteration decodes a decoding result of at most one codeword. If the first received codeword in the group to be decoded is not up to the preset decoding iteration number, no decoding result is output. It should be noted that the decoding result of the output referred to in the embodiment of the present invention refers to receiving.
  • the decoding result output by the FEC decoder in the end instead of the decoding result of the group to be decoded obtained after each iteration, the result of one iteration decoding of the group to be decoded is in the FEC decoder Recycled, not output.
  • FIG. 3 is a schematic structural diagram of a hardware of an FEC decoding apparatus according to an embodiment of the present disclosure, where the apparatus includes:
  • the memory 301 is configured to store and store a set of program instructions
  • the processor 302 is configured to invoke the program instructions stored in the memory 301 to perform the following operations:
  • the sign bit decision is to judge the non-negative number to be 1, and the negative number to be 0. ;
  • the codeword after each data recovery is combined with each codeword that has not been subjected to the sign bit decision to form a new group to be decoded for FEC decoding.
  • the detecting, in the group to be decoded, whether all codewords satisfy the checksum of 0 instruction includes:
  • the method further comprises: after the codeword after each data is restored and each codeword that has not been subjected to the sign bit decision is formed into a new group to be decoded, and the FEC decoding instruction is further included:
  • the instructions further include:
  • the method further includes:
  • the detecting whether the at least one codeword exists in the group to be decoded has performed a sign bit decision instruction includes:
  • the method further includes:
  • the judged flag of each codeword that has undergone a sign bit decision is changed to an undecided flag.
  • the instructions further include:
  • the processor 302 may be a central processing unit (CPU), and the memory 301 may be an internal memory of a random access memory (RAM) type.
  • the memory 301 and the processor 1302 may be integrated into one or more independent circuits or hardware, such as an Application Specific Integrated Circuit (ASIC).
  • ASIC Application Specific Integrated Circuit
  • FIG. 4 is a flowchart of a method for decoding an FEC according to an embodiment of the present invention, where the method includes:
  • FEC decoding is performed on the group to be decoded, and the decoding result does not change, and the group to be decoded is not needed.
  • FEC decoding repeatedly, performing a sign bit decision on the group to be decoded, and determining, by the group to be decoded, that the data greater than or equal to 0 is 1, that is, replacing the group to be decoded with 1 Data greater than or equal to 0; data of less than 0 in the group to be decoded is determined to be 0, that is, data replaced by 0 is replaced by 0, and the result of performing sign bit decision on the group to be decoded is used as a team The result of the iterative decoding of the decoding group is described.
  • FEC decoding is performed every decoding.
  • the FEC decoding is not performed, and only the sign bit decision is performed, and the sign bit decision is only for the group to be decoded.
  • the data in the data takes the sign bit and does not need to repeatedly perform complex FEC decoding, thereby reducing the power consumption required for FEC decoding.
  • the method of FEC decoding described in FIG. 4 is a method corresponding to the FEC decoding apparatus shown in FIG. 1.
  • the technical implementation process is similar to that described in FIG. 1, referring to the technology in the FEC apparatus shown in FIG. The description of the implementation process is not repeated here.
  • FIG. 5 is a flowchart of a method for decoding an FEC according to an embodiment of the present invention, where the method includes:
  • 502 Detect whether all codewords in the group to be decoded carry a decoding success identifier, and if yes, perform 503; if not, 505.
  • 503 Perform a sign bit decision on the group to be decoded, where the sign bit is determined to be a non-negative number decision of 1, and a negative number decision of 0.
  • 505 Detect whether at least one codeword exists in the to-be-decoded group, and if yes, perform 506; if not, perform 511.
  • 511 Perform FEC decoding on the to-be-decoded group.
  • the FEC decoding method described in FIG. 5 corresponds to the FEC decoding apparatus shown in FIG. 2.
  • the method and the technical implementation process are similar to those described in FIG. 2. Referring to the description of the technical implementation process in the FEC device shown in FIG. 2, details are not described herein again.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

本发明实施例提供了译码装置及方法，获取待译码组，检测所述待译码组中所有码字是否都满足校验和为0；当所述待译码组中所有码字都都满足校验和为0时，对所述待译码组执行符号位判决。当所述待译码组中不是所有码字都满足校验和为0时，检测所述待译码组中每个码字是否执行过符号位判决，当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。当待译码组中所有码字都都满足校验和为0时，不执行FEC译码，仅执行符号位判决，即对每个码字执行多次译码的过程中，并不是每次都执行FEC译码，降低了FEC译码所需的功耗。

Description

一种FEC译码的装置及方法 技术领域
本发明涉及通信技术领域，尤其是涉及一种FEC译码的装置及方法。
背景技术
随着通信技术的发展，光纤传输以其信息容量大、抗干扰能力强以及传输速度快等优点成为当前通信系统中主导的数据传输方式。采用光纤传输系统进行数据传输时，发送端将所要发送的数据进行前向纠错码(Forward Error Correction，FEC)编码，将FEC编码后的基带信号进行相位调制，将相位调制后的数据发送到传输光纤传输至接收端。接收端将接收到的数据通过相干调解恢复出基带信号，对基带信号采用模数转换获得数字信号，采用数字处理算法对数字信号进行色散补偿、时钟恢复、解偏振复用以及载波相位估计等处理输出多电平数字信号，根据所述多电平数字信号获得数据的对数似然比(Likelihood Ratio，LLR)，对传输数据的LLR进行FEC译码获得发送端所要传输的数据。
光纤传输的速率不断提升，从40Gb/s提升到100Gb/s，甚至可以达到400Gb/s，FEC译码所需处理的数据量也不断增加，FEC译码所需的功耗也不断增大。传统的FEC译码采用迭代译码方式，预先设置每个码字的迭代次数N，对每个码字执行N次迭代译码后输出该码字的译码结果。一般情况下，大部分码字经过M次迭代译码后已经成功完成译码，剩余的M-N次译码并没有起到译码的作用，M-N次多余的迭代译码造成功耗的浪费。其中，M为小于N的自然数。
发明内容
本发明实施例提供了FEC译码的装置及方法，当所述待译码组所有码字都完成译码时，则不用执行FEC译码，仅执行符号位判决，降低了FEC译码所需的功耗。
本发明实施例第一方面提供了一种FEC译码装置，所述装置包括：
获取单元，用于获取待译码组，所述待译码组包括预设个数的码字；
第一检测单元，用于检测所述待译码组中是否所有码字都满足校验和为0；
判决单元，用于当所述待译码组中所有码字都满足校验和为0时，对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0；
第二检测单元，用于当所述待译码组中不是所有码字都满足校验和为0时，检测所述待译码组中是否存在至少一个码字执行过符号位判决；
恢复单元，用于当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数；
第一译码单元，用于将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。
在本发明实施例第一方面的第一种可能的实现方式中，
所述第一检测单元，具体用于检测所述待译码组中所有码字是否都携带有译码成功标识；当所述待译码组中所有码字携带有译码成功标识时，所述待译码组中所有码字都满足校验和为0；当所述待译码组中存在至少一个码字没有携带有译码成功标识时，所述待译码组中不是所有码字都满足校验和为0；
所述装置还包括：
第一校验单元，用于计算所述新的待译码组中进行FEC译码后的每个码字的校验和；
第一添加单元，用于给所述新的待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
结合本发明实施例第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述装置还包括：
第二译码单元，用于当所述待译码组中所有的码字都没执行过符号位判决时，对所述待译码组进行FEC译码；
第二校验单元，用于计算所述待译码组中进行FEC译码后的每个码字的校验和；
第二添加单元，用于给所述待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
在本发明实施例第一方面第三种可能的实现方式中，所述装置还包括：
第三添加单元，用于给所述待译码组中的每个码字添加已判决标识；
所述第二检测单元，具体用于检测所述待译码组中是否存在至少一个码字携带有已判决标识；
所述装置还包括：
修改单元，用于将每个执行过符号位判决的码字的已判决标识改为未判决标识。
结合本发明实施例第一方面至第一方面的第三种可能的实现方式，在第四种可能的实现方式中，所述装置还包括：
输出单元，用于判断所述待译码组中按照时序排列最先接收的码字的译码次数是否到达预设译码迭代次数，如果是，输出所述按照时序排列最先接收的码字的译码结果。
本发明实施例第二方面提供了一种FEC译码方法，所述方法包括：
获取待译码组，所述待译码组包括预设个数的码字；
检测所述待译码组中是否所有码字都满足校验和为0；
当所述待译码组中所有码字都满足校验和为0时，对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0；
当所述待译码组中不是所有码字都满足校验和为0时，检测所述待译码组中是否存在至少一个码字执行过符号位判决；
当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数；
将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待 译码组进行FEC译码。
在本发明实施例第二方面第一种可能的实现方式中，所述检测所述待译码组中是否所有码字都满足校验和为0包括：
检测所述待译码组中所有码字是否都携带有译码成功标识；
当所述待译码组中所有码字都携带有译码成功标识时，所述待译码组中所有码字都满足校验和为0；
当所述待译码组中存在至少一个码字没有携带有译码成功标识时，所述待译码组中不是所有码字都满足校验和为0；
所述将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码后还包括：
计算所述新的待译码组中进行FEC译码后的每个码字的校验和；
给所述新的待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
结合本发明实施例第二方面第一种可能的实现方式，在第二种可能的实现方式中，所述方法还包括：
当所述待译码组中所有的码字都没执行过符号位判决时，对所述待译码组进行FEC译码；
计算所述待译码组中进行FEC译码后的每个码字的校验和；
给所述待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
在本发明实施例第二方面第三种可能的实现方式中，所述对所述待译码组执行符号位判决后还包括：
给所述待译码组中的每个码字添加已判决标识；
所述检测所述待译码组中是否存在至少一个码字执行过符号位判决包括：
检测所述待译码组中是否存在至少一个码字携带有已判决标识；
所述对每个执行过符号位判决的码字执行数据恢复后还包括：
将每个执行过符号位判决的码字的已判决标识改为未判决标识。
结合本发明实施例第二方面至第二方面第三种可能的实现方式，在第四种 可能的实现方式中，所述方法还包括：
判断所述待译码组中按照时序排列最先接收的码字的译码次数是否到达预设译码迭代次数，如果是，输出所述按照时序排列最先接收的码字的译码结果。
由上述技术方案可以看出，本发明实施例有如下有益效果：
本发明实施例提供了译码装置及方法，获取待译码组，检测所述待译码组中所有码字是否都满足校验和为0；当所述待译码组中所有码字都都满足校验和为0时，对所述待译码组执行符号位判决。当所述待译码组中不是所有码字都满足校验和为0时，检测所述待译码组中每个码字是否执行过符号位判决，当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。当待译码组中所有码字都都满足校验和为0时，不执行FEC译码，仅执行符号位判决，即对每个码字执行多次译码的过程中，并不是每次都执行FEC译码，降低了FEC译码所需的功耗。
附图说明
图1为本发明实施例提供的FEC译码装置结构示意图；
图2为本发明实施例提供的FEC译码装置结构示意图；
图3为本发明实施例提供的FEC译码装置硬件结构示意图；
图4为本发明实施例提供的FEC译码方法流程图；
图5为本发明实施例提供的FEC译码方法流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚地描述。
图1为本发明实施例提供的FEC译码装置结构示意图，所述装置包括：
获取单元101，用于获取待译码组，所述待译码组包括预设个数的码字。
发送端将所要发送的数据分成K个码字，每个码字包含预设长度的传输数据，将K个码字编码后发送到接收端。接收端对所接收的传输数据进行译码时，也将所接收的传输数据分成K个待译码的码字，每个待译码的码字也包含预设长度的传输数据。其中，K为大于0的整数。
每次译码时将预设个数的待译码的码字组成一个待译码组，所述待译码组中的每个码字按照码字接收的先后顺序排列，先接收的码字排列在前，后接收的码字排列在后。这里需要说明的是，每个待译码组所包含的待译码的码字的预设个数可以根据实际需要自行设定，并且每码字中所包含的传输数据的预设长度也可以根据实际需要自行设定，这里不进行具体限定。
举例说明：发送端编码时将10000bit的传输数据分成500个码字，每个码字包含20bit的传输数据，其中19bit是已知数据信息位，1bit是数据编码校验位。接收端将接收到得传输数据也分成500个码字，每个码字包含20bit的传输数据。
所述待译码组中所包含的预设个数的待译码的码字，对于每个待译码的码字来说，若该待译码的码字已执行过FEC译码，则该待译码的码字为上一次对该待译码的码字FEC译码后的译码结果。举例说明：先执行对待译码组abcd的FEC译码，再执行对译码组efgh的FEC译码，则对译码组cdef执行译码时，所获取的码字cd是对abcd执行FEC译码后所得的cd，所获取的ef是对defg执行FEC译码后所得的ef，其中，a，b，c，d，e，f，g，h都是待译码的码字。
第一检测单元102，用于检测所述待译码组中是否所有码字都满足校验和为0，如果是，进入判决单元103；如果否，进入第二检测单元104。
发送端在对传输数据进行编码时，设定码字的校验关系，一般情况下，所设定的码字的校验关系为该码字中的所有数据信息校验和为0。在接收端，当一个码字满足校验和为0时，表示该码字译码成功；当一个码字不满足校验和为0时，表示该码字译码失败。
在检测所述待译码组中是否所有码字都满足校验和为0时，所述待译码组 中包含预设个数的待译码的码字，分别计算每个待译码的码字是否满足校验和为0，当每个待译码的码字都满足校验和为0时，所述待译码组中所有码字都译码成功；当存在至少一个待译码的码字校验和不为0时，所述待译码组中不是所有码字都译码成功。
判决单元103，用于对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0。
当所述待译码组中所有码字都满足校验和为0时，再对所述待译码组执行FEC译码，译码结果不会发生改变，则无需对所述待译码组重复执行FEC译码，对所述待译码组执行符号位判决即可，将所述待译码组中的大于或等于0的数据判决为1，即用1替换所述待译码组中的大于或等于0的数据；将所述待译码组中小于0的数据判决为0，即用0代替小于0的数据，将对所述待译码组执行符号位判决的结果作为队所述待译码组此次迭代译码的结果。
现有技术中，每次译码都要执行FEC译码。而本发明中，若所述待译码组中所有码字都满足校验和为0，则不执行FEC译码，而仅执行符号位判决，符号位判决仅仅是对所述待译码组中的数据取符号位，不用重复执行复杂的FEC译码，从而降低了FEC译码所需的功耗。
第二检测单元104，用于检测所述待译码组中是否存在至少一个码字执行过符号位判决。
恢复单元105，用于当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数。
第一译码单元106，用于将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。
当所述待译码组中不是所有码字都满足校验和为0时，先检测所述待译码组中是否存在至少一个码字执行过符号位判决。判决的标准是，当一个码字执行过符号位判决时，所述码字中的数据都是0或1。则检测所述待译码组中每个码字中的所有数据是否都是0或1，当一个码字中的所有数据都是0或1时， 该码字执行过符号位判决；当一个码字中有除了0和1以外的其他数值的数据时，该码字没有执行过符号位判决。
当所述待译码组中存在至少一个码字执行过符号位判决时，对每个执行过符号位判决的码字执行数据恢复。所述数据恢复指的是将该码字中的0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数。所述模数转换最大值由接收端的模数转换器的参数决定。举例说明，当接收端的模数转换器进行模数转换的最大值为31时，对执行过符号位判决的码字进行数据恢复，将该码字中的0恢复为-31，将1恢复为31。
将所述待译码组中每个执行过符号位判决的码字进行数据恢复，将数据恢复后的每个执行过符号位判决的码字和所述待译码组中原有的每个没有执行过符号位判决的码字组成新的待译码组，对所述新的待译码组执行FEC译码，获得此次迭代译码的译码结果。
这里需要说明的是，当所述待译码组中所有码字都没有执行过符号位判决时，直接对所述待译码组执行FEC译码即可。
由上述内容可知，本发明实施例有如下有益效果：
当待译码组中所有码字都都满足校验和为0时，不执行FEC译码，仅执行符号位判决，即对每个码字执行多次译码的过程中，并不是每次都执行FEC译码，降低了FEC译码所需的功耗。
图2为本发明实施例提供的FEC译码装置结构示意图，所述装置包括：
获取单元201，用于获取待译码组，所述待译码组包括预设个数的码字。
图2所示的获取单元201与图1所示的FEC译码装置中的获取单元101类似，参考图1所示的FEC译码装置中的获取单元101的描述，这里不再赘述。
第一检测单元202，用于检测所述待译码组中所有码字是否携带有译码成功标识，如果是，进入判决单元203；如果否，进入第二检测单元205。
所述待译码组中的每个待译码的码字，在该码字上一次迭代译码结束后，计算该码字校验和，当该码字的校验和为0时，给该码字添加一个译码成功标识。则检测所述待译码组中所有码字是否携带有译码成功标识，即为检测所述 待译码组中所有码字是否校验和为0。当再次将该码字作为所述待译码组中的一个码字时，无需重复计算该码字的校验和，只需检测该码字是否携带有译码成功标识即可。
当所述待译码组中所有码字都携带有译码成功标识时，所述待译码组中所有码字的校验和都为0；当所述待译码组中存在至少一个码字没有携带有译码成功标识时，表示所述待译码组中至少存在一个码字校验和不为0，即所述待译码组中不是所有的码字的校验和都为0。
判决单元203，用于对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0。
当所述待译码组中所有码字都携带有译码成功标识时，表示所述待译码组中所有码字都满足校验和为0时，再对所述待译码组执行FEC译码，译码结果不会发生改变，则无需对所述待译码组重复执行FEC译码，对所述待译码组执行符号位判决即可。对所述待译码组执行符号位判决即为将所述待译码组中的大于或等于0的数据判决为1，即用1替换所述待译码组中的大于或等于0的数据；将所述待译码组中小于0的数据判决为0，即用0代替小于0的数据，将对所述待译码组执行符号位判决的结果作为队所述待译码组此次迭代译码的结果。
第三添加单元204，用于给所述待译码组中的每个码字添加已判决标识。
当所述待译码组中所有码字都携带有译码成功标识时，对所述待译码组执行符号位判决，执行符号位判决后，给所述待译码组中每个码字添加已判决标识，表示该码字执行过符号位判决。
则后续判断一个码字是否执行过符号位判决时，无需重复查询是否该码字中所有的数据都是0和1，而只需检测该码字是否携带有已判决标识即可，简化检测一个码字是否执行过符号位判决的步骤。
第二检测单元205，用于检测所述待译码组中是否存在至少一个码字携带有已判决标识，如果是，进入恢复单元206；如果否，进入第二译码单元211。
恢复单元206，用于对每个携带有已判决标识的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的 正数。
当所述待译码组中不是所有的码字都携带有译码成功标识时，检测所述待译码组中是否存在至少一个码字携带有已判决标识。当一个码字携带有已判决标识时，表示该码字执行过符号位判决，即该码字中所有的数据都是0和1。由于FEC译码是对正负数执行译码，因此需要对携带有已判决标识的码字进行数据恢复。
所述数据恢复指的是将该码字中的0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数。所述模数转换最大值由接收端的模数转换器的参数决定。
第一译码单元207，用于将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。
将所述待译码组中每个执行数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组，对所述新的待译码组执行FEC译码。
修改单元208，用于将每个执行过符号位判决的码字的已判决标识改为未判决标识。
由于对所述待译码组中每个执行过符号位判决的码字执行了数据恢复，所述待译码组中每个执行过符号位判决的码字中的数据不再只有0和1，不满足执行过符号位判决的条件，因此，要将每个执行过符号位判决的码字的已判决标识改为未判决标识。
第一校验单元209，用于计算所述新的待译码组中进行FEC译码后的每个码字的校验和。
第一添加单元210，用于给所述新的待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
第二译码单元211，用于对所述待译码组进行FEC译码。
计算所述新的待译码组中进行FEC译码后的每个码字的校验和，给所述新的待译码组中进行FEC译码后校验和为0的码字添加译码成功标识，表示该码字译码成功。当该码字作为另一个待译码组中的待译码的码字时，判断该码字是否携带有译码成功标识，即可判断该码字是否校验和为0，无需重复计算该 码字的校验和。
第二校验单元212，用于计算所述待译码组中进行FEC译码后的每个码字的校验和。
第二添加单元213，用于给所述待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
当所述待译码组中的所有码字都没有执行过符号位判决时，直接对所述待译码组执行FEC译码即可。计算所述待译码组中进行FEC译码后的每个码字的校验和，给所述待译码组中进行FEC译码后校验和为0的码字添加译码成功标识，表示该码字译码成功。当该码字作为另一个待译码组中的待译码的码字时，判断该码字是否携带有译码成功标识，即可判断该码字是否校验和为0，无需重复计算该码字的校验和。
输出单元214，用于判断所述待译码组中按照时序排列最先接收的码字的译码次数是否到达预设译码迭代次数，如果是，输出所述按照时序排列最先接收的码字的译码结果。
本次迭代译码结束后，获取所述待译码组中按照时序排列最先接收的码字，即所述待译码组中排在第一个的码字，判断该码字的译码次数是否到达预设译码迭代次数，如果是，输出该码字的译码结果。所述预设译码迭代次数可以根据实际需要自行设定，这里不进行具体限定。
每次迭代译码实际上只是针对所述待译码组中按照时序排列最先接收的码字进行译码，当所述待译码组中按照时序排列最先接收的码字的译码次数是否到达预设译码迭代次数时，该按照时序排列最先接收的码字肯定已经完成译码，可以输出该按照时序排列最先接收的码字的译码结果。
举例说明：对包含f，g，h，i四个码字的待译码组译码结束后，获取按照时序排列最先接收的码字f，判断码字f的译码次数是否到达预设译码迭代次数，如果是，输出码字f的译码结果。
每次迭代译码最多输出1个码字的译码结果，若所述待译码组中按照时序排列最先接收的码字没有到达预设译码迭代次数，则没有译码结果输出。这里需要说明的是，本发明实施例中所指的输出的译码结果，指的是接收 端中FEC译码器所输出的译码结果，而不是每次迭代后所获得的待译码组的译码结果，所述待译码组的一次迭代译码结果会在FEC译码器中循环使用，不输出。
图3为本发明实施例提供的FEC译码装置硬件结构示意图，所述装置包括：
存储器301，以及与所述存储器相连的处理器302，所述存储器301用于存储存储一组程序指令，所述处理器302用于调用所述存储器301存储的程序指令执行如下操作：
获取待译码组，所述待译码组包括预设个数的码字；
检测所述待译码组中是否所有码字都满足校验和为0；
当所述待译码组中所有码字都满足校验和为0时，对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0；
当所述待译码组中不是所有码字都满足校验和为0时，检测所述待译码组中是否存在至少一个码字执行过符号位判决；
当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数；
将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。
可选的，所述检测所述待译码组中是否所有码字都满足校验和为0指令包括：
检测所述待译码组中所有码字是否携带有译码成功标识；
当所述待译码组中所有码字携带有译码成功标识时，所述待译码组中所有码字都满足校验和为0；
当所述待译码组中存在至少一个码字没有携带有译码成功标识时，所述待译码组中不是所有码字都满足校验和为0；
所述将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码指令后还包括：
计算所述新的待译码组中进行FEC译码后的每个码字的校验和；
给所述新的待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
可选的，所述指令还包括：
当所述待译码组中所有的码字都没执行过符号位判决时，对所述待译码组进行FEC译码；
计算所述待译码组中进行FEC译码后的每个码字的校验和；
给所述待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
可选的，所述对所述待译码组执行符号位判决指令后还包括：
给所述待译码组中的每个码字添加已判决标识；
所述检测所述待译码组中是否存在至少一个码字执行过符号位判决指令包括：
检测所述待译码组中是否存在至少一个码字携带有已判决标识；
所述对每个执行过符号位判决的码字执行数据恢复指令后还包括：
将每个执行过符号位判决的码字的已判决标识改为未判决标识。
可选的，所述指令还包括：
判断所述待译码组中按照时序排列最先接收的码字的译码次数是否到达预设译码迭代次数，如果是，输出所述按照时序排列最先接收的码字的译码结果。
所述处理器302可以为中央处理器(Central Processing Unit，CPU)，所述存储器301可以为随机存取存储器(Random Access Memory，RAM)类型的内部存储器。所述存储器301和所述处理器1302可以集成为一个或多个独立的电路或硬件，如：专用集成电路(Application Specific Integrated Circuit，ASIC)。
图3所示的FEC译码装置硬件实现结构中，所述处理器执行的操作的 技术实现过程与对图1和图2所示的FEC译码装置的技术实现过程类似，参考图1和图2所示的FEC装置中的描述，这里不再赘述。
图4为本发明实施例提供的FEC译码方法流程图，所述方法包括：
401：获取待译码组，所述待译码组包括预设个数的码字。
402：检测所述待译码组中是否所有码字都满足校验和为0，如果是，执行403；如果否执行404。
403：对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0。
当所述待译码组中所有码字都满足校验和为0时，再对所述待译码组执行FEC译码，译码结果不会发生改变，则无需对所述待译码组重复执行FEC译码，对所述待译码组执行符号位判决即可，将所述待译码组中的大于或等于0的数据判决为1，即用1替换所述待译码组中的大于或等于0的数据；将所述待译码组中小于0的数据判决为0，即用0代替小于0的数据，将对所述待译码组执行符号位判决的结果作为队所述待译码组此次迭代译码的结果。
现有技术中，每次译码都要执行FEC译码。而本发明中，若所述待译码组中所有码字都满足校验和为0，则不执行FEC译码，而仅执行符号位判决，符号位判决仅仅是对所述待译码组中的数据取符号位，不用重复执行复杂的FEC译码，从而降低了FEC译码所需的功耗。
404：检测所述待译码组中是否存在至少一个码字执行过符号位判决。
405：当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数。
406：将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。
图4所述的FEC译码的方法是与图1所示的FEC译码的装置所对应的方法，技术实现过程与图1描述类似，参考图1所示的FEC装置中对技术 实现过程的描述，这里不再赘述。
图5为本发明实施例提供的FEC译码方法流程图，所述方法包括：
501：获取待译码组，所述待译码组包括预设个数的码字。
502：检测所述待译码组中所有码字是否都携带有译码成功标识，如果是，执行503；如果否，505。
503：对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0。
504：给所述待译码组中的每个码字添加已判决标识。
505：检测所述待译码组中是否存在至少一个码字携带有已判决标识，如果是，执行506；如果否，执行511。
506：对每个携带有已判决的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数。
507：将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。
508：将每个执行过符号位判决的码字的已判决标识改为未判决标识。
509：计算所述新的待译码组中进行FEC译码后的每个码字的校验和。
510：给所述新的待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
511：对所述待译码组进行FEC译码。
512：计算所述待译码组中进行FEC译码后的每个码字的校验和。
513：给所述待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
514：判断所述待译码组中按照时序排列最先接收的码字的译码次数是否到达预设译码迭代次数，如果是，输出所述按照时序排列最先接收的码字的译码结果。
图5所述的FEC译码的方法是与图2所示的FEC译码的装置所对应的 方法，技术实现过程与图2描述类似，参考图2所示的FEC装置中对技术实现过程的描述，这里不再赘述。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质可以是下述介质中的至少一种：只读存储器(Read-Only Memory，ROM)、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅是本发明的优选实施方式，并非用于限定本发明的保护范围。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种FEC译码装置，其特征在于，所述装置包括：
    获取单元，用于获取待译码组，所述待译码组包括预设个数的码字；
    第一检测单元，用于检测所述待译码组中是否所有码字都满足校验和为0；
    判决单元，用于当所述待译码组中所有码字都满足校验和为0时，对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0；
    第二检测单元，用于当所述待译码组中不是所有码字都满足校验和为0时，检测所述待译码组中是否存在至少一个码字执行过符号位判决；
    恢复单元，用于当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数；
    第一译码单元，用于将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。
  2. 根据权利要求1所述的装置，其特征在于，
    所述第一检测单元，具体用于检测所述待译码组中所有码字是否都携带有译码成功标识；当所述待译码组中所有码字携带有译码成功标识时，所述待译码组中所有码字都满足校验和为0；当所述待译码组中存在至少一个码字没有携带有译码成功标识时，所述待译码组中不是所有码字都满足校验和为0；
    所述装置还包括：
    第一校验单元，用于计算所述新的待译码组中进行FEC译码后的每个码字的校验和；
    第一添加单元，用于给所述新的待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
  3. 根据权利要求2所述的装置，其特征在于，所述装置还包括：
    第二译码单元，用于当所述待译码组中所有的码字都没执行过符号位判决 时，对所述待译码组进行FEC译码；
    第二校验单元，用于计算所述待译码组中进行FEC译码后的每个码字的校验和；
    第二添加单元，用于给所述待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
  4. 根据权利要求1所述的装置，其特征在于，所述装置还包括：
    第三添加单元，用于给所述待译码组中的每个码字添加已判决标识；
    所述第二检测单元，具体用于检测所述待译码组中是否存在至少一个码字携带有已判决标识；
    所述装置还包括：
    修改单元，用于将每个执行过符号位判决的码字的已判决标识改为未判决标识。
  5. 根据权利要求1-4任意一项所述的装置，其特征在于，所述装置还包括：
    输出单元，用于判断所述待译码组中按照时序排列最先接收的码字的译码次数是否到达预设译码迭代次数，如果是，输出所述按照时序排列最先接收的码字的译码结果。
  6. 一种FEC译码方法，其特征在于，所述方法包括：
    获取待译码组，所述待译码组包括预设个数的码字；
    检测所述待译码组中是否所有码字都满足校验和为0；
    当所述待译码组中所有码字都满足校验和为0时，对所述待译码组执行符号位判决，所述符号位判决为将非负数判决为1，将负数判决为0；
    当所述待译码组中不是所有码字都满足校验和为0时，检测所述待译码组中是否存在至少一个码字执行过符号位判决；
    当所述待译码组中存在至少一个执行过符号位判决的码字时，对每个执行过符号位判决的码字执行数据恢复，所述数据恢复为将0恢复为模数转换最大值的负数，将1恢复为模数转换最大值的正数；
    将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码。
  7. 根据权利要求6所述的方法，其特征在于，所述检测所述待译码组中是否所有码字都满足校验和为0包括：
    检测所述待译码组中所有码字是否都携带有译码成功标识；
    当所述待译码组中所有码字都携带有译码成功标识时，所述待译码组中所有码字都满足校验和为0；
    当所述待译码组中存在至少一个码字没有携带有译码成功标识时，所述待译码组中不是所有码字都满足校验和为0；
    所述将每个数据恢复后的码字与每个未执行过符号位判决的码字组成新的待译码组进行FEC译码后还包括：
    计算所述新的待译码组中进行FEC译码后的每个码字的校验和；
    给所述新的待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
  8. 根据权利要求7所述的方法，其特征在于，所述方法还包括：
    当所述待译码组中所有的码字都没执行过符号位判决时，对所述待译码组进行FEC译码；
    计算所述待译码组中进行FEC译码后的每个码字的校验和；
    给所述待译码组中进行FEC译码后校验和为0的码字添加译码成功标识。
  9. 根据权利要求6所述的方法，其特征在于，所述对所述待译码组执行符号位判决后还包括：
    给所述待译码组中的每个码字添加已判决标识；
    所述检测所述待译码组中是否存在至少一个码字执行过符号位判决包括：
    检测所述待译码组中是否存在至少一个码字携带有已判决标识；
    所述对每个执行过符号位判决的码字执行数据恢复后还包括：
    将每个执行过符号位判决的码字的已判决标识改为未判决标识。
  10. 根据权利要求6-9任意一项所述的方法，其特征在于，所述方法还包 括：
    判断所述待译码组中按照时序排列最先接收的码字的译码次数是否到达预设译码迭代次数，如果是，输出所述按照时序排列最先接收的码字的译码结果。
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