WO2016123884A1 - 动车组牵引控制系统 - Google Patents

动车组牵引控制系统 Download PDF

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Publication number
WO2016123884A1
WO2016123884A1 PCT/CN2015/079333 CN2015079333W WO2016123884A1 WO 2016123884 A1 WO2016123884 A1 WO 2016123884A1 CN 2015079333 W CN2015079333 W CN 2015079333W WO 2016123884 A1 WO2016123884 A1 WO 2016123884A1
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Prior art keywords
signal
module
board
bus
interface
Prior art date
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Ceased
Application number
PCT/CN2015/079333
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English (en)
French (fr)
Inventor
崔凤钊
张亚伟
孙国斌
李震
曹虎
梁大伟
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CRRC Qingdao Sifang Rolling Stock Research Institute Co Ltd
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CRRC Qingdao Sifang Rolling Stock Research Institute Co Ltd
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Application filed by CRRC Qingdao Sifang Rolling Stock Research Institute Co Ltd filed Critical CRRC Qingdao Sifang Rolling Stock Research Institute Co Ltd
Priority to US15/322,066 priority Critical patent/US9669732B2/en
Priority to EP15880839.4A priority patent/EP3121670B1/en
Priority to JP2017502875A priority patent/JP6294560B2/ja
Priority to RU2016149861A priority patent/RU2641558C1/ru
Publication of WO2016123884A1 publication Critical patent/WO2016123884A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L15/00—Methods, circuits, or devices for controlling the traction-motor speed of electrically-propelled vehicles
    • B60L15/32—Control or regulation of multiple-unit electrically-propelled vehicles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L15/00—Methods, circuits, or devices for controlling the traction-motor speed of electrically-propelled vehicles
    • B60L15/002—Methods, circuits, or devices for controlling the traction-motor speed of electrically-propelled vehicles for control of propulsion for monorail vehicles, suspension vehicles or rack railways; for control of magnetic suspension or levitation for vehicles for propulsion purposes
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/4185—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by the network communication
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L2200/00—Type of vehicles
    • B60L2200/26—Rail vehicles
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21021—Intelligent I-O, executes tasks independently from main cpu
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21137—Analog to digital conversion, ADC, DAC
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/24—Pc safety
    • G05B2219/24048—Remote test, monitoring, diagnostic
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25012—Two different bus systems
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25032—CAN, canbus, controller area network bus
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25127—Bus for analog and digital communication
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25318—Power supply module in common for all modules
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/26—Pc applications
    • G05B2219/2637—Vehicle, car, auto, wheelchair
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02T90/10—Technologies relating to charging of electric vehicles
    • Y02T90/16—Information or communication technologies improving the operation of electric vehicles

Definitions

  • the invention relates to the field of railway electronics, and in particular to a traction control system for an EMU train.
  • the EMU traction control system is the core power controller of the EMU train.
  • the EMU traction control system controls the four-quadrant rectifier, brake chopper, and traction inverter IGBT switch to obtain control that meets the vehicle traction/braking performance requirements.
  • the main circuit structure diagram of the current EMU traction control system is shown in Figure 1.
  • the single-phase high-voltage power is received by the pantograph and is output to the four-quadrant unit through the secondary side of the transformer, and the rectified high-voltage direct current is output to the inverter power module through the intermediate DC bus. After being inverterd by the inverter power module, it is output to the traction motor to control the traction motor to run.
  • the current control unit traction drive system control unit uses a 32-bit processor host, Siemens uses AMD's ElanSC520, clocked at 133MHz; Bombardier uses Freescale's MC68360, clocked at 25MHz; ALSTOM uses ST's STPC, clocked at 133MHz; Zhuzhou Adopt MPC5200D, the main frequency is 533MHz.
  • Control algorithm processor selection Siemens uses DSP56002, clocked at 100MHz; Bombardier uses DSP56302, clocked at 100MHz; Alstom uses ADI 21062, clocked at 160MHz; Zhuzhou company uses TMS320C6713, clocked at 200MHz .
  • the processor chips used by various companies are relatively early products.
  • the chip models are older, the system response is slower, many chips have been discontinued, and the production cost is higher due to the discontinuation of the chips.
  • the object of the present invention is to provide a traction control system for an EMU train, which can simultaneously realize control of two sets of four-quadrant power modules and two sets of inverter power modules.
  • the EMU traction control system is used for controlling the inverter/four-quadrant power module of the EMU traction converter, mainly comprising a power module, an inverter/four-quadrant module, an I/O module, and a network.
  • Module and debug module are used for controlling the inverter/four-quadrant power module of the EMU traction converter, mainly comprising a power module, an inverter/four-quadrant module, an I/O module, and a network.
  • Module and debug module is used for controlling the inverter/four-quadrant power module of the EMU traction converter, mainly comprising a power module, an inverter/four-quadrant module, an I/O module, and a network.
  • Module and debug module are used for controlling the inverter/four-quadrant power module of the EMU traction converter, mainly comprising a power module, an inverter/four-quadrant module, an I/O module, and a network.
  • the inverter/four-quadrant module is mainly composed of a fast computing board, a signal sampling board and a pulse interface board.
  • the signal sampling board is mainly configured to receive an external sensor signal, receive a pulse feedback signal sent by the pulse interface board, and receive a control signal sent by the fast operation board, and send a pulse signal to the pulse interface board to the
  • the fast computing board transmits the processed acquisition signal and sends a relay control signal to the I/O module.
  • the fast computing board is mainly configured to receive analog and digital signals collected and processed by the signal sampling board, receive a control signal sent by the processor host, and send a control signal to the signal sampling board to the Network module Send processing signals.
  • the traction control unit can control two sets of inverter power modules and two sets of four-quadrant power modules through a pulse interface board;
  • the pulse interface board is mainly configured to receive the IGBT status signal from the inverter/four-quadrant power module, receive an IGBT control signal sent by the signal sampling board, and send an IGBT status signal to the signal sampling board,
  • the inverter/four-quadrant power module emits an IGBT control signal.
  • the signal sampling board and the fast computing board perform bidirectional communication through a high speed differential LinkPort bus;
  • the signal sampling board and the I/O module perform two-way communication through a high speed bus
  • the I/O module and the inverter/four-quadrant module perform bidirectional communication through a high speed bus
  • the I/O module communicates with the network module and the debugging module through a CAN bus.
  • the network module is composed of a network board, and the network module receives the digital quantity and the analog quantity signal sent by the I/O module, and transmits the signal to the processor host via the CPCI bus, and receives the command signal of the processor host through the CPCI bus. And sending a command to the I/O module, controlling the I/O module to output digital and analog signals, and controlling the MVB interface unit to perform data interaction with the external MVB bus; and simultaneously transmitting the MVB data to the processing through the CPCI bus.
  • the debugging module is composed of a debugging board, and the debugging module receives a debugging command and a debugging signal sent by the processor host through the CPCI bus, and the debugging module receives the debugging signal sent by the signal sampling board through the high-speed bus, and the debugging module
  • the analog debug signal is output through a 32-channel analog output circuit.
  • the power module supplies power to the inverter/four-quadrant module, the I/O module, the network module, and the debugging module, and the power module supplies power to the inverter/four-quadrant power module.
  • the power module described supplies power to the internal sensors of the traction converter.
  • the signal sampling board includes a current/voltage collecting unit and a clock management unit, and the current/voltage collecting unit is composed of an interconnected signal conditioning circuit and an ADC sampling circuit;
  • the current/voltage collecting unit has multiple paths, which are all connected to the signal sampling board, and the clock management unit is respectively connected with the signal sampling board and the fast calculation board, and the signal conditioning circuit comprises a first resistor, a second resistor, a filter capacitor and an operation.
  • An input end of the signal conditioning circuit is connected to the sampling sensor end, an input end of the signal conditioning circuit is connected to the first end of the first resistor, and a second end of the first resistor is respectively connected to the first end of the second resistor and the operational amplifier
  • the positive input terminal, the second end of the second resistor is grounded, the inverting input terminal of the operational amplifier is connected to the reference voltage terminal, the output end of the operational amplifier is connected to the ADC sampling circuit; the input end of the signal conditioning circuit is also grounded via the filter capacitor .
  • the pulse interface board can realize photoelectric conversion function, and the pulse interface board includes a PWM level conversion circuit, a photoelectric conversion unit, an electro-optical conversion unit, and a backplane interface unit, and the PWM level conversion circuit passes through the backplane interface unit and the signal sampling board. Connected, also includes a self-diagnostic unit;
  • the self-diagnosis unit includes an input diagnosis unit and an output diagnosis unit;
  • the photoelectric conversion unit and the electro-optic conversion unit have a plurality of groups, and the photoelectric conversion unit includes a multiplexer, a buffer, and a photoelectric conversion circuit, and the backplane interface unit is connected to the multiplexer via the buffer I, and multiplexed
  • the device is connected to the photoelectric conversion circuit via a buffer II;
  • the electro-optical conversion unit comprises a multiplexer, a buffer and an electro-optical conversion circuit, the electro-optical conversion circuit is connected to the multiplexer via the buffer III, and the multiplexer is buffered
  • the IV is connected to the backplane interface unit;
  • the output diagnostic unit includes a multiplexer and an output self-diagnosis circuit, and an output end of the buffer II of each group of photoelectric conversion units is connected to an input end of the multiplexer outputted from the diagnostic unit, and outputs an input end of the self-diagnostic circuit.
  • the output of the multiplexer is connected to the backplane interface unit;
  • the input diagnostic unit includes a multiplexer and an input self-diagnostic circuit, and the input of the multiplexer is interfaced with the backplane
  • the units are connected, and the output ends are multiplexed and connected to the input terminals of each group of electro-optic conversion unit buffers III.
  • a protocol converter of the CPCI bus and the ISA bus is designed between the network module and the processor host for two-way communication
  • the protocol converter includes a CPCI local bus interface extended timing module, an ISA bus interface timing module, a CPCI bus matching ISA bus timing interface module, and a clock management module;
  • the CPCI local bus interface extended timing module passes the address and data signals AD[31:0 ⁇ , command/byte enable signal C/BE [3:0], slave ready signal TRDY, stop data transfer signal STOP, frame period signal FRAME and master ready signal IRDY communicate with the local CPCI bus;
  • the ISA bus interface timing module passes the data enable signal S_DATA_VLD, the address enable signal ADDR_VLD, the read enable signal barx_rd, the write enable signal barx_wr, the byte enable signal S_CBE, the data signal D[31:0], and the address signal A.
  • the ISA bus interface timing module passes the data signal S D, the address signal SA, the read/write IO device signal IOW/IOR, the read/write MEMORY device signal MEMR/MEMW, the address latch signal BALE communicate with the local ISA bus;
  • the CPCI bus matches the ISA bus timing interface module by playing The break reconnect signal USER_STOP is in communication with the CPCI local bus interface extended timing module;
  • the clock management module is the CPCI local bus interface extended timing module, the ISA bus interface timing module, and the CPCI bus matching ISA bus timing
  • the interface module provides an operating clock.
  • the main frame of the EMU traction control system adopts a high-strength reinforcement chassis, and the chassis panels on both sides of the reinforcement chassis adopt a reinforcement panel.
  • the double-assisted device is provided at the connection between each type of board of the EMU traction control system and the main box board card slot, and the double
  • the puller is mainly composed of a base plate, a pin and a flip plate, and the upper portion of the substrate is connected to the flip plate, the flip plate is an L-shaped plate, and the lower left portion of the L-shaped plate is hinged with the substrate at the hinge portion.
  • the substrate is provided with a clamping plate positioning card slot, the positioning card slot is matched with the lower portion of the L-shaped plate, and the lower portion of the substrate is fixed with the double-row pin, the pin It is used for connecting with the card slot, and one side of the substrate is further provided with a bolt hole fixed to the card.
  • the processor host of the EMU traction control system is connected to the lower computer board through the CPCI bus, including the fast computing board, the network module and the debugging module, and transmits the instructions to the lower board through the CPCI bus, and the lower board
  • the state information is transmitted to the processor host through the CPCI bus to realize the overall control inside the EMU traction control system;
  • the signal sampling board and the fast computing board perform bidirectional communication through the high-speed differential LinkPort bus to realize fast control of the inverter power module and the four-quadrant power module;
  • the network board communicates with each board of the I/O module through the CAN bus, and the digital and analog signals sent by the boards of the I/O module are transmitted to the processor host via the CPCI bus to ensure The stability and reliability of information transmission of the EMU traction control system;
  • Commonly used data communication protocols are CAN, etc. These protocols have lower data acquisition and transmission rates than LinkPort.
  • the invention realizes the LinkPort transmission between the signal sampling board and the fast computing board.
  • the LinkPort is an LVDS (Low Voltage Differential Signal) which is a low voltage differential signal, and has the advantages of high speed, ultra low power consumption, low noise and low cost. characteristic. Data transmission through LinkPort greatly improves the data transmission speed, and the data transmission speed can reach 400 Mbit/s. Quick control of the traction control unit is possible;
  • the EMU traction control system adopts mainstream control chip and advanced design ideas, and adopts QNX embedded real-time operating system.
  • the operating system has low resource occupancy rate and strong professionalism, and is suitable for special field applications.
  • the system is streamlined, the security level is high, the real-time performance is high, the code execution efficiency is high, and multi-tasking is supported.
  • the chassis structure of the EMU traction control system has been improved.
  • the main box of the EMU traction control system adopts a high-strength reinforced chassis, and all the boards and the main box board card slot are provided with double-assisted devices, and the structure is more stable.
  • Figure 1 is a schematic diagram of the main circuit of the current EMU traction control system
  • FIG. 2 is a schematic structural view of a traction control system for an EMU of the present invention
  • FIG. 3 is a schematic structural view of a sampling board and a fast computing board
  • FIG. 4 is a schematic structural diagram of a signal sampling circuit signal conditioning circuit
  • Figure 5 is a schematic diagram of LinkPort communication
  • Figure 8 is a schematic structural view of a pulse interface board
  • FIG. 9 is a schematic structural diagram of a circuit of a remote control unit of a pulse interface board
  • FIG. 10 is a schematic structural diagram of a pulse interface board input self-diagnosis circuit
  • FIG. 11 is a schematic structural diagram of a pulse interface board output diagnostic circuit
  • Figure 12 is a schematic structural view of a double assister
  • Figure 13 is a schematic structural diagram of the protocol converter
  • Figure 14 is a specific timing diagram of TRDY, STOP, FRAME, and IRDY;
  • Figure 15 is a partial timing diagram of the protocol converter IO read access
  • Figure 16 is a flow chart of the protocol converter access
  • Figure 18 is a flow chart of the EMU traction control system.
  • the EMU traction control system can simultaneously control two sets of four-quadrant power modules and two sets of inverter power modules.
  • the EMU traction control system mainly includes a power module, an inverter/four-quadrant module, an I/O module, a network module, and a debugging module.
  • the power module consists of multiple power boards, including 110V to 24V power boards, 110V to 5V power boards, 110V to 3.3v power boards, and 110V to 15V power boards.
  • the main function of the power module is to supply power to the inverter/four-quadrant module, I/O module, network module and debugging module. At the same time, it supplies power to the inverter/four-quadrant power module and supplies power to the internal sensor of the traction converter.
  • the I/O module provides external I/O control, primarily for state acquisition and control output.
  • the I/O modules mainly include digital input boards, digital output boards, and analog input and output boards.
  • the I/O module and the inverter/four-quadrant module communicate bidirectionally through a high-speed bus, and the I/O module communicates with the network module and the debug module via the CAN bus.
  • the function of the inverter/four-quadrant module is to realize the control of the traction converter and the control of the four-quadrant, mainly by fast operation.
  • the board, the signal sampling board and the pulse interface board are composed.
  • the fast computing board is divided into an inverter fast computing board and a four-quadrant fast computing board;
  • the signal sampling board is divided into an inverter signal sampling board and a four-quadrant signal sampling board;
  • the pulse interface board is divided into an inverter pulse interface board and four quadrants. Pulse interface board.
  • the inverter signal sampling board is mainly used for receiving an external sensor signal, receiving a pulse feedback signal sent by the inverter pulse interface board, and receiving a control signal sent by the inverter fast calculation board, and transmitting a pulse signal to the inverter pulse interface board. Sending the processed acquisition signal to the inverter fast calculation board and transmitting the relay control signal to the I/O module.
  • the inverter fast computing board is mainly used for receiving analog and digital signals collected and processed by the inverter signal sampling board, receiving control signals from the processor host, and transmitting control signals to the inverter signal sampling board to the network.
  • the module sends processing information.
  • the inverter pulse interface board is connected to at most 2 sets of inverter power modules
  • the inverter pulse interface board is mainly used for receiving the IGBT status signal from the inverter power module, receiving the IGBT control signal sent by the inverter signal sampling board, and transmitting the IGBT status signal to the inverter signal sampling board to the inverter
  • the power module emits an IGBT control signal.
  • the inverter signal sampling board and the inverter fast computing board perform bidirectional communication through the high speed differential LinkPort bus; the inverter signal sampling board and the I/O module perform bidirectional communication through the high speed bus; the inverter fast computing board and the network module and The debug module communicates bidirectionally over the CPCI bus.
  • the four-quadrant signal sampling board is mainly used for receiving an external sensor signal, receiving a pulse feedback signal sent by a four-quadrant pulse interface board, and receiving a control signal sent by a four-quadrant fast computing board, and transmitting a pulse signal to the four-quadrant pulse interface board to the four quadrants.
  • the fast computing board sends the processed acquisition signal and sends a relay control signal to the I/O module.
  • the four-quadrant fast computing board is mainly used for receiving analog and digital signals collected and processed by the four-quadrant signal sampling board, receiving control signals from the processor host, and transmitting control signals to the four-quadrant signal sampling board, and transmitting and processing to the network module. information.
  • the four-quadrant pulse interface board is connected to at most two sets of four-quadrant power modules;
  • the four-quadrant pulse interface board is mainly used for receiving the IGBT status signal from the four-quadrant power module, receiving the IGBT control signal from the four-quadrant signal sampling board, and transmitting the IGBT status signal to the four-quadrant signal sampling board, and issuing the IGBT control to the four-quadrant power module. signal.
  • the four-quadrant signal sampling board and the four-quadrant fast computing board perform bidirectional communication through the high-speed differential LinkPort bus; the four-quadrant signal sampling board and the I/O module perform bidirectional communication through the high-speed bus; the four-quadrant fast computing board and the network module and the debugging module pass the CPCI
  • the bus performs two-way communication.
  • the network module is composed of a network board, and the network module receives the digital and analog signals sent by the I/O module, and transmits the signal to the processor host via the CPCI bus, and receives the command signal of the processor host through the CPCI bus, and sends the command signal to the processor host.
  • the /O module sends commands to control the I/O module to output digital and analog signals, and to control the MVB interface unit to interact with the external MVB bus; simultaneously send MVB data to the processor host via the CPCI bus, and through the CPCI bus The data that the processor host needs to send is sent to the MVB interface unit.
  • the debugging module is mainly used to complete real-time debugging with other boards in the network.
  • the debugging module is composed of a debugging board.
  • the debugging module receives the debugging command and debugging signal sent by the processor host through the CPCI bus.
  • the debugging module receives the debugging signal sent by the signal sampling board through the high-speed bus, and the debugging module outputs the simulation through the 32-channel analog output circuit. Debug signal.
  • the purpose of the traction control system is to control the IGBT switch inside the converter to achieve AC to DC to AC conversion.
  • the sensor on the circuit collects the current and voltage signals of the circuits of the traction converter, feeds the signal back to the fast calculation board via the signal sampling board, analyzes the signal, and gives the control signal in combination with the operation result.
  • the sampling signal includes a current signal and a voltage signal
  • the present invention designs a current-voltage multiplexing acquisition unit.
  • the signal sampling board includes a current/voltage collecting unit and a clock management unit.
  • the current/voltage acquisition unit is composed of an interconnected signal conditioning circuit and an ADC sampling circuit.
  • FIG. 4 is a schematic structural diagram of the signal conditioning circuit.
  • the signal conditioning circuit comprises a first resistor R1, a second resistor R2, a filter capacitor C and an operational amplifier OP.
  • the input terminal IN of the signal conditioning circuit is connected to the signal acquisition end, and the input terminal IN of the signal conditioning circuit is connected to the first resistor R1.
  • the second end of the first resistor R1 is respectively connected to the first end of the second resistor R2 and the forward input terminal of the operational amplifier OP, the second end of the second resistor R2 is grounded, and the reverse input terminal of the operational amplifier OP Connected to the reference voltage terminal V, the output terminal OUT of the operational amplifier is connected to the ADC sampling circuit; the input terminal IN of the signal conditioning circuit is also grounded via the filter capacitor C.
  • the signal acquisition end of the signal conditioning circuit is a voltage signal acquisition end or a current signal acquisition end, and collects data such as network voltage, network flow, and inverter current on the train.
  • the first resistor R1 and the second resistor R2 are low-power, large-resistance precision resistors; when the input end of the signal conditioning circuit is connected to the current signal collecting end,
  • the first resistor R1 is a high power, low resistance current limiting resistor
  • the second resistor R2 is a high power, low resistance sampling resistor.
  • the amplification factor of the proportional op amp circuit is flexibly designed by configuring the resistors R3, R4 and R5 to achieve the purpose of measuring the input current or voltage of any size.
  • the signal conditioning circuit collects a current signal or a voltage signal, and the sampling signal is subjected to analog-to-digital conversion by an ADC sampling circuit, and the converted data is transmitted to the signal sampling board.
  • the signal sampling board sends the data to the fast computing board via LinkPort for data processing, and the fast computing board passes the processed data to the signal sampling board via LinkPort.
  • FIG. 5 shows the schematic of the LinkPort communication.
  • LinkPort communication needs to execute the chip unit to collect and transmit data on both the rising and falling edges of the clock.
  • the data collected and transmitted each time is a 4-bit differential signal.
  • the principle of transmitting and receiving the LinkPort of the signal sampling board of the invention is that the signal sampling board performs data transceiving processing on both the rising edge and the falling edge of the clock.
  • FIG. 6 and Figure 7 show the LinkPort receiving data flow chart of the signal sampling board and the LinkPort transmission data flow chart of the signal sampling board.
  • the FPGA inside the signal sampling board completes data transmission and reception, and the DSP on the fast computing board is a unit for data interaction and data operation with the FPGA.
  • the FPGA comes with dual-port RAM, and the FPGA sends data to the DSP via LinkPort.
  • the data storage line of the dual-port RAM is used as the FPGA data processing module, and the data waiting data line is used as the LinkPort communication module.
  • the FPGA is connected via LinkPort.
  • the DSP sends the data flow as:
  • the FPGA sends the sampling signal received from the ADC sampling circuit to the data storage data line of the dual port RAM, that is, the FPGA data processing module;
  • the FPGA converts the encapsulated data into a single-ended signal to a differential signal
  • the FPGA gives a data transmission signal on the rising and falling edges of the clock, and sends the converted data to the DSP.
  • the data storage line of the dual port RAM is used as the LinkPort communication module, and the data line to be taken is taken as the FPGA data processing module.
  • the process of receiving the data from the DSP via the LinkPort is:
  • the FPGA receives the data sent by the DSP on the rising and falling edges of the clock
  • the FPGA performs differential signal to single-ended signal conversion on the received data
  • the FPGA performs data analysis on the converted data, and parses the data of the four-bit package into unit data;
  • the FPGA sends the parsed data to the data storage data line of the dual port RAM, that is, the LinkPort communication module;
  • the FPGA will take the data from the dual-port RAM data line, that is, the FPGA data processing module, and participate in the application.
  • the pulse interface board mainly realizes the function of signal switching in the traction control system, and the inverter/four-quadrant power module for receiving the traction converter emits an IGBT status signal, and the receiving signal sampling board is connected to the inverter of the traction converter.
  • the signal sampling board After receiving the operation control signal of the fast calculation board, the signal sampling board is transmitted to the pulse interface board, and the pulse interface board receives The electrical signal is obtained.
  • the pulse interface board In order to avoid the interference of the strong electric power and the surrounding electromagnetic environment to the IGBT drive signal, the pulse interface board is designed as a photoelectric conversion board. As shown in Figure 8, the structure of the pulse interface board is:
  • the utility model comprises a PWM level conversion circuit, a photoelectric conversion unit, an electro-optical conversion unit and a backplane interface unit, the PWM level conversion circuit is connected with the backplane interface unit, and further comprises a self-diagnosis unit, wherein the self-diagnosis unit comprises an input diagnosis unit and an output diagnosis unit
  • the drawing shown in FIG. 1 of the present embodiment is a set of photoelectric conversion units and a set of electro-optical conversion units. Due to the expandability of the backplane interface unit, the photoelectric conversion unit and the electro-optic conversion unit have multiple groups.
  • the photoelectric conversion unit includes a multiplexer 10, a buffer, and a photoelectric conversion circuit 3.
  • the backplane interface unit is connected to the multiplexer 10 via the buffer D1, and the multiplexer 10 is connected to the photoelectric conversion circuit 3 via the buffer D2.
  • the output end of the photoelectric conversion circuit is connected to the driving module of the traction control unit of the train;
  • the electro-optical conversion unit comprises a multiplexer 2, a buffer and an electro-optical conversion circuit 4, an input end of the electro-optical conversion circuit 4 and a driving module of the train traction control unit Connected, the output of the electro-optical conversion circuit 4 is connected to the multiplexer 2 via the buffer D3, and the multiplexer 2 is connected to the backplane interface unit via the buffer D4;
  • the output diagnostic unit includes a multiplexer and an output self-diagnostic circuit
  • the output end of the buffer D2 of each group of photoelectric conversion units is connected to the input end of the multiplexer 6 outputted from the diagnostic unit, and the input end of the output self-diagnosis circuit is connected to the output end of the buffer D2, and the multiplexer
  • the output end is connected to the backplane interface unit;
  • the input diagnostic unit includes a multiplexer 1 and an input self-diagnostic circuit, and the input end of the multiplexer 1 and the backplane interface unit Even, division multiple output terminals respectively connected to an input of the electro-optical conversion units each damper D3.
  • Fig. 10 and Fig. 11 are schematic diagrams showing the structure of the input self-diagnosis circuit and the output diagnostic circuit, respectively.
  • the input self-diagnosis circuit includes an input end and a test signal end, and the test signal end receives the test signal from the multiplexer 1, the input end is connected to the output end of the electro-optical conversion module, and the test signal and the input end are two signals. After the XOR gate 5, it is used as an input to the buffer D3.
  • Each electro-optical conversion unit has an independent input self-diagnosis circuit, and its test signal terminals are connected to the multiplexer 1.
  • the output signal end of the output self-diagnosis circuit is connected to the output end of the buffer D2, and the output end of the buffer D2 of each photoelectric conversion unit is connected with an independent output diagnostic circuit, and each output diagnostic circuit is The output is connected to the multiplexer 6.
  • a power output circuit is designed in the pulse interface board for convenience.
  • the input end of the power output unit 7 is connected to the backplane interface unit, the input voltage is from the backplane power supply voltage, and the output end is connected to the traction drive unit.
  • the power output circuit in this embodiment is outputted by 4 channels, and can output 15V voltage for use by the traction drive unit.
  • a power detection 9 circuit is also provided to detect the state of the backplane power supply.
  • the pulse interface board further includes a remote control unit 8, the output of which is connected to the enable terminals of the multiplexer on the photoelectric conversion unit and the electro-optical conversion unit, respectively.
  • FIG. 2 is a schematic structural diagram of an embodiment of a remote control unit 8 including a remote input terminal and an enable end of the multiplexer in the diagram of the output end of the board and the output end of the board. Even, the multiplexer is enabled low. You can choose whether to perform remote control as needed.
  • the resistor R1 When the remote control unit 8 is needed, the resistor R1 is not connected to the circuit, and a 24V voltage optocoupler is applied between the remote input terminals IN+ and IN-, the circuit is turned on, and the remote input terminal and the card output terminal are connected by optocoupler, the optocoupler The emitter is connected to the ground, the photocoupler collector is connected to the power supply via the resistor R2, and the R2 output terminal is the ENABLE terminal, and the output is low level, thereby realizing the function of remotely controlling the operation of the photoelectric board.
  • the remote control unit 8 When the remote control unit 8 is not required to operate, the voltage input between the remote input terminals IN+ and IN- is cut off, and the card output terminal of the remote control unit operates. Connect R1 to the circuit, the R1 input terminal is connected to R2, the output terminal is grounded, and the ENABLE terminal is fixed to output low level.
  • the status indication circuit can also be configured as needed to visually reflect the working status of the board.
  • the status indicating unit includes an output status indicating unit and an input status indicating unit. The input end of the output status indicating unit is connected to the input end of the photoelectric conversion circuit; and the input end of the input status indicating circuit is connected to the output end of the electro-optical conversion circuit.
  • the status indicating unit is composed of multiple LED lights, and each LED light is connected to the output of the corresponding multiplexer.
  • the backplane interface unit receives the electrical signal of the signal sampling board, converts the 3.3V TTL signal into a 5V TTL signal through a PWM level conversion circuit, and transmits the signal to the photoelectric conversion circuit, and converts the electrical signal into an optical signal and transmits the optical signal to the train traction driving unit through the optical fiber. .
  • the electrical signal of the traction drive unit is converted by the electro-optical conversion unit to the electrical signal and fed back to the signal sampling board.
  • the path of the signal is selected by the multiplexer 10 and the multiplexer 2, and the multiplexer 6 and the multiplexer 10 are selected to perform self-diagnosis on a certain photoelectric conversion unit or electro-optical conversion unit.
  • the mainframe of the EMU traction control system uses a high-strength reinforced chassis.
  • the reinforced panels on the chassis panels on both sides provide better stability, shock and impact resistance than traditional standard chassis.
  • the double-assisted puller is provided at the connection between the various boards of the EMU traction control system and the main box board card slot.
  • the structure of the double-assisted puller is shown in Figure 12.
  • the double puller is mainly composed of a substrate 11, a pin 12, and a flip plate 13.
  • the upper portion of the substrate 11 is connected to the pulling plate 13, and the pulling plate 12 is an L-shaped plate.
  • the lower left portion of the L-shaped plate is hinged with the substrate 11 at the hinge portion and is rotatable at an angle along the hinge portion.
  • the base plate 11 is provided with a clamping plate 13 for positioning a card slot, and the positioning card slot is matched with a lower portion of the L-shaped plate.
  • a double row of pins 12 are fixed to the lower portion of the substrate 11, and the pins 12 are for connecting to the card slot.
  • a bolt hole fixed to the card is further provided on one side of the substrate 11.
  • the network card receives the digital and analog signals in the I/O module through the CAN bus, and exchanges information with the processor host through the CPCI bus. Since the MVB network card is installed on the network board of the EMU traction control system, the MVB board communicates with the network board through the ISA bus, and the network board and the processor host are connected by Compact PCI. Two-way communication is performed using the CPCI bus. In order to solve the problem that the CPCI bus on the CPU and the ISA bus on the MVB device cannot communicate directly in the prior art, a protocol converter of the CPCI bus and the ISA bus is designed.
  • the protocol converter is mainly composed of four modules, which are CPCI local bus interface extended timing module, ISA bus interface timing module, CPCI bus matching ISA bus timing interface module and clock management module.
  • the CPCI local bus interface extended timing module mainly completes the configuration of the access space IO/MEMORY of the CPCI bus, the read/write access control of the CPCI bus, the address decoding and the command decoding.
  • the interface between the local CPCI bus and the CPCI local bus interface extended timing module is shown in FIG.
  • the main signals between the two include: address and data signals AD[31:0], command/byte enable signals C/BE[3:0], slave ready signal TRDY, stop data transfer signal STOP, frame
  • the periodic signal FRAME and the master device are ready for the signal IRDY.
  • the MVB device directly communicating with the CPCI bus simply does not react, the data packet The loss is serious.
  • the wait signal S_WAIT is inserted in the CPCI bus read/write operation, and the slave device ready signal TRDY is controlled on the CPCI bus; when the CPCI bus is accessed in the MEMROY mode, the CPCI bus is read/written on the CPCI bus.
  • the stop data transfer signal STOP is inserted.
  • the CPCI bus Before the MEMROY device is not completed, the CPCI bus is always interrupted and reconnected. The CPCI bus always requests the current read/write operation until the current operation does not insert a stop.
  • the data transfer signal STOP the CPCI bus will initiate the next read/write access.
  • the stop data transfer signal STOP is issued by the slave device, and when the stop data transfer signal STOP is valid, it indicates that the slave device requests the master device to terminate the current data transfer.
  • 14 is a specific timing chart of the slave device ready signal TRDY, the stop data transfer signal STOP, the frame period signal FRAME, and the master ready signal IRDY.
  • the interface between the CPCI local bus interface extended timing module and the ISA bus interface timing module is shown in Figure 13.
  • the main signals between the two include the data enable signal S_DATA_VLD, the address enable signal ADDR_VLD, the read enable signal barx_rd, the write enable signal barx_wr, the byte enable signal S_CBE, the data signal D[31:0], and the address signal. A[31:0].
  • the operation command of the CPCI bus is identified by the IP CORE module of XILINX Corporation, and the read/write enable signal S_WRDN, the address enable signal ADDR_VLD, the data enable signal S_DATA_VLD, the byte enable signal S_CBE, and the spatial decode signal BASE_HIT are generated.
  • the intermediate data buffer BUFFER needs to be established, that is, when the write operation of the CPCI bus is about to occur, the CPCI bus data is written to the data buffer BUFFER. Then pass to the ISA bus; when the read operation of the CPCI bus is about to occur, the ISA bus data is first transmitted to the data buffer BUFFER, and then transmitted to the CPCI bus.
  • the read enable signal barx_rd and the write enable signal barx_wr are obtained in the following manner: due to the ISAB-based MVB device in the current traction controller, the ISA bus supported by different manufacturers' MVB communication devices operates differently, which may be IO device, MEMROY device or both, the CPCI bus access space should be configured according to actual needs, and then the chip signal of the MVB device is determined according to the address signal and address enable signal ADDR_VLD provided by the CPCI bus.
  • the /write enable signal S_WRDN and the spatial decode signal BASE_HIT determine the space IO/MEMORY of this operation, and finally obtain the actually used read enable signal barx_rd and write enable signal barx_wr.
  • x represents a selected space, and the value is 0, 1, or 2
  • the write enable signal barx_wr x represents a selected space, and the value is 0, 1, or 2.
  • the interface between the CPCI bus matching ISA bus timing interface module and the CPCI local bus interface extended timing module is shown in FIG.
  • the main signal between the two is to interrupt the reconnection signal USER_STOP.
  • This signal is mainly used to interrupt the stop data transmission signal STOP.
  • the CPCI bus device initiates access to the ISA bus device. When accessed in MEMORY mode, the CPCI bus matches the ISA.
  • the bus timing interface module interrupts the reconnection signal USER_STOP in real time to interrupt the stop data transfer signal STOP, so that the ISA bus device has sufficient time to complete the read/write access and solve the CPCI bus and ISA bus read/write operation speed. Inconsistent issues.
  • the interface between the ISA bus interface timing module and the local ISA bus is shown in Figure 13.
  • the main signals between the two include: data signal SD, address signal SA, read/write IO device signal IOW/IOR, read/write MEMORY device signal MEMR/MEMW, address latch signal BALE.
  • the clock management module provides an operating clock for the CPCI local bus interface extended timing module, the ISA bus interface timing module, and the CPCI bus matching ISA bus timing interface module by using the FPGA internal clock network and the phase locked loop.
  • Figure 15 is a partial timing diagram of the protocol converter IO read access.
  • Figure 16 is a flow chart of the protocol converter access.
  • the process of real-time access of the master CPU device to the MVB device of the ISA bus interface through the CPCI bus is:
  • the EMU traction control system is the core component of the traction converter. It mainly controls all I/O control, analog pulse quantity acquisition, converter control, four-quadrant control, pulse interface control, network communication control and Logical scheduling control, etc.
  • the function module of the EMU traction control system or the control software of the board has relative independence, and there is a strict signal interface definition between the module or the board.
  • the data exchange through the standard bus ensures the data is valid in real time.
  • the software architecture of the EMU traction control system is shown in Figure 17.
  • the logic scheduling software, the converter control software, the four-quadrant control software, the signal acquisition/PWM generation software, and the pulse interface control software are self-detected; and the communication between the MVB network and the logic scheduling control software is completed through the network communication control software;
  • the four-quadrant pulse interface board, the four-quadrant signal sampling board and the four-quadrant fast calculation board and communication with other modules are completed by the four-quadrant control software;
  • the inverter pulse interface board and the inverter are completed by the inverter control software. Communication between the signal sampling board and the inverter's fast computing board and between other modules.
  • step 3 Check if the network communication is successful, if the network communication is unsuccessful, return to step 3); if the network communication is successful, start the four-quadrant control software;
  • step 6 Check if the inverter control program is started successfully. If the inverter control program is not started successfully, start the inverter protection program, record the fault and display the error; if the inverter control program starts successfully, return to step 5).
  • the EMU traction control system can achieve the following functions:
  • the invention adopts the current mainstream control chip and advanced system architecture, and meets the functional requirements of the existing EMU and high-speed rail for the traction control system.
  • the processor host of the invention adopts the mainstream Intel Atom series processor, and the main frequency reaches 1.3 to 1.6 GHz; the control algorithm processor adopts ADI TS203S, and the main frequency is 250 MHz. Selecting the current mainstream processor chip can greatly improve system performance.
  • CPCI/CAN bus technology embedded real-time operating system (QNX) and DSP technology, on the basis of absorbing the advanced design concept of the EMU (self-test, self-diagnosis, real-time self-monitoring, etc.), the EMUs are summarized.

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Abstract

公开了一种动车组列车的牵引控制系统，该动车组牵引控制系统的处理器主机通过CPCI总线连接下位机板卡，包括快速运算板、网络模块和调试模块，通过CPCI总线将指令传递给下位机板卡，同时下位机板卡通过CPCI总线将状态信息传递给处理器主机，实现动车组牵引控制系统内部的总体控制。信号采样板与快速运算板通过高速差分LinkPort总线进行双向通讯，实现对逆变器功率模块和四象限功率模块的快速控制，网络板卡通过CAN总线与I/O模块的各板卡进行双向通讯，并将I/O模块的各板卡发出的数字量和模拟量信号经CPCI总线传递给处理器主机，保证动车组牵引控制系统信息传输的稳定性和可靠性。

Description

动车组牵引控制系统 技术领域
本发明涉及铁路电子领域，具体的说，涉及动车组列车的牵引控制系统。
背景技术
动车组牵引控制系统是动车组列车的核心动力控制器。动车组牵引控制系统控制四象限整流器、制动斩波器、牵引逆变器的IGBT开关，以获得满足车辆牵引/制动性能要求的控制。
当前动车组牵引控制系统的主电路结构图见图1。单相高压电由受电弓接收，经过变压器二次侧输出到四象限单元整流，整流后的高压直流电经过中间直流母线输出到逆变器功率模块。经逆变器功率模块逆变后输出到牵引电机，控制牵引电机运行。
现行动车组牵引传动系统控制单元都采用32位处理器主机，西门子采用AMD公司的ElanSC520，主频133MHz；庞巴迪采用Freescale公司MC68360，主频25MHz；ALSTOM采用ST公司的STPC,主频133MHz；株洲所采用MPC5200D,主频533MHz。
控制算法处理器的选择方面，西门子采用了DSP56002，主频100MHz；庞巴迪公司采用了DSP56302，主频100MHz；阿尔斯通公司采用了ADI 21062，主频160MHz；株洲所公司采用了TMS320C6713，主频200MHz。
目前各公司使用的处理器芯片都是相对早期产品，芯片型号较老，系统响应较慢，很多芯片已经停产，且由于芯片停产导致其生产成本较高。
发明内容
本发明的目的是提供一种动车组列车的牵引控制系统，可同时实现2组四象限功率模块和2组逆变器功率模块控制。
本发明的技术方案是：动车组牵引控制系统用于控制动车组牵引变流器的逆变器/四象限功率模块工作，主要包括电源模块、逆变/四象限模块、I/O模块、网络模块和调试模块。
所述逆变器/四象限模块主要由快速运算板、信号采样板和脉冲接口板组成。
所述信号采样板主要用于接收外部传感器信号、接收所述脉冲接口板发送的脉冲反馈信号和接收所述快速运算板发送的控制信号，以及向所述脉冲接口板发送脉冲信号、向所述快速运算板发送处理后的采集信号和向所述I/O模块发送继电器控制信号。
所述快速运算板主要用于接收所述信号采样板采集并处理的模拟量和数字量信号、接收所述处理器主机发出的控制信号，以及向所述信号采样板发送控制信号、向所述网络模块发 送处理信号。
牵引控制单元通过脉冲接口板可控制2组逆变器功率模块和2组四象限功率模块；
所述脉冲接口板主要用于接收所述逆变器/四象限功率模块发出IGBT状态信号，接收所述信号采样板发出的IGBT控制信号；以及向所述信号采样板发送IGBT状态信号，向所述逆变器/四象限功率模块发出IGBT控制信号。
所述信号采样板与所述快速运算板通过高速差分LinkPort总线进行双向通讯；
所述信号采样板与所述I/O模块通过高速总线进行双向通讯；
所述快速运算板、所述网络模块、所述调试模块和所述处理器主机之间通过CPCI总线进行双向通讯；
所述I/O模块与所述逆变器/四象限模块通过高速总线进行双向通讯；
所述I/O模块与所述网络模块和所述调试模块通过CAN总线进行双向通讯。
所述网络模块由网络板卡构成，所述网络模块接收I/O模块发来的数字量和模拟量信号，并经CPCI总线传递给处理器主机，以及通过CPCI总线接收处理器主机的命令信号，并向所述I/O模块发送命令，控制所述I/O模块输出数字量和模拟量信号，以及控制MVB接口单元与外部MVB总线进行数据交互；同时通过CPCI总线发送MVB数据发送至处理器主机，以及通过CPCI总线将处理器主机需要发送的数据发送至MVB接口单元。
所述调试模块由调试板卡构成，所述调试模块通过CPCI总线接收处理器主机发送的调试命令和调试信号，所述的调试模块通过高速总线接收信号采样板发送的调试信号，所述调试模块通过32路模拟量输出电路输出模拟量调试信号。
所述电源模块为所述逆变/四象限模块、所述I/O模块、所述网络模块和所述调试模块供电，同时所述的电源模块为逆变/四象限功率模块供电，同时所述的电源模块为牵引变流器内部传感器供电。
更进一步的：由于传感器采集的信号有电流量也有电压量，信号采样板包括电流/电压采集单元和时钟管理单元，电流/电压采集单元由相互连接的信号调理电路、ADC采样电路构成；
所述电流/电压采集单元有多路，均连接到信号采样板，时钟管理单元分别与信号采样板和快速运算版相连，所述信号调理电路包括第一电阻，第二电阻、滤波电容和运算放大器，信号调理电路的输入端连接到采样传感器端，信号调理电路的输入端连接到第一电阻的第一端，第一电阻的第二端分别连接到第二电阻的第一端和运算放大器的正向输入端，第二电阻的第二端接地，运算放大器的反向输入端与参考电压端相连，运算放大器的输出端连接到ADC采样电路；信号调理电路的输入端还经滤波电容接地。
更进一步的：脉冲接口板可以实现光电转换功能，脉冲接口板包括PWM电平转换电路、光电转换单元、电光转换单元和背板接口单元，PWM电平转换电路经背板接口单元与信号采样板相接，还包括自诊断单元；
所述自诊断单元包括输入诊断单元和输出诊断单元；
所述光电转换单元和电光转换单元均有多组，所述光电转换单元包括多路选择器、缓冲器和光电转换电路，背板接口单元经缓冲器I与多路选择器相连，多路选择器经缓冲器II与光电转换电路相连；所述电光转换单元包括多路选择器、缓冲器和电光转换电路，电光转换电路经缓冲器III与多路选择器相连，多路选择器经缓冲器IV与背板接口单元相连；
所述输出诊断单元包括多路选择器和输出自诊断电路，每组光电转换单元的缓冲器II的输出端与输出自诊断单元的多路选择器的输入端相连，输出自诊断电路的输入端与缓冲器II2的输出端相连，多路选择器的输出端与背板接口单元相连；所述输入诊断单元包括多路选择器和输入自诊断电路，多路选择器的输入端与背板接口单元相连，输出端分多路，分别连接到每组电光转换单元缓冲器III的输入端。
为实现处理器主机CPU设备和控制板上的MVB设备通过ISA总线接口进行直接通讯，在所述网络模块与处理器主机之间设计一种CPCI总线和ISA总线的协议转换器进行双向通讯，该协议转换器包括CPCI局部总线接口扩展时序模块、ISA总线接口时序模块、CPCI总线匹配ISA总线时序接口模块和时钟管理模块；所述CPCI局部总线接口扩展时序模块通过地址与数据信号AD【31:0】、命令/字节使能信号C/BE【3:0】、从设备准备好信号TRDY、停止数据传送信号STOP、帧周期信号FRAME和主设备准备好信号IRDY与局部CPCI总线进行通讯；所述ISA总线接口时序模块通过数据使能信号S_DATA_VLD、地址使能信号ADDR_VLD、读使能信号barx_rd、写使能信号barx_wr、字节使能信号S_CBE、数据信号D【31:0】和地址信号A【31:0】与所述CPCI局部总线接口扩展时序模块进行通讯；所述ISA总线接口时序模块通过数据信号SD、地址信号SA、读/写IO设备信号IOW/IOR、读/写MEMORY设备信号MEMR/MEMW、地址锁存信号BALE与局部ISA总线进行通讯；所述CPCI总线匹配ISA总线时序接口模块通过打断重连信号USER_STOP与所述CPCI局部总线接口扩展时序模块进行通讯；所述时钟管理模块为所述CPCI局部总线接口扩展时序模块、所述ISA总线接口时序模块和所述CPCI总线匹配ISA总线时序接口模块提供工作时钟。
与标准牵引控制机箱相比，所述动车组牵引控制系统的主机箱采用高强度加固机箱，该加固机箱的两侧机箱面板采用加固面板。
所述动车组牵引控制系统的各类板卡与主机箱板卡卡槽连接处均设有双助拔器，所述双 助拔器主要由基板、插针和扳动板组成，所述基板上部连接所述扳动板，所述扳动板为L型板，L型板的左下部与所述基板在铰接部铰接，并可沿铰接部呈一定角度旋转，所述基板上设有扳动板定位卡槽，定位卡槽与L型板的下部相匹配，所述基板下部固定双排插针，所述插针用于与板卡卡槽相连接，所述基板一侧还设有与板卡固定的螺栓孔。
本发明与现有技术相比的有益效果为：
(1)该动车组牵引控制系统的处理器主机通过CPCI总线连接下位机板卡，包括快速运算板、网络模块和调试模块，通过CPCI总线将指令传递给下位机板卡，同时下位机板卡通过CPCI总线将状态信息传递给处理器主机，实现动车组牵引控制系统内部的总体控制；
(2)信号采样板与快速运算板通过高速差分LinkPort总线进行双向通讯，实现对逆变器功率模块和四象限功率模块的快速控制；
(3)网络板卡通过CAN总线与I/O模块的各板卡进行双向通讯，并将I/O模块的各板卡发出的数字量和模拟量信号经CPCI总线传递给处理器主机，保证动车组牵引控制系统信息传输的稳定性和可靠性；
(4)常用的数据通信协议是CAN等，这些协议与LinkPort相比，数据采集及传输速率低。本发明的实现了信号采样板和快速运算板之间的LinkPort传输，LinkPort是一种LVDS(Low Voltage Differential Signal)即低电压差分信号，具有高速、超低功耗、低噪声和低成本的优良特性。通过LinkPort进行数据传输，较大程度上提高了数据传输速度，数据传输速度可达到400Mbit/s。可实现牵引控制单元的快速控制；
(5)动车组牵引控制系统采用主流控制芯片和先进的设计思路，采用QNX嵌入式实时操作系统。本操作系统资源占用率低，专业性强，适合特殊领域应用，系统精简，安全等级高，实时性高，代码执行效率高，支持多任务。
(6)对动车组牵引控制系统的机箱结构进行了改进。动车组牵引控制系统的主机箱采用高强度加固机箱，各类板卡与主机箱板卡卡槽连接处均设有双助拔器，结构更稳定
附图说明
图1为当前动车组牵引控制系统的主电路结构图；
图2为本发明动车组牵引控制系统的结构示意图；
图3为采样板和快速运算板结构示意图；
图4为信号采样板信号调理电路结构示意图；
图5为LinkPort通信原理图；
图6为信号采样板的LinkPort接收数据流程图；
图7为信号采样板的LinkPort发送数据流程图；
图8为脉冲接口板结构示意图；
图9为脉冲接口板远程控制单元电路结构示意图；
图10为脉冲接口板输入自诊断电路结构示意图；
图11为脉冲接口板输出诊断电路结构示意图；
图12为双助拔器的结构示意图；
图13为该协议转换器的结构示意图；
图14为TRDY、STOP、FRAME和IRDY的具体时序图；
图15为该协议转换器IO读访问局部时序图；
图16为该协议转换器访问流程图；
图17动车组牵引控制系统的软件架构；
图18动车组牵引控制系统的流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，均属于本发明的保护范围。
实施例1
动车组牵引控制系统，可同时控制2组四象限功率模块和2组逆变器功率模块。参见图2，动车组牵引控制系统主要包括电源模块、逆变/四象限模块、I/O模块、网络模块和调试模块。
电源模块由多块电源板组成，包括110V转24V电源板、110V转5V电源板、110V转3.3v电源板和110V转15V电源板。电源模块的主要功能是为逆变/四象限模块、I/O模块、网络模块和调试模块供电，同时为逆变/四象限功率模块供电，为牵引变流器内部传感器供电。
I/O模块提供对外的I/O控制，主要用于状态采集和控制输出。I/O模块主要包括数字量输入板卡、数字量输出板卡和模拟量输入输出板卡。I/O模块与逆变器/四象限模块通过高速总线进行双向通讯，I/O模块与网络模块和调试模块通过CAN总线进行双向通讯。
逆变器/四象限模块的功能是实现牵引变流器的控制和四象限的控制，主要由快速运算 板、信号采样板和脉冲接口板组成。快速运算板分为逆变器快速运算板和四象限快速运算板；信号采样板分为逆变器信号采样板和四象限信号采样板；脉冲接口板分为逆变器脉冲接口板和四象限脉冲接口板。
逆变器信号采样板主要用于接收外部传感器信号、接收逆变器脉冲接口板发送的脉冲反馈信号和接收逆变器快速运算板发送的控制信号，以及向逆变器脉冲接口板发送脉冲信号、向逆变器快速运算板发送处理后的采集信号和向I/O模块发送继电器控制信号。
逆变器快速运算板主要用于接收逆变器信号采样板采集并处理的模拟量和数字量信号、接收处理器主机发出的控制信号，以及向逆变器信号采样板发送控制信号、向网络模块发送处理信息。
逆变器脉冲接口板最多与2组逆变器功率模块相连；
逆变器脉冲接口板主要用于接收逆变器功率模块发出IGBT状态信号，接收逆变器信号采样板发出的IGBT控制信号；以及向逆变器信号采样板发送IGBT状态信号，向逆变器功率模块发出IGBT控制信号。
逆变器信号采样板与逆变器快速运算板通过高速差分LinkPort总线进行双向通讯；逆变器信号采样板与I/O模块通过高速总线进行双向通讯；逆变器快速运算板与网络模块和调试模块通过CPCI总线进行双向通讯。
四象限信号采样板主要用于接收外部传感器信号、接收四象限脉冲接口板发送的脉冲反馈信号和接收四象限快速运算板发送的控制信号，以及向四象限脉冲接口板发送脉冲信号、向四象限快速运算板发送处理后的采集信号和向I/O模块发送继电器控制信号。
四象限快速运算板主要用于接收四象限信号采样板采集并处理的模拟量和数字量信号、接收处理器主机发出的控制信号，以及向四象限信号采样板发送控制信号、向网络模块发送处理信息。
四象限脉冲接口板最多与2组四象限功率模块相连；
四象限脉冲接口板主要用于接收四象限功率模块发出IGBT状态信号，接收四象限信号采样板发出的IGBT控制信号；以及向四象限信号采样板发送IGBT状态信号，向四象限功率模块发出IGBT控制信号。
四象限信号采样板与四象限快速运算板通过高速差分LinkPort总线进行双向通讯；四象限信号采样板与I/O模块通过高速总线进行双向通讯；四象限快速运算板与网络模块和调试模块通过CPCI总线进行双向通讯。
网络模块由网络板卡构成，网络模块接收I/O模块发来的数字量和模拟量信号，并经CPCI总线传递给处理器主机，以及通过CPCI总线接收处理器主机的命令信号，并向I/O模块发送命令，控制I/O模块输出数字量和模拟量信号，以及控制MVB接口单元与外部MVB总线进行数据交互；同时通过CPCI总线发送MVB数据发送至处理器主机，以及通过CPCI总线将处理器主机需要发送的数据发送至MVB接口单元。
调试模块主要用于配合网络中其它板卡完成实时调试。调试模块由调试板卡构成，调试模块通过CPCI总线接收处理器主机发送的调试命令和调试信号，调试模块通过高速总线接收信号采样板发送的调试信号，调试模块通过32路模拟量输出电路输出模拟量调试信号。
如图3所示，牵引控制系统的目的是控制变流器内部的IGBT开关来实现交流到直流再到交流的转换。工作时，电路上的传感器采集牵引变流器各电路的电流和电压信号，将信号经由信号采样板反馈到快速运算板，对信号进行分析运算，结合运算结果给出控制信号。由于采样信号包含电流信号和电压信号，本发明设计了电流电压复用采集单元。其中，信号采样板包括电流/电压采集单元和时钟管理单元。电流/电压采集单元由相互连接的信号调理电路和ADC采样电路构成。
电流/电压采集单元有多路，均连接到信号采样板，时钟管理单元分别与信号采样板和快速运算板相连，图4为信号调理电路的结构示意图。信号调理电路包括第一电阻R1，第二电阻R2、滤波电容C和运算放大器OP，信号调理电路的输入端IN连接到信号采集端，信号调理电路的输入端IN连接到第一电阻R1的第一端，第一电阻R1的第二端分别连接到第二电阻R2的第一端和运算放大器OP的正向输入端，第二电阻R2的第二端接地，运算放大器OP的反向输入端与参考电压端V相连，运算放大器的输出端OUT连接到ADC采样电路；信号调理电路的输入端IN还经滤波电容C接地。
信号调理电路的信号采集端为电压信号采集端或电流信号采集端，采集列车上的网压、网流、逆变器电流等数据。当信号调理电路的输入端连接到电压信号采集端，所述第一电阻R1和第二电阻R2均为低功率、大阻值精密电阻；当信号调理电路的输入端连接到电流信号采集端，所述第一电阻R1为高功率、低阻值限流电阻，第二电阻R2为高功率、低阻值采样电阻。最后再经过运算放大器OP，通过配置电阻R3、R4和R5灵活设计比例运放电路的放大系数，达到适用于测量任何大小的输入电流或者电压的目的。
信号调理电路采集电流信号或电压信号，采样信号经ADC采样电路进行模数转换，转换后数据传递到信号采样板。
信号采样板经LinkPort将数据发送到快速运算板进行数据处理，快速运算板经LinkPort将处理后的数据传递到信号采样板端。
图5给出了LinkPort通信原理图。从图5中可以看出，LinkPort通信需要执行芯片单元在时钟上升沿和下降沿均进行数据采集和发送，每次数据采集和发送的数据是4位差分信号。本发明信号采样板发送和接收LinkPort的原理为：使信号采样板在时钟的上升沿和下降沿均进行数据收发处理。
图6和图7分别给出了信号采样板的LinkPort接收数据流程图和信号采样板的LinkPort发送数据流程图。信号采样板内部的FPGA完成数据收发，快速运算板上DSP为与FPGA进行数据交互和数据运算的单元。FPGA自带双口RAM，FPGA经LinkPort向DSP发送数据的过程中，双口RAM的数据存储线作为FPGA数据处理模块，数据待取数据线作为LinkPort通信模块，从图7可见，FPGA经LinkPort向DSP发送数据流程为：
(a)FPGA将从ADC采样电路接收到的采样信号发送到双口RAM的数据存储数据线，即FPGA数据处理模块；
(b)FPGA从双口RAM的数据待取数据线，即LinkPort通信模块中，将相邻单端信号四位为一组进行数据封装；
(c)FPGA将封装后的数据进行单端信号到差分信号的转换；
(d)FPGA在时钟的上升沿和下降沿给出数据发送信号，将转换后的数据发送到DSP。
FPGA经LinkPort从DSP接收数据的过程中，双口RAM的数据存储线作为LinkPort通信模块，数据待取数据线作为FPGA数据处理模块，从图6可见，FPGA经LinkPort从DSP接收数据流程为：
(e)FPGA在时钟的上升沿和下降沿，分别接收DSP发送来的数据；
(f)FPGA对接收到的数据进行差分信号到单端信号转换；
(g)FPGA对转换完成的数据进行数据解析，将四位一组封装的数据解析成单位数据；
(h)FPGA将解析后的数据发送到双口RAM的数据存储数据线，即LinkPort通信模块中；
(i)FPGA将从双口RAM的数据待取数据线，即FPGA数据处理模块中取数，并参与运用。
脉冲接口板在牵引控制系统中主要实现信号转接的作用，用于接收牵引变流器的逆变器/四象限功率模块发出IGBT状态信号，接收信号采样板对牵引变流器的逆变器/四象限功率模块的IGBT控制信号；以及向信号采样板发出牵引变流器的逆变器/四象限功率模块的IGBT状态信号，向牵引变流器的逆变器/四象限功率模块发出IGBT控制信号。
信号采样板接收到快速运算板的运算控制信号后，传递到脉冲接口板，脉冲接口板接收 到的为电信号，为避免强电及周围复杂电磁环境对IGBT驱动信号的干扰，脉冲接口板设计为光电转换板。如图8所示，脉冲接口板的结构为：
包括PWM电平转换电路、光电转换单元、电光转换单元和背板接口单元，PWM电平转换电路与背板接口单元相接，还包括自诊断单元，自诊断单元包括输入诊断单元和输出诊断单元，本实施例的图1给出的附图是一组光电转换单元和一组电光转换单元，由于背板接口单元的可扩展性，光电转换单元和电光转换单元均有多组。光电转换单元包括多路选择器10、缓冲器和光电转换电路3，背板接口单元经缓冲器D1与多路选择器10相连，多路选择器10经缓冲器D2与光电转换电路3相连，光电转换电路的输出端连接到列车的牵引控制单元的驱动模块；电光转换单元包括多路选择器2、缓冲器和电光转换电路4，电光转换电路4的输入端与列车牵引控制单元的驱动模块相连，电光转换电路4的输出端经缓冲器D3与多路选择器2相连，多路选择器2经缓冲器D4与背板接口单元相连；输出诊断单元包括多路选择器和输出自诊断电路，每组光电转换单元的缓冲器D2的输出端与输出自诊断单元的多路选择器6的输入端相连，输出自诊断电路的输入端与缓冲器D2的输出端相连，多路选择器6的输出端与背板接口单元相连；输入诊断单元包括多路选择器1和输入自诊断电路，多路选择器1的输入端与背板接口单元相连，输出端分多路，分别连接到每组电光转换单元缓冲器D3的输入端。
图10和图11分别给出了输入自诊断电路和输出诊断电路的结构示意图。
如图10所示，输入自诊断电路包括输入端和测试信号端，测试信号端接收来自多路选择器1的测试信号，输入端连接电光转换模块的输出端，测试信号与输入端的两个信号经异或门5后，作为缓冲器D3的输入。每路电光转换单元均有独立的输入自诊断电路，其测试信号端均连接到多路选择器1。
如图11所示，输出自诊断电路的输出信号端连接到缓冲器D2的输出端，每一路光电转换单元的缓冲器D2的输出端均连接有独立的输出诊断电路，各路输出诊断电路的输出连接到多路选择器6。
由于列车牵引驱动单元一般需要外部独立供电，为提供方便在脉冲接口板中设计了电源输出电路。电源输出单元7的输入端与背板接口单元相连，其输入电压来自背板供电电压，输出端与牵引驱动单元相连。本实施例中的电源输出电路由4路输出，可输出15V电压，供牵引驱动单元使用。还设置了电源检测9电路，检测背板供电电源的状态。
脉冲接口板还包括远程控制单元8，远程控制单元8的输出端分别与光电转换单元和电光转换单元上的多路选择器的使能端相连。图2给出了远程控制单元8的一种实施方式结构示意图，远程控制电路包括远程输入端和板卡输出端图中ENABLE端与多路选择器的使能端相 连，多路选择器为低电平使能。可根据需要选择是否进行远程控制。当需要远程控制单元8时，电阻R1不接入电路，将远程输入端IN+与IN-之间施加24V电压光耦，电路导通，远程输入端和板卡输出端经光耦连接，光耦发射极与地相接，光耦集电极经电阻R2与电源相接，R2输出端为ENABLE端，输出低电平，实现远程控制光电板卡工作的功能。当不需要远程控制单元8工作时，切断远程输入端IN+与IN-之间的电压输入，远程控制单元的板卡输出端工作。将R1接入电路，R1输入端与R2相接，输出端接地，ENABLE端固定输出低电平。
根据需要还可以配置状态指示电路，直观反映板卡的工作状态。状态指示单元包括输出状态指示单元和输入状态指示单元，输出状态指示单元的输入端与光电转换电路的输入端相连；输入状态指示电路的输入端与电光转换电路的输出端相连。状态指示单元由多路LED灯组成，每路LED灯与对应的多路选择器的输出端相连。
背板接口单元接收信号采样板的电信号，经过PWM电平转换电路将3.3V TTL信号转换为5V TTL信号后传给光电转换电路，将电信号转换为光信号经光纤传输至列车牵引驱动单元。牵引驱动单元的电信号经电光转换单元进行光信号到电信号的转换，反馈到信号采样板。工作中通过多路选择器10和多路选择器2分别选择信号的通路，通过多路选择器6和多路选择器10选择对某一路光电转换单元或电光转换单元进行自诊断。
动车组牵引控制系统的主机箱采用高强度加固机箱。两侧机箱面板采用加固面板，与传统标准机箱相比，加固机箱具有更好的稳定性、抗震和抗冲击性能。
动车组牵引控制系统的各类板卡与主机箱板卡卡槽连接处均设有双助拔器，双助拔器的结构参见图12。
双助拔器主要由基板11、插针12和扳动板13组成。基板11上部连接扳动板13，扳动板12为L型板，L型板的左下部与基板11在铰接部铰接，并可沿铰接部呈一定角度旋转。基板11上设有扳动板13定位卡槽，该定位卡槽与L型板的下部相匹配。基板11下部固定双排插针12，该插针12用于与板卡卡槽相连接。基板11一侧还设有与板卡固定的螺栓孔。当扳动板沿铰接部旋转至与定位卡槽相吻合时，扳动板13底部与板卡卡槽上部相抵，板卡被拔出。
如上网络板卡通过CAN总线接收I/O模块中的数字量和模拟量信号，并通过CPCI总线与处理器主机之间进行信息交互。由于动车组牵引控制系统的网络板卡上安装有MVB网卡，MVB板卡与网络板卡之间通过ISA总线进行通讯，而网络板卡与处理器主机之间通过Compact PCI连接，两者之间采用CPCI总线进行双向通讯。为解决现有技术中CPU上的CPCI总线和MVB设备上的ISA总线无法直接通讯的问题，设计一种CPCI总线和ISA总线的协议转换器。
该协议转换器主要由4个模块组成，分别为CPCI局部总线接口扩展时序模块、ISA总线接口时序模块、CPCI总线匹配ISA总线时序接口模块和时钟管理模块。
CPCI局部总线接口扩展时序模块主要完成对CPCI总线的访问空间IO/MEMORY进行配置、CPCI总线的读写访问控制、地址译码和命令译码。局部CPCI总线与CPCI局部总线接口扩展时序模块之间的接口连接如图13所示。两者之间的主要信号包括：地址与数据信号AD【31:0】、命令/字节使能信号C/BE【3:0】、从设备准备好信号TRDY、停止数据传送信号STOP、帧周期信号FRAME和主设备准备好信号IRDY。
对于停止数据传送信号STOP：由于CPCI总线是高速设备而ISA总线是慢速设备，且CPCI总线的读/写操作时间是很快的，与CPCI总线直接通讯的MVB设备根本反应不过来，数据包丢失严重。当CPCI总线以IO方式访问时，在CPCI总线读/写操作中插入等待信号S_WAIT，对CPCI总线的从设备准备好信号TRDY进行控制；当CPCI总线以MEMROY方式访问时，在CPCI总线读/写操作中插入停止数据传送信号STOP，在MEMROY设备本次操作未完成之前，CPCI总线一直处于被打断重连的状态，CPCI总线一直请求当前的读/写操作，直到当前一次操作中不插入停止数据传送信号STOP，CPCI总线才会发起下一次读/写访问。停止数据传送信号STOP由从设备发出，当停止数据传送信号STOP有效时表示从设备请求主设备终止当前的数据传送。图14为从设备准备好信号TRDY、停止数据传送信号STOP、帧周期信号FRAME和主设备准备好信号IRDY的具体时序图。
CPCI局部总线接口扩展时序模块与ISA总线接口时序模块的接口连接如图13所示。两者之间的主要信号包括数据使能信号S_DATA_VLD、地址使能信号ADDR_VLD、读使能信号barx_rd、写使能信号barx_wr、字节使能信号S_CBE、数据信号D【31:0】和地址信号A【31:0】。
采用XILINX公司的IP CORE模块对CPCI总线的操作命令进行识别，产生读/写使能信号S_WRDN、地址使能信号ADDR_VLD、数据使能信号S_DATA_VLD、字节使能信号S_CBE和空间译码信号BASE_HIT。
对于数据使能信号S_DATA_VLD，由于CPCI总线和ISA总线的读/写速度不一致，需要建立中间数据缓存区BUFFER，即当CPCI总线的写操作即将发生时，将CPCI总线数据写到数据缓存区BUFFER，再传给ISA总线；当CPCI总线的读操作即将发生时，将ISA总线数据先传给数据缓存区BUFFER，再传给CPCI总线。
读使能信号barx_rd和写使能信号barx_wr的获得方式为：由于当前牵引控制器中基于ISA总线的MVB设备，不同厂商的MVB通讯设备支持的ISA总线的操作方式不一样，可为 IO设备、MEMROY设备或两者兼有，应根据实际需求，对CPCI总线访问空间进行配置，再根据CPCI总线提供的地址信号和地址使能信号ADDR_VLD，确定MVB设备的片选信号，进一步结合读/写使能信号S_WRDN和空间译码信号BASE_HIT确定本次操作的空间IO/MEMORY，最终得到实际使用的读使能信号barx_rd和写使能信号barx_wr。其中，读使能信号barx_rd中x代表选择的空间，取值为0、1或2；写使能信号barx_wr中x代表选择的空间，取值为0、1或2。
CPCI总线匹配ISA总线时序接口模块与CPCI局部总线接口扩展时序模块之间的接口连接如图13所示。两者之间的主要信号为打断重连信号USER_STOP，该信号主要用于打断停止数据传送信号STOP，CPCI总线设备发起对ISA总线设备的访问，当以MEMORY方式访问时，CPCI总线匹配ISA总线时序接口模块实时作出打断重连信号USER_STOP来打断停止数据传送信号STOP，以便留给ISA总线设备充裕的时间来完成本次读/写访问，解决CPCI总线和ISA总线读/写操作速度不一致的问题。
ISA总线接口时序模块与局部ISA总线之间的接口连接如图13所示。两者之间的主要信号包括：数据信号SD、地址信号SA、读/写IO设备信号IOW/IOR、读/写MEMORY设备信号MEMR/MEMW、地址锁存信号BALE。
时钟管理模块利用FPGA内部时钟网络和锁相环为CPCI局部总线接口扩展时序模块、ISA总线接口时序模块和CPCI总线匹配ISA总线时序接口模块提供工作时钟。图15为该协议转换器IO读访问局部时序图。
图16为该协议转换器访问流程图。主控CPU设备通过CPCI总线对ISA总线接口的MVB设备的实时访问的过程为：
1)确定CPCI总线访问空间IO/MEMORY，当CPCI总线以MEMROY方式访问插入停止数据传送信号STOP；当CPCI总线以IO方式访问插入等待信号S_WAIT，等待ISA总线设备准备好；
2)利用地址使能信号ADDR_VLD、读使能信号barx_rd、写使能信号barx_wr和字节使能信号S_CBE确定CPCI总线访问ISA总线的实际地址信号SA和访问模式，其中访问模式包括读操作和写操作；
3)作出ISA总线的地址锁存信号BALE；
4)根据字节使能信号S_CBE，判断32位数据中被使能的字节数据，从中间数据缓存区BUFFER中筛选出相应的8位数据或16位数据与MVB设备进行数据交互；
5)根据ISA总线规定的读/写信号脉冲宽度，确定读/写IO设备信号IOW/IOR和读/写 MEMORY设备信号MEMR/MEMW，进而完成主控CPU设备通过CPCI总线对ISA总线接口的MVB设备的实时访问。
动车组牵引控制系统是牵引变流器的核心部件，主要对牵引变流器所有的I/O控制、模拟量脉冲量采集、变流器控制、四象限控制、脉冲接口控制、网络通讯控制和逻辑调度控制等。动车组牵引控制系统的功能模块或板卡的控制软件具有相对独立性，且模块或板卡之间有严格的信号接口定义，通过标准总线进行数据交互，保证数据实时有效。
动车组牵引控制系统的软件架构如图17。通过测试软件完成逻辑调度软件、变流器控制软件、四象限控制软件、信号采集/PWM生成软件、脉冲接口控制软件的自检测；通过网络通讯控制软件完成MVB网络与逻辑调度控制软件的通讯；通过四象限控制软件完成四象限脉冲接口板、四象限信号采样板和四象限快速运算板之间以及与其它模块间的通讯；通过逆变器控制软件完成逆变器脉冲接口板、逆变器信号采样板和逆变器快速运算板之间以及与其它模块间的通讯。
动车组牵引控制系统的运行流程如图18：
1)动车组牵引控制系统初始化；
2)系统初始化是否成功，若系统初始化失败，显示错误；若系统初始化成功，启动系统自检测程序；
3)系统自检测是否成功，若系统自检测不成功，显示错误；若系统自检测成功，启动网络通信控制软件；
4)检测网络通信是否成功，若网络通信不成功，返回步骤3)；若网络通讯成功，启动四象限控制软件；
5)检测四象限控制程序是否启动成功，若四象限控制程序启动不成功，启动四象限保护程序，记录故障并显示错误；若四象限控制程序启动成功，启动逆变器控制程序；
6)检测逆变器控制程序是否启动成功，若逆变器控制程序启动不成功，启动逆变器保护程序，记录故障并显示错误；若逆变器控制程序启动成功，返回步骤5)。
综上，动车组牵引控制系统可实现以下功能：
1)实现2组牵引变流器控制；
2)实现2组四象限控制；
3)实现逻辑控制与保护控制；
4)实现与列车网络系统MVB通讯；
5)实现与列车制动系统的电空制动配合；
6)实现电力牵引和电机制动；
7)实现过分相控制；
8)实现防空转控制；
9)故障记录与诊断维护。
本发明采用了目前主流控制芯片和先进的系统构架，符合现有动车组和高铁对于牵引控制系统的功能需求。本发明处理器主机采用了主流的Intel凌动系列处理器,主频达到1.3～1.6GHz；控制算法处理器采用了ADI TS203S，主频250MHz。选用了现行主流处理器芯片，可以大大提升系统性能。通过对CPCI/CAN总线技术、嵌入式实时操作系统(QNX)和DSP技术的成熟应用，在吸收动车组先进设计理念(自测试、自诊断、实时自监测等)基础上，总结了动车组各个电气系统实际应用中的经验和教训，并有效结合到软硬件设计中，经过完全独立、自主设计，开发了动车组牵引控制系统高端软硬件平台。该平台在动车组网络、牵引、辅助系统，以及城轨地铁等产品中得到考核验证，达到了国内外先进水平。
本领域技术人员可理解图只为一个优选的实施例的示意图，图中的工作流程并不一定是实施本发明所必须的。
最后应说明的是：以上实施例仅用于说明本发明的技术方案，而非对其进行限制，尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (7)

  1. 动车组牵引控制系统，用于控制动车组牵引变流器的逆变器/四象限功率模块工作，该系统主要包括电源模块、逆变/四象限模块、I/O模块、网络模块和调试模块，其特征在于：
    所述逆变器/四象限模块主要由快速运算板、信号采样板和脉冲接口板组成，
    所述信号采样板主要用于接收外部传感器信号、接收所述脉冲接口板发送的脉冲反馈信号和接收所述快速运算板发送的控制信号，以及向所述脉冲接口板发送脉冲信号、向所述快速运算板发送处理后的采集信号和向所述I/O模块发送继电器控制信号；
    所述快速运算板主要用于接收所述信号采样板采集并处理的模拟量和数字量信号、接收所述处理器主机发出的控制信号，以及向所述信号采样板发送控制信号、向所述网络模块发送处理信号；
    脉冲接口板最多与2组逆变器功率模块和2组四象限功率模块相连；
    所述脉冲接口板主要用于接收所述逆变器/四象限功率模块发出IGBT状态信号，接收所述信号采样板发出的IGBT控制信号；以及向所述信号采样板发送IGBT状态信号，向所述逆变器/四象限功率模块发出IGBT控制信号；
    所述信号采样板与所述快速运算板通过高速差分LinkPort总线进行双向通讯；
    所述信号采样板与所述I/O模块通过高速总线进行双向通讯；
    所述快速运算板、所述网络模块、所述调试模块和所述处理器主机之间通过CPCI总线进行双向通讯；
    所述I/O模块与所述逆变器/四象限模块通过高速总线进行双向通讯；
    所述I/O模块与所述网络模块和所述调试模块通过CAN总线进行双向通讯；
    所述网络模块由网络板卡构成，所述网络模块接收I/O模块发来的数字量和模拟量信号，并经CPCI总线传递给处理器主机，以及通过CPCI总线接收处理器主机的命令信号，并向所述I/O模块发送命令，控制所述I/O模块输出数字量和模拟量信号，以及控制MVB接口单元与外部MVB总线进行数据交互；同时通过CPCI总线发送MVB数据发送至处理器主机，以及通过CPCI总线将处理器主机需要发送的数据发送至MVB接口单元；
    所述调试模块由调试板卡构成，所述调试模块通过CPCI总线接收处理器主机发送的调试命令和调试信号，所述调试模块通过高速总线接收信号采样板发送的调试信号；
    所述电源模块为所述逆变/四象限模块、所述I/O模块、所述网络模块和所述调试模块供电。
  2. 根据权利要求1所述的动车组牵引控制系统，其特征在于：所述信号采样板包括电流/电 压采集单元和时钟管理单元，所述电流/电压采集单元包括信号调理电路和与信号调理电路连接的ADC采样电路；所述电流/电压采集单元有多路，均连接到信号采样板，所述信号调理电路包括第一电阻，第二电阻、滤波电容和运算放大器，信号调理电路的输入端连接到采样传感器端，信号调理电路的输入端连接到第一电阻的第一端，第一电阻的第二端分别连接到第二电阻的第一端和运算放大器的正向输入端，第二电阻的第二端接地，运算放大器的反向输入端与参考电压端相连，运算放大器的输出端连接到ADC采样电路；信号调理电路的输入端还经滤波电容接地。
  3. 根据权利要求1所述的动车组牵引控制系统，其特征在于：所述脉冲接口板包括PWM电平转换电路、光电转换单元、电光转换单元和背板接口单元，PWM电平转换电路经背板接口单元与信号采样板相接，还包括自诊断单元；
    所述自诊断单元包括输入诊断单元和输出诊断单元；
    所述光电转换单元包括多路选择器、缓冲器和光电转换电路，背板接口单元经缓冲器D1与多路选择器相连，多路选择器经缓冲器D2与光电转换电路相连；所述电光转换单元包括多路选择器、缓冲器和电光转换电路，电光转换电路经缓冲器D3与多路选择器相连，多路选择器经缓冲器D4与背板接口单元相连；
    所述输出诊断单元包括多路选择器和输出自诊断电路，每组光电转换单元的缓冲器D2的输出端与输出自诊断单元的多路选择器的输入端相连，输出自诊断电路的输入端与缓冲器D2的输出端相连，多路选择器的输出端与背板接口单元相连；所述输入诊断单元包括多路选择器和输入自诊断电路，多路选择器的输入端与背板接口单元相连，输出端分多路，分别连接到每组电光转换单元缓冲器D3的输入端。
  4. 根据权利要求1所述的动车组牵引控制系统，其特征在于：所述网络模块与处理器主机之间通过CPCI总线和ISA总线的协议转换器进行双向通讯，该协议转换器包括CPCI局部总线接口扩展时序模块、ISA总线接口时序模块、CPCI总线匹配ISA总线时序接口模块和时钟管理模块；
    所述CPCI局部总线接口扩展时序模块通过地址与数据信号AD【31:0】、命令/字节使能信号C/BE【3:0】、从设备准备好信号TRDY、停止数据传送信号STOP、帧周期信号FRAME和主设备准备好信号IRDY与局部CPCI总线进行通讯；
    所述ISA总线接口时序模块通过数据使能信号S_DATA_VLD、地址使能信号ADDR_VLD、读使能信号barx_rd、写使能信号barx_wr、字节使能信号S_CBE、数据信号D 【31:0】和地址信号A【31:0】与所述CPCI局部总线接口扩展时序模块进行通讯；
    所述ISA总线接口时序模块通过数据信号SD、地址信号SA、读/写IO设备信号IOW/IOR、读/写MEMORY设备信号MEMR/MEMW、地址锁存信号BALE与局部ISA总线进行通讯；
    所述CPCI总线匹配ISA总线时序接口模块通过打断重连信号USER_STOP与所述CPCI局部总线接口扩展时序模块进行通讯；
    所述时钟管理模块为所述CPCI局部总线接口扩展时序模块、所述ISA总线接口时序模块和所述CPCI总线匹配ISA总线时序接口模块提供工作时钟。
  5. 根据权利要求1所述的动车组牵引控制系统，其特征在于：所述I/O模块主要包括数字量输入板卡、数字量输出板卡和模拟量输入输出板卡。
  6. 根据权利要求1所述的动车组牵引控制系统，其特征在于：所述动车组牵引控制系统的主机箱采用高强度加固机箱，该加固机箱的两侧机箱面板采用加固面板。
  7. 根据权利要求1所述的动车组牵引控制系统，其特征在于：所述动车组牵引控制系统的各类板卡与主机箱板卡卡槽连接处均设有双助拔器，所述双助拔器主要由基板、插针和扳动板组成，所述基板上部连接所述扳动板，所述扳动板为L型板，L型板的左下部与所述基板在铰接部铰接，并可沿铰接部呈一定角度旋转，所述基板上设有扳动板定位卡槽，定位卡槽与L型板的下部相匹配，所述基板下部固定双排插针，所述插针用于与板卡卡槽相连接，所述基板一侧还设有与板卡固定的螺栓孔。
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