WO2016123931A1 - 薄膜晶体管及其制造方法、显示基板和显示装置 - Google Patents

薄膜晶体管及其制造方法、显示基板和显示装置 Download PDF

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Publication number
WO2016123931A1
WO2016123931A1 PCT/CN2015/085281 CN2015085281W WO2016123931A1 WO 2016123931 A1 WO2016123931 A1 WO 2016123931A1 CN 2015085281 W CN2015085281 W CN 2015085281W WO 2016123931 A1 WO2016123931 A1 WO 2016123931A1
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Prior art keywords
channel region
gate insulating
insulating layer
thin film
film transistor
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PCT/CN2015/085281
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English (en)
French (fr)
Inventor
赵娜
许徐飞
史高飞
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US14/913,160 priority Critical patent/US10043916B2/en
Priority to EP15832664.5A priority patent/EP3076437B1/en
Publication of WO2016123931A1 publication Critical patent/WO2016123931A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators

Definitions

  • the embodiments of the present invention generally relate to the field of display technology, and in particular, to a thin film transistor having a channel structure with an increased aspect ratio and a manufacturing method thereof, as well as a display substrate and a display device.
  • TFT LCD liquid crystal display
  • TFT LCD realizes the adjustment of the brightness of each sub-pixel by controlling the voltage on each of the sub-pixels arranged in a matrix, thereby completing a complete and accurate display screen.
  • the gate on a certain row in the matrix is applied with the turn-on voltage Von and the TFT device is turned on, the source and drain on both sides of the TFT channel are turned on, and a given signal is added to the sub-pixel electrode from the data line.
  • the voltage difference between the sub-pixel electrode and the common electrode determines the deflection of the liquid crystal molecules on the sub-pixel area, and ultimately affects the brightness and display effect of the sub-pixel.
  • the improvement of LCD display picture quality has become one of the competition focuses of LCD products.
  • the size of the turn-on voltage directly determines the picture quality, and how to improve the TFT on-current Ion is an important research content.
  • the aperture ratio is also an important factor that affects the brightness of the picture.
  • the aperture ratio refers to the ratio between the area of the light passing portion after removing the wiring portion, transistor portion (usually hidden by a black matrix), etc. of each sub-pixel and the entire area of each sub-pixel. The higher the aperture ratio, the higher the efficiency of light passing.
  • the panel When light is emitted through the backlight, not all light can pass through the panel, such as the signal traces for the LCD source driver chip and gate driver chip, as well as the TFT itself, and the storage capacitor for storing voltage.
  • the area where it is located is obstructed by light. In addition to the incomplete light transmission in these areas, the light passing through these areas is not controlled by the voltage and cannot display the correct gray scale. Therefore, the black matrix must be used to shield them so as not to interfere with other light transmission areas.
  • the ratio of the effective light-transmitting area to the total area is called the aperture ratio. Therefore, reducing the size of the TFT and increasing the on-current of the TFT can significantly improve the quality of the LCD display.
  • FIGS. 1 and 2 schematically show the structure of a thin film transistor.
  • the thin film transistor includes a gate 11, a gate insulating layer 12, and an active layer 13 laminated on a substrate 10.
  • the active layer 13 may also be covered with a passivation layer 14.
  • a source (S) region, a drain (D) region, and a channel region between the source and drain regions are formed in the active layer 13.
  • the channel structure is a planar structure, that is, the surface of the active layer facing close to the gate is flat or substantially flat at least in the channel region.
  • the length L and width W of the channel region of this thin film transistor are defined by the source and drain regions, and are usually limited by the manufacturing process, such as the minimum size of photolithography.
  • the minimum size of photolithography is usually reduced to reduce the length of the channel region It is difficult for L to increase the aspect ratio W/L.
  • a thin film transistor is provided.
  • a thin film transistor includes a gate, a gate insulating layer, and an active layer laminated on a base substrate, and a source region, a drain region, and a channel region are formed in the active layer.
  • the surface of the source layer facing the gate insulating layer is at least partially formed with a non-planar surface in the channel region, so that the non-planar surface of the active layer has a meandering shape in the width direction of the channel region.
  • the zigzag shape may include a first concave-convex structure.
  • the first concave-convex structure may include ribs and grooves that are alternately arranged along the width direction of the channel region and extend in the length direction of the channel region, respectively.
  • the surface of the gate insulating layer facing the active layer may be formed with a second concavo-convex structure matching the shape of the first concavo-convex structure in the channel region.
  • the active layer may have a uniform thickness in the channel region.
  • the surface of the active layer facing away from the gate insulating layer may be formed with a third concavo-convex structure consistent with the first concavo-convex structure in the channel region.
  • the surface of the gate facing the gate insulating layer may be formed with a fourth concave-convex structure consistent with the first concave-convex structure in the channel region.
  • the gate insulating layer has a uniform thickness in the channel region.
  • a method of manufacturing a thin film transistor is provided.
  • a method of manufacturing a thin film transistor includes the following steps:
  • An active layer is formed on the gate insulating layer so that the surface of the active layer facing the gate insulating layer is formed with a non-planar surface matching the shape of the non-planar surface of the gate insulating layer in the channel region, so that the The non-planar surface of the source layer has a meandering shape in the width direction of the channel region.
  • the step of forming the non-planar surface of the gate insulating layer may include: forming a concavo-convex structure in a region of the surface of the gate insulating layer facing away from the gate that corresponds to the channel region of the thin film transistor.
  • the step of forming the concave-convex structure may include: in a region of the gate insulating layer facing away from the gate, which corresponds to the channel region of the thin film transistor, forming alternately along the width direction of the channel region Ridges and grooves which are arranged in a ground and respectively extend in the length direction of the channel region.
  • the step of forming ridges and grooves may include: using a patterning process to form a plurality of grooves in a region of the gate insulating layer facing away from the gate, which corresponds to the channel region of the thin film transistor. .
  • the patterning process may include the following sub-steps:
  • the semi-transmissive part of the half-mask plate corresponds to the channel area
  • the fully transparent part of the half-mask plate corresponds to another area except the channel area
  • the photoresist layer is lithographically etched and etched by means of the half-mask, so that the photoresist layer is located in the channel To Forming a plurality of trenches in a portion within the region, and forming a via hole exposing the gate insulating layer in a portion of the photoresist layer located in the other region;
  • the base substrate is used as the etching stop layer to continue etching to form another via hole in the gate insulating layer corresponding to the via hole in the photoresist layer, and to form another via hole in the gate insulating layer corresponding to The plurality of grooves of the plurality of grooves;
  • the active layer may be formed to have a uniform thickness in the channel region.
  • a method of manufacturing a thin film transistor is provided.
  • the method includes the following steps: forming a gate on a base substrate; forming a non-planar surface in a region of the gate facing away from the base substrate that corresponds to the channel region of the thin film transistor Forming a gate insulating layer covering at least the gate on the base substrate, the gate insulating layer having a uniform thickness in the channel region; and forming an active layer on the gate insulating layer so that the active layer faces
  • the surface of the gate insulating layer is formed with a non-planar surface consistent with the non-planar surface of the gate in the channel region, so that the non-planar surface of the active layer has a meandering shape in the width direction of the channel region.
  • the non-planar structure of the active layer may include a concavo-convex structure
  • the concavo-convex structure may include ridges and grooves that are alternately arranged in the width direction of the channel region and extend in the length direction of the channel region, respectively.
  • a method of manufacturing a thin film transistor includes the following steps: forming an active layer on a base substrate; Forming a non-planar surface such that the non-planar surface of the active layer has a meandering shape in the width direction of the channel region; forming a gate insulating layer covering at least the active layer on the base substrate; and insulating the gate A gate is formed on the layer.
  • the non-planar structure of the active layer may include a concavo-convex structure, and the concavo-convex structure may include ridges and grooves that are alternately arranged in the width direction of the channel region and extend in the length direction of the channel region, respectively.
  • the non-planar surface of the active layer includes a concavo-convex structure.
  • the concavo-convex structure includes ribs and grooves that are alternately arranged along the width direction of the channel region and extend in the length direction of the channel region, respectively.
  • a display substrate including a base substrate, and the above-mentioned thin film transistor formed on the base substrate or the thin film transistor manufactured according to the above-mentioned method.
  • a display device including the above-mentioned display substrate.
  • FIG. 1 is a perspective view schematically showing a partially cut-away structure of a conventional thin film transistor
  • FIG. 2 is a cross-sectional view taken along the width direction of the channel region of the thin film transistor shown in FIG. 1;
  • FIG. 3 is a cross-sectional view schematically showing the structure of a thin film transistor according to an exemplary embodiment of the present invention
  • FIG. 4 is a cross-sectional view schematically showing the structure of a thin film transistor according to another exemplary embodiment of the present invention.
  • FIG. 5 is a schematic flowchart showing a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention
  • FIG. 6A-6F show a schematic flow chart of a method for manufacturing a thin film transistor according to another exemplary embodiment of the present invention, in which FIG. 6A illustrates the structure after forming a gate and a gate insulating layer on a substrate, and FIG. 6B Illustrates the structure after a photoresist layer is formed on the structure shown in FIG. 6A, and FIG. 6C shows the structure after the first photolithography is performed to form grooves in the portion of the photoresist layer corresponding to the channel region.
  • FIG. 6D shows the structure after the first photolithography is performed to form grooves in the portion of the gate insulating layer corresponding to the channel region,
  • FIG. 6E shows the structure after the photoresist layer is stripped, and FIG. 6F shows To The structure after the active layer is formed on the structure shown in FIG. 6E;
  • FIG. 7 shows a schematic flow of a method of manufacturing a thin film transistor according to yet another exemplary embodiment of the present invention.
  • a thin film transistor which includes a gate, a gate insulating layer, and an active layer laminated on a base substrate, and the active region and the drain are formed in the active layer.
  • FIG. 3 schematically shows the structure of a thin film transistor according to an exemplary embodiment of the present invention.
  • the thin film transistor according to this embodiment includes a gate electrode 110, a gate insulating layer 120, and an active layer 130 laminated on a base substrate 100.
  • an active electrode region and a drain electrode are formed in the active layer 130.
  • Region (not shown in Figure 3) and channel region.
  • the active layer 130 may also be covered with a passivation layer 140 for protection.
  • the surface of the active layer 130 facing the gate insulating layer 120 is at least partially formed with a non-planar surface structure in the channel region, so that the non-planar surface of the active layer has a meandering shape in the width direction of the channel region.
  • the surface of the active layer 130 facing the gate insulating layer 120 is formed with the first uneven structure 131, so that the channel region of the thin film transistor is in the width direction (the left and right directions in FIG. 3). It is zigzag, thereby providing an increased channel width W'compared to the channel width W of a conventional thin film transistor.
  • the aspect ratio of the thin film transistor can be effectively increased, thereby increasing the on-current of the transistor and reducing the power consumption; while maintaining the same aspect ratio as the conventional thin film transistor.
  • the effective width of the channel of the thin film transistor of the present invention is increased, the channel length can be reduced, thereby reducing the area of the thin film transistor, and thus the aperture ratio of the display device can be increased.
  • the first concave-convex structure 131 may include ribs and ribs that are alternately arranged along the width direction of the channel region and respectively extend in the length direction of the channel region (the direction perpendicular to the paper in FIG. 3). Groove. It can be understood that the non-planar channel structure of the present invention is not limited to the form of the concave-convex structure 131, and may be, for example, a curved structure, a stepped structure, a groove structure, a sawtooth structure, and the like.
  • the uneven structure 131 may also include other shapes, such as bumps or bumps formed on the surface of the active layer facing the gate insulating layer.
  • the surface of the gate insulating layer 120 facing the active layer 130 may be formed with a second uneven structure 121 matching the first uneven structure 131 in the channel region, for example, the second uneven structure 121
  • a matching groove is correspondingly formed at the position of the convex ridge of the first concave-convex structure 131
  • a matching convex ridge is correspondingly formed at the position of the groove of the first concave-convex structure 131.
  • the concavo-convex structure 121 can be formed on the gate insulating layer 120 first, and then the active layer 130 can be formed on the gate insulating layer by, for example, a deposition process, so that the source layer 130 can face the source layer 130 without additional processes.
  • a concave-convex structure 131 matching the shape of the concave-convex structure 121 is formed on the surface of the gate insulating layer 120.
  • the surface of the active layer 130 facing away from the gate insulating layer 120 may be formed with a third uneven structure 132 consistent with the first uneven structure 131 in the channel region.
  • the active layer 130 is in the trench region.
  • the channel area has a substantially uniform or constant thickness, which is advantageous in terms of increasing on-current and improving current uniformity.
  • FIG. 4 schematically shows the structure of a thin film transistor according to another exemplary embodiment of the present invention.
  • the surface of the active layer 130' facing the gate insulating layer 120' is formed with a similar uneven structure 131', so that the channel region of the thin film transistor is in the width direction (the left and right directions in FIG. 4). Zigzag, providing increased channel width W'.
  • the difference from FIG. 3 is that the surface of the gate 110' in FIG. 4 facing the gate insulating layer 120' is formed in the channel region with a concave-convex structure 111 consistent with the concave-convex structure 131'.
  • an additional patterning process can be used to treat the surface of the active layer away from the gate insulating layer.
  • a concave-convex structure is formed to ensure that the active layer has a substantially uniform thickness in the channel region.
  • the above description is based on bottom-gate thin film transistors as an example, but the present invention is also applicable to top-gate thin film transistors, and other MOS transistors can also use the non-planar channel structure of the present invention to increase the aspect ratio.
  • the non-planar channel structure can be directly formed on the active layer, avoiding additional non-planar processing of the gate or the gate insulating layer.
  • the method of manufacturing a thin film transistor may include the following steps:
  • an active layer is formed on the gate insulating layer, so that the surface of the active layer facing the gate insulating layer is formed with a non-planar surface structure matching the non-planar surface of the gate insulating layer in the channel region, so that all The non-planar surface of the active layer has a meandering shape in the width direction of the channel region.
  • a gate electrode 110 is sequentially formed on a base substrate 100 such as a glass substrate. And the gate insulating layer 120 covering at least the gate 110; subsequently, a photoresist layer 150 covering the gate insulating layer 120 is formed, as shown in FIG. 6B.
  • a half-mask (not shown) is provided, the semi-transmissive portion of the half-mask corresponds to the channel region of the thin film transistor to be formed, and the fully transmissive portion of the half-mask corresponds to the channel region except the channel region.
  • the other area outside such as the output terminal area of the thin film transistor or the peripheral area of the display device, and with the help of To
  • the photoresist layer 150 is lithographically etched and etched on the half-mask to form a plurality of trenches 151 in the portion of the photoresist layer 150 located in the channel region CR, and the photoresist layer 150 is located where A via 152 exposing the gate insulating layer 120 is formed in a part of the other region, as shown in FIG.
  • the depth of the trench 151 of the photoresist layer 150 in the channel region can be made smaller than the depth of the via 152, that is, there is a remaining photoresist layer in the channel region CR. .
  • the gate insulating layer 120 may be slightly over-etched in the via 152.
  • the base substrate 100 is used as an etching stop layer, or an additional etching stop layer is formed between the gate insulating layer 120 and the base substrate 110, and the gate insulating layer 120 is etched at the via hole 152.
  • the gate insulating layer 120 is etched at the via hole 152.
  • another via hole 122 corresponding to the via hole 152 in the photoresist layer is formed in the gate insulating layer 120, and a trench 151 is formed in a portion of the gate insulating layer 120 located in the channel region CR.
  • a plurality of grooves 123 as shown in FIG. 6D.
  • the remaining photoresist layer is stripped by an ashing process to form the structure shown in FIG. 6E.
  • the surface of the gate insulating layer 120 away from the gate 100 (that is, the surface facing the active layer to be formed) is located in the channel
  • a concave-convex structure 121 is formed in the region, which includes a groove 123 and adjacent ribs 124.
  • the grooves 123 and the ribs 124 are alternately arranged along the width direction of the channel region and extend in the length direction of the channel region, respectively.
  • the via 152 does not need to penetrate the gate insulating layer during etching, but may only extend through a part of the gate insulating layer, as long as a suitable concave-convex structure can be formed in the channel region.
  • a patterned active layer 130 is formed on the gate insulating layer 120 having the concave-convex structure 121.
  • a concave-convex structure 131 matching the shape of the concave-convex structure 121 is formed on the surface of 130 facing the gate insulating layer 120, which includes a convex rib 133 corresponding to the groove 123 and a groove 134 corresponding to the convex rib 124, as shown in FIG. 6F.
  • the active layer 130 has a uniform thickness in the channel region.
  • a concave-convex structure 131 may be formed on the surface of the active layer 130 facing away from the gate insulating layer 120.
  • the bump structure may be formed on the base substrate 100 (see FIGS. 3 and 4).
  • the concave-convex structure is formed on the gate insulating layer by using a half mask, but the present invention is not limited to this, for example, a suitable mask may be used and the process may be controlled. Parameters are directly etched on the surface of the gate insulating layer to form the required concavo-convex structure.
  • FIGS. 6A-6F An example is schematically illustrated in FIGS. 6A-6F in which the uneven structure is formed on the gate insulating layer, and the uneven structure is formed in the channel region on the surface of the active layer facing the gate insulating layer.
  • Plane trench structure For the structure shown in FIG. 4, by forming an uneven structure in the channel region on the surface of the gate facing the gate insulating layer, it is also possible to form an uneven structure in the channel region on the surface of the active layer facing the gate insulating layer.
  • the method of manufacturing a thin film transistor may include the following steps:
  • a non-planar surface 111 such as a concavo-convex structure, in a region of the gate 110' away from the surface of the base substrate 100 that corresponds to the channel region of the thin film transistor;
  • a gate insulating layer 120' covering at least the gate 110' is formed on the base substrate 100.
  • the gate insulating layer 120' has a uniform thickness in the channel region, so that the gate insulating layer 120' is located in the channel region.
  • a concave-convex structure corresponding to the concave-convex structure of the gate 110' is also formed on the surface away from the gate 110', wherein a uniform gate insulating layer can facilitate the switching control of the gate to the channel;
  • the active layer 130' is formed on the gate insulating layer 120', so that the surface of the active layer 130' facing the gate insulating layer 120' is formed in the channel region with a non-planar surface consistent with the non-planar surface of the gate 110'
  • the planar surface such as the uneven structure 131', forms a non-planar channel structure in the width direction of the channel region.
  • the concavo-convex structure 131' may include ribs and grooves that are alternately arranged along the width direction of the channel region and extend in the length direction of the channel region, respectively.
  • a method of manufacturing a thin film transistor of the present invention is described above only by taking a bottom-gate thin film transistor as an example.
  • a method of manufacturing a thin film transistor may include the following steps:
  • a non-planar surface is formed on the portion of the active layer that faces away from the base substrate and is located in the channel region of the thin film transistor, so that the non-planar surface of the active layer has the width direction of the channel region To A zigzag shape;
  • the non-planar surface may include a concave-convex structure, which includes, for example, ribs and grooves that are alternately arranged along the width direction of the channel region and respectively extend in the length direction of the channel region;
  • a gate is formed on the gate insulating layer.
  • the present invention also provides a display substrate, which includes a base substrate, and the above-mentioned thin film transistor formed on the substrate or the thin film transistor manufactured according to the above-mentioned method.
  • the present invention also provides a display device, which includes the above-mentioned display substrate.
  • the display device may include a TFT liquid crystal display device, such as an LCD TV, a mobile phone, an e-book, a tablet computer, and the like.

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Abstract

一种具有宽长比增加的沟道结构的薄膜晶体管及其制造方法，以及包括该薄膜晶体管的显示基板和显示装置。该薄膜晶体管包括层叠在衬底基板(100)上的栅极(110)、栅极绝缘层(120)和有源层(130)，在有源层(130)中形成有源极区域、漏极区域和沟道区域，其中有源层(130)的面向栅极绝缘层(120)的表面在沟道区域中至少部分地形成有非平面表面，使得所述有源层(130)的非平面表面在沟道区域的宽度方向上具有曲折的形状。

Description

薄膜晶体管及其制造方法、显示基板和显示装置 技术领域
本发明的实施例一般地涉及显示技术领域，并且具体地，涉及一种具有宽长比增加的沟道结构的薄膜晶体管及其制造方法，以及显示基板和显示装置。
背景技术
随着液晶显示技术的不断发展，薄膜晶体管(TFT)在诸如TFT LCD(液晶显示器)之类的显示装置中得到了广泛的应用。TFT LCD是通过控制排列成矩阵的亚像素点中的每一个上的电压，来实现对每个亚像素点的亮度的调节，进而完成完整准确的显示画面。当矩阵中的某一行上的栅极加上开启电压Von，TFT器件打开时，TFT沟道两边的源极和漏极导通，给定的信号从数据线上加入到亚像素电极上。亚像素电极和公共电极之间的电压差决定了该亚像素区域上液晶分子的偏转情况，最终影响该亚像素的亮度和显示效果。
对LCD显示画面品质的改善已经成为LCD产品的竞争焦点之一，其中，开启电压的大小直接决定了画面的品质，而如何提高TFT的导通电流Ion是重要的研究内容。在影响画面品质的因素中，开口率也是影响画面亮度的重要因素。开口率指除去每一个亚像素的配线部、晶体管部(通常采用黑色矩阵隐藏)等后的光线通过部分的面积和每一个次像素整体的面积之间的比例。开口率越高，光线通过的效率越高。当光线经由背光板发射出来时，并不是所有的光线都能穿过面板，比如给LCD源极驱动芯片及栅极驱动芯片用的信号走线，以及TFT本身，还有储存电压用的储存电容等所在的区域都对光线有阻挡租用。这些区域除了不完全透光外，也由于经过这些区域的光线不受电压控制，而无法显示正确的灰阶，所以都需利用黑矩阵加以遮蔽，以免干扰其它透光区域。而有效的透光区域与全部面积的比例就称之为开口率。因此，减小TFT的尺寸、增大TFT的导通电流等可以明显地改善LCD显示画面品质。
影响薄膜晶体管的导通电流的一个重要因素是晶体管的宽长比(W/L)。图1和2示意性地示出了一种薄膜晶体管的结构。如图所示，该薄膜晶体管包括层叠在基板10上的栅极11、栅极绝缘层12和有源层13，在有源层13上还可以覆盖有钝化层14。其中，在有源层13中形成有源极(S)区域、漏极(D)区域以及位于源、漏极区域之间的沟道区域。在图1和2中图示的薄膜晶体管中，其沟道结构是平面结构，即有源层的面向靠近栅极的表面至少在沟道区域中是平坦的或基本上平坦的，因此，这种薄膜晶体管的沟道区域的长度L和宽度W由源、漏极区域限定，并且通常受制造工艺，如受光刻最小尺寸限制，通常减小光刻最小尺寸来减小沟道区域的长度L进而增大宽长比W/L是困难的。
发明内容
为了克服现有技术存在的上述和其它问题和缺陷中的至少一种，提出了本发明。
根据本发明的一个方面，提出了一种薄膜晶体管。
根据一个示例性实施例，薄膜晶体管包括层叠在衬底基板上的栅极、栅极绝缘层和有源层，在有源层中形成有源极区域、漏极区域和沟道区域，其中有源层的面向栅极绝缘层的表面在沟道区域中至少部分地形成有非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。
在进一步的实施例中，所述曲折的形状可以包括第一凹凸结构。
在进一步的实施例中，第一凹凸结构可以包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
在进一步的实施例中，栅极绝缘层的面向有源层的表面在沟道区域中可以形成有与第一凹凸结构形状匹配的第二凹凸结构。
在进一步的实施例中，有源层在沟道区域中可以具有均一的厚度。
在进一步的实施例中，有源层的背离栅极绝缘层的表面在沟道区域中可以形成有与第一凹凸结构一致的第三凹凸结构。
在进一步的实施例中，栅极的面向栅极绝缘层的表面在沟道区域中可以形成有与第一凹凸结构一致的第四凹凸结构。
在进一步的实施例中，栅极绝缘层在沟道区域中具有均一的厚度。
根据本发明的另一个方面，提供了一种制造薄膜晶体管的方法。
根据一个示例性的实施例，制造薄膜晶体管的方法包括下述步骤：
在衬底基板上形成栅极；
在衬底基板上形成至少覆盖栅极的栅极绝缘层；
在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中形成非平面表面；以及
在栅极绝缘层上形成有源层，使得有源层的面向栅极绝缘层的表面在沟道区域中形成有与栅极绝缘层的非平面表面形状匹配的非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。
在进一步的实施例中，形成栅极绝缘层的非平面表面的步骤可以包括：在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中形成凹凸结构。
在进一步的实施例中，形成所述凹凸结构的步骤可以包括：在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中，形成沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
在进一步的实施例中，形成凸棱和凹槽的步骤可以包括：采用构图工艺在在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中形成多个凹槽。
在进一步的实施例中，所述构图工艺可以包括下述子步骤：
在栅极绝缘层上形成光刻胶；
提供一半掩模板，该半掩模板的半透光部分对应于沟道区域，且该半掩模板的全透光部分对应于除沟道区域之外的另一个区域；
借助于所述半掩模板对光刻胶层进行光刻和刻蚀，以在光刻胶层位于沟道 区域内的部分中形成多个沟槽，并在光刻胶层位于所述另一个区域中的部分中形成露出栅极绝缘层的过孔；
以衬底基板为刻蚀阻挡层继续进行刻蚀，以在栅极绝缘层中形成对应于光刻胶层中的所述过孔的另一个过孔，并在栅极绝缘层中形成对应于所述多个沟槽的所述多个凹槽；以及
灰化并剥离光刻胶层。
在进一步的实施例中，所述有源层可以被形成为在沟道区域中具有均一的厚度。
根据本发明的又一个方面，提供了一种制造薄膜晶体管的方法。
根据一个示例性的实施例，该方法包括下述步骤：在衬底基板上形成栅极；在栅极的背离衬底基板的表面的对应于薄膜晶体管的沟道区域的区域中形成非平面表面；在衬底基板上形成至少覆盖栅极的栅极绝缘层，该栅极绝缘层在沟道区域中具有均一的厚度；以及在栅极绝缘层上形成有源层，使得有源层的面向栅极绝缘层的表面在沟道区域中形成有与栅极的非平面表面一致的非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。在此方面中，有源层的非平面结构可以包括凹凸结构，该凹凸结构可以包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
根据本发明的再一个方面，制造薄膜晶体管的方法包括下述步骤：在衬底基板上形成有源层；在有源层的背离衬底基板的表面位于薄膜晶体管的沟道区域中的部分上形成非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状；在衬底基板上形成至少覆盖有源层的栅极绝缘层；以及在栅极绝缘层上形成栅极。在此方面中，有源层的非平面结构可以包括凹凸结构，该凹凸结构可以包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
根据上述方法的一个示例性实施例，有源层的非平面表面包括凹凸结构。
根据上述方法的另一个示例性实施例，凹凸结构包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
根据本发明的进一步的方面，提供了一种显示基板，其包括衬底基板，和形成在衬底基板上的上述薄膜晶体管或根据上述方法制造的薄膜晶体管。
根据本发明的其它进一步的方面，提供了一种显示装置，包括上述显示基板。
通过下文中参照附图对本发明所作的详细描述，本发明的其它目的和优点将显而易见，并可帮助对本发明有全面的理解。
附图说明
通过参考附图能够更加清楚地理解本发明的特征和优点，附图是示意性的而不应理解为对本发明进行任何限制，在附图中：
图1是示意性地示出一种现有的薄膜晶体管的局部剖切结构的透视图；
图2是沿图1中示出的薄膜晶体管的沟道区域的宽度方向截取的剖面图；
图3是示意性地示出根据本发明的一个示例性实施例的薄膜晶体管的结构的剖视图；
图4是示意性地示出根据本发明的另一个示例性实施例的薄膜晶体管的结构的剖视图；
图5是示出根据本发明的一个示例性实施例的制造薄膜晶体管的方法的示意性流程图；
图6A-6F示出根据本发明的又一个示例性实施例的制造薄膜晶体管的方法的示意性流程，其中图6A图示了在基板上形成栅极和栅极绝缘层之后的结构，图6B图示了在图6A中示出的结构上形成光刻胶层之后的结构，图6C示出进行第一次光刻以在光刻胶层对应于沟道区域的部分中形成凹槽之后的结构，图6D示出进行第一次光刻以在栅极绝缘层中对应于沟道区域的部分中形成凹槽之后的结构，图6E示出剥离了光刻胶层之后的结构，以及图6F示出了 在图6E中示出的结构上形成有源层之后的结构；
图7示出根据本发明的又一个示例性实施例的制造薄膜晶体管的方法的示意性流程。
具体实施方式
在下面的详细描述中，为便于说明，阐述了许多具体的细节以提供对本发明的实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其它情况下，公知的结构和装置以图示的方式体现以简化附图。
根据本发明的一个总的构思，提供了一种薄膜晶体管，其包括层叠在衬底基板上的栅极、栅极绝缘层和有源层，在有源层中形成有源极区域、漏极区域和沟道区域，其中有源层的面向栅极绝缘层的表面在沟道区域中至少部分地形成有非平面表面，使得有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。
图3示意性地示出了根据本发明的一个示例性实施例的薄膜晶体管的结构。如图所示，根据该实施例的薄膜晶体管包括层叠在衬底基板100上的栅极110、栅极绝缘层120和有源层130，在有源层130中形成有源极区域、漏极区域(图3中未示出)和沟道区域。在一个示例中，在有源层130上还可以覆盖有起保护作用的钝化层140。
有源层130的面向栅极绝缘层120的表面在沟道区域中至少部分地形成有非平面表面结构，从而使得有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。在图3所示的示例中，有源层130的面向栅极绝缘层120的表面形成有第一凹凸结构131，使得薄膜晶体管的沟道区域在宽度方向(如图3中的左右方向)上是曲折的，从而与常规薄膜晶体管的沟道宽度W相比，提供了增加的沟道宽度W’。由此，能够有效地增加薄膜晶体管的宽长比，因此增加晶体管的导通电流，减小功耗；而在保持与常规薄膜晶体管相同的宽长比的情况 下，由于本发明的薄膜晶体管的沟道的有效宽度增加，因此能够减小沟道长度，从而减小薄膜晶体管的面积，进而能够提高显示装置的开口率。
如图3所示，第一凹凸结构131可以包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向(如图3中垂直于纸面的方向)上延伸的凸棱和凹槽。可以理解，本发明的非平面沟道结构不限于凹凸结构131的形式，例如可以为曲面结构、台阶形结构、沟槽结构、锯齿结构等形式。而凹凸结构131也可以包括其它形状，如形成在有源层的面向栅极绝缘层的表面上的凸点或凸块。
如图3所示，栅极绝缘层120的面向有源层130的表面在沟道区域中可以形成有与第一凹凸结构131匹配的第二凹凸结构121，示例性地，第二凹凸结构121在第一凹凸结构131的凸棱的位置处对应地形成有匹配的凹槽，而在第一凹凸结构131的凹槽的位置处对应地形成有匹配的凸棱。
如下文将描述的那样，可以先在栅极绝缘层120上形成凹凸结构121，随后在栅极绝缘层上例如通过沉积工艺形成有源层130，从而无需额外的工艺就能在源层130面向栅极绝缘层120的表面上形成与凹凸结构121形状适配的凹凸结构131。在这种情况下，有源层130的背离栅极绝缘层120的表面在沟道区域中可以形成有与第一凹凸结构131一致的第三凹凸结构132，此时，有源层130在沟道区域中具有基本上均匀或不变的厚度，这在提高导通电流和改善电流均匀性方面是有利的。
图4示意性地示出根据本发明的另一个示例性实施例的薄膜晶体管的结构。在图4中，有源层130’的面向栅极绝缘层120’的表面形成有类似的凹凸结构131’，使得薄膜晶体管的沟道区域在宽度方向(如图4中的左右方向)上是曲折的，提供增加的沟道宽度W’。与图3的不同之处在于，图4中的栅极110’的面向栅极绝缘层120’的表面在沟道区域中形成有与凹凸结构131’一致的凹凸结构111，此时，通过简单地沉积或热生长栅极绝缘层120’以及沉积有源层130’，就能通过形状匹配在有源层130’的面向栅极绝缘层120’的表面形成对应的凹 凸结构131’。
可以理解，对于图3和4示出的结构，在通过沉积工艺形成的有源层的厚度不均匀的情况下，可以采用附加的构图工艺对有源层的背离栅极绝缘层的表面进行处理，如形成凹凸结构，以确保有源层在沟道区域中具有基本上均一的厚度。
此外，以上描述是以底栅型薄膜晶体管为例进行描述的，但本发明同样适用于顶栅型薄膜晶体管，并且其它的MOS晶体管也可以采用本发明的非平面沟道结构增加宽长比。如下文所述，对于顶栅型薄膜晶体管，非平面沟道结构可以是直接在有源层上形成的，避免对栅极或栅极绝缘层的附加的非平面处理。
以下将参照图5和图6A-6F描述根据本发明的示例性实施例的制造薄膜晶体管的方法的示意性流程。在图5中示出的示例性实施例中，制造薄膜晶体管的方法可以包括下述步骤：
S1，在衬底基板上形成栅极；
S2，在衬底基板上形成至少覆盖栅极的栅极绝缘层；
S3，在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中形成非平面表面；以及
S4，在栅极绝缘层上形成有源层，使得有源层的面向栅极绝缘层的表面在沟道区域中形成有与栅极绝缘层的非平面表面匹配的非平面表面结构，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。
在图6A-6F示出的根据本发明的另一个示例性实施例的制造薄膜晶体管的方法中，首先如图6A所示，在诸如玻璃基板之类的衬底基板100上依次形成栅极110和至少覆盖栅极110的栅极绝缘层120；随后，形成覆盖栅极绝缘层120的光刻胶层150，如图6B所示。
接下来，提供一半掩模板(未示出)，该半掩模板的半透光部分对应于将形成的薄膜晶体管的沟道区域，且该半掩模板的全透光部分对应于除沟道区域之外的另一个区域，如薄膜晶体管的输出端区域或显示装置的外围区域，并借助 于该半掩模板对光刻胶层150进行光刻和刻蚀，以在光刻胶层150位于沟道区域CR内的部分中形成多个沟槽151，且在光刻胶层150位于所述另一个区域中的部分中形成露出栅极绝缘层120的过孔152，如图6C所示。此时，由于采用上述半掩模板，可以使得光刻胶层150位于沟道区域内的沟槽151的深度小于其过孔152的深度，即在沟道区域CR内存在剩余的光刻胶层。可以在过孔152中稍微过刻蚀栅极绝缘层120。
接着，例如以衬底基板100为刻蚀阻挡层，或者在栅极绝缘层120和衬底基板110之间形成有附加的刻蚀阻挡层，在过孔152处继续刻蚀栅极绝缘层120，并在沟道区域CR内继续刻蚀剩余的光刻胶层和邻近的栅极绝缘层，直到在过孔152处露出衬底基板。此时，在栅极绝缘层120中形成对应于光刻胶层中的过孔152的另一个过孔122，并在栅极绝缘层120位于沟道区域CR的部分中形成对应于沟槽151的多个凹槽123，如图6D所示。然后，通过灰化工艺剥离剩余的光刻胶层，形成图6E中所示的结构，在栅极绝缘层120背离栅极100的表面(即面向将形成的有源层的表面)位于沟道区域中形成凹凸结构121，其包括凹槽123和相邻的凸棱124。如上文所述，这些凹槽123和凸棱124沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸。可以理解，进行刻蚀时过孔152没有必要贯穿栅极绝缘层，而是可以只延伸穿过栅极绝缘层的一部分，只要可以通过在沟道区域中形成合适的凹凸结构。
然后，例如通过沉积工艺或其它合适的半导体工艺，在具有凹凸结构121的栅极绝缘层120上形成图案化的有源层130，此时，在薄膜晶体管的沟道区域内，在有源层130面向栅极绝缘层120的表面上形成与凹凸结构121形状匹配的凹凸结构131，其包括与凹槽123对应的凸棱133和与凸棱124对应的凹槽134，如图6F所示。在均匀沉积有源层130的情况下，有源层130在沟道区域中具有均匀的厚度，此时在有源层130的背离栅极绝缘层120的表面上可以形成有与凹凸结构131一致的凹凸结构。最后，可以在衬底基板100上形成至少覆盖所形成的薄膜晶体管的钝化层(参见图3和4)。
可以理解，在图6A-6F中示出的示例性实施例中，通过采用半掩模板在栅极绝缘层上形成凹凸结构，但本发明不限于此，例如可以采用合适的掩模并控制工艺参数而直接在栅极绝缘层的表面上进行刻蚀以形成所需要的凹凸结构。
在图6A-6F中示意性地图示了一种示例，其中通过在栅极绝缘层上形成的凹凸结构，在有源层面向栅极绝缘层的表面在沟道区域中形成凹凸结构，即非平面沟道结构。对于图4所示的结构，通过在栅极的面向栅极绝缘层的表面在沟道区域中形成凹凸结构，也可以在有源层面向栅极绝缘层的表面在沟道区域中形成凹凸结构，此时，制造薄膜晶体管的方法可以包括下述步骤：
在衬底基板100上形成栅极110’；
在栅极110’的背离衬底基板100的表面的对应于薄膜晶体管的沟道区域的区域中形成非平面表面111，如凹凸结构；
在衬底基板100上形成至少覆盖栅极110’的栅极绝缘层120’，该栅极绝缘层120’在沟道区域中具有均一的厚度，从而在沟道区域内在栅极绝缘层120’背离栅极110’的表面上也形成有与栅极110’的凹凸结构对应的凹凸结构，其中均匀的栅极绝缘层可以有利于栅极对沟道的开关控制；以及
在栅极绝缘层120’上形成有源层130’，使得有源层130’的面向栅极绝缘层120’的表面在沟道区域中形成有与栅极110’的非平面表面一致的非平面表面，如凹凸结构131’，以在沟道区域的宽度方向上形成非平面沟道结构。如图所示，凹凸结构131’可以包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
可以看出，以上仅以底栅型薄膜晶体管为例对本发明的制造薄膜晶体管的方法进行了说明。根据本发明，对于顶栅型薄膜晶体管，制造薄膜晶体管的方法可以包括下述步骤：
在衬底基板上形成有源层；
在有源层的背离衬底基板的表面位于薄膜晶体管的沟道区域中的部分上形成非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有 曲折的形状；该非平面表面可以包括凹凸结构，其例如包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽；
在基板上形成至少覆盖有源层的栅极绝缘层；以及
在栅极绝缘层上形成栅极。
此外，本发明还提供了一种显示基板，其包括衬底基板，和形成在衬底基上的上文所述的薄膜晶体管或根据上文所述的方法制造的薄膜晶体管。
进一步，本发明还提供了一种显示装置，其包括上述显示基板。该显示装置可以包括TFT液晶显示装置，如液晶电视、手机、电子书、平板电脑等。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (20)

  1. 一种薄膜晶体管，包括层叠在衬底基板上的栅极、栅极绝缘层和有源层，在有源层中形成有源极区域、漏极区域和沟道区域，其中有源层的面向栅极绝缘层的表面在沟道区域中至少部分地形成有非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。
  2. 根据权利要求1所述的薄膜晶体管，其中所述曲折的形状包括第一凹凸结构。
  3. 根据权利要求2所述的薄膜晶体管，其中第一凹凸结构包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
  4. 根据权利要求2所述的薄膜晶体管，其中栅极绝缘层的面向有源层的表面在沟道区域中形成有与第一凹凸结构形状匹配的第二凹凸结构。
  5. 根据权利要求1-4中任一项所述的薄膜晶体管，其中有源层在沟道区域中具有均一的厚度。
  6. 根据权利要求2-4中任一项所述的薄膜晶体管，其中有源层的背离栅极绝缘层的表面在沟道区域中形成有与第一凹凸结构一致的第三凹凸结构。
  7. 根据权利要求2-4中任一项所述的薄膜晶体管，其中栅极的面向栅极绝缘层的表面在沟道区域中形成有与第一凹凸结构一致的第四凹凸结构。
  8. 根据权利要求7所述的薄膜晶体管，其中栅极绝缘层在沟道区域中具有均一的厚度。
  9. 一种制造薄膜晶体管的方法，包括下述步骤：
    在衬底基板上形成栅极；
    在衬底基板上形成至少覆盖栅极的栅极绝缘层；
    在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中形成非平面表面；以及
    在栅极绝缘层上形成有源层，使得有源层的面向栅极绝缘层的表面在沟道区域中形成有与栅极绝缘层的非平面表面形状匹配的非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。
  10. 根据权利要求9所述的方法，其中形成栅极绝缘层的非平面表面的步骤包括：
    在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中形成凹凸结构。
  11. 根据权利要求10所述的方法，其中形成所述凹凸结构的步骤包括：
    在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中，形成沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
  12. 根据权利要求11所述的方法，其中形成凸棱和凹槽的步骤包括：
    采用构图工艺在在栅极绝缘层的背离栅极的表面的对应于薄膜晶体管的沟道区域的区域中形成多个凹槽。
  13. 根据权利要求12所述的方法，其中所述构图工艺包括下述子步骤：
    在栅极绝缘层上形成光刻胶；
    提供一半掩模板，该半掩模板的半透光部分对应于沟道区域，且该半掩模板的全透光部分对应于除沟道区域之外的另一个区域；
    借助于所述半掩模板对光刻胶层进行光刻和刻蚀，以在光刻胶层位于沟道区域内的部分中形成多个沟槽，并在光刻胶层位于所述另一个区域中的部分中形成露出栅极绝缘层的过孔；
    以衬底基板为刻蚀阻挡层继续进行刻蚀，以在栅极绝缘层中形成对应于光刻胶层中的所述过孔的另一个过孔，并在栅极绝缘层中形成对应于所述多个沟槽的所述多个凹槽；以及
    灰化并剥离光刻胶层。
  14. 根据权利要求9-13中任一项所述的方法，其中所述有源层被形成为在沟道区域中具有均一的厚度。
  15. 一种制造薄膜晶体管的方法，包括下述步骤：
    在衬底基板上形成栅极；
    在栅极的背离衬底基板的表面的对应于薄膜晶体管的沟道区域的区域中形成非平面表面；
    在衬底基板上形成至少覆盖栅极的栅极绝缘层，该栅极绝缘层在沟道区域中具有均一的厚度；以及
    在栅极绝缘层上形成有源层，使得有源层的面向栅极绝缘层的表面在沟道区域中形成有与栅极的非平面表面一致的非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状。
  16. 一种制造薄膜晶体管的方法，包括下述步骤：
    在衬底基板上形成有源层；
    在有源层的背离衬底基板的表面位于薄膜晶体管的沟道区域中的部分上形成非平面表面，使得所述有源层的非平面表面在沟道区域的宽度方向上具有曲折的形状；
    在衬底基板上形成至少覆盖有源层的栅极绝缘层；以及
    在栅极绝缘层上形成栅极。
  17. 根据权利要求15或16所述的方法，其中有源层的非平面表面包括凹凸结构。
  18. 根据权利要求17所述的方法，其中凹凸结构包括沿沟道区域的宽度方向交替地排列且分别在沟道区域的长度方向上延伸的凸棱和凹槽。
  19. 一种显示基板，包括：
    衬底基板；和
    形成在衬底基板上的、根据权利要求1-8中任一项所述的薄膜晶体管或根据权利要求9-18中任一项所述的方法制造的薄膜晶体管。
  20. 一种显示装置，包括权利要求19所述的显示基板。
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