WO2016123991A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2016123991A1
WO2016123991A1 PCT/CN2015/090714 CN2015090714W WO2016123991A1 WO 2016123991 A1 WO2016123991 A1 WO 2016123991A1 CN 2015090714 W CN2015090714 W CN 2015090714W WO 2016123991 A1 WO2016123991 A1 WO 2016123991A1
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Prior art keywords
signal input
node
clock signal
thin film
output
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Ceased
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PCT/CN2015/090714
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English (en)
French (fr)
Inventor
马占洁
孙拓
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US15/021,990 priority Critical patent/US10019923B2/en
Priority to EP15880933.5A priority patent/EP3255626B1/en
Publication of WO2016123991A1 publication Critical patent/WO2016123991A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • the display device needs to include a gate drive circuit.
  • the gate driving circuit includes a plurality of shift registers that are cascaded with each other.
  • the shift register includes an input module, an output module, and an output control module.
  • the input module includes M1, the output module includes M2 and M3, and the output control module includes M4 and M5. , C1 and C2, where M1-M5 are low-level PMOSFETs.
  • the timing diagram of the working process is as shown in FIG. 2. In the t1 phase, the start signal input from the start signal input terminal STV and the first clock signal input from the first clock signal input terminal CK1 are low level signals, and the second clock The second clock signal input by the signal input terminal CK2 is a high level signal.
  • M1, M2, M3, M4 and M5 are both turned on, and the signal output terminal Output outputs a high level (non-valid signal); in the t2 phase,
  • the start signal input from the start signal input terminal STV and the first clock signal input from the first clock signal input terminal CK1 are a high level signal
  • the second clock signal input from the second clock signal input terminal CK2 is a low level signal
  • M1 M4 and M5 are turned off. Due to the action of C2 and C1, M2 and M3 are turned on, and the signal output terminal Output outputs a low level (valid signal).
  • the inventors have found that when the second clock signal input by the second clock signal input terminal CK2 changes, the signal on the gate of M2 is affected by the coupling capacitance formed between the gate and the drain of M2, thereby affecting the output terminal.
  • the output signal of the Output output causes the output signal to deteriorate, affecting the output of the shift register.
  • the present disclosure provides a shift register and a driving method thereof, a gate driving circuit, and a display device, which can reduce the influence of a change of a clock signal associated with an output module on an output signal, and improve an output effect of the shift register.
  • an embodiment of the present disclosure provides a shift register including: an input module, an output module, and an output control module;
  • the input module is configured to control signal transmission between the start signal input end and the first node lose;
  • the output module is configured to control a signal output of a signal output
  • the output module includes a first output unit and a second output unit, wherein the first output unit is coupled to the first node, and the first node is configured to Controlling the first output unit, the first output unit is configured to control signal transmission between a second clock signal input and the signal output, the second output unit is coupled to a second node, the a second node configured to control the second output unit, the second output unit configured to control signal transmission between the first level signal input and the signal output;
  • the output control module includes a first control unit configured to control a level of the first node, and a second control unit configured to control the first The level of the two nodes.
  • the input module includes a first thin film transistor, a gate of the first thin film transistor is connected to a first clock signal input end, a first pole is connected to the start signal input end, and a second pole is connected to the first node.
  • the first output unit includes a second thin film transistor, a gate of the second thin film transistor is connected to the first node, a first pole is connected to the signal output end, and a second pole is connected to the second clock signal input end .
  • the second output unit includes a third thin film transistor, a gate of the third thin film transistor is connected to the second node, a first pole is connected to the first level signal input end, and a second pole is connected to the signal output end.
  • the first control unit includes a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a first capacitor and a second capacitor; wherein the gate of the fourth thin film transistor The pole is connected to the first node, the first pole is connected to the third node, and the second pole is connected to the first level signal input end;
  • the gate of the fifth thin film transistor is connected to the third clock signal input end, the first pole is connected to the third node, and the second pole is connected to the second level signal input end;
  • the gate of the sixth thin film transistor is connected to the third node, the first pole is connected to the second pole of the seventh thin film transistor, and the second pole is connected to the first level signal input end;
  • the gate of the seventh thin film transistor is connected to the second clock signal input end, the first pole is connected to the first node, and the second pole is connected to the first pole of the sixth thin film transistor;
  • a gate of the eighth thin film transistor is connected to the third clock signal input end, and the first pole is connected The first level signal input end, the second pole is connected to the first node;
  • One end of the first capacitor is connected to the signal output end, and the other end is connected to the first node;
  • One end of the second capacitor is connected to the third node, and the other end is connected to the first level signal input end.
  • the second control unit includes a ninth thin film transistor, a tenth thin film transistor, and a third capacitor;
  • the gate of the ninth thin film transistor is connected to the first node, the first pole is connected to the start signal input end, and the second pole is connected to the second node;
  • the gate of the tenth thin film transistor is connected to the third clock signal input end, the first pole is connected to the second node, and the second pole is connected to the second level signal input end;
  • One end of the third capacitor is connected to the second node, and the other end is connected to the first level signal input end.
  • the first level signal input terminal inputs a high level
  • the second level signal input terminal inputs a low level
  • the first extreme source the second extreme drain
  • the thin film transistor is N-type
  • the first level signal input terminal inputs a low level
  • the second level signal input terminal inputs a high level, the first extreme drain, and the second extreme source.
  • Embodiments of the present disclosure provide a shift register including: an input module, an output module, and an output control module; the input module controls signal transmission between the start signal input end and the first node; and the output module control signal a signal output at the output end, the output module includes a first output unit and a second output unit, wherein the first output unit is connected to the first node, and the first node controls signal transmission between the second clock signal input end and the signal output end, The second output unit is connected to the second node, and the second node controls signal transmission between the first level signal input end and the signal output end; the output control module includes a first control unit and a second control unit, wherein the first control unit controls The level of the first node, the second control unit controls the level of the second node, thereby stabilizing the levels of the first node and the second node, reducing the influence of the change of the clock signal associated with the output module on the output signal, and improving the shift The output effect of the bit register.
  • an embodiment of the present disclosure further provides a gate driving circuit including a plurality of shift registers according to any one of the above.
  • Embodiments of the present disclosure also provide a display device including the gate drive circuit described above.
  • an embodiment of the present disclosure further provides a driving method of a shift register, including:
  • the output control module includes a first control unit and a second control unit, the output module includes a first output unit and a second output unit, wherein the first node is controlled by the first control unit Leveling, further controlling the first output unit by the first node, controlling a level of the second node by the second control unit, and further controlling the second output unit by the second node.
  • the driving method comprises:
  • the second clock signal input to the second clock signal input end and the third clock signal input to the third clock signal input end are at a high level, the start signal input from the start signal input end and the first input end of the first clock signal input end A clock signal is low;
  • the first node is at a low level, and the second clock signal is transmitted to the signal output end;
  • the start signal is transmitted to the second node, the second node is at a low level, and a high level signal of the high level signal input end is transmitted to the signal output end;
  • a start signal input by the start signal input end, a first clock signal input by the first clock signal input end, and a third clock signal input by the third clock signal input end are at a high level, the first The second clock signal input to the input of the two clock signals is at a low level;
  • the start signal is transmitted to the second node, and the high level signal is transmitted to the signal output end;
  • a start signal input by the start signal input end, a first clock signal input by the first clock signal input end, and a second clock signal input by the second clock signal input end are at a high level, the first The third clock signal input to the input of the three clock signals is at a low level;
  • the high level signal is transmitted to the first node, and the first node is at a high level
  • the low level signal is transmitted to the second node, and the high level signal is transmitted to the signal output end;
  • a start signal input by the start signal input terminal, a second clock signal input by the second clock signal input end, and a third clock signal input by the third clock signal input end are at a high level, the first The first clock signal input to a clock signal input terminal is at a low level;
  • the start signal is transmitted to the first node, and the first node is at a high level
  • the high level signal is transmitted to the signal output end;
  • a start signal input by the start signal input end, a first clock signal input by the first clock signal input end, and a third clock signal input by the third clock signal input end are at a high level, the first The second clock signal input to the input of the two clock signals is at a low level;
  • the high level signal is transmitted to the first node, and the first node is at a high level
  • the high level signal is transmitted to the signal output end;
  • a start signal input by the start signal input end, a first clock signal input by the first clock signal input end, and a second clock signal input by the second clock signal input end are at a high level, the first The third clock signal input to the input of the three clock signals is at a low level;
  • the high level signal is transmitted to the first node, and the first node is at a high level
  • the low level signal is transmitted to the second node, and the high level signal is transmitted to the signal output end.
  • the driving method comprises:
  • the second clock signal input by the second clock signal input end and the third clock signal input by the third clock signal input end are at a low level, the start signal input from the start signal input end and the first input end of the first clock signal input end A clock signal is high;
  • the first node is at a high level, and the second clock signal is transmitted to the signal output end,
  • the start signal is transmitted to the second node, and the second node is at a high level.
  • a start signal input by the start signal input end, a first clock signal input by the first clock signal input end, and a third clock signal input by the third clock signal input end are at a low level.
  • the second clock signal input to the second clock signal input terminal is at a high level;
  • the low level signal is transmitted to the signal output end;
  • a start signal input by the start signal input end, a first clock signal input by the first clock signal input end, and a second clock signal input by the second clock signal input end are at a low level, the first The third clock signal input to the input of the three clock signals is at a high level;
  • the low level signal is transmitted to the first node, and the first node is at a low level
  • the high level signal is transmitted to the second node, and the low level signal is transmitted to the signal output end;
  • a start signal input by the start signal input terminal, a second clock signal input by the second clock signal input end, and a third clock signal input by the third clock signal input end are at a low level, the first The first clock signal input to a clock signal input terminal is at a high level;
  • the start signal is transmitted to the first node, and the first node is at a low level
  • the low level signal is transmitted to the signal output end;
  • a start signal input by the start signal input end, a first clock signal input by the first clock signal input end, and a third clock signal input by the third clock signal input end are at a low level, the first The second clock signal input to the input of the two clock signals is at a high level;
  • the low level signal is transmitted to the first node, and the first node is at a low level
  • the low level signal is transmitted to the signal output end;
  • a start signal input by the start signal input end, a first clock signal input by the first clock signal input end, and a second clock signal input by the second clock signal input end are at a low level, the first The third clock signal input to the input of the three clock signals is at a high level;
  • the high level signal is transmitted to the second node, and the low level signal is transmitted to the signal output end.
  • Embodiments of the present disclosure provide a driving method of a shift register, the driving method including: The input module controls a signal input between the start signal input end and the first node; the signal output of the signal output end is controlled by the output module; and the output module is controlled by the output control module, the output control module includes a first control unit and a second control unit
  • the output module includes a first output unit and a second output unit, wherein the level of the first node is controlled by the first control unit, the first node controls the first output unit, and the second node controls the level of the second node
  • the second node controls the second output unit, so that the levels of the first node and the second node can be stabilized, the influence of the change of the clock signal associated with the output module on the output signal is reduced, and the output effect of the shift register is improved.
  • 1 is a circuit diagram of a known shift register
  • FIG. 2 is a timing diagram of a driving process of a known shift register
  • FIG. 3 is a schematic circuit diagram of a first type of shift register according to an embodiment of the present disclosure
  • FIG. 4 is a schematic circuit diagram of a second shift register according to an embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of a driving process of a first shift register according to an embodiment of the present disclosure
  • FIG. 6 is a timing diagram of a driving process of a second shift register according to an embodiment of the present disclosure.
  • 3 output control module; 31 - first control unit; 32 - second control unit.
  • the embodiment of the present disclosure provides a shift register, as shown in FIGS. 3 and 4, the shift register includes an input module 1, an output module 2, and an output control module 3.
  • the input module 1 controls signal transmission between the start signal input terminal STV and the first node P.
  • the output module 2 controls the signal output of the signal output terminal OUTPUT
  • the output module 2 includes a first output unit 21 and a second output unit 22, wherein the first output unit 21 is connected to the first node P, and the first node P controls the first output unit 21, the first output unit 21 controls signal transmission between the second clock signal input terminal CK2 and the signal output terminal OUTPUT, the second output unit 22 is connected to the second node Q, the second node Q controls the second output unit 22, and the second The output unit 22 controls signal transmission between the high level signal input terminal VGH and the signal output terminal OUTPUT.
  • the output control module 3 includes a first control unit 31 and a second control unit 32, wherein the first control unit 31 controls the level of the first node P, and the second control unit 32 controls the level of the second node Q.
  • the first control unit 31 can stabilize the level of the first node P, thereby lowering the second clock signal. The effect of the change on the output signal improves the output of the shift register.
  • the input module 1 includes a first thin film transistor M1, and the first thin film transistor M1 is a p-type thin film transistor or an n-type thin film transistor, and the gate of the first thin film transistor M1 is connected to the first
  • the clock signal input terminal CK1 the first pole is connected to the start signal input terminal STV, and the second pole is connected to the first node P, so that the first thin film transistor M1 can be controlled by the first clock signal input by the first clock signal input terminal CK1. Turning on and off, thereby controlling signal transmission between the start signal input terminal STV and the first node P.
  • the first output unit 21 includes a second thin film transistor M2, and the second thin film transistor M2 is a p-type thin film transistor or an n-type thin film transistor, and the gate connection of the second thin film transistor M2
  • the first node P, the first pole is connected to the signal output terminal OUTPUT, and the second pole is connected to the second clock signal input terminal CK2, so that the second thin film transistor M2 can be controlled to be turned on and off by the level of the first node P, thereby controlling Signal transmission between the second clock signal input terminal CK2 and the signal output terminal OUTPUT.
  • the second output unit 22 includes a third thin film transistor M3.
  • the third thin film transistor M3 is a p-type thin film transistor, as shown in FIG. 3, the third thin film transistor M3 The gate is connected to the second node Q, the first pole is connected to the high level signal input terminal VGH, and the second pole is connected to the signal output terminal OUTPUT, so that the third thin film crystal can be controlled by the level of the second node Q.
  • the opening and closing of the body tube M3 controls the signal transmission between the high level signal input terminal VGH and the signal output terminal OUTPUT.
  • the gate of the third thin film transistor M3 is connected to the second node Q, the first pole is connected to the low level signal input terminal VGL, and the second pole is connected to the signal.
  • the output terminal OUTPUT can control the opening and closing of the third thin film transistor M3 through the level of the second node Q, thereby controlling the signal transmission between the low level signal input terminal VGL and the signal output terminal OUTPUT.
  • the first control unit 31 includes a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, and an eighth thin film transistor M8.
  • the gate of the fourth thin film transistor M4 is connected to the first node P, the first pole is connected to the third node R, and the second pole is connected high.
  • the level signal input terminal VGH can control the opening and closing of the fourth thin film transistor M4 through the level of the first node P, thereby controlling the signal transmission between the high level signal input terminal VGH and the third node R.
  • the gate of the fifth thin film transistor M5 is connected to the third clock signal input terminal CK3, the first pole is connected to the third node R, and the second pole is connected to the low level signal input terminal VGL, so that the fifth film can be controlled by the third clock signal.
  • the transistor M5 is turned on and off, thereby controlling signal transmission between the low level signal input terminal VGL and the third node R.
  • the gate of the sixth thin film transistor M6 is connected to the third node R, the first pole is connected to the second pole of the seventh thin film transistor M7, and the second pole is connected to the high level signal input terminal VGH, so that the level of the third node R can be passed.
  • the opening and closing of the sixth thin film transistor M6 is controlled to control signal transmission between the high level signal input terminal VGH and the second electrode of the seventh thin film transistor M7.
  • the gate of the seventh thin film transistor M7 is connected to the second clock signal input terminal CK2, the first pole is connected to the first node P, and the second pole is connected to the first pole of the sixth thin film transistor M6, so that the second clock signal can be used to control the first
  • the seven thin film transistors M7 are turned on and off, thereby controlling signal transmission between the first node P and the first electrode of the sixth thin film transistor M6.
  • the gate of the eighth thin film transistor M8 is connected to the third clock signal input terminal CK3, the first pole is connected to the high level signal input terminal VGH, and the second pole is connected to the first node P, so that the eighth film can be controlled by the third clock signal.
  • the transistor M8 is turned on and off, thereby controlling signal transmission between the high level signal input terminal VGH and the first node P.
  • One end of the first capacitor C1 is connected to the signal output terminal OUTPUT, and the other end is connected to the first node P, so that the level of the first node P can be controlled by the first capacitor C1.
  • One end of the second capacitor C2 is connected to the third node R, and the other end is connected to the high level signal input terminal VGH, so that the level of the third node R can be controlled by the second capacitor C2.
  • the gate of the fourth thin film transistor M4 is connected to the first node P, the first pole is connected to the third node R, and the second pole is connected low.
  • the level signal is input to the VGL so that the turn-on and turn-off of the fourth thin film transistor M4 can be controlled by the level of the first node P, thereby controlling the signal transmission between the low-level signal input terminal VGL and the third node R.
  • the gate of the fifth thin film transistor M5 is connected to the third clock signal input terminal CK3, the first pole is connected to the third node R, and the second pole is connected to the high level signal input terminal VGH, so that the fifth thin film transistor can be controlled by the third clock signal.
  • the opening and closing of M5 controls the signal transmission between the high level signal input terminal VGH and the third node R.
  • the gate of the sixth thin film transistor M6 is connected to the third node R, the first pole is connected to the second pole of the seventh thin film transistor M7, and the second pole is connected to the low level signal input terminal VGL, so that the level of the third node R can be passed.
  • the opening and closing of the sixth thin film transistor M6 is controlled to control signal transmission between the low level signal input terminal VGL and the second electrode of the seventh thin film transistor M7.
  • the gate of the seventh thin film transistor M7 is connected to the second clock signal input terminal CK2, the first pole is connected to the first node P, and the second pole is connected to the first pole of the sixth thin film transistor M6, so that the seventh clock can be controlled by the second clock signal.
  • the thin film transistor M7 is turned on and off, thereby controlling signal transmission between the first node P and the first electrode of the sixth thin film transistor M6.
  • the gate of the eighth thin film transistor M8 is connected to the third clock signal input terminal CK3, the first pole is connected to the low level signal input terminal VGL, and the second pole is connected to the first node P, so that the eighth thin film transistor can be controlled by the third clock signal.
  • the M8 is turned on and off to control the signal transmission between the low level signal input terminal VGL and the first node P.
  • One end of the first capacitor C1 is connected to the signal output terminal OUTPUT, and the other end is connected to the first node P, so that the level of the first node P can be controlled by the first capacitor C1.
  • One end of the second capacitor C2 is connected to the third node R, and the other end is connected to the low-level signal input terminal VGL, so that the level of the third node R can be controlled by the second capacitor C2.
  • the second control unit 32 includes a ninth thin film transistor M9, a tenth thin film transistor M10, and a third capacitor C3.
  • the gate of the ninth thin film transistor M9 is connected to the first node P, the first pole is connected to the start signal input terminal, and the second pole is connected.
  • the second node Q is connected.
  • the gate of the tenth thin film transistor M10 is connected to the third clock signal input terminal CK3, the first pole is connected to the second node Q, and the second pole is connected to the low level signal input terminal VGL, so that the tenth thin film can be controlled by the third clock signal.
  • the transistor M10 is turned on and off, thereby controlling signal transmission between the low level signal input terminal VGL and the second node Q.
  • One end of the third capacitor C3 is connected to the second node Q, and the other end is connected to the high level signal input terminal VGH, so that the level of the second node Q can be controlled by the third capacitor C3.
  • the gate of the ninth thin film transistor M9 is connected to the first node P, and the first pole is connected to the start signal input terminal STV, and the second pole The second node Q is connected so that the turn-on and turn-off of the ninth thin film transistor M9 can be controlled by the level of the first node P, thereby controlling the signal transmission between the start signal input terminal STV and the second node Q.
  • the gate of the tenth thin film transistor M10 is connected to the third clock signal input terminal CK3, the first pole is connected to the second node Q, and the second pole is connected to the high level signal input terminal VGH, so that the tenth thin film can be controlled by the third clock signal.
  • the transistor M10 is turned on and off, thereby controlling signal transmission between the high level signal input terminal VGH and the second node Q.
  • One end of the third capacitor C3 is connected to the second node Q, and the other end is connected to the low-level signal input terminal VGL, so that the level of the second node Q can be controlled by the third capacitor C3.
  • all the thin film transistors in the shift register in the embodiment of the present disclosure are thin film transistors of the same type, that is, the first to tenth thin film transistors in FIG. 3 are all p-type thin film transistors, FIG. 4
  • the first to tenth thin film transistors are all n-type thin film transistors, wherein in the case of a p-type thin film transistor, the first extreme source, the second extremely drain, in the case of an n-type thin film transistor, the first extreme The drain, the second source.
  • Embodiments of the present disclosure provide a shift register including: an input module, an output module, and an output control module; the input module controls signal transmission between the start signal input end and the first node; and the output module control signal a signal output at the output end, the output module includes a first output unit and a second output unit, wherein the first output unit is connected to the first node, and the first node controls signal transmission between the second clock signal input end and the signal output end, The second output unit is connected to the second node, and the second node controls signal transmission between the high (low) level signal input end and the signal output end;
  • the control module includes a first control unit and a second control unit, wherein the first control unit controls the level of the first node, and the second control unit controls the level of the second node, thereby being capable of stabilizing the first node and the second node
  • the level reduces the influence of the change of the clock signal associated with the output module on the output signal, improving the output effect of the shift register.
  • an embodiment of the present disclosure further provides a gate driving circuit including a plurality of shift registers according to any one of the above.
  • Embodiments of the present disclosure also provide a display device including the gate drive circuit described above.
  • the display device can be any product or component having a display function such as a liquid crystal panel, a tablet computer, a television, a display, a notebook computer, an electronic paper, a mobile phone, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure provides a method for driving a shift register according to the first embodiment.
  • the driving method of the shift register includes:
  • the signal transmission between the start signal input terminal STV and the first node P is controlled by the input module 1.
  • the signal output of the signal output terminal OUTPUT is controlled by the output module 2.
  • the output module 2 is controlled by the output control module 3.
  • the output control module 3 includes a first control unit 31 and a second control unit 32.
  • the output module 2 includes a first output unit 21 and a second output unit 22, wherein the first node P is controlled by the first control unit 31. Ping, the first node P controls the first output unit 21, the second control unit 32 controls the level of the second node Q, and the second node Q controls the second output unit 22, thereby stabilizing the first node P and the second node
  • the level of Q reduces the influence of the change of the clock signal associated with the output module 2 on the output signal, improving the output effect of the shift register.
  • the driving method of the shift register shown in FIG. 3 is divided into six stages, and the timing chart of the driving process is as shown in FIG. 5.
  • the first to tenth thin film transistors are p-type thin film transistors, that is, A thin film transistor that is turned on when the signal applied to the gate is a low level signal and turned off when the high level signal is turned off.
  • the first stage t1 The first stage t1:
  • the second clock signal input by the second clock signal input terminal CK2 and the third clock signal input by the third clock signal input terminal CK3 are at a high level, and the start signal input from the start signal input terminal STV is The first clock signal input by the first clock signal input terminal CK1 is at a low level.
  • the first thin film transistor M1 is turned on, the start signal is transmitted to the first node P, the eighth thin film transistor M8 is turned off, the first node P is at a low level, the second thin film transistor M2 is turned on, and the second The clock signal is transmitted to the signal output terminal OUTPUT, and the first capacitor C1 is charged, the fourth thin film transistor M4 is turned on, and the high level signal input from the high level signal input terminal VGH is transmitted to the third node R, and the third node R is high.
  • the sixth thin film transistor M6 is turned off, and the second capacitor C2 is charged, the fifth thin film transistor M5 is turned off, and the seventh thin film transistor M7 is turned off.
  • the sixth thin film transistor M6 and the seventh thin film transistor M7 are both turned off, the high level signal input to the high level signal input terminal VGH cannot be transmitted to the first node P, thereby not affecting the gate of the second thin film transistor M2. The signal applied on it.
  • the ninth thin film transistor M9 is turned on, the tenth thin film transistor M10 is turned off, the start signal is transmitted to the second node Q, the second node Q is at a low level, the third thin film transistor M3 is turned on, and the high level signal input terminal VGH is high.
  • the flat signal is transmitted to the signal output terminal OUTPUT, thereby further stabilizing the high level signal outputted at the signal output terminal OUTPUT, and charging the third capacitor C3.
  • the start signal input by the start signal input terminal STV, the first clock signal input by the first clock signal input terminal CK1, and the third clock signal input by the third clock signal input terminal CK3 are at a high level.
  • the second clock signal input by the second clock signal input terminal CK2 is at a low level.
  • the first thin film transistor M1 is turned off
  • the eighth thin film transistor M8 is turned off
  • the coupling capacitance between the gate and the second electrode of the second thin film transistor M2 causes the level of the first node P to continue to decrease
  • the first capacitor C1 The discharge causes the second thin film transistor M2 to be turned on, the second clock signal is transmitted to the signal output terminal OUTPUT, the fourth thin film transistor M4 is turned on, the high level signal is transmitted to the third node R, and the third node R is at the high level, the second capacitor
  • the C2 discharge turns off the sixth thin film transistor M6, the fifth thin film transistor M5 is turned off, and the seventh thin film transistor M7 is turned on.
  • the sixth thin film transistor M6 is turned off, even if the seventh thin film transistor M7 is turned on, the high level signal input from the high level signal input terminal VGH cannot be transmitted to the first node P, thereby not affecting the second thin film transistor M2.
  • the signal applied to the gate since the sixth thin film transistor M6 is turned off, even if the seventh thin film transistor M7 is turned on, the high level signal input from the high level signal input terminal VGH cannot be transmitted to the first node P, thereby not affecting the second thin film transistor M2. The signal applied to the gate.
  • the ninth thin film transistor M9 is turned on, the start signal is transmitted to the second node Q, the tenth thin film transistor M10 is turned off, the third capacitor C3 is discharged to turn on the third thin film transistor M3, and the high level signal is transmitted to the signal output terminal OUTPUT.
  • the output signal of the signal output terminal OUTPUT is the sum of the high level signal and the second clock signal, so that the level of the output signal in the second stage is low.
  • the third stage t3 The third stage t3:
  • the start signal input by the start signal input terminal STV, the first clock signal input The first clock signal input by the terminal CK1 and the second clock signal input by the second clock signal input terminal CK2 are at a high level, and the third clock signal input by the third clock signal input terminal CK3 is at a low level.
  • the first thin film transistor M1 is turned off, the eighth thin film transistor M8 is turned on, the high level signal is transmitted to the first node P, the first node P is at a high level, the second thin film transistor M2 is turned off, and the first capacitor C1 is turned off.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned on, the low level signal is transmitted to the second node Q, the third thin film transistor M3 is turned on, the high level signal is transmitted to the signal output terminal OUTPUT, and the third capacitor C3 is charged. .
  • the start signal input by the start signal input terminal STV, the second clock signal input by the second clock signal input terminal CK2, and the third clock signal input by the third clock signal input terminal CK3 are at a high level.
  • the first clock signal input by the first clock signal input terminal CK1 is at a low level.
  • the first thin film transistor M1 is turned on, the start signal is transmitted to the first node P, the eighth thin film transistor M8 is turned off, the first node P is at a high level, the second thin film transistor M2 is turned off, and the first capacitor C1 is charged.
  • the fourth thin film transistor M4 is turned off, the fifth thin film transistor M5 is turned off, the second capacitor C2 is discharged to turn on the sixth thin film transistor M6, and the seventh thin film transistor M7 is turned off. Since the seventh thin film transistor M7 is turned off, even if the sixth thin film transistor M6 is turned on, the high level signal input from the high level signal input terminal VGH cannot be transmitted to the first node P.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned off, the third capacitor C3 is discharged to turn on the third thin film transistor M3, and the high level signal is transmitted to the signal output terminal OUTPUT.
  • the fifth stage t5 The fifth stage t5:
  • the start signal input by the start signal input terminal STV, the first clock signal input by the first clock signal input terminal CK1, and the third clock signal input by the third clock signal input terminal CK3 are at a high level.
  • the second clock signal input by the second clock signal input terminal CK2 is at a low level.
  • the first thin film transistor M1 is turned off, the eighth thin film transistor M8 is turned off, the second capacitor C2 is discharged to turn on the sixth thin film transistor M6, the seventh thin film transistor M7 is turned on, and the high level signal is transmitted to the first node P, first Node P is at a high level, second thin film transistor M2 is turned off, and The first capacitor C1 is charged, the fourth thin film transistor M4 is turned off, and the fifth thin film transistor M5 is turned off.
  • the sixth thin film transistor M6 is turned on, the seventh thin film transistor M7 is turned on, and the high level signal can be transmitted to the first node P to maintain the high level of the first node P, so that the second clock signal is caused by the high level.
  • the coupling capacitance between the gate and the second electrode of the second thin film transistor M2 does not affect the signal applied on the gate of the second thin film transistor M2.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned off, the third capacitor C3 is discharged to turn on the third thin film transistor M3, and the high level signal is transmitted to the signal output terminal OUTPUT.
  • the start signal input by the start signal input terminal STV, the first clock signal input by the first clock signal input terminal CK1, and the second clock signal input by the second clock signal input terminal CK2 are at a high level.
  • the third clock signal input by the third clock signal input terminal CK3 is at a low level.
  • the first thin film transistor M1 is turned off, the eighth thin film transistor M8 is turned on, the high level signal is transmitted to the first node P, the first node P is at a high level, the second thin film transistor M2 is turned off, and the first capacitor C1 is turned off.
  • Charging, the fourth thin film transistor M4 is turned off, the fifth thin film transistor M5 is turned on, the low level signal is transmitted to the third node R, the third node R is at a low level, the sixth thin film transistor M6 is turned on, and the second capacitor C2 is charged.
  • the seventh thin film transistor M7 is turned off.
  • the purpose of charging the second capacitor C2 is to enable the second capacitor C2 to stably maintain the opening of the sixth thin film transistor M6 when the next second clock signal is at a low level, thereby making the sixth thin film transistor M6 and the seventh thin film
  • the transistor M7 can be turned on at the same time when the second clock signal is at a low level, and then the high level signal is transmitted to the first node P to prevent the second clock signal from changing between the high level and the low level.
  • a signal applied to the gate of the thin film transistor M2 stabilizes the closing of the second thin film transistor M2, stabilizes the signal output on the signal output terminal OUTPUT, and improves the output effect of the shift register.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned on, the low level signal is transmitted to the second node Q, the third thin film transistor M3 is turned on, the high level signal is transmitted to the signal output terminal OUTPUT, and the third capacitor C3 is charged. .
  • the shift register will repeat the fourth to sixth stages until the start signal of the STV input of the next start signal input terminal is low level. The first phase begins.
  • the driving method of the shift register shown in FIG. 4 is divided into six stages, and the timing chart of the driving process is as shown in FIG. 6.
  • the first to tenth thin film transistors are all n-type thin film transistors, That is, the thin film transistor that is turned on when the signal applied on the gate is a high level signal and turned off when the low level signal is turned off.
  • the first stage t1 The first stage t1:
  • the second clock signal input by the second clock signal input terminal CK2 and the third clock signal input by the third clock signal input terminal CK3 are at a low level, and the start signal input from the start signal input terminal STV is The first clock signal input by the first clock signal input terminal CK1 is at a high level.
  • the first thin film transistor M1 is turned on, the start signal is transmitted to the first node P, the eighth thin film transistor M8 is turned off, the first node P is at a high level, the second thin film transistor M2 is turned on, and the second clock signal is transmitted to the signal.
  • the output terminal OUTPUT charges the first capacitor C1, the fourth thin film transistor M4 is turned on, the low level signal input by the low level signal input terminal VGL is transmitted to the third node R, and the third node R is at the low level, the sixth The thin film transistor M6 is turned off, and the second capacitor C2 is charged, the fifth thin film transistor M5 is turned off, and the seventh thin film transistor M7 is turned off.
  • the sixth thin film transistor M6 and the seventh thin film transistor M7 are both turned off, the low level signal input by the low level signal input terminal VGL cannot be transmitted to the first node P, thereby not affecting the gate of the second thin film transistor M2. The signal applied on it.
  • the ninth thin film transistor M9 is turned on, the tenth thin film transistor M10 is turned off, the start signal is transmitted to the second node Q, the second node Q is at a high level, the third thin film transistor M3 is turned on, and the low level signal input terminal VGL is low.
  • the flat signal is transmitted to the signal output terminal OUTPUT, thereby further stabilizing the low level signal outputted at the signal output terminal OUTPUT, and charging the third capacitor C3.
  • the start signal input by the start signal input terminal STV, the first clock signal input by the first clock signal input terminal CK1, and the third clock signal input by the third clock signal input terminal CK3 are at a low level.
  • the second clock signal input by the second clock signal input terminal CK2 is at a high level.
  • the first thin film transistor M1 is turned off
  • the eighth thin film transistor M8 is turned off
  • the coupling capacitance between the gate and the second electrode of the second thin film transistor M2 causes the level of the first node P to continue to rise
  • the first capacitor The C1 discharge turns on the second thin film transistor M2
  • the second clock signal is transmitted to the signal output terminal OUTPUT
  • the fourth thin film transistor M4 is turned on
  • the low level signal is transmitted to the third node R
  • the third node R is at the low level
  • the second The discharge of the capacitor C2 causes the sixth thin film transistor M6 to be turned off
  • the fifth thin film transistor M5 is turned off
  • the seventh thin film transistor M7 is turned on.
  • the sixth thin film transistor M6 is turned off, even if the seventh thin film transistor M7 is turned on, the low level signal input by the low level signal input terminal VGL cannot be transmitted to the first node P, thereby not affecting the second thin film transistor M2.
  • the signal applied to the gate since the sixth thin film transistor M6 is turned off, even if the seventh thin film transistor M7 is turned on, the low level signal input by the low level signal input terminal VGL cannot be transmitted to the first node P, thereby not affecting the second thin film transistor M2. The signal applied to the gate.
  • the ninth thin film transistor M9 is turned on, the start signal is transmitted to the second node Q, the tenth thin film transistor M10 is turned off, the third capacitor C3 is discharged to turn on the third thin film transistor M3, and the low level signal is transmitted to the signal output terminal OUTPUT.
  • the output signal of the signal output terminal OUTPUT is the sum of the low level signal and the second clock signal, so that the level of the output signal in the second stage is higher.
  • the third stage t3 The third stage t3:
  • the start signal input by the start signal input terminal STV, the first clock signal input by the first clock signal input terminal CK1, and the second clock signal input by the second clock signal input terminal CK2 are at a low level.
  • the third clock signal input by the third clock signal input terminal CK3 is at a high level.
  • the first thin film transistor M1 is turned off, the eighth thin film transistor M8 is turned on, the low level signal is transmitted to the first node P, the first node P is at a low level, the second thin film transistor M2 is turned off, and the first capacitor C1 is turned off.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned on, the high level signal is transmitted to the second node Q, the third thin film transistor M3 is turned on, the low level signal is transmitted to the signal output terminal OUTPUT, and the third capacitor C3 is charged. .
  • the start signal input by the start signal input terminal STV, the second clock signal input by the second clock signal input terminal CK2, and the third clock signal input by the third clock signal input terminal CK3 are at a low level.
  • the first clock signal input by the first clock signal input terminal CK1 is at a high level.
  • the first thin film transistor M1 is turned on, the start signal is transmitted to the first node P, the eighth thin film transistor M8 is turned off, the first node P is at a low level, the second thin film transistor M2 is turned off, and the first capacitor C1 is charged.
  • the fourth thin film transistor M4 is turned off, the fifth thin film transistor M5 is turned off, the second capacitor C2 is discharged to turn on the sixth thin film transistor M6, and the seventh thin film transistor M7 is turned off. Since the seventh thin film transistor M7 is turned off, even if the sixth thin film transistor M6 is turned on, the low level signal input from the low level signal input terminal VGL cannot be transmitted to the first node P.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned off, and the third capacitor C3 is placed.
  • the third thin film transistor M3 is turned on, and the low level signal is transmitted to the signal output terminal OUTPUT.
  • the fifth stage t5 The fifth stage t5:
  • the start signal input by the start signal input terminal STV, the first clock signal input by the first clock signal input terminal CK1, and the third clock signal input by the third clock signal input terminal CK3 are at a low level.
  • the second clock signal input by the second clock signal input terminal CK2 is at a high level.
  • the first thin film transistor M1 is turned off, the eighth thin film transistor M8 is turned off, the second capacitor C2 is discharged to turn on the sixth thin film transistor M6, the seventh thin film transistor M7 is turned on, and the low level signal is transmitted to the first node P, first The node P is at a low level, the second thin film transistor M2 is turned off, and the first capacitor C1 is charged, the fourth thin film transistor M4 is turned off, and the fifth thin film transistor M5 is turned off.
  • the sixth thin film transistor M6 is turned on, the seventh thin film transistor M7 is turned on, and the low level signal can be transmitted to the first node P to maintain the low level of the first node P, thereby causing the second clock signal to be low level.
  • the coupling capacitance between the gate and the second electrode of the second thin film transistor M2 does not affect the signal applied on the gate of the second thin film transistor M2.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned off, the third capacitor C3 is discharged to turn on the third thin film transistor M3, and the low level signal is transmitted to the signal output terminal OUTPUT.
  • the start signal input by the start signal input terminal STV, the first clock signal input by the first clock signal input terminal CK1, and the second clock signal input by the second clock signal input terminal CK2 are at a low level.
  • the third clock signal input by the third clock signal input terminal CK3 is at a high level.
  • the first thin film transistor M1 is turned off, the eighth thin film transistor M8 is turned on, the low level signal is transmitted to the first node P, the first node P is at a low level, the second thin film transistor M2 is turned off, and the first capacitor C1 is turned off.
  • Charging, the fourth thin film transistor M4 is turned off, the fifth thin film transistor M5 is turned on, the high level signal is transmitted to the third node R, the third node R is at the high level, the sixth thin film transistor M6 is turned on, and the second capacitor C2 is charged.
  • the seventh thin film transistor M7 is turned off.
  • the purpose of charging the second capacitor C2 is to enable the second capacitor C2 to stably maintain the opening of the sixth thin film transistor M6 when the next second clock signal is at a high level, thereby making the sixth thin film transistor M6 and the seventh thin film
  • the transistor M7 can be turned on while the second clock signal is at a high level, and then the low level signal is transmitted to the first node P to prevent the second clock signal from changing between the low level and the high level.
  • a signal applied to the gate of the thin film transistor M2 stabilizes the closing of the second thin film transistor M2, stabilizes the signal output on the signal output terminal OUTPUT, and improves the output effect of the shift register.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned on, the high level signal is transmitted to the second node Q, the third thin film transistor M3 is turned on, the low level signal is transmitted to the signal output terminal OUTPUT, and the third capacitor C3 is charged. .
  • the shift register will repeat the fourth to sixth stages until the start signal of the STV input of the next start signal input terminal is low level. The first phase begins.
  • Embodiments of the present disclosure provide a driving method of a shift register, the driving method includes: controlling, by an input module, a signal input between a start signal input end and a first node; and outputting, by the output module, a signal output of the signal output end;
  • the output control module controls the output module, the output control module includes a first control unit and a second control unit, the output module includes a first output unit and a second output unit, wherein the level of the first node is controlled by the first control unit, One node controls the first output unit, the second control unit controls the level of the second node, and the second node controls the second output unit, thereby stabilizing the levels of the first node and the second node, and reducing the clock associated with the output module
  • the effect of the change in the signal on the output signal improves the output of the shift register.
  • the present disclosure can be implemented by means of software plus necessary general hardware, and of course, can also be implemented by hardware.
  • the technical solutions of the present disclosure may be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer, a hard disk or an optical disk, etc., including a plurality of instructions for causing a computer device (may be a personal computer, server, or network device, etc.) performs the methods described in various embodiments of the present disclosure.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置，其中该移位寄存器包括输入模块(1)、输出模块(2)和输出控制模块(3)；输出模块(2)包括第一输出单元(21)和第二输出单元(22)，其中，第一节点(P)控制第一输出单元(21)，第一输出单元(21)控制第二时钟信号输入端(CK2)和信号输出端(OUT-PUT)之间的信号传输，第二节点(Q)控制第二输出单元(22)，第二输出单元(22)控制高/低电平信号输入端(VGH/VGL)和信号输出端(OUT-PUT)之间的信号传输；输出控制模块(3)包括第一控制单元(31)和第二控制单元(32)，其中，第一控制单元(31)控制第一节点(P)的电平，第二控制单元(32)控制第二节点(Q)的电平。根据本公开的方案能够降低输出模块关联的时钟信号的变化对输出信号的影响，改善移位寄存器的输出效果。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
为了实现显示装置的正常显示，显示装置需要包括栅极驱动电路。具体地，栅极驱动电路包括多个相互级联的移位寄存器。
具体地，移位寄存器的结构如图1所示，该移位寄存器包括输入模块、输出模块和输出控制模块，其中，输入模块包括M1，输出模块包括M2和M3，输出控制模块包括M4、M5、C1和C2，其中，M1-M5均为低电平开启的PMOSFET。其工作过程的时序图如图2所示，在t1阶段，起始信号输入端STV输入的起始信号和第一时钟信号输入端CK1输入的第一时钟信号为低电平信号，第二时钟信号输入端CK2输入的第二时钟信号为高电平信号，此时，M1、M2、M3、M4和M5均开启，信号输出端Output输出高电平(非有效信号)；在t2阶段，起始信号输入端STV输入的起始信号和第一时钟信号输入端CK1输入的第一时钟信号为高电平信号，第二时钟信号输入端CK2输入的第二时钟信号为低电平信号，M1、M4和M5关闭，由于C2和C1的作用，M2和M3开启，信号输出端Output输出低电平(有效信号)。
发明人发现，在第二时钟信号输入端CK2输入的第二时钟信号变化时，M2的栅极上的信号会受到M2的栅极和漏极之间形成的耦合电容的影响，进而影响输出端Output输出的输出信号，导致输出信号变差，影响移位寄存器的输出效果。
发明内容
本公开提供了一种移位寄存器及其驱动方法、栅极驱动电路、显示装置，能够降低输出模块关联的时钟信号的变化对输出信号的影响，改善移位寄存器的输出效果。
根据第一方面，本公开实施例提供了一种移位寄存器，其包括：输入模块、输出模块和输出控制模块；
所述输入模块被配置为控制起始信号输入端和第一节点之间的信号传 输；
所述输出模块被配置为控制信号输出端的信号输出，所述输出模块包括第一输出单元和第二输出单元，其中，所述第一输出单元连接第一节点，所述第一节点被配置为控制所述第一输出单元，所述第一输出单元被配置为控制第二时钟信号输入端和所述信号输出端之间的信号传输，所述第二输出单元连接第二节点，所述第二节点被配置为控制所述第二输出单元，所述第二输出单元被配置为控制第一电平信号输入端和所述信号输出端之间的信号传输；
所述输出控制模块包括第一控制单元和第二控制单元，其中，所述第一控制单元被配置为控制所述第一节点的电平，所述第二控制单元被配置为控制所述第二节点的电平。
所述输入模块包括第一薄膜晶体管，所述第一薄膜晶体管的栅极连接第一时钟信号输入端，第一极连接所述起始信号输入端，第二极连接所述第一节点。
所述第一输出单元包括第二薄膜晶体管，所述第二薄膜晶体管的栅极连接所述第一节点，第一极连接所述信号输出端，第二极连接所述第二时钟信号输入端。
所述第二输出单元包括第三薄膜晶体管，所述第三薄膜晶体管的栅极连接所述第二节点，第一极连接所述第一电平信号输入端，第二极连接所述信号输出端。
所述第一控制单元包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第一电容和第二电容；其中，所述第四薄膜晶体管的栅极连接所述第一节点，第一极连接第三节点，第二极连接所述第一电平信号输入端；
所述第五薄膜晶体管的栅极连接第三时钟信号输入端，第一极连接所述第三节点，第二极连接第二电平信号输入端；
所述第六薄膜晶体管的栅极连接所述第三节点，第一极连接所述第七薄膜晶体管的第二极，第二极连接所述第一电平信号输入端；
所述第七薄膜晶体管的栅极连接所述第二时钟信号输入端，第一极连接所述第一节点，第二极连接所述第六薄膜晶体管的第一极；
所述第八薄膜晶体管的栅极连接所述第三时钟信号输入端，第一极连接 所述第一电平信号输入端，第二极连接所述第一节点；
所述第一电容的一端连接所述信号输出端，另一端连接所述第一节点；
所述第二电容的一端连接所述第三节点，另一端连接所述第一电平信号输入端。
所述第二控制单元包括第九薄膜晶体管、第十薄膜晶体管和第三电容；
其中，所述第九薄膜晶体管的栅极连接所述第一节点，第一极连接所述起始信号输入端，第二极连接所述第二节点；
所述第十薄膜晶体管的栅极连接第三时钟信号输入端，第一极连接所述第二节点，第二极连接第二电平信号输入端；
所述第三电容的一端连接所述第二节点，另一端连接所述第一电平信号输入端。
可选地，当其中的薄膜晶体管为p型时，第一电平信号输入端输入高电平，第二电平信号输入端输入低电平，第一极为源极，第二极为漏极，当其中的薄膜晶体管为N型时，第一电平信号输入端输入低电平，第二电平信号输入端输入高电平，第一极为漏极，第二极为源极。
本公开实施例提供了一种移位寄存器，该移位寄存器包括：输入模块、输出模块和输出控制模块；输入模块控制起始信号输入端和第一节点之间的信号传输；输出模块控制信号输出端的信号输出，输出模块包括第一输出单元和第二输出单元，其中，第一输出单元连接第一节点，第一节点控制第二时钟信号输入端和信号输出端之间的信号传输，第二输出单元连接第二节点，第二节点控制第一电平信号输入端和信号输出端之间的信号传输；输出控制模块包括第一控制单元和第二控制单元，其中，第一控制单元控制第一节点的电平，第二控制单元控制第二节点的电平，从而能够稳定第一节点和第二节点的电平，降低输出模块关联的时钟信号的变化对输出信号的影响，改善移位寄存器的输出效果。
此外，本公开实施例还提供了一种栅极驱动电路，该栅极驱动电路包括多个相互级联的以上任一项所述的移位寄存器。
本公开实施例还提供了一种显示装置，该显示装置包括以上所述的栅极驱动电路。
根据又一方面，本公开实施例还提供了一种移位寄存器的驱动方法，包括：
通过输入模块控制起始信号输入端和第一节点之间的信号传输；
通过输出控制模块控制输出模块；以及
通过输出模块控制信号输出端的信号输出；
其中，所述输出控制模块包括第一控制单元和第二控制单元，所述输出模块包括第一输出单元和第二输出单元，其中，通过所述第一控制单元控制所述第一节点的电平，进而通过所述第一节点控制所述第一输出单元，通过所述第二控制单元控制所述第二节点的电平，进而通过所述第二节点控制所述第二输出单元。
可选地，该驱动方法包括：
在第一阶段，
第二时钟信号输入端输入的第二时钟信号和第三时钟信号输入端输入的第三时钟信号为高电平，起始信号输入端输入的起始信号和第一时钟信号输入端输入的第一时钟信号为低电平；
所述起始信号传输至所述第一节点，所述第一节点处于低电平，所述第二时钟信号传输至所述信号输出端；
所述起始信号传输至所述第二节点，所述第二节点处于低电平，所述高电平信号输入端的高电平信号传输至所述信号输出端；
在第二阶段，
所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第三时钟信号输入端输入的第三时钟信号为高电平，所述第二时钟信号输入端输入的第二时钟信号为低电平；
所述第二时钟信号传输至所述信号输出端，
所述起始信号传输至所述第二节点，所述高电平信号传输至所述信号输出端；
在第三阶段，
所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第二时钟信号输入端输入的第二时钟信号为高电平，所述第三时钟信号输入端输入的第三时钟信号为低电平；
所述高电平信号传输至所述第一节点，所述第一节点处于高电平，
所述低电平信号传输至所述第二节点，所述高电平信号传输至所述信号输出端；
在第四阶段，
所述起始信号输入端输入的起始信号、所述第二时钟信号输入端输入的第二时钟信号和所述第三时钟信号输入端输入的第三时钟信号为高电平，所述第一时钟信号输入端输入的第一时钟信号为低电平；
所述起始信号传输至所述第一节点，所述第一节点处于高电平，
所述高电平信号传输至所述信号输出端；
在第五阶段，
所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第三时钟信号输入端输入的第三时钟信号为高电平，所述第二时钟信号输入端输入的第二时钟信号为低电平；
所述高电平信号传输至所述第一节点，所述第一节点处于高电平，
所述高电平信号传输至所述信号输出端；
在第六阶段，
所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第二时钟信号输入端输入的第二时钟信号为高电平，所述第三时钟信号输入端输入的第三时钟信号为低电平；
所述高电平信号传输至所述第一节点，所述第一节点处于高电平，
所述低电平信号传输至所述第二节点，所述高电平信号传输至所述信号输出端。
可选地，该驱动方法包括：
在第一阶段，
第二时钟信号输入端输入的第二时钟信号和第三时钟信号输入端输入的第三时钟信号为低电平，起始信号输入端输入的起始信号和第一时钟信号输入端输入的第一时钟信号为高电平；
所述起始信号传输至所述第一节点，所述第一节点处于高电平，所述第二时钟信号传输至所述信号输出端，
所述起始信号传输至所述第二节点，所述第二节点处于高电平，
所述低电平信号输入端的低电平信号传输至所述信号输出端；
在第二阶段，
所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第三时钟信号输入端输入的第三时钟信号为低电平，所 述第二时钟信号输入端输入的第二时钟信号为高电平；
所述第二时钟信号传输至所述信号输出端，
所述起始信号传输至所述第二节点，
所述低电平信号传输至所述信号输出端；
在第三阶段，
所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第二时钟信号输入端输入的第二时钟信号为低电平，所述第三时钟信号输入端输入的第三时钟信号为高电平；
所述低电平信号传输至所述第一节点，所述第一节点处于低电平，
所述高电平信号传输至所述第二节点，所述低电平信号传输至所述信号输出端；
在第四阶段，
所述起始信号输入端输入的起始信号、所述第二时钟信号输入端输入的第二时钟信号和所述第三时钟信号输入端输入的第三时钟信号为低电平，所述第一时钟信号输入端输入的第一时钟信号为高电平；
所述起始信号传输至所述第一节点，所述第一节点处于低电平，
所述低电平信号传输至所述信号输出端；
在第五阶段，
所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第三时钟信号输入端输入的第三时钟信号为低电平，所述第二时钟信号输入端输入的第二时钟信号为高电平；
所述低电平信号传输至所述第一节点，所述第一节点处于低电平，
所述低电平信号传输至所述信号输出端；
在第六阶段，
所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第二时钟信号输入端输入的第二时钟信号为低电平，所述第三时钟信号输入端输入的第三时钟信号为高电平；
所述低电平信号传输至所述第一节点，
所述高电平信号传输至所述第二节点，所述低电平信号传输至所述信号输出端。
本公开实施例提供了一种移位寄存器的驱动方法，该驱动方法包括：通 过输入模块控制起始信号输入端和第一节点之间的信号输入；通过输出模块控制信号输出端的信号输出；通过输出控制模块控制输出模块，输出控制模块包括第一控制单元和第二控制单元，输出模块包括第一输出单元和第二输出单元，其中，通过第一控制单元控制第一节点的电平，第一节点控制第一输出单元，通过第二控制单元控制第二节点的电平，第二节点控制第二输出单元，从而能够稳定第一节点和第二节点的电平，降低输出模块关联的时钟信号的变化对输出信号的影响，改善移位寄存器的输出效果。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种已知的移位寄存器的电路示意图；
图2为一种已知的移位寄存器的驱动过程的时序图；
图3为本公开实施例提供的第一种移位寄存器的电路示意图；
图4为本公开实施例提供的第二种移位寄存器的电路示意图；
图5为本公开实施例提供的第一种移位寄存器的驱动过程的时序图；
图6为本公开实施例提供的第二种移位寄存器的驱动过程的时序图。
附图标记说明：
1—输入模块；2—输出模块；21—第一输出单元；22—第二输出单元；
3—输出控制模块；31—第一控制单元；32—第二控制单元。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
实施例一
本公开实施例提供了一种移位寄存器，如图3和图4所示，该移位寄存器包括输入模块1、输出模块2和输出控制模块3。
具体地，输入模块1控制起始信号输入端STV和第一节点P之间的信号传输。
输出模块2控制信号输出端OUTPUT的信号输出，输出模块2包括第一输出单元21和第二输出单元22，其中，第一输出单元21连接第一节点P，第一节点P控制第一输出单元21，第一输出单元21控制第二时钟信号输入端CK2和信号输出端OUTPUT之间的信号传输，第二输出单元22连接第二节点Q，第二节点Q控制第二输出单元22，第二输出单元22控制高电平信号输入端VGH和信号输出端OUTPUT之间的信号传输。
输出控制模块3包括第一控制单元31和第二控制单元32，其中，第一控制单元31控制第一节点P的电平，第二控制单元32控制第二节点Q的电平。此时，当第二时钟信号输入端CK2输入的第二时钟信号在高电平和低电平之间变化时，第一控制单元31能够稳定第一节点P的电平，从而降低第二时钟信号的变化对输出信号的影响，改善移位寄存器的输出效果。
为了便于本领域技术人员理解，本公开实施例提供了以上所述的各个模块和单元的具体的结构：
可选地，如图3和图4所示，输入模块1包括第一薄膜晶体管M1，第一薄膜晶体管M1为p型薄膜晶体管或者n型薄膜晶体管，第一薄膜晶体管M1的栅极连接第一时钟信号输入端CK1，第一极连接起始信号输入端STV，第二极连接第一节点P，从而可以通过第一时钟信号输入端CK1输入的第一时钟信号，控制第一薄膜晶体管M1的开启和关闭，从而控制起始信号输入端STV和第一节点P之间的信号传输。
可选地，如图3和图4所示，第一输出单元21包括第二薄膜晶体管M2，第二薄膜晶体管M2为p型薄膜晶体管或者n型薄膜晶体管，第二薄膜晶体管M2的栅极连接第一节点P，第一极连接信号输出端OUTPUT，第二极连接第二时钟信号输入端CK2，从而可以通过第一节点P的电平，控制第二薄膜晶体管M2的开启和关闭，从而控制第二时钟信号输入端CK2和信号输出端OUTPUT之间的信号传输。
可选地，如图3和图4所示，第二输出单元22包括第三薄膜晶体管M3，当第三薄膜晶体管M3为p型薄膜晶体管时，如图3所示，第三薄膜晶体管M3的栅极连接第二节点Q，第一极连接高电平信号输入端VGH，第二极连接信号输出端OUTPUT，从而可以通过第二节点Q的电平，控制第三薄膜晶 体管M3的开启和关闭，从而控制高电平信号输入端VGH和信号输出端OUTPUT之间的信号传输。
当第三薄膜晶体管M3为n型薄膜晶体管时，如图4所示，第三薄膜晶体管M3的栅极连接第二节点Q，第一极连接低电平信号输入端VGL，第二极连接信号输出端OUTPUT，从而可以通过第二节点Q的电平，控制第三薄膜晶体管M3的开启和关闭，从而控制低电平信号输入端VGL和信号输出端OUTPUT之间的信号传输。
可选地，如图3和图4所示，第一控制单元31包括第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、第八薄膜晶体管M8、第一电容C1和第一电容C2。
当第四至第八薄膜晶体管均为p型薄膜晶体管时，如图3所示，第四薄膜晶体管M4的栅极连接第一节点P，第一极连接第三节点R，第二极连接高电平信号输入端VGH，从而可以通过第一节点P的电平，控制第四薄膜晶体管M4的开启和关闭，从而控制高电平信号输入端VGH和第三节点R之间的信号传输。
第五薄膜晶体管M5的栅极连接第三时钟信号输入端CK3，第一极连接第三节点R，第二极连接低电平信号输入端VGL，从而可以通过第三时钟信号，控制第五薄膜晶体管M5的开启和关闭，从而控制低电平信号输入端VGL和第三节点R之间的信号传输。
第六薄膜晶体管M6的栅极连接第三节点R，第一极连接第七薄膜晶体管M7的第二极，第二极连接高电平信号输入端VGH，从而可以通过第三节点R的电平，控制第六薄膜晶体管M6的开启和关闭，从而控制高电平信号输入端VGH和第七薄膜晶体管M7的第二极之间的信号传输。
第七薄膜晶体管M7的栅极连接第二时钟信号输入端CK2，第一极连接第一节点P，第二极连接第六薄膜晶体管M6的第一极，从而可以通过第二时钟信号，控制第七薄膜晶体管M7的开启和关闭，从而控制第一节点P和第六薄膜晶体管M6的第一极之间的信号传输。
第八薄膜晶体管M8的栅极连接第三时钟信号输入端CK3，第一极连接高电平信号输入端VGH，第二极连接第一节点P，从而可以通过第三时钟信号，控制第八薄膜晶体管M8的开启和关闭，从而控制高电平信号输入端VGH和第一节点P之间的信号传输。
第一电容C1的一端连接信号输出端OUTPUT，另一端连接第一节点P，从而可以通过第一电容C1控制第一节点P的电平。
第二电容C2的一端连接第三节点R，另一端连接高电平信号输入端VGH，从而可以通过第二电容C2控制第三节点R的电平。
当第四至第八薄膜晶体管均为n型薄膜晶体管时，如图4所示，第四薄膜晶体管M4的栅极连接第一节点P，第一极连接第三节点R，第二极连接低电平信号输入端VGL，从而可以通过第一节点P的电平，控制第四薄膜晶体管M4的开启和关闭，从而控制低电平信号输入端VGL和第三节点R之间的信号传输。
第五薄膜晶体管M5的栅极连接第三时钟信号输入端CK3，第一极连接第三节点R，第二极连接高电平信号输入端VGH，从而可以通过第三时钟信号控制第五薄膜晶体管M5的开启和关闭，从而控制高电平信号输入端VGH和第三节点R之间的信号传输。
第六薄膜晶体管M6的栅极连接第三节点R，第一极连接第七薄膜晶体管M7的第二极，第二极连接低电平信号输入端VGL，从而可以通过第三节点R的电平，控制第六薄膜晶体管M6的开启和关闭，从而控制低电平信号输入端VGL和第七薄膜晶体管M7的第二极之间的信号传输。
第七薄膜晶体管M7的栅极连接第二时钟信号输入端CK2，第一极连接第一节点P，第二极连接第六薄膜晶体管M6的第一极，从而可以通过第二时钟信号控制第七薄膜晶体管M7的开启和关闭，从而控制第一节点P和第六薄膜晶体管M6的第一极之间的信号传输。
第八薄膜晶体管M8的栅极连接第三时钟信号输入端CK3，第一极连接低电平信号输入端VGL，第二极连接第一节点P，从而可以通过第三时钟信号控制第八薄膜晶体管M8的开启和关闭，从而控制低电平信号输入端VGL和第一节点P之间的信号传输。
第一电容C1的一端连接信号输出端OUTPUT，另一端连接第一节点P，从而可以通过第一电容C1控制第一节点P的电平。
第二电容C2的一端连接第三节点R，另一端连接低电平信号输入端VGL，从而可以通过第二电容C2控制第三节点R的电平。
可选地，如图3和图4所示，第二控制单元32包括第九薄膜晶体管M9、第十薄膜晶体管M10和第三电容C3。
当第九、第十薄膜晶体管均为p型薄膜晶体管时，如图3所示，第九薄膜晶体管M9的栅极连接第一节点P，第一极连接起始信号输入端，第二极连接第二节点Q。
第十薄膜晶体管M10的栅极连接第三时钟信号输入端CK3，第一极连接第二节点Q，第二极连接低电平信号输入端VGL，从而可以通过第三时钟信号，控制第十薄膜晶体管M10的开启和关闭，从而控制低电平信号输入端VGL和第二节点Q之间的信号传输。
第三电容C3的一端连接第二节点Q，另一端连接高电平信号输入端VGH，从而可以通过第三电容C3控制第二节点Q的电平。
当第九、第十薄膜晶体管均为n型薄膜晶体管时，如图4所示，第九薄膜晶体管M9的栅极连接第一节点P，第一极连接起始信号输入端STV，第二极连接第二节点Q，从而可以通过第一节点P的电平，控制第九薄膜晶体管M9的开启和关闭，从而控制起始信号输入端STV和第二节点Q之间的信号传输。
第十薄膜晶体管M10的栅极连接第三时钟信号输入端CK3，第一极连接第二节点Q，第二极连接高电平信号输入端VGH，从而可以通过第三时钟信号，控制第十薄膜晶体管M10的开启和关闭，从而控制高电平信号输入端VGH和第二节点Q之间的信号传输。
第三电容C3的一端连接第二节点Q，另一端连接低电平信号输入端VGL，从而可以通过第三电容C3控制第二节点Q的电平。
需要说明的是，本公开实施例中的移位寄存器中的所有薄膜晶体管均为同种类型的薄膜晶体管，即，图3中的第一至第十薄膜晶体管均为p型薄膜晶体管，图4中的第一至第十薄膜晶体管均为n型薄膜晶体管，其中在p型薄膜晶体管的情况下，第一极为源极，第二极为漏极，在n型薄膜晶体管的情况下，第一极为漏极，第二极为源极。
本公开实施例提供了一种移位寄存器，该移位寄存器包括：输入模块、输出模块和输出控制模块；输入模块控制起始信号输入端和第一节点之间的信号传输；输出模块控制信号输出端的信号输出，输出模块包括第一输出单元和第二输出单元，其中，第一输出单元连接第一节点，第一节点控制第二时钟信号输入端和信号输出端之间的信号传输，第二输出单元连接第二节点，第二节点控制高(低)电平信号输入端和信号输出端之间的信号传输；输出 控制模块包括第一控制单元和第二控制单元，其中，第一控制单元控制第一节点的电平，第二控制单元控制第二节点的电平，从而能够稳定第一节点和第二节点的电平，降低输出模块关联的时钟信号的变化对输出信号的影响，改善移位寄存器的输出效果。
此外，本公开实施例还提供了一种栅极驱动电路，该栅极驱动电路包括多个相互级联的以上任一项所述的移位寄存器。
本公开实施例还提供了一种显示装置，该显示装置包括以上所述的栅极驱动电路。该显示装置可以为：液晶面板、平板电脑、电视机、显示器、笔记本电脑、电子纸、手机、数码相框、导航仪等任何具有显示功能的产品或部件。
实施例二
本公开实施例提供了一种实施例一中所述的移位寄存器的驱动方法，该移位寄存器的驱动方法包括：
通过输入模块1控制起始信号输入端STV和第一节点P之间的信号传输。
通过输出模块2控制信号输出端OUTPUT的信号输出。
通过输出控制模块3控制输出模块2。
其中，输出控制模块3包括第一控制单元31和第二控制单元32，输出模块2包括第一输出单元21和第二输出单元22，其中，通过第一控制单元31控制第一节点P的电平，第一节点P控制第一输出单元21，通过第二控制单元32控制第二节点Q的电平，第二节点Q控制第二输出单元22，从而能够稳定第一节点P和第二节点Q的电平，降低输出模块2关联的时钟信号的变化对输出信号的影响，改善移位寄存器的输出效果。
具体地，如图3所示的移位寄存器的驱动方法分为六个阶段，驱动过程的时序图如图5所示，此时，第一至第十薄膜晶体管均为p型薄膜晶体管，即栅极上施加的信号为低电平信号时开启，高电平信号时关闭的薄膜晶体管。
第一阶段t1：
如图5所示，第二时钟信号输入端CK2输入的第二时钟信号和第三时钟信号输入端CK3输入的第三时钟信号为高电平，起始信号输入端STV输入的起始信号和第一时钟信号输入端CK1输入的第一时钟信号为低电平。
此时，第一薄膜晶体管M1开启，起始信号传输至第一节点P，第八薄膜晶体管M8关闭，第一节点P处于低电平，第二薄膜晶体管M2开启，第二 时钟信号传输至信号输出端OUTPUT，并对第一电容C1充电，第四薄膜晶体管M4开启，高电平信号输入端VGH输入的高电平信号传输至第三节点R，第三节点R处于高电平，第六薄膜晶体管M6关闭，并对第二电容C2充电，第五薄膜晶体管M5关闭，第七薄膜晶体管M7关闭。由于第六薄膜晶体管M6和第七薄膜晶体管M7均关闭，从而使得高电平信号输入端VGH输入的高电平信号无法传输至第一节点P，进而不会影响第二薄膜晶体管M2的栅极上施加的信号。
第九薄膜晶体管M9开启，第十薄膜晶体管M10关闭，起始信号传输至第二节点Q，第二节点Q处于低电平，第三薄膜晶体管M3开启，高电平信号输入端VGH的高电平信号传输至信号输出端OUTPUT，从而进一步稳定信号输出端OUTPUT上输出的高电平信号，并对第三电容C3充电。
第二阶段t2：
如图5所示，起始信号输入端STV输入的起始信号、第一时钟信号输入端CK1输入的第一时钟信号和第三时钟信号输入端CK3输入的第三时钟信号为高电平，第二时钟信号输入端CK2输入的第二时钟信号为低电平。
此时，第一薄膜晶体管M1关闭，第八薄膜晶体管M8关闭，第二薄膜晶体管M2的栅极和第二极之间的耦合电容使第一节点P的电平继续降低，且第一电容C1放电使第二薄膜晶体管M2开启，第二时钟信号传输至信号输出端OUTPUT，第四薄膜晶体管M4开启，高电平信号传输至第三节点R，第三节点R处于高电平，第二电容C2放电使第六薄膜晶体管M6关闭，第五薄膜晶体管M5关闭，第七薄膜晶体管M7开启。由于第六薄膜晶体管M6关闭，因此，即使第七薄膜晶体管M7开启，高电平信号输入端VGH输入的高电平信号也无法传输至第一节点P，进而不会影响第二薄膜晶体管M2的栅极上施加的信号。
第九薄膜晶体管M9开启，起始信号传输至第二节点Q，第十薄膜晶体管M10关闭，第三电容C3放电使第三薄膜晶体管M3开启，高电平信号传输至信号输出端OUTPUT。
在第二阶段中，信号输出端OUTPUT的输出信号为高电平信号和第二时钟信号之和，从而第二阶段中输出信号的电平较低。
第三阶段t3：
如图5所示，起始信号输入端STV输入的起始信号、第一时钟信号输入 端CK1输入的第一时钟信号和第二时钟信号输入端CK2输入的第二时钟信号为高电平，第三时钟信号输入端CK3输入的第三时钟信号为低电平。
此时，第一薄膜晶体管M1关闭，第八薄膜晶体管M8开启，高电平信号传输至第一节点P，第一节点P处于高电平，第二薄膜晶体管M2关闭，并对第一电容C1充电，第四薄膜晶体管M4关闭，第五薄膜晶体管M5开启，低电平信号输入端VGL输入的低电平信号传输至第三节点R，第三节点R处于低电平，第六薄膜晶体管M6开启，并对第二电容C2充电，第七薄膜晶体管M7关闭。由于第七薄膜晶体管M7关闭，因此，即使第六薄膜晶体管M6开启，高电平信号输入端VGH输入的高电平信号仍然无法传输至第一节点P。
第九薄膜晶体管M9关闭，第十薄膜晶体管M10开启，低电平信号传输至第二节点Q，第三薄膜晶体管M3开启，高电平信号传输至信号输出端OUTPUT，并对第三电容C3充电。
第四阶段t4：
如图5所示，起始信号输入端STV输入的起始信号、第二时钟信号输入端CK2输入的第二时钟信号和第三时钟信号输入端CK3输入的第三时钟信号为高电平，第一时钟信号输入端CK1输入的第一时钟信号为低电平。
此时，第一薄膜晶体管M1开启，起始信号传输至第一节点P，第八薄膜晶体管M8关闭，第一节点P处于高电平，第二薄膜晶体管M2关闭，并对第一电容C1充电，第四薄膜晶体管M4关闭，第五薄膜晶体管M5关闭，第二电容C2放电使第六薄膜晶体管M6开启，第七薄膜晶体管M7关闭。由于第七薄膜晶体管M7关闭，因此，即使第六薄膜晶体管M6开启，高电平信号输入端VGH输入的高电平信号仍然无法传输至第一节点P。
第九薄膜晶体管M9关闭，第十薄膜晶体管M10关闭，第三电容C3放电使第三薄膜晶体管M3开启，高电平信号传输至信号输出端OUTPUT。
第五阶段t5：
如图5所示，起始信号输入端STV输入的起始信号、第一时钟信号输入端CK1输入的第一时钟信号和第三时钟信号输入端CK3输入的第三时钟信号为高电平，第二时钟信号输入端CK2输入的第二时钟信号为低电平。
此时，第一薄膜晶体管M1关闭，第八薄膜晶体管M8关闭，第二电容C2放电使第六薄膜晶体管M6开启，第七薄膜晶体管M7开启，高电平信号传输至第一节点P，第一节点P处于高电平，第二薄膜晶体管M2关闭，并 对第一电容C1充电，第四薄膜晶体管M4关闭，第五薄膜晶体管M5关闭。此时，由于第六薄膜晶体管M6开启，第七薄膜晶体管M7开启，高电平信号能够传输至第一节点P，维持第一节点P的高电平，从而使得第二时钟信号由高电平变为低电平时，第二薄膜晶体管M2的栅极和第二极之间的耦合电容不会影响在第二薄膜晶体管M2的栅极上施加的信号。
第九薄膜晶体管M9关闭，第十薄膜晶体管M10关闭，第三电容C3放电使第三薄膜晶体管M3开启，高电平信号传输至信号输出端OUTPUT。
第六阶段t6：
如图5所示，起始信号输入端STV输入的起始信号、第一时钟信号输入端CK1输入的第一时钟信号和第二时钟信号输入端CK2输入的第二时钟信号为高电平，第三时钟信号输入端CK3输入的第三时钟信号为低电平。
此时，第一薄膜晶体管M1关闭，第八薄膜晶体管M8开启，高电平信号传输至第一节点P，第一节点P处于高电平，第二薄膜晶体管M2关闭，并对第一电容C1充电，第四薄膜晶体管M4关闭，第五薄膜晶体管M5开启，低电平信号传输至第三节点R，第三节点R处于低电平，第六薄膜晶体管M6开启，并对第二电容C2充电，第七薄膜晶体管M7关闭。其中，对第二电容C2充电的目的在于，使第二电容C2在下一个第二时钟信号为低电平时能够稳定地维持第六薄膜晶体管M6的开启，从而使得第六薄膜晶体管M6和第七薄膜晶体管M7能够在第二时钟信号为低电平同时打开，进而将高电平信号传输至第一节点P，以避免第二时钟信号在高电平和低电平之间变化时，影响在第二薄膜晶体管M2的栅极上施加的信号，从而稳定第二薄膜晶体管M2的关闭，稳定信号输出端OUTPUT上的信号输出，改善移位寄存器的输出效果。
第九薄膜晶体管M9关闭，第十薄膜晶体管M10开启，低电平信号传输至第二节点Q，第三薄膜晶体管M3开启，高电平信号传输至信号输出端OUTPUT，并对第三电容C3充电。
需要补充的是，在第一至第六阶段结束后，移位寄存器将会重复第四至第六阶段，直至下一次起始信号输入端STV输入的起始信号为低电平时，再从第一阶段开始。
具体地，如图4所示的移位寄存器的驱动方法分为六个阶段，驱动过程的时序图如图6所示，此时，第一至第十薄膜晶体管均为n型薄膜晶体管， 即栅极上施加的信号为高电平信号时开启，低电平信号时关闭的薄膜晶体管。
第一阶段t1：
如图6所示，第二时钟信号输入端CK2输入的第二时钟信号和第三时钟信号输入端CK3输入的第三时钟信号为低电平，起始信号输入端STV输入的起始信号和第一时钟信号输入端CK1输入的第一时钟信号为高电平。
此时，第一薄膜晶体管M1开启，起始信号传输至第一节点P，第八薄膜晶体管M8关闭，第一节点P处于高电平，第二薄膜晶体管M2开启，第二时钟信号传输至信号输出端OUTPUT，并对第一电容C1充电，第四薄膜晶体管M4开启，低电平信号输入端VGL输入的低电平信号传输至第三节点R，第三节点R处于低电平，第六薄膜晶体管M6关闭，并对第二电容C2充电，第五薄膜晶体管M5关闭，第七薄膜晶体管M7关闭。由于第六薄膜晶体管M6和第七薄膜晶体管M7均关闭，从而使得低电平信号输入端VGL输入的低电平信号无法传输至第一节点P，进而不会影响第二薄膜晶体管M2的栅极上施加的信号。
第九薄膜晶体管M9开启，第十薄膜晶体管M10关闭，起始信号传输至第二节点Q，第二节点Q处于高电平，第三薄膜晶体管M3开启，低电平信号输入端VGL的低电平信号传输至信号输出端OUTPUT，从而进一步稳定信号输出端OUTPUT上输出的低电平信号，并对第三电容C3充电。
第二阶段t2：
如图6所示，起始信号输入端STV输入的起始信号、第一时钟信号输入端CK1输入的第一时钟信号和第三时钟信号输入端CK3输入的第三时钟信号为低电平，第二时钟信号输入端CK2输入的第二时钟信号为高电平。
此时，第一薄膜晶体管M1关闭，第八薄膜晶体管M8关闭，第二薄膜晶体管M2的栅极和第二极之间的耦合电容使第一节点P的电平继续升高，且第一电容C1放电使第二薄膜晶体管M2开启，第二时钟信号传输至信号输出端OUTPUT，第四薄膜晶体管M4开启，低电平信号传输至第三节点R，第三节点R处于低电平，第二电容C2放电使第六薄膜晶体管M6关闭，第五薄膜晶体管M5关闭，第七薄膜晶体管M7开启。由于第六薄膜晶体管M6关闭，因此，即使第七薄膜晶体管M7开启，低电平信号输入端VGL输入的低电平信号也无法传输至第一节点P，进而不会影响第二薄膜晶体管M2的栅极上施加的信号。
第九薄膜晶体管M9开启，起始信号传输至第二节点Q，第十薄膜晶体管M10关闭，第三电容C3放电使第三薄膜晶体管M3开启，低电平信号传输至信号输出端OUTPUT。
在第二阶段中，信号输出端OUTPUT的输出信号为低电平信号和第二时钟信号之和，从而第二阶段中输出信号的电平较高。
第三阶段t3：
如图6所示，起始信号输入端STV输入的起始信号、第一时钟信号输入端CK1输入的第一时钟信号和第二时钟信号输入端CK2输入的第二时钟信号为低电平，第三时钟信号输入端CK3输入的第三时钟信号为高电平。
此时，第一薄膜晶体管M1关闭，第八薄膜晶体管M8开启，低电平信号传输至第一节点P，第一节点P处于低电平，第二薄膜晶体管M2关闭，并对第一电容C1充电，第四薄膜晶体管M4关闭，第五薄膜晶体管M5开启，高电平信号输入端VGH输入的高电平信号传输至第三节点R，第三节点R处于高电平，第六薄膜晶体管M6开启，并对第二电容C2充电，第七薄膜晶体管M7关闭。由于第七薄膜晶体管M7关闭，因此，即使第六薄膜晶体管M6开启，低电平信号输入端VGL输入的低电平信号仍然无法传输至第一节点P。
第九薄膜晶体管M9关闭，第十薄膜晶体管M10开启，高电平信号传输至第二节点Q，第三薄膜晶体管M3开启，低电平信号传输至信号输出端OUTPUT，并对第三电容C3充电。
第四阶段t4：
如图6所示，起始信号输入端STV输入的起始信号、第二时钟信号输入端CK2输入的第二时钟信号和第三时钟信号输入端CK3输入的第三时钟信号为低电平，第一时钟信号输入端CK1输入的第一时钟信号为高电平。
此时，第一薄膜晶体管M1开启，起始信号传输至第一节点P，第八薄膜晶体管M8关闭，第一节点P处于低电平，第二薄膜晶体管M2关闭，并对第一电容C1充电，第四薄膜晶体管M4关闭，第五薄膜晶体管M5关闭，第二电容C2放电使第六薄膜晶体管M6开启，第七薄膜晶体管M7关闭。由于第七薄膜晶体管M7关闭，因此，即使第六薄膜晶体管M6开启，低电平信号输入端VGL输入的低电平信号仍然无法传输至第一节点P。
第九薄膜晶体管M9关闭，第十薄膜晶体管M10关闭，第三电容C3放 电使第三薄膜晶体管M3开启，低电平信号传输至信号输出端OUTPUT。
第五阶段t5：
如图6所示，起始信号输入端STV输入的起始信号、第一时钟信号输入端CK1输入的第一时钟信号和第三时钟信号输入端CK3输入的第三时钟信号为低电平，第二时钟信号输入端CK2输入的第二时钟信号为高电平。
此时，第一薄膜晶体管M1关闭，第八薄膜晶体管M8关闭，第二电容C2放电使第六薄膜晶体管M6开启，第七薄膜晶体管M7开启，低电平信号传输至第一节点P，第一节点P处于低电平，第二薄膜晶体管M2关闭，并对第一电容C1充电，第四薄膜晶体管M4关闭，第五薄膜晶体管M5关闭。此时，由于第六薄膜晶体管M6开启，第七薄膜晶体管M7开启，低电平信号能够传输至第一节点P，维持第一节点P的低电平，从而使得第二时钟信号由低电平变为高电平时，第二薄膜晶体管M2的栅极和第二极之间的耦合电容不会影响在第二薄膜晶体管M2的栅极上施加的信号。
第九薄膜晶体管M9关闭，第十薄膜晶体管M10关闭，第三电容C3放电使第三薄膜晶体管M3开启，低电平信号传输至信号输出端OUTPUT。
第六阶段t6：
如图6所示，起始信号输入端STV输入的起始信号、第一时钟信号输入端CK1输入的第一时钟信号和第二时钟信号输入端CK2输入的第二时钟信号为低电平，第三时钟信号输入端CK3输入的第三时钟信号为高电平。
此时，第一薄膜晶体管M1关闭，第八薄膜晶体管M8开启，低电平信号传输至第一节点P，第一节点P处于低电平，第二薄膜晶体管M2关闭，并对第一电容C1充电，第四薄膜晶体管M4关闭，第五薄膜晶体管M5开启，高电平信号传输至第三节点R，第三节点R处于高电平，第六薄膜晶体管M6开启，并对第二电容C2充电，第七薄膜晶体管M7关闭。其中，对第二电容C2充电的目的在于，使第二电容C2在下一个第二时钟信号为高电平时能够稳定地维持第六薄膜晶体管M6的开启，从而使得第六薄膜晶体管M6和第七薄膜晶体管M7能够在第二时钟信号为高电平同时打开，进而将低电平信号传输至第一节点P，以避免第二时钟信号在低电平和高电平之间变化时，影响在第二薄膜晶体管M2的栅极上施加的信号，从而稳定第二薄膜晶体管M2的关闭，稳定信号输出端OUTPUT上的信号输出，改善移位寄存器的输出效果。
第九薄膜晶体管M9关闭，第十薄膜晶体管M10开启，高电平信号传输至第二节点Q，第三薄膜晶体管M3开启，低电平信号传输至信号输出端OUTPUT，并对第三电容C3充电。
需要补充的是，在第一至第六阶段结束后，移位寄存器将会重复第四至第六阶段，直至下一次起始信号输入端STV输入的起始信号为低电平时，再从第一阶段开始。
本公开实施例提供了一种移位寄存器的驱动方法，该驱动方法包括：通过输入模块控制起始信号输入端和第一节点之间的信号输入；通过输出模块控制信号输出端的信号输出；通过输出控制模块控制输出模块，输出控制模块包括第一控制单元和第二控制单元，输出模块包括第一输出单元和第二输出单元，其中，通过第一控制单元控制第一节点的电平，第一节点控制第一输出单元，通过第二控制单元控制第二节点的电平，第二节点控制第二输出单元，从而能够稳定第一节点和第二节点的电平，降低输出模块关联的时钟信号的变化对输出信号的影响，改善移位寄存器的输出效果。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本公开可借助软件加必需的通用硬件的方式来实现，当然也可以通过硬件来实施。此外，本公开的技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在可读取的存储介质中，如计算机的软盘，硬盘或光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述的方法。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年2月3日递交的中国专利申请第201510055859.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (12)

  1. 一种移位寄存器，包括：输入模块、输出模块和输出控制模块；
    所述输入模块被配置为控制起始信号输入端和第一节点之间的信号传输；
    所述输出模块被配置为控制信号输出端的信号输出，所述输出模块包括第一输出单元和第二输出单元，其中，所述第一输出单元连接第一节点，所述第一节点被配置为控制所述第一输出单元，所述第一输出单元被配置为控制第二时钟信号输入端和所述信号输出端之间的信号传输，所述第二输出单元连接第二节点，所述第二节点被配置为控制所述第二输出单元，所述第二输出单元被配置为控制第一电平信号输入端和所述信号输出端之间的信号传输；
    所述输出控制模块包括第一控制单元和第二控制单元，其中，所述第一控制单元被配置为控制所述第一节点的电平，所述第二控制单元被配置为控制所述第二节点的电平。
  2. 根据权利要求1所述的移位寄存器，其中，所述输入模块包括第一薄膜晶体管，所述第一薄膜晶体管的栅极连接第一时钟信号输入端，第一极连接所述起始信号输入端，第二极连接所述第一节点。
  3. 根据权利要求1或2所述的移位寄存器，其中，所述第一输出单元包括第二薄膜晶体管，所述第二薄膜晶体管的栅极连接所述第一节点，第一极连接所述信号输出端，第二极连接所述第二时钟信号输入端。
  4. 根据权利要求1-3任一项所述的移位寄存器，其中，所述第二输出单元包括第三薄膜晶体管，所述第三薄膜晶体管的栅极连接所述第二节点，第一极连接所述第一电平信号输入端，第二极连接所述信号输出端。
  5. 根据权利要求1-4任一项所述的移位寄存器，其中，所述第一控制单元包括第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第一电容和第二电容；其中，所述第四薄膜晶体管的栅极连接所述第一节点，第一极连接第三节点，第二极连接所述第一电平信号输入端；
    所述第五薄膜晶体管的栅极连接第三时钟信号输入端，第一极连接所述第三节点，第二极连接第二电平信号输入端；
    所述第六薄膜晶体管的栅极连接所述第三节点，第一极连接所述第七薄膜晶体管的第二极，第二极连接所述第一电平信号输入端；
    所述第七薄膜晶体管的栅极连接所述第二时钟信号输入端，第一极连接所述第一节点，第二极连接所述第六薄膜晶体管的第一极；
    所述第八薄膜晶体管的栅极连接所述第三时钟信号输入端，第一极连接所述第一电平信号输入端，第二极连接所述第一节点；
    所述第一电容的一端连接所述信号输出端，另一端连接所述第一节点；
    所述第二电容的一端连接所述第三节点，另一端连接所述第一电平信号输入端。
  6. 根据权利要求1-5任一项所述的移位寄存器，其中，所述第二控制单元包括第九薄膜晶体管、第十薄膜晶体管和第三电容；其中，所述第九薄膜晶体管的栅极连接所述第一节点，第一极连接所述起始信号输入端，第二极连接所述第二节点；
    所述第十薄膜晶体管的栅极连接第三时钟信号输入端，第一极连接所述第二节点，第二极连接第二电平信号输入端；
    所述第三电容的一端连接所述第二节点，另一端连接所述第一电平信号输入端。
  7. 根据权利要求2-6任一项所述的移位寄存器，其中，当其中的薄膜晶体管为p型时，第一电平信号输入端输入高电平，第二电平信号输入端输入低电平，第一极为源极，第二极为漏极，当其中的薄膜晶体管为N型时，第一电平信号输入端输入低电平，第二电平信号输入端输入高电平，第一极为漏极，第二极为源极。
  8. 一种栅极驱动电路，包括多个相互级联的如权利要求1-7任一项所述的移位寄存器。
  9. 一种显示装置，包括如权利要求8所述的栅极驱动电路。
  10. 一种移位寄存器的驱动方法，包括：
    通过输入模块控制起始信号输入端和第一节点之间的信号传输；
    通过输出控制模块控制输出模块；以及
    通过输出模块控制信号输出端的信号输出，
    其中，所述输出控制模块包括第一控制单元和第二控制单元，所述输出模块包括第一输出单元和第二输出单元，通过所述第一控制单元控制第一节 点的电平，进而通过所述第一节点的电平控制所述第一输出单元，通过所述第二控制单元控制第二节点的电平，进而通过所述第二节点的电平控制所述第二输出单元。
  11. 根据权利要求10所述的移位寄存器的驱动方法，包括：
    在第一阶段，
    第二时钟信号输入端输入的第二时钟信号和第三时钟信号输入端输入的第三时钟信号为高电平，起始信号输入端输入的起始信号和第一时钟信号输入端输入的第一时钟信号为低电平；
    所述起始信号传输至第一节点，所述第一节点处于低电平，所述第二时钟信号传输至所述信号输出端；
    所述起始信号传输至第二节点，所述第二节点处于低电平，高电平信号输入端的高电平信号传输至所述信号输出端；
    在第二阶段，
    所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第三时钟信号输入端输入的第三时钟信号为高电平，所述第二时钟信号输入端输入的第二时钟信号为低电平；
    所述第二时钟信号传输至所述信号输出端；
    所述起始信号传输至所述第二节点，所述高电平信号传输至所述信号输出端；
    在第三阶段，
    所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第二时钟信号输入端输入的第二时钟信号为高电平，所述第三时钟信号输入端输入的第三时钟信号为低电平；
    高电平信号传输至所述第一节点，所述第一节点处于高电平，低电平信号传输至所述第二节点，所述高电平信号传输至所述信号输出端；
    在第四阶段，
    所述起始信号输入端输入的起始信号、所述第二时钟信号输入端输入的第二时钟信号和所述第三时钟信号输入端输入的第三时钟信号为高电平，所述第一时钟信号输入端输入的第一时钟信号为低电平；
    所述起始信号传输至所述第一节点，所述第一节点处于高电平，所述高电平信号传输至所述信号输出端；
    在第五阶段，
    所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第三时钟信号输入端输入的第三时钟信号为高电平，所述第二时钟信号输入端输入的第二时钟信号为低电平；
    高电平信号传输至所述第一节点，所述第一节点处于高电平，
    高电平信号传输至所述信号输出端；
    在第六阶段，
    所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第二时钟信号输入端输入的第二时钟信号为高电平，所述第三时钟信号输入端输入的第三时钟信号为低电平；
    高电平信号传输至所述第一节点，所述第一节点处于高电平，
    低电平信号传输至所述第二节点，高电平信号传输至所述信号输出端。
  12. 根据权利要求10所述的移位寄存器的驱动方法，包括：
    在第一阶段，
    第二时钟信号输入端输入的第二时钟信号和第三时钟信号输入端输入的第三时钟信号为低电平，起始信号输入端输入的起始信号和第一时钟信号输入端输入的第一时钟信号为高电平；
    所述起始信号传输至第一节点，所述第一节点处于高电平，所述第二时钟信号传输至所述信号输出端；
    所述起始信号传输至第二节点，所述第二节点处于高电平，低电平信号传输至所述信号输出端；
    在第二阶段，
    所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第三时钟信号输入端输入的第三时钟信号为低电平，所述第二时钟信号输入端输入的第二时钟信号为高电平；
    所述第二时钟信号传输至所述信号输出端，
    所述起始信号传输至所述第二节点，所述低电平信号传输至所述信号输出端；
    在第三阶段，
    所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第二时钟信号输入端输入的第二时钟信号为低电平，所 述第三时钟信号输入端输入的第三时钟信号为高电平；
    低电平信号传输至所述第一节点，所述第一节点处于低电平；所述高电平信号传输至所述第二节点，所述低电平信号传输至所述信号输出端；
    在第四阶段，
    所述起始信号输入端输入的起始信号、所述第二时钟信号输入端输入的第二时钟信号和所述第三时钟信号输入端输入的第三时钟信号为低电平，所述第一时钟信号输入端输入的第一时钟信号为高电平；
    所述起始信号传输至所述第一节点，所述第一节点处于低电平；
    所述低电平信号传输至所述信号输出端；
    在第五阶段，
    所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第三时钟信号输入端输入的第三时钟信号为低电平，所述第二时钟信号输入端输入的第二时钟信号为高电平；
    所述低电平信号传输至所述第一节点，所述第一节点处于低电平；
    所述低电平信号传输至所述信号输出端；
    在第六阶段，
    所述起始信号输入端输入的起始信号、所述第一时钟信号输入端输入的第一时钟信号和所述第二时钟信号输入端输入的第二时钟信号为低电平，所述第三时钟信号输入端输入的第三时钟信号为高电平；
    所述低电平信号传输至所述第一节点，所述第一节点处于低电平；
    所述高电平信号传输至所述第二节点，所述低电平信号传输至所述信号输出端。
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